DAC8551-Q1 [TI]
DAC8551-Q1 汽车类 16 位、超低毛刺脉冲、电压输出 DAC;
| 型号： | DAC8551-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DAC8551-Q1 汽车类 16 位、超低毛刺脉冲、电压输出 DAC 脉冲 |
| 文件： | 总29页 (文件大小：1392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DAC8551-Q1
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
DAC8551-Q1 汽车类 16 位、超低毛刺脉冲、电压输出 DAC
1 特性
3 说明
1
•
适用于汽车电子 应用
具有符合 AEC-Q100 的下列结果：
DAC8551-Q1 是一款小型、低功耗、电压输出、16 位
数模转换器 (DAC)，符合汽车类 应用的需求。
DAC8551-Q1 具有出色的线性度，并且最大限度减少
了意外的码间瞬态电压。DAC8551-Q1 器件采用时钟
速率达 30MHz 的通用三线制串口，并且兼容标准的
SPI、QSPI、Microwire 和数字信号处理器 (DSP) 接
口。
•
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
•
•
•
•
•
•
•
•
•
•
•
相对精度：16 最低有效位 (LSB) 积分非线性 (INL)
超低毛刺脉冲：0.1nV-s
DAC8551-Q1 需要使用一个外部基准电压来设置其输
出范围。DAC8551-Q1 包含一个上电复位电路，可确
保 DAC 输出在 0V 时上电，并在器件被执行有效写操
作之前一直保持此状态。DAC8551-Q1 包含一个由串
口访问的掉电特性，可将器件在 5V 电压下的电流消耗
降低至 800μA。
稳定时间：8μs 达到 ±0.003% 满量程范围 (FSR)
电源：3.2V 至 5.5V
上电复位为零量程
微功耗运行：5V 时为 160μA
具有施密特触发输入的低功耗串口
支持轨至轨运行的片上输出缓冲放大器
掉电能力
DAC8551-Q1 在 5V 电压下的功耗仅为 800µW，在掉
电模式下的功耗降至 4μW 以下。DAC8551-Q1 采用
VSSOP-8 封装。
二进制输入
SYNC 中断功能
表 1. 器件信息(1)
采用微型超薄小外形尺寸封装 (VSSOP)-8 封装
器件型号
封装
封装尺寸（标称值）
超薄小外形尺寸封装
(VSSOP) (8)
2 应用
DAC8551-Q1
3.00mm × 3.00mm
•
•
汽车雷达
车用传感器
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
DAC8551-Q1 功能框图
VDD
VFB
VREF
Ref (+)
VOUT
16-Bit DAC
16
DAC Register
16
SYNC
SCLK
DIN
Resistor
Network
Shift Register
PWD Control
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASEB8
DAC8551-Q1
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 14
7.5 Programming .......................................................... 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
8.3 System Examples .................................................. 19
Power Supply Recommendations...................... 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Timing Requirements............................................... 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 文档支持................................................................ 21
11.2 社区资源................................................................ 21
11.3 商标....................................................................... 21
11.4 静电放电警告......................................................... 21
11.5 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
Changes from Original (February 2016) to Revision A
Page
•
已将数据表从“产品预览”更改为“量产数据” ............................................................................................................................. 1
2
Copyright © 2016, Texas Instruments Incorporated
DAC8551-Q1
www.ti.com.cn
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
V
1
2
3
4
8
7
6
5
GND
DD
V
D
REF
IN
V
SCLK
SYNC
FB
V
OUT
Table 2. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-trigger logic input.
DIN
7
I
GND
8
6
GND Ground reference point for all circuitry on the device
SCLK
I
I
Serial clock input. Data can be transferred at rates up to 3 0MHz. Schmitt-trigger logic input.
Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC
going low enables the input shift register, and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which
case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8551-Q1).
Schmitt-trigger logic input.
SYNC
5
VDD
1
3
4
2
PWR Power supply input, 3.2 V to 5.5 V.
VFB
I
O
I
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Reference voltage input.
VOUT
VREF
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–65
MAX
6
UNIT
V
VDD to GND
Digital input voltage to GND
VOUT to GND
DIN, SCLK and SYNC
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
150
V
V
VREF to GND
V
VFB to GND
V
Junction temperature range, TJ max
Storage temperature, Tstg
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2016, Texas Instruments Incorporated
3
DAC8551-Q1
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 4, 5, and
8)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
3.2
0
NOM
MAX
UNIT
V
POWER SUPPLY
Supply voltage
VDD to GND
5.5
VDD
VDD
DIGITAL INPUTS
Digital input voltage
DIN, SCLK and SYNC
V
REFERENCE INPUT
VREF Reference input voltage
AMPLIFIER FEEDBACK INPUT
VFB Output amplifier feedback input
TEMPERATURE RANGE
0
V
VOUT
V
TA
Operating ambient temperature
–40
125
°C
6.4 Thermal Information
DAC8551-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
173.7
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94.2
65.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
10.2
ψJB
92.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VDD = 3.2 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
STATIC PERFORMANCE(1)
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
LSB
Relative accuracy
Differential nonlinearity
Offset error
±4
±0.35
±1
±16
±2
LSB
±15
±0.5
±0.2
mV
Full-scale error
±0.05
±0.02
±5
% of FSR
% of FSR
μV/°C
Gain error
Offset error drift
ppm of
FSR/°C
Gain temperature coefficient
±1
PSRR
Power-supply rejection ratio
RL = 2 kΩ, CL = 200 pF
0.75
mV/V
(1) Linearity calculated using a reduced code range of 485 to 64,741; output unloaded.
4
Copyright © 2016, Texas Instruments Incorporated
DAC8551-Q1
www.ti.com.cn
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
Electrical Characteristics (continued)
VDD = 3.2 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
OUTPUT CHARACTERISTICS(2)
Output voltage range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VREF
V
To ±0.003% FSR, 0200h to FD00h
RL = 2 kΩ, 0 pF < CL < 200 pF
Output voltage settling time
Slew rate
8
μs
1.4
470
1000
0.1
0.1
1
V/μs
pF
RL = ∞
Capacitive load stability
RL = 2 kΩ
pF
Code change glitch impulse
Digital feedthrough
1 LSB change around major carry
50 kΩ series resistance on digital lines
At mid-code input
nV-s
nV-s
Ω
DC output impedance
Short-circuit current
VDD = 3.2 V to 5.5 V
35
mA
AC PERFORMANCE
SNR
THD
Signal-to-noise ratio
84
–80
84
dB
dB
dB
dB
Total harmonic distortion
Spurious-free dynamic range
BW = 20 kHz, VDD = 5 V, VREF = 4.5 V, fOUT = 1 kHz
First 19 harmonics removed for SNR calculation
SFDR
SINAD Signal to noise and distortion
76
REFERENCE INPUT
VREF = VDD = 5.5 V
VREF = VDD = 3.6 V
50
25
Reference current
μA
Reference input range
Reference input impedance
LOGIC INPUTS(2)
0
VDD
V
125
±1
kΩ
Input current
μA
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
0.3×VDD
0.1×VDD
VIN
VIN
L
Input low voltage
V
0.7×VDD
0.9×VDD
H
Input high voltage
Pin capacitance
V
3
pF
POWER REQUIREMENTS
VDD
Supply voltage
3.2
5.5
V
Normal mode, input code = 32,768, no load, does not include
reference current. VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V
160
110
250
Normal mode, input code = 32,768, no load, does not include
reference current. VIH = VDD and VIL = GND,
VDD = 3.2 V to 3.6 V
240
IDD
Supply current
μA
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V
0.8
0.5
3
3
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3.2 V to 3.6 V
POWER EFFICIENCY
IOUT / IDD
ILOAD = 2 mA, VDD = 5 V
89%
TEMPERATURE RANGE
TA
Ambient temperature
–40
125
°C
(2) Specified by design and characterization; not production tested.
Copyright © 2016, Texas Instruments Incorporated
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DAC8551-Q1
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
6.6 Timing Requirements(1)(2)
VDD = 3.2 V to 5.5 V and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 5.5 V
25
30
fSCLK Serial clock frequency
MHz
40
34
13
13
22.5
13
0
t1
t2
t3
t4
t5
t6
t7
SCLK cycle time
SCLK high time
SCLK low time
ns
ns
ns
ns
ns
ns
ns
SYNC to SCLK rising edge setup time
Data setup time
0
5
5
5
Data hold time
5
0
24th SCLK falling edge to SYNC rising edge
0
50
34
50
t8
t9
Minimum SYNC high time
ns
ns
24th SCLK falling edge to SYNC falling edge
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See the Serial-Write-Operation Timing Diagram.
6.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Coming out of power-down mode,
VDD = 5 V
2.5
Power-up time
µs
Coming out of power-down mode,
VDD = 3.3 V
5
t9
t1
SCLK
SYNC
1
24
t8
t2
t3
t7
t4
t6
t5
DB23
DIN
DB0
DB23
Figure 1. Serial-Write-Operation Timing Diagram
6
Copyright © 2016, Texas Instruments Incorporated
DAC8551-Q1
www.ti.com.cn
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
6.8 Typical Characteristics
At TA = 25°C, VDD = 5 V unless otherwise noted.
6
6
4
VDD = 5V, VREF = 4.99V
VDD = 5V, VREF = 4.99V
4
2
2
0
0
-2
-4
-6
-2
-4
-6
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 2. Linearity Error and Differential Linearity Error vs
Digital Input Code (–40°C)
Figure 3. Linearity Error and Differential Linearity Error vs
Digital Input Code (25°C)
10
6
VDD = 5 V
VDD = 5V, VREF = 4.99V
4
2
VREF = 4.99 V
0
-2
-4
-6
5
1.0
0.5
0
0
-0.5
-1.0
-5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 4. Linearity Error and Differential Linearity Error vs
Digital Input Code (125°C)
Figure 5. Offset Error vs Temperature
0
6
5
4
3
2
1
0
VDD = 5 V
VREF = 4.99 V
DAC Loaded with FFFFh
-5
VDD = 5.5V
VREF = VDD - 10mV
DAC Loaded with 0000h
-10
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10
Temperature (°C)
I(SOURCE/SINK) (mA)
Figure 6. Full-Scale Error vs Temperature
Figure 7. Source and Sink Current Capability
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ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
300
250
200
150
100
50
VREF = VDD = 5 V
VDD = VREF = 5V
250
200
Reference Current Included
150
100
50
0
0
-50
-25
0
25
50
75
100
125
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Temperature (°C)
Figure 9. Power-Supply Current vs Temperature
Figure 8. Supply Current vs Digital Input Code
300
1
0.8
0.6
0.4
0.2
0
VREF = VDD
VREF = VDD
280
260
240
220
200
180
160
140
120
100
Reference Current Included, No Load
3.2
3.6
4
4.4
4.8
5.2
5.5
3.2
3.6
4
4.4
4.8
5.2
5.5
VDD (V)
VDD (V)
Figure 10. Supply Current vs Supply Voltage
Figure 11. Power-Down Current vs Supply Voltage
1800
1600
1400
1200
1000
800
TA = 25°C, SCL Input (all other inputs = GND)
Trigger Pulse 5V/div
VDD = VREF = 5.5V
VDD = 5V
VREF = 4.096V
From Code: D000
600
To Code: FFFF
400
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
200
0
Time (2ms/div)
0
1
2
3
4
5
VLOGIC (V)
Figure 13. Full-Scale Settling Time: 5-V Rising Edge
Figure 12. Supply Current vs Logic Input Voltage
8
Copyright © 2016, Texas Instruments Incorporated
DAC8551-Q1
www.ti.com.cn
ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Rising
Edge
1V/div
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 14. Full-Scale Settling Time: 5-V Falling Edge
Figure 15. Half-Scale Settling Time: 5-V Rising Edge
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
Figure 16. Half-Scale Settling Time: 5-V Falling Edge
Figure 17. Glitch Impulse: 5 V, 1-LSB Step, Rising Edge
VDD = 5V
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 18. Glitch Impulse: 5 V, 1-LSB Step, Falling Edge
Figure 19. Glitch Impulse: 5 V, 16-LSB Step, Rising Edge
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 20. Glitch Impulse: 5 V, 16-LSB Step, Falling Edge
Figure 21. Glitch Impulse: 5 V, 256-LSB Step, Rising Edge
-40
VDD = 5V
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
VREF = 4.9V
-50
-1dB FSR Digital Input
fS = 1MSPS
-60
-70
Measurement Bandwidth = 20kHz
THD
Glitch: Not Detected
Theoretical Worst Case
-80
-90
2nd Harmonic
1
3rd Harmonic
-100
Time (400ns/div)
0
2
3
4
5
fOUT (kHz)
Figure 22. Glitch Impulse: 5 V, 256-LSB Step, Falling Edge
Figure 23. Total Harmonic Distortion vs Output Frequency
98
VREF = VDD = 5V
VDD = 5V
-10
-30
-1dB FSR Digital Input
VREF = 4.096V
fOUT = 1kHz
96
fS = 1MSPS
Measurement Bandwidth = 20kHz
94
f
= 1MSPS
CLK
-50
92
90
88
86
84
-70
-90
-110
-130
0
5
10
15
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5
fOUT (kHz)
Frequency (kHz)
Figure 25. Power Spectral Density
Figure 24. Signal-to-Noise Ratio vs Output Frequency
10
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DAC8551-Q1
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ZHCSEV4A –FEBRUARY 2016–REVISED MARCH 2016
Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
350
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
300
250
200
150
100
100
1k
10k
100k
Frequency (Hz)
Figure 26. Output Noise Density
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7 Detailed Description
7.1 Overview
The DAC8551-Q1 is a small, low-power, voltage-output, 16-bit digital-to-analog converters (DACs) qualified for
automotive applications. The DAC8551-Q1 provides good linearity, and minimizes undesired code-to-code
transient voltages. The DAC8551-Q1 devices use a versatile 3-wire serial interface that operates at clock rates to
30 MHz and is compatible with standard SPI, QSPI, Microwire, and digital signal processor (DSP) interfaces.
The DAC8551-Q1 requires an external reference voltage to set its output range. The DAC8551-Q1 incorporates
a power-on-reset circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the
device takes place. The DAC8551-Q1 contain a power-down feature, accessed over the serial interface, that
reduces the current consumption of the device to 800 nA at 5 V.
The DAC8551-Q1 power consumption is only 800 µW at 5 V, reducing to less than 4 μW in power-down mode.
The DAC8551-Q1 is available in a VSSOP-8 package.
7.2 Functional Block Diagram
VFB
VREF
Ref (+)
16-Bit DAC
16
VOUT
GND
VDD
DAC Register
16
SYNC
SCLK
DIN
Resistor
Network
Shift Register
PWD Control
7.3 Feature Description
7.3.1 DAC Section
The DAC8551-Q1 architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a
block diagram of the DAC architecture.
VREF
50kW
50kW
VFB
62kW
REF (+)
VOUT
DAC
Register
Register String
REF (-)
GND
Figure 27. DAC8551-Q1 Architecture
The input coding to the DAC8551-Q1 device is straight binary, so the ideal output voltage is given by:
DIN
65536
VOUT
+
VREF
(1)
where DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65
535.
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Feature Description (continued)
7.3.1.1 Resistor String
The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. Monotonicity is ensured
because of the string resistor architecture.
7.3.1.2 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of
0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink
capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.4 V/μs with a full-
scale setting time of 8 μs with the output unloaded.
The inverting input of the output amplifier is brought out to the VFB pin. This configuration allows for better
accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected between these points for specific applications.
VREF
RDIVIDER
VREF
2
R
To Output Amplifier
(2x Gain)
R
R
R
Figure 28. Resistor String
7.3.2 Power-On Reset
The DAC8551-Q1 contains a power-on-reset circuit that controls the output voltage during power up. On power
up, the DAC registers are filled with zeros and the output voltages are 0 V; they remain that way until a valid
write sequence is made to the DAC. The power-on reset is useful in applications where it is important to know
the state of the output of the DAC while it is in the process of powering up.
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7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC8551-Q1 supports four separate modes of operation. These modes are programmable by setting two
bits (PD1 and PD0) in the control register. Table 3 shows how the state of the bits corresponds to the mode of
operation of the device.
Table 3. Operating Modes
PD1 (DB17)
PD0 (DB16)
OPERATING MODE
0
—
0
0
—
1
Normal operation
Power-down modes
Output typically 1 kΩ to GND
Output typically 100 kΩ to GND
High-Z
1
0
1
1
When both bits are set to 0, the device works normally with its typical current consumption of 160 μA at 5 V.
However, for the three power-down modes, the supply current falls to 800 nA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of
known values. This configuration has the advantage that the output impedance of the device is known while it is
in power-down mode. There are three different options. The output is connected internally to GND through a 1
kΩ resistor, a 100 kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated in Figure 29.
VFB
Amplifier
VOUT
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
Figure 29. Output Stage During Power Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power down. The time to exit power-down is typically 2.5 μs for VDD = 5 V, and
5 μs for VDD = 3.3 V. See the Typical Characteristics for more information.
14
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7.5 Programming
The DAC8551-Q1 has a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs. See the Serial Write Operation Timing Diagram section for
an example of a typical write sequence.
The input shift register is 24 bits wide, as shown in Figure 30. The first six bits are don't care bits. The next two
bits (PD1 andPD0) are control bits that control which mode of operation the part is in (normal mode or any one of
three power-down modes). A more complete description of the various modes is located in the Power-Down
Modes section. The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th
falling edge of SCLK.
DB23
DB0
X
X
X
X
X
X
PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 30. DAC8551-Q1 Data-Input Register Format
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8551-Q1 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change
in the mode of operation).
At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought high again just before the next write sequence.
7.5.1 SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 31.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 31. SYNC Interrupt Facility
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Applications
8.2.1 Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116
V+
XTR116
VREG
V+
Regulator
C2 || C3
0.1001 µF
Vref
Reference
C1
2.2 µF
U1
R1
102.4 kΩ
V+
Vref
R2
49.9 W
V+
IIN
VOUT
DAC8551-Q1
+
B
U2
Q1
R3
25.6 kΩ
Q1
RLIM
E
IRET
2475 Ω
25 Ω
Return
IO
Figure 32. Loop-Powered Transmitter
8.2.1.1 Design Requirements
This design is commonly referred to as a loop-powered, or 2-wire, 4 mA to 20 mA transmitter. The transmitter
has only two external input terminals: a supply connection and an output, or return, connection. The transmitter
communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its
return current. In order to conform to the 4 mA to 20 mA communication standard, the complete transmitter must
consume less than 4 mA of current. The DAC8551-Q1 enables the accurate control of the loop current from 4
mA to 20 mA in 16-bit steps.
8.2.1.2 Detailed Design Procedure
Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides
simplicity and improved performance due to the matched internal resistors. The output current can be modified if
necessary by looking using Equation 2.
æ
ç
ö
÷
VREG
R1
V
´ Code
2N ´R3
æ
ö
÷
ø
2475 W
25 W
ref
IOUT (Code) =
+
´ 1+
ç
ç
÷
è
è
ø
(2)
For more details of this application, see 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design
(TIDUAO7). It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.
16
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Typical Applications (continued)
8.2.1.3 Application Curves
Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 33. The
linearity of the output or INL is in Figure 34.
10
8
0.1
0.05
0
6
4
2
0
-2
-4
-6
-8
-10
-0.05
-0.1
0
10k
20k
30k
Code
40k
50k
60k 65535
0
10k
20k
30k
Code
40k
50k
60k 65535
D001
D002
Figure 33. Total Unadjusted Error
Figure 34. Integral Nonlineareity
8.2.2 Bipolar Operation Using the DAC8551-Q1
The DAC8551-Q1 has been designed for single-supply operation, but a bipolar output range is also possible
using the circuit in Figure 35. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at
the amplifier output is achievable using an OPA703 as the output amplifier.
VREF
6 V
R1
10 kW
R2
10 kW
OPA703
–6 V
5 V
VFB
DAC8551-Q1
VREF
VOUT
10 mF
0.1 mF
Three-Wire
Serial Interface
Figure 35. Bipolar Output Range
The output voltage for any input code can be calculated as follows:
R1 ) R2
R2
R1
D
65536
ǒ Ǔ
ǒ Ǔ ǒ Ǔ
VO +
ƪ
VREF
* VREF
ƫ
R1
(3)
(4)
where D represents the input code in decimal (0–65 535)
with VREF = 5V, R1 = R2 = 10 kΩ.
10 D
ǒ Ǔ* 5V
VO +
65536
Using this example, an output voltage range of ±5 V with 0000h corresponding to a –5 V output and FFFFh
corresponding to a 5 V output can be achieved. Similarly, using VREF = 2.5 V, a ±2.5 V output voltage range can
be achieved.
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8.2.3 Using the REF02 As a Power Supply for the DAC8551-Q1
Due to the extremely low supply current required by the DAC8551-Q1, an alternative option is to use a precision
reference such as the REF02 device to supply the required voltage to the device, as illustrated in Figure 36.
15 V
5 V
REF02
285 mA
SYNC
Three-Wire
VOUT = 0 V to 5 V
Serial
Interface
DAC8551-Q1
SCLK
DIN
Figure 36. REF02 As a Power Supply to the DAC8551-Q1
This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at
some value other than 5 V. The REF02 device outputs a steady supply voltage for the DAC8551-Q1. If the
REF02 device is used, the current it must supply to the DAC8551-Q1 is 200 μA. This configuration is with no
load on the output of the DAC. When a DAC output is loaded, the REF02 also must supply the current to the
load.
The total current required (with a 5 kΩ load on the DAC output) is:
5V
5kW
200mA )
+ 1.2mA
(5)
The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2 mA current
drawn from it. This value corresponds to a 3.9 LSB error.
18
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8.3 System Examples
8.3.1 Interface from DAC8551-Q1 to 8051
See Figure 37 for a serial interface between the DAC8551-Q1 and a typical 8051-type microcontroller. The setup
for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8551-Q1, while RXD drives the serial
data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this
case, port line P3.3 is used. When data are to be transmitted to the DAC8551-Q1, P3.3 is taken low. The 8051
transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the
serial data in a format that has the LSB first. The DAC8551-Q1 requires data with the MSB as the first bit
received. The 8051 transmit routine must therefore take this into account, and mirror the data as needed.
80C51 or 80L51(1)
P3.3
DAC8551-Q1(1)
SYNC
TXD
RXD
SCLK
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 37. Interface from DAC8551-Q1 Devices to 80C51 or 80L51
8.3.2 Interface from DAC8551-Q1 to Microwire
Figure 38 shows an interface between the DAC8551-Q1 and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and is clocked into the DAC8551-Q1 on the rising edge of the
SK signal.
MicrowireTM
DAC8551-Q1(1)
SYNC
CS
SCLK
DIN
SK
SO
NOTE: (1) Additional pins omitted for clarity.
Figure 38. Interface from DAC8551-Q1 Devices to Microwire
8.3.3 Interface from DAC8551-Q1 to 68HC11
Figure 39 shows a serial interface between the DAC8551-Q1 and the 68HC11 microcontroller. SCK of the
68HC11 drives the SCLK of the DAC8551-Q1, whereas the MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
68HC11(1)
PC7
DAC8551-Q1(1)
SYNC
SCK
SCLK
DIN
MOSI
NOTE: (1) Additional pins omitted for clarity.
Figure 39. Interface from DAC8551-Q1 Devices to 68HC11
The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes
data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to
the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to
the DAC88551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken high at the end of this procedure.
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9 Power Supply Recommendations
The DAC8551-Q1 can operate within the specified supply voltage range of 3.2 V to 5.5 V. The power applied to
VDD should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high-
frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. In order to further minimize noise from the power supply, a strong
recommendation is to include a 1 μF to 10 μF capacitor and 0.1 μF bypass capacitor. The current consumption
on the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical
Characteristics table. The power supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DAC8551-Q1 offers single-supply operation, and are often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DAC8551-Q1, all return currents, including digital and analog return currents
for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground
plane. This plane would be separate from the ground connection for the digital components until they were
connected at the power-entry point of the system.
As with the GND connection, VDD should be connected to a power-supply plane or trace that is separate from the
connection for digital logic until they are connected at the power-entry point. In addition, a 1 μF to 10 μF
capacitor and 0.1 μF bypass capacitor are strongly recommended. In some situations, additional bypassing may
be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise.
10.2 Layout Example
1
2
3
4
8
7
6
5
Figure 40. Layout Diagram
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
《通过 EMC/EMI 测试的双线制 4mA-20mA 发送器参考设计》（文献编号：TIDUAO7）
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。本数据随时可能发生变更并
且不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DAC6551AQDGKRQ1
DAC8551AQDGKRQ1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
D61Q
D81Q
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC6551AQDGKRQ1
DAC8551AQDGKRQ1
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DAC6551AQDGKRQ1
DAC8551AQDGKRQ1
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
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