DAC8802 [TI]
Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter; 双通道，串行输入14位乘法数位类比转换器
| 型号： | DAC8802 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter |
| 文件： | 总18页 (文件大小：1883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC8802
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
Relative Accuracy: 1 LSB Max
Differential Nonlinearity: 1 LSB Max
2-mA Full-Scale Current ±20%,
with VREF = ±10 V
0.5 µs Settling Time
Midscale or Zero-Scale Reset
Separate 4Q Multiplying Reference Inputs
Reference Bandwidth: 10 MHz
Reference Dynamics: –105 dB THD
SPI™-Compatible 3-Wire Interface:
50 MHz
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power-On Reset
The DAC8802 is
digital-to-analog converter (DAC) designed to operate
from a single +2.7 V to 5.5 V supply.
a dual, 14-bit, current-output
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature tracking
for the full-scale output when combined with an
external I-to-V precision amplifier.
•
•
•
•
•
•
A
doubled-buffered, serial data interface offers
high-speed, 3-wire, SPI and microcontroller
compatible inputs using serial data in (SDI), clock
(CLK), and
a
chip-select (CS).
A
common
•
•
•
•
level-sensitive load DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from
previously loaded input registers. Additionally, an
internal power-on reset forces the output voltage to
zero at system turn-on. An MSB pin allows system
reset assertion (RS) to force all registers to zero code
when MSB = 0, or to half-scale code when MSB = 1.
Industry-Standard Pin Configuration
APPLICATIONS
•
•
•
Automatic Test Equipment
Instrumentation
The DAC8802 is available in an TSSOP-16 package.
Digitally Controlled Calibration
V
REF
A B
D0
D1
D2
D3
R
A
FB
14
Input
DAC A
D4
D5
I
A
DAC A
OUT
Register
Register
R
R
D6
A
GND
A
D7
D8
D9
D10
D11
D12
D13
A0
R
B
FB
Input
DAC B
DAC B
I
B
OUT
SDI
Register
R
Register
R
A1
A
GND
B
CS
CLK
EN
A
DAC
Power-On
Reset
B
Decode
DGND
RS
MSB
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
PRODUCT
DAC8802IPW
Tubes, 90
DAC8802
±1
±1
–40°C to +85°C
TSSOP-16
PW
DAC8802IPWR
Tape and Reel, 2500
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or
see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
DAC8802
–0.3 to +8
–18 to +18
– 0.3 to + 8
– 0.3 to VDD + 0.3
–0.3 to +0.3
±50
UNIT
V
VDD to GND
VREF to GND
V
Logic inputs and output to GND
V(IOUT) to GND
V
V
AGNDX to DGND
V
Input current to any pin except supplies
Package power dissipation
Thermal resistance, θJA
Maximum junction temperature (TJmax)
Operating temperature range
Storage temperature range
mA
W
(TJmax – TA)/θJA
100
°C/W
°C
°C
°C
150
– 40 to +85
– 65 to + 150
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
2
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS(1)
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
STATIC PERFORMANCE(2)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
14
±1
±1
10
20
±4
Bits
LSB
LSB
nA
Relative accuracy
INL
DNL
Differential nonlinearity
Data = 0000h, TA = 25°C
Data = 0000h, TA = TA max
Data = 3FFFh
Output leakage current
IOUT
X
nA
Full-scale gain error
Full-scale tempco(3)
Feedback resistor
GFSE
±0.75
mV
TCVFS
1
5
ppm/°C
kΩ
RFB
X
VDD = 5 V
REFERENCE INPUT
VREFX Range
VREF
RREF
RREF
CREF
X
X
X
X
–15
4
15
6
V
Input resistance
5
1
5
kΩ
%
Input resistance match
Input capacitance(3)
ANALOG OUTPUT
Output current
Channel-to-channel
pF
IOUT
X
X
Data = 3FFFh
1.6
2.5
mA
pF
Output capacitance(3)
COUT
Code-dependent
50
LOGIC INPUTS AND OUTPUT
VDD = +2.7 V
VDD = +5 V
VDD = +2.7 V
VDD = +5 V
0.6
0.8
V
V
Input low voltage
Input high voltage
VIL
VIH
2.1
2.4
V
V
Input leakage current
Input capacitance(3)
Logic output low voltage
IIL
CIL
1
10
µA
pF
V
VOL
VOH
IOL = 1.6 mA
0.4
Logic output high voltage
IOH = 100 µA
4
V
(4)
INTERFACE TIMING(3)
,
Clock width high
tCH
tCL
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock width low
CS to Clock setup
Clock to CS hold
tCSS
tCSH
tPD
25
2
Clock to SDO prop delay
Load DAC pulsewidth
Data setup
20
tLDAC
tDS
25
20
20
5
Data hold
tDH
Load setup
tLDS
tLDH
Load hold
25
(1) Specifications subject to change without notice.
(2) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter
amplifier. The DAC8802 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at +25°C.
(3) These parameters are specified by design and not subject to production testing.
(4) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
SUPPLY CHARACTERISTICS
Power supply range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
VDD RANGE
IDD
2.7
5.5
5
V
µA
µA
mW
%
Logic inputs = 0 V, VDD = +4.5 V to +5.5 V
Logic inputs = 0 V, VDD = +2.7 V to +3.6 V
Logic inputs = 0 V
2
1
Positive supply current
2.5
Power dissipation
PDISS
PSS
0.0275
0.006
Power supply sensitivity
AC CHARACTERISTICS(5)
∆VDD = ±5%
To ±0.1% of full-scale,
Data = 0000h to 3FFFh to 0000h
µs
µs
0.3
0.5
Output voltage settling time
ts
To ±0.006% of full-scale,
Data = 0000h to 3FFFh to 0000h
Reference multiplying BW
DAC glitch impulse
BW –3 dB VREFX = 100 mVRMS, Data = 3FFFh, CFB = 3 pF
10
5
MHz
nV/s
dB
Q
VREFX = 10 V, Data = 1FFFh to 2000h to 1FFFh
Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz
Feedthrough error
VOUTX/VREF
X
–70
Data = 0000h, VREFB = 100 mVRMS
Adjacent channel, f = 100 kHz
,
dB
Crosstalk error
VOUTA/VREF
B
–100
Digital feedthrough
Q
THD
en
CS = 1 and fCLK = 1 MHz
1
–105
12
nV/s
dB
Total harmonic distortion
Output spot noise voltage
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
f = 1 kHz, BW = 1 Hz
nV/√Hz
(5) All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.
PARAMETER MEASUREMENT INFORMATION
SDI
A1
A0
D13 D12 D11 D10
D1 D0
CLK
Input REG. LD
t
t
csh
CSS
t
ds
t
t
ch
t
cl
dh
CS
t
lds
t
LDAC
LDH
t
LDAC
Figure 1. DAC8802 Timing Diagram
4
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
PIN CONFIGURATIONS
DAC8802
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RFB
VREF
IOUT
A
A
A
CLK
LDAC
MSB
VDD
DGND
CS
AGND
AGND
IOUT
A
B
B
B
B
VREF
RFB
RS
SDI
PIN DESCRIPTION
PIN
NAME
RFB
DESCRIPTION
1
A
Establish voltage output for DAC A by connecting to external amplifier output.
DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage.
Can be tied to VDD pin.
2
VREF
A
3
4
5
6
IOUT
A
DAC A Current output.
DAC A Analog ground.
DAC B Analog ground.
DAC B Current output.
AGND
A
B
AGND
IOUT
B
DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage.
Can be tied to VDD pin.
7
VREF
B
8
9
RFB
B
Establish voltage output for DAC B by connecting to external amplifier output.
Serial data input; data loads directly into the shift register.
SDI
Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.
Register data = 0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for
DAC8802.
10
RS
Chip-select; active low input. Disables shift register loading when high. Transfers serial
register data to input register when CS/LDAC goes high. Does not affect LDAC operation.
11
CS
12
13
DGND
VDD
Digital ground.
Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system
power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB
14
MSB
pin can be permanently tied to ground or VDD
.
Load DAC register strobe; level sensitive active low. Transfers all input register data to
the DAC registers. Asynchronous active low input. See Table 2 for operation.
15
16
LDAC
CLK
Clock input. Positive edge clocks data into shift register.
5
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
T
A
= +25°C
T
T
T
= +25°C
A
A
A
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 2.
Figure 3.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
T
A
= -40°C
= -40°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 4.
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
T
A
= +85°C
= +85°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 6.
Figure 7.
6
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
T
T
T
= +25°C
T
T
T
= +25°C
A
A
A
A
A
A
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 8.
Figure 9.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= -40°C
= -40°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 10.
Figure 11.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= +85°C
= +85°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 12.
Figure 13.
7
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
180
6
0
-6
160
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
V
= +5.0V
DD
140
120
100
80
60
40
V
= +2.7V
DD
20
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10
100
1k
10k
100k
1M
10M
100M
Logic Input Voltage (V)
Bandwidth (Hz)
Figure 14.
Figure 15.
DAC GLITCH
DAC SETTLING TIME
Voltage Output Settling
Code: 1FFFh to 2000h
LDAC Pulse
Trigger Pulse
Time (0.2ms/div)
Time (0.1ms/div)
Figure 16.
Figure 17.
8
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
T
T
T
= +25°C
T
T
T
= +25°C
A
A
A
A
A
A
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 18.
Figure 19.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= -40°C
= -40°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 20.
Figure 21.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= +85°C
= +85°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 22.
Figure 23.
9
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
T
T
T
= +25°C
T
T
T
= +25°C
A
A
A
A
A
A
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
0
0
0
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 24.
Figure 25.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= -40°C
= -40°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 26.
Figure 27.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
= +85°C
= +85°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2048 4096 6144 8192 10240 12288 14336 16383
2048 4096 6144 8192 10240 12288 14336 16383
Code
Code
Figure 28.
Figure 29.
10
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
THEORY OF OPERATION
CIRCUIT OPERATION
The DAC8802 contains two 14-bit, current-output, digital-to-analog converters (DACs). Each DAC has its own
independent multiplying reference input. The DAC8802 uses a 3-wire, SPI-compatible serial data interface, with a
configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC
strobe enables two-channel simultaneous updates for hardware-synchronized output voltage changes.
Digital-to-Analog Converters
The DAC8802 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC. Each
DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is
connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the
external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full
14-bit accuracy.
V
DD
R
R
R
V
X
REF
R X
FB
2R
2R
2R
R
5 kΩ
S2
S1
I X
OUT
A X
GND
DGND
Digital interface connections are omitted for clarity.
Switches S1 and S2 are closed; V must be powered.
DD
Figure 30. Typical Equivalent DAC Channel
The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only
used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to
VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D)
according to Equation 1:
D
16384
VOUT + *VREF
(1)
Note that the output polarity is opposite of the VREF polarity for dc reference voltages.
The DAC is also designed to accommodate ac reference input signals. The DAC8802 accommodates input
reference voltages in the range of -15 V to +15 V. The reference voltage inputs exhibit a constant nominal input
resistance of 5 kΩ, ±20%. On the other hand, DAC outputs IOUTA and B are code-dependent and produce
various output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8802
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor
(CFB) may be needed to provide a critically damped output response for step changes in reference input
voltages.
11
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF external
feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,
a clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is
best to derive the DAC8802 5-V supply from the system analog supply voltages (do not use the digital 5-V
supply); see Figure 31.
15 V
Analog
Power
2R
Supply
5 V
+
R
V
DD
R
R
R
R X
FB
V
X
REF
2R
2R
2R
R
Ω
5 k
15 V
S2
S1
I X
OUT
V
CC
V
OUT
A1
+
A X
GND
V
EE
Load
DGND
DGND
Digital interface connections are omitted for clarity.
Switches S1 and S2 are closed; V must be powered.
DD
Figure 31. Recommended Kelvin-Sensed Hookup
V
REF
A B
CS
EN
V
DD
CLK
R
A
FB
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
14
Input
DAC A
I
A
DAC A
OUT
R
Register
Register
R
A
A
GND
R
B
FB
D10
D11
D12
D13
A0
Input
DAC B
I
B
DAC B
OUT
Register
Register
R
R
DAC
A
A
B
GND
B
Decode
A1
Set
MSB
Set
MSB
Power-On
Reset
DGND
MSB
LDAC
RS
Figure 32. System Level Digital Interfacing
12
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
SERIAL DATA INTERFACE
The DAC8802 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8802 is
clocked into the serial input register in an 16-bit data-word format. MSB bits are loaded first. Table 1 defines the
16 data-word bits for the DAC8802.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing specifications of the Electrical
Characteristics. Data can only be clocked in while the CS chip select pin is active low. For the DAC8802, only
the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the
DAC8802. Keeping the CS line low between the first and second byte transfer will result in a successful serial
register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8802,
Table 1, Table 2, Table 3, and Figure 1 define the characteristics of the software serial interface.
Table 1. Serial Input Register Data Format, Data Loaded MSB First(1)
Bit
B15
A1
B14
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0 (LSB)
D0
Data
(1) Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to
logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8802 shift register are ignored; only the
last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 2. Control Logic Truth Table(1)
CS
H
L
CLK
X
LDAC
H
RS
H
H
H
H
H
H
H
H
L
MSB
X
SERIAL SHIFT REGISTER
No effect
INPUT REGISTER
DAC REGISTER
Latched
Latched
Latched
Latched
Latched
L
H
X
No effect
Latched
Latched
Latched
L
↑+
H
H
X
Shift register data advanced one bit
L
H
X
No effect
No effect
No effect
No effect
No effect
No effect
No effect
↑+
H
H
H
H
H
L
H
X
Selected DAC updated with current SR contents Latched
X
L
X
Latched
Transparent
X
H
X
Latched
Latched
X
↑+
H
X
Latched
Latched
X
0
Latched data = 0000h
Latched data = 2000h
Latched data = 0000h
Latched data = 2000h
X
H
L
H
(1) ↑+ = Positive logic transition; X = Do not care
Table 3. Address Decode
A1
0
A0
0
DAC DECODE
None
0
1
DAC A
1
0
DAC B
1
1
DAC A and DAC B
13
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
Figure 33 shows the equivalent logic interface for the key digital control pins for the DAC8802.
To Input Register
A
Address
Decoder
CS
B
EN
Shift Register
CLK
SDI
Figure 33. DAC8802 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
POWER ON RESET
When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth
positive ramp without drooping, in order to have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The DAC register data stays at the zero or half-scale setting until a valid serial register data load takes
place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD, as
shown in Figure 34.
V
DD
250 W
DIGITAL
INPUTS
DGND
Figure 34. Equivalent ESD Protection Circuits
PCB LAYOUT
The DAC8802 is a high-accuracy DAC that can have its performance compromised by grounding and printed
circuit board (PCB) lead trace resistance. The 14-bit DAC8802 with a 10-V full-scale range has an LSB value of
610 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as
2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 mΩ will cause 1 LSB of
voltage drop. The preferred PCB layout for the DAC8802 is to have all AGNDX pins connected directly to an
analog ground plane at the unit. The noninverting input of each channel I/V converter should also either connect
directly to the analog ground plane or have an individual sense trace back to the AGNDX pin connection. The
feedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR drops from
contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8802.
14
DAC8802
www.ti.com
SBAS351A–AUGUST 2005–REVISED DECEMBER 2005
APPLICATION INFORMATION
The DAC8802, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 35.
An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1
and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented
by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation
(Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = -10 V to VOUT = 10 V.
D
8192
+ ǒ
Ǔ
VOUT
* 1 VREF
(2)
10 kΩ
10 kΩ
10 V
5 kΩ
OPA277
V
OUT
V
REF
-
10 V < V
< +10V
OUT
V
DD
V
REF
X
R
X
FB
I
X
OUT
One Channel
DAC8802
OPA277
AGND
X
Digital interface connections omitted for clarity.
Figure 35. Four-Quadrant Multiplying Application Circuit
Cross-Reference
The DAC8802 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIED
INL
(LSB)
DNL
(LSB)
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS-REFERENCE
PRODUCT
PART NUMBER
16-Lead Thin Shrink
Small-Outline Package
DAC8802IPW
±1
±1
-40°C to +85°C
TSSOP-16
AD5555CRU
15
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2006
PACKAGING INFORMATION
Orderable Device
DAC8802IPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DAC8802IPWG4
DAC8802IPWR
DAC8802IPWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
DAC8803IDBTG4
14-Bit, Quad Channel, Serial Interface, Multiplying Digital-to-Analog Converter 28-SSOP -40 to 85
TI
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