DAC8803IDBT_技术文档

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

FEATURES

DESCRIPTION

•

Relative Accuracy: 1 LSB Max

The DAC8803 is a quad, 14-bit, current-output digi-

tal-to-analog converter (DAC) designed to operate

from a single 2.7 V to 5-V supply.

Differential Nonlinearity: 1 LSB Max

2-mA Full-Scale Current ±20%,

With V_REF= ±10 V

0.5-µs Settling Time

Midscale or Zero-Scale Reset

The applied external reference input voltage V_REF

determines the full-scale output current. An internal

feedback resistor (R_FB) provides temperature tracking

for the full-scale output when combined with an

external I-to-V precision amplifier.

•

Four Separate 4-Quadrant Multiplying

Reference Inputs

A

doubled buffered serial data interface offers

•

Reference Bandwidth: 10 MHz

Reference Dynamics: -105 dB THD

50-MHz SPI™-Compatible 3-Wire Interface

Double Buffered Registers Enable

Simultaneous Multichannel Update

Internal Power On Reset

high-speed, 3-wire, SPI and microcontroller compat-

ible inputs using serial data in (SDI), clock (CLK), and

a chip select (CS). In addition, a serial data out pin

(SDO) allows for daisy chaining when multiple pack-

ages are used. A common level-sensitive load DAC

strobe (LDAC) input allows simultaneous update of all

DAC outputs from previously loaded input registers.

Additionally, an internal power on reset forces the

output voltage to zero at system turn on. An MSB pin

allows system reset assertion (RS) to force all regis-

ters to zero code when MSB = 0, or to half-scale

code when MSB = 1.

Compact SSOP-28 Package

Industry-Standard Pin Configuration

APPLICATIONS

•

Automatic Test Equipment

Instrumentation

The DAC8803 is packaged in a SSOP package.

Digitally Controlled Calibration

A

B C D

V

REF

D0

D1

R A

FB

SDO

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

A0

Input

Register

DAC A

Register

DAC A

DAC B

DAC C

DAC D

I

A

OUT

R

A

GND

R

B

FB

Input

Register

DAC B

Register

16

I

C

OUT

A

B

GND

R

C

FB

A1

Input

Register

DAC C

Register

I

C

OUT

SDI

CS

A

C

GND

R

D

FB

CLK

EN

Input

Register

DAC D

Register

I

D

OUT

R

A

DAC

B

C

D

A

D

GND

2:4

Power-on

Reset

A

F

GND

Decode

DGND

RS

MSB

LDAC

V

SS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the forma-

tive or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the

right to change or discontinue these products without notice.

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MINIMUM

DIFFERENTIAL

NONLINEARITY

(LSB)

SPECIFIED

TEMPERATURE

RANGE

TRANSPORT

MEDIA

QUANTITY

RELATIVE

ACCURACY

(LSB)

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

ORDERING

NUMBER

PRODUCT

DAC8803IDBT

DAC8803IDBR

Tape and Reel, 250

Tape and Reel, 2500

DAC8803

±1

-40°C to +85°C

SSOP-28

DB

(1) For the most current specifications and package information, see the Package Option Addendum at the end of this document, or see the

TI website at www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

DAC8803

-0.3 to +8

-0.3 to -7

-18 to +18

-0.3 to +8

-0.3 to V_DD+ 0.3

-0.3 to +0.3

±50

UNIT

V

V_DDto GND

V_SSto GND

V

V_REFto GND

V

Logic inputs and output to GND

V(I_OUT) to GND

V

A_GNDX to DGND

V

Input current to any pin except supplies

Package power dissipation

mA

(T_Jmax - T_A)/θ_JA

100

Thermal resistance, θ_JA

28-Lead shrink surface-mount (RS-28)

°C/W

°C

Maximum junction temperature (T_Jmax)

Operating temperature range, Model A

Storage temperature range

150

-40 to +85

-65 to +150

215

°C

Lead temperature

RS-28 (Vapor phase 60s)

RS-28 (Infrared 15s)

°C

220

°C

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.

2

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS⁽¹⁾

V_DD= 5 V ± 10%; V_SS= 0 V, I_OUTX = Virtual GND, A_GNDX = 0 V, V_REFA, B, C, D = 10 V, T_A= full operating temperature range,

unless otherwise noted.

DAC8803

PARAMETER

STATIC PERFORMANCE⁽²⁾

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

14

±1

10

20

±3

Bits

LSB

nA

Relative accuracy

Differential nonlinearity

Output leakage current

DNL

I_OUT

X

Data = 0000h, T_A= 25°C

Data = 0000h, T_A= T_Amax

Data = FFFFh

nA

Full-scale gain error

Full-scale tempco⁽³⁾

Feedback resistor

REFERENCE INPUT

V_REFX Range

G_FSE

±0.75

1

mV

TCV_FS

ppm/°C

kΩ

R_FB

X

V_DD= 5 V

V_REF

R_REF

C_REF

X

-15

4

15

8

V

Input resistance

6

1

5

kΩ

%

Input resistance match

Input capacitance⁽³⁾

ANALOG OUTPUT

Output current

Output capacitance⁽³⁾

LOGIC INPUTS AND OUTPUT

Input low voltage

Channel-to-channel

pF

I_OUT

X

Data = FFFFh

1.25

2.5

mA

pF

C_OUT

Code-dependent

80

V_IL

V_DD= +2.7 V

V_DD= +5 V

V_DD= +2.7 V

V_DD= +5 V

0.6

0.8

V

Input high voltage

V_IH

I_IL

2.1

2.4

V

Input leakage current

Input capacitance⁽³⁾

Logic output low voltage

1

10

µA

pF

V

C_IL

V_OL

V_OH

I_OL= 1.6 mA

I_OH= 100 µA

0.4

Logic output high voltage

4

V

(4)

INTERFACE TIMING⁽³⁾

,

Clock width high

t_CH

t_CL

25

0

ns

Clock width low

CS to Clock setup

Clock to CS hold

t_CSS

t_CSH

t_PD

25

2

Clock to SDO prop delay

Load DAC pulsewidth

Data setup

20

t_LDAC

t_DS

25

20

5

Data hold

t_DH

Load setup

t_LDS

t_LDH

Load hold

25

SUPPLY CHARACTERISTICS

Power supply range

Positive supply current

V_{DD RANGE}

I_DD

2.7

5.5

5

V

Logic inputs = 0 V

2

µA

(1) Specifications subject to change without notice.

(2) All static performance tests (except I_OUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter

amplifier. The DAC8803 R_FBterminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.

(3) These parameters are specified by design and not subject to production testing.

(4) All input control signals are specified with t_R= t_F= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

3

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

V_DD= 5 V ± 10%; V_SS= 0 V, I_OUTX = Virtual GND, A_GNDX = 0 V, V_REFA, B, C, D = 10 V, T_A= full operating temperature range,

unless otherwise noted.

DAC8803

PARAMETER

SYMBOL

I_DD

I_SS

CONDITIONS

V_DD= +4.5 V to +5.5 V

V_DD= +2.7 V to +3.6 V

Logic inputs = 0 V, V_SS= -5 V

Logic inputs = 0 V

MIN

TYP

2

MAX

5

UNIT

µA

1

2.5

µA

Negative supply current

Power dissipation

0.001

1

µA

P_DISS

P_SS

0.025

0.006

mW

%

Power supply sensitivity

AC CHARACTERISTICS⁽⁵⁾

Output voltage settling time

∆V_DD= ±5%

t_s

To ±0.1% of full-scale,

Data = 0000h to FFFFh to 0000h

µs

0.5

1

To ±0.006% of full-scale,

Data = 0000h to FFFFh to 0000h

Reference multiplying BW

DAC glitch impulse

Feedthrough error

Crosstalk error

BW -3 dB V_REFX = 100 mV_RMS, Data = FFFF_H, C_FB= 15 pF

10

1

MHz

nV/s

dB

Q

V_REFX = 10 V, Data = 0000h to 8000h to 0000h

Data = 0000h, V_REFX = 100 mV_RMS, f = 100 kHz

V_OUTX/V_REF

V_OUTA/V_REF

X

B

-70

Data = 0000h, V_REFB = 100 mV_RMS

Adjacent channel, f = 100 kHz

,

dB

-90

Digital feedthrough

Q

THD

e_n

CS = 1 and f_CLK= 1 MHz

2

-105

12

nV/s

dB

Total harmonic distortion

Output spot noise voltage

V_REF= 5 V_PP, Data = FFFFh, f = 1 kHz

f = 1 kHz, BW = 1 Hz

nV/√Hz

(5) All ac characteristic tests are performed in a closed-loop system using an OPA627 I-to-V converter amplifier.

4

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

PIN CONFIGURATIONS

DAC8803

(TOP VIEW)

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A

I

V

A

D

GND

2

A

I

OUT

3

A

REF

V

REF

4

R

A

FB

R

FB

5

MSB

RS

DGND

6

V

A

SS

7

V

F

DD

GND

8

CS

CLK

SDI

LDAC

SDO

NC

9

10

11

12

13

14

R

B

R

C

FB

V

REF

OUT

GND

I

A

I

OUT

A

GND

NC − No internal connection

PIN DESCRIPTION

NAME

A_GNDA, A_GNDB, A_GNDC, A_GND

I_OUTA, I_OUTB, I_OUTC, I_OUT

DESCRIPTION

1, 14, 15, 28

2, 13, 16, 27

D

DAC A, B, C, D Analog ground

DAC A, B, C, D Current output

D

DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale

output voltage. Can be tied to V_DD

3, 12, 17, 26

V_REFA, V_REFB, V_REFC, V_REFD

.

4, 11, 18, 25

5

R_FBA, R_FBB, R_FBC, R_FBD,

MSB

Establish voltage output for DAC A, B, C, D by connecting to external amplifier output.

MSB Bit set during a reset pulse (RS) or at system power on if tied to ground or V_DD

Reset pin, active low. Input register and DAC registers are set to all zeros or half scale

code (8000h) determined by the voltage on the MSB pin. Register data = 8000h when

MSB = 1.

6

7

8

RS

V_DD

CS

Positive power-supply input. Specified range of operation 5 V ±10%.

Chip-select; active low input. Disables shift register loading when high. Transfers shift

register data to input register when CS/LDAC goes high. Does not affect LDAC

operation.

9

CLK

SDI

NC

Clock input; positive edge triggered clocks data into shift register

Serial data input; data loads directly into the shift register.

Not connected; leave floating

10

19

Serial data output; input data load directly into shift register. Data appears at SDO, 19

clock pulses after input at the SDI pin.

20

21

SDO

Load DAC register strobe; level sensitive active low. Tranfers all input register data to

the DAC registers. Asynchronous active low input. See Table 1 for operation.

LDAC

22

23

24

A_GND

F

High current analog force ground.

V_SS

Negative bias power-supply input. Specified range of operation -0.3 V to -5.5 V.

Digital ground.

DGND

5

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel A

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 1.

Figure 2.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 3.

Figure 4.

6

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 5.

Figure 6.

7

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel B

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 7.

Figure 8.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 9.

Figure 10.

8

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 11.

Figure 12.

9

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel C

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 13.

Figure 14.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 15.

Figure 16.

10

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 17.

Figure 18.

11

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel D

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 19.

Figure 20.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 21.

Figure 22.

12

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 23.

Figure 24.

13

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

REFERENCE MULTIPLYING BANDWIDTH

6

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

6

−

12

18

24

30

36

42

48

54

60

66

72

78

84

90

96

V_DD= +5.0V

−

102

108

114

V_DD= +2.7V

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Logic Input Voltage (V)

10

100

1k

10k

100k

1M

10M

100M

Bandwidth (Hz)

Figure 25.

Figure 26.

DAC GLITCH

DAC SETTLING TIME

Voltage Output Settling

Code: 7FFFh to 8000h

Trigger Pulse

µ

Time (0.1 s/div)

Time (0.2 s/div)

Figure 27.

Figure 28.

Channel A

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 29.

Figure 30.

14

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 31.

Figure 32.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 33.

Figure 34.

15

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel B

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 35.

Figure 36.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 37.

Figure 38.

16

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 39.

Figure 40.

17

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel C

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 41.

Figure 42.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 43.

Figure 44.

18

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 45.

Figure 46.

19

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

Channel D

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 47.

Figure 48.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 49.

Figure 50.

20

DAC8803

www.ti.com

SBAS340A–JANUARY 2005–REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V_DD= +2.7 V (continued)

At T_A= +25°C, +V_DD= +2.7 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Graphic

Forthcoming

Figure 51.

Figure 52.

PARAMETER MEASUREMENT INFORMATION

SDI

A1

A0

D8

D2

D13 D13 D12 D11 D10

D9

D7

D1 D0

CLK

Input REG. LD

t

csh

CSS

t

ds

t

dh

t

ch

t

cl

CS

t

lds

t

pd

t

LDAC

LDH

t

SDO

LDAC

Figure 53. DAC8803 Timing Diagram

CIRCUIT OPERATION

The DAC8803 contains four 14-bit, current-output, digital-to-analog converters respectively. Each DAC has its

own independent multiplying reference input. The DAC8803 uses a 3-wire SPI compatible serial data interface,

with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an

LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage changes.

D/A Converter

The DAC8803 contains four current-steering R-2R ladder DACs. Figure 54 shows a typical equivalent DAC.

Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R_FBX pin

is connected to the output of the external amplifier. The I_OUTX terminal is connected to the inverting input of the

external amplifier. The A_GNDX pin should be Kelvin-connected to the load point in the circuit requiring the full

14-bit accuracy.

21

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

The DAC is designed to operate with both negative or positive reference voltages. The V_DDpower pin is only

used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the

internal 5 kΩ feedback resistor. If users are attempting to measure the value of R_FB, power must be applied to

V_DDin order to achieve continuity. An additional V_SSbias pin is used to guard the substrate during high

temperature applications to minimize zero-scale leakage currents that double every 10°C. The DAC output

voltage is determined by V_REFand the digital data (D) according to Equation 1:

D

16384

V_OUT+ *V_REF

(1)

Note that the output polarity is opposite to the V_REFpolarity for dc reference voltages.

V

DD

RRR

V

REF

X

R X

FB

2R

R

5 kW

S2

S1

I

X

OUT

A

F

GND

X

GND

From Other DACS A

GND

V

CC

DGND

Digital interface connections omitted for clarity.

Switches S1 and S2 are closed, V must be powered.

DD

Figure 54. Typical Equivalent DAC Channel

The DAC is also designed to accommodate ac reference input signals. The DAC8803 accommodates input

reference voltages in the range of -12 V to +12 V. The reference voltage inputs exhibit a constant nominal input

resistance of 5 kΩ, ± 20%. On the other hand, the DAC outputs I_OUTA, B, C, D are code-dependent and produce

various output resistances and capacitances.

The choice of external amplifier should take into account the variation in impedance generatedby the DAC8803

on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,

dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor

(C_FB) may be needed to provide a critically damped output response for step changes in reference input

voltages.

Figure 5 and Figure 6 show the gain vs frequency performance at various attenuation settings using a 23 pF

external feedback capacitor connected across the I_OUTX and R_FBX terminals. In order to maintain good analog

performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,

clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not

suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is

best to derive the DAC8803 5-V supply from the system analog supply voltages. (Do not use the digital 5-V

supply.) See Figure 55.

22

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

15 V

Analog

Power

Supply

2R

R

5 V

+

V

DD

RRR

R X

FB

V

REF

X

2R

R

5 kW

15 V

S2

S1

I

X

OUT

V

CC

A

F

V

A1

GND

OUT

+

X

GND

V

EE

Load

From Other DACS A

GND

DGND

V

SS

Digital interface connections omitted for clarity.

Switches S1 and S2 are closed, V must be powered.

DD

Figure 55. Recommended Kelvin-Sensed Hookup

23

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

V

REF

A B C D

CS

EN

CLK

V

DD

R

I

A

SDI

FB

D0

D1

16

DAC A

Input

DAC A

Register

R

OUT

Register

R

D2

D3

A

GND

A

D4

D5

D6

D7

D8

D9

R B

FB

D10

D11

D12

D13

A0

DAC B

Register

Input

Register

I

C

DAC B

DAC C

DAC D

OUT

ADC

2:4

A

GND

B

A

B

C

D

SDO

A1

Decode

R

I

C

FB

DAC C

Register

Input

Register

OUT

R

A

GND

C

R

I

D

FB

DAC D

Register

Input

Register

D

OUT

R

A D

GND

Set

MSB

Set MSB

Power-

on

Reset

A

GND

F

DGND

MSB

LDAC

RS

V

SS

Figure 56. System Level Digital Interfacing

SERIAL DATA INTERFACE

The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of the DAC8803 is

clocked into the serial input register in an 14-bit data-word format. MSB bits are loaded first. Table 3 defines the

16 data-word bits for the DAC8803.

Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data

setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked

in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register

are interrogated when the CS pin returns to the logic high state.

Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the

DAC8803. Keeping the CS line low between the first, second, and third byte transfers results in a successful

serial register update. Similarly, two right-justified data bytes can be written to the DAC8803. Keeping the CS line

low between the first and second byte transfer will result in a successful serial register update.

24

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new

data to the target DAC register, determined by the decoding of address bits A1and A0. For DAC8803, Table 1,

Table 3 and Figure 57 define the characteristics of the software serial interface. Figures 8 and 9 show the

equivalent logic interface for the key digital control pins for DAC8803.

To Input Register

A

B

C

D

Address

Decoder

CS

EN

Shift Register

th

CLK

SDI

th

19 /17

CLOCK

SDO

Figure 57. DAC8803 Equivalent Logic Interface

Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If

these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all

input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).

POWER ON RESET

When the V_DDpower supply is turned on, an internal reset strobe forces all the Input and DAC registers to the

zero-code state or half-scale, depending on the MSB pin voltage. The V_DDpower supply should have a smooth

positive ramp without drooping in order to have consistent results, especially in the region of V_DD= 1.5 V to 2.3

V. The V_SSsupply has no effect on the power-on reset performance. The DAC register data stays at zero or

half-scale setting until a valid serial register data load takes place.

ESD Protection Circuits

All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (DGND) and V_DDas

shown in Figure 58.

V

DD

5 kW

DIGITAL

INPUTS

DGND

Figure 58. Equivalent ESD Protection Circuits

25

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

PCB LAYOUT

In printed circuit board (PCB) layout, all analog ground, A_GNDX, should be tied together. Amplifiers suitable for:

Table 1. Control Logic Truth Table⁽¹⁾

CS

H

CLK

X

LDAC

RS

H

MSB

X

SERIAL SHIFT REGISTER

No effect

INPUT REGISTER

DAC REGISTER

Latched

H

Latched

L

H

X

No effect

Latched

L

↑+

H

X

Shift register data advanced one bit

L

H

X

No effect

↑+

L

H

X

Selected DAC updated with current SR

contents

H

X

L

H

L

X

0

No effect

Latched

Transparent

Latched

X

↑+

H

Latched

X

Latched data = 0000h

Latched data = 8000h

Latched data = 0000h

Latched data = 8000h

↑+

H

L

H

(1) ↑+ Positive logic transition; X = Do not care

Table 2. Serial Input Register Data Format, Data Loaded MSB First⁽¹⁾

Bit

B17

(MSB)

B16

A0

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

D3

B2

D2

B1

D1

B0

(LSB)

Data

A1

X

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D0

(1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to

logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded

DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored, only the

last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.

Table 3. Address Decode

A1

0

A0

0

DAC DECODE

DAC A

0

1

DAC B

1

0

DAC C

1

DAC D

26

DAC8803

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SBAS340A–JANUARY 2005–REVISED APRIL 2005

APPLICATION INFORMATION

The DAC8803, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the

full-scale output I_OUTis the inverse of the input reference voltage at V_REF

.

Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. An additional external

op amp A2 is added as a summing amp. In this circuit the first and second amps (A1 and A2) provide a gain of

2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented by using a 10-V offset of

the reference voltage to bias A2. According to the following circuit transfer equation ( Equation 2), input data (D)

from code 0 to full scale produces output voltages of V_OUT= -10 V to V_OUT= 10 V.

V_OUT+ (Dń32, 768 * 1) V_REF

(2)

10 kW

10 V

5 kW

A2

V

OUT

V

REF

−10 V < V < +10 V

OUT

V

X

V

X

FB

DD

REF

I X

OUT

One Channel

DAC8803

A1

A

GND

FA

A

GND

X

SS

Digital interface connections omitted for clarity.

Figure 59. Four-Quadrant Multiplying Application Circuit

Cross-Reference

The DAC8803 has an industry-standard pinout. Table 4 provides the cross-reference information.

Table 4. Cross-Reference

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

PACKAGE

OPTION

CROSS-

REFERENCE PART

PRODUCT

INL (LSB)

DNL (LSB)

DAC8803IDB

±1

-40°C to +85°C

28-Lead MicroSOIC

SSOP-28

AD5554BRS

27

PACKAGE OPTION ADDENDUM

www.ti.com

13-Apr-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SSOP

Drawing

DAC8803IDBR

DAC8803IDBT

PREVIEW

DB

28

2500

250

TBD

Call TI

DB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

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Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

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www.ti.com/video

microcontroller.ti.com

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Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	DAC8803IDBT
厂家：	TEXAS INSTRUMENTS
描述：	Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter 四，电流输出，串行输入14位乘法数位类比转换器转换器数模转换器光电二极管
文件：	总30页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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