DLP2000 [TI]
DLP® 0.2 nHD DMD;型号: | DLP2000 |
厂家: | TEXAS INSTRUMENTS |
描述: | DLP® 0.2 nHD DMD |
文件: | 总37页 (文件大小:1496K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLP2000
ZHCSJN3B –MARCH 2019 –REVISED MAY 2022
DLP2000 (0.2 nHD) DMD
1 特性
3 说明
DLP2000 数字微镜器件 (DMD) 是一款数控微光机电系
统(MOEMS) 空间照明调制器(SLM)。当与适当的光学
系统配合使用时,DLP2000 DMD 可显示非常清晰的高
质量图像或视频。DLP2000 是 DLP2000 DMD 和
DLPC2607 显示控制器所组成的芯片组的一部分。
DLPA1000 PMIC/LED 驱动器也支持此芯片组。
DLP2000 紧凑的物理尺寸非常适合于注重小外形尺寸
和低功耗的便携式设备。紧凑封装弥补了小尺寸 LED
的不足,从而可实现高效、可靠耐用的光引擎。
• 超紧凑0.2 英寸(5.55mm) 对角线微镜阵列
– 640 × 360 铝制微米级微镜阵列,采用正交布局
– 7.56 微米微镜间距
– 12° 微镜倾斜(相对于平坦表面)
– 角落照明,实现最优的效率和光学引擎尺寸
• 专用DLPC2607 显示控制器和DLPA1000
PMIC/LED 驱动器,确保可靠运行
2 应用
• 物联网(IoT) 器件,包括:
请访问 TI DLP®Pico™ 显示技术入门页,了解如何开始
使用DLP2000 DMD。
– 控制面板
– 安全系统
– 恒温器
DLP2000 提供成的资源,可帮助用户加快设计周期。
这些资源包括量产就绪型光学模块、光学模块制造商和
设计公司。
• 可穿戴显示
• 产品嵌入式显示屏,包括:
– 平板电脑
– 摄像头
– 人工智能(AI) 助理
• 微数字标牌
• 超低功耗智能附件投影仪
器件信息(1)
封装尺寸(标称值)
器件型号
DLP2000
封装
FQC (42)
14.12mm × 4.97mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
DLP2000 DMD
DLPA1000
DLPC2607
Display Controller
DATA(11:0)
Digital Micromirror Device
Power Management
VBIAS
DCLK
VOFFSET
LOADB
VRESET
SCTRL
DRC_BUS
DRC_OEZ
DRC_STROBE
SAC_BUS
SCAN_TEST
VCC
VSS
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS140
DLP2000
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ZHCSJN3B –MARCH 2019 –REVISED MAY 2022
Table of Contents
7.5 Window Characteristics and Optics.......................... 18
7.6 Micromirror Array Temperature Calculation.............. 19
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 20
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................25
9.1 Power Supply Power-Up Procedure......................... 25
9.2 Power Supply Power-Down Procedure.....................25
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................30
11.1 第三方产品免责声明................................................30
11.2 Device Support........................................................30
11.3 Related Links.......................................................... 30
11.4 接收文档更新通知................................................... 30
11.5 支持资源..................................................................30
11.6 Trademarks............................................................. 31
11.7 Electrostatic Discharge Caution..............................31
11.8 术语表..................................................................... 31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 Storage Conditions..................................................... 6
6.3 ESD Ratings............................................................... 7
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information....................................................8
6.6 Electrical Characteristics.............................................8
6.7 Timing Requirements..................................................9
6.8 System Mounting Interface Loads.............................11
6.9 Physical Characteristics of the Micromirror Array.....12
6.10 Micromirror Array Optical Characteristics............... 14
6.11 Window Characteristics...........................................15
6.12 Chipset Component Usage Specification............... 16
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................18
Information.................................................................... 32
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
• 根据最新的德州仪器(TI) 和行业数据表标准对本文档进行了更新.......................................................................1
• Updated Micromirror Array Optical Characteristics ......................................................................................... 14
Changes from Revision * (April 2019) to Revision A (November 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................7
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5 Pin Configuration and Functions
H
G
F
E
D C B A
1
2
3
4
5
6
7
K
J
9
1
5
11
13
15
17
19
21
23
25
27
29
31
33
35
10
15
20
21
37
38
39
41
图5-1. FQC Package 42-Pin LGA Bottom View
表5-1. Pin Functions
PIN
DATA
RATE
PACKAGE NET
LENGTH (mm)
TYPE
SIGNAL
DESCRIPTION
NAME
NO.
DATA INPUTS
DATA(0)
J13
J2
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
Input data bus
8.83
7.53
6.96
7.05
7.56
7.07
7.61
7.68
7.31
6.76
8.18
7.81
7.78
DATA(1)
DATA(2)
J4
DATA(3)
J6
DATA(4)
J7
DATA(5)
J8
DATA(6)
J12
J10
K4
K2
K7
K6
K9
DATA(7)
DATA(8)
DATA(9)
DATA(10)
DATA(11)
DCLK
Input data clock
CONTROL INPUTS
LOADB
K10
Input
LVCMOS
DDR
Parallel latch load enable
7.64
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表5-1. Pin Functions (continued)
PIN
DATA
RATE
PACKAGE NET
LENGTH (mm)
TYPE
SIGNAL
DESCRIPTION
NAME
NO.
SCTRL
K12
Input
LVCMOS
LVCMOS
DDR
Serial control (sync)
8.62
Reset control serial bus. synchronous to
rising edge of DCLK. Bond pad does not
connect to internal pull down.
DRC_BUS
DRC_OEZ
K14
K18
Input
Input
7.28
4.69
Active low. Output enable signal for internal
reset driver circuitry. Bond pads do not
connect to internal pulldown.
LVCMOS
LVCMOS
Rising edge on DRC_STROBE latches in
the control signals. Synchronous to rising
edge of DCLK. Bond pad does not connect
to internal pulldown.
DRC_STROBE
SAC_BUS
J15
Input
7.61
Stepped address control serial bus.
Synchronous to rising edge of DCLK. Bond
pad does not connect to internal pulldown.
K16
K20
Input
Input
LVCMOS
LVCMOS
8.17
1.18
SCAN_TEST
MUX’ed output for scanned chip ID
POWER
Power supply for positive bias level of
mirror reset signal
VBIAS
J16
K15
J20
Power
Power
Power
Power supply for high voltage CMOS logic.
Power supply for stepped high voltage at
mirror address electrodes. Power supply for
offset level of mirror reset signal
VOFFSET
VRESET
Power supply for negative reset level of
mirror reset signal
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
J11
J21
K1
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power supply for low voltage CMOS logic.
Power supply for normal high voltage at
mirror address electrodes. Power supply for
offset level of mirror reset signal during
power down
K11
K21
J3
J5
J9
J14
J17
J18
J19
K3
Common return. Ground for all power
K5
K8
K13
K17
K19
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ZHCSJN3B –MARCH 2019 –REVISED MAY 2022
Pin Functions—Test Pads
Electrical Test Pad
A1
DLP® System Board
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
A39
A41
B2
B4
B6
B38
C3
D4
E4
F3
G2
G4
G6
G38
H1
H3
H5
H7
H9
H11
H13
H15
H17
H19
H21
H23
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Pin Functions—Test Pads (continued)
Electrical Test Pad
DLP® System Board
H25
H27
H29
H31
H33
H35
H37
H39
H41
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
Supply Voltage
VCC
LVCMOS logic supply voltage(2)
Mirror electrode and HVCMOS voltage(2)
Mirror electrode voltage
4
8.75
VOFFSET
VBIAS
|VBIAS –VOFFSET
VRESET
V
17
V
Supply voltage delta(3)
8.75
V
|
Mirror electrode voltage
0.5
V
–11
–0.5
60
Input voltage: other inputs See (2)
.
VCC + 0.3
80
V
Input Voltage
Clock Frequency
Environmental
DCLK
Clock frequency
MHz
°C
°C
Temperature—operational(4)
Temperature—non-operational(4)
–20
–40
90
TARRAY and TWINDOW
90
See note(5)
.
Dew point temperature—operating and
non-operating (non-condensing)
TDP
°C
°C
Absolute temperature delta between any
point on the window edge and the ceramic
test point TP1(6)
30
|TDELTA
|
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to GND (VSS). VOFFSET, VCC, VBIAS, VRESET and VSS power supplies are required for the normal
DMD operating mode.
(3) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than 8.75 V.
(4) The highest temperature of the active array (as calculated in 节7.6) or of any point along the Window Edge as defined in 图7-1.
(5) The DLP2000 DMD is intended for use in well controlled, low dew point environments. Please contact your local TI sales person or TI
distributor representative to determine if this device is suitable for your application and operating environment compared to other DMD
solutions. DLP® Products offers a broad portfolio of DMDs suitable for a wide variety of applications.
(6) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1.
6.2 Storage Conditions
Applicable before the DMD is installed in the final product
MIN
MAX
UNIT
TDMD
DMD Temperature
85
°C
–40
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6.2 Storage Conditions (continued)
Applicable before the DMD is installed in the final product
MIN
MAX
UNIT
TDP
Dew Point Temperature
(non-condensing)
See Note(1)
°C
(1) The DLP2000 DMD is intended for use in well controlled, low dew point environments. Please contact your local TI sales person or TI
distributor representative to determine if this device is suitable for your application and operating environment compared to other DMD
solutions. DLP Products offers a broad portfolio of DMDs suitable for a wide variety of applications.
6.3 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
1.65
8.25
15.5
NOM
1.8
MAX
1.95
8.75
16.5
8.75
UNIT
V
VCC
LVCMOS logic power supply voltage(1)
Mirror electrode and HVCMOS voltage(1)
Mirror electrode voltage
VOFFSET
VBIAS
8.5
V
16
V
Supply Voltage
Input Voltage
(2)
V
Supply voltage delta |VBIAS –VOFFSET
|
VRESET
VP
Mirror electrode voltage
V
–9.5
0.4*VCC
0.3*VCC
0.1*VCC
0
–10
–10.5
0.7*VCC
0.6*VCC
0.4*VCC
40 to 70
75
Positive going threshold voltage
Negative going threshold voltage
Hysteresis voltage (Vp –Vn)
V
VN
V
VH
V
Array temperature—long-term operational(3) (4) (5) (6)
Array Temperature –short-term operational(4) (7)
TARRAY
°C
°C
°C
–20
|TDELTA
|
Absolute temperature difference between any point on
the window edge and the ceramic test point TP1(8)
15
Window temperature—operational(3) (9)
TWINDOW
TDP
90
°C
°C
Environmental
Dew point temperature (non-condensing)
See
note(10)
.
ILLUV
ILLVIS
ILLIR
Illumination wavelength < 400 nm(3)
0.68 mW/cm2
Thermally limited
10 mW/cm2
Illumination wavelengths between 400 nm and 700 nm
Illumination wavelength > 700 nm
(1) All voltage values are with respect to GND (VSS). VOFFSET, VCC, VBIAS, VRESET , and VSS power supplies are required for the normal
DMD operating mode.
(2) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than 8.75 V.
(3) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination
reduces device lifetime.
(4) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in 图7-1 and the package thermal resistance in 节7.6.
(5) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to 节7.7 for a definition of micromirror landed duty cycle.
(6) Long-term is defined as the usable life of the device
(7) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as cumulative time over the usable life of the device and is less than 500 hours for temperatures between the long-term
maximum and 75°C, and less than 500 hours for temperatures between 0°C and –20°C.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1.
(9) Window temperature is the highest temperature on the window edge shown in 图7-1.
(10) The DLP2000 DMD is intended for use in well controlled, low dew point environments. Please contact your local TI sales person or TI
distributor representative to determine if this device is suitable for your application and operating environment compared other DMD
solutions. DLP Products offers a broad portfolio of DMDs suitable for a wide variety of applications.
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80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45
100/0 95/5
D001
Micromirror Landed Duty Cycle
图6-1. Max Recommended Array Temperature—Derating Curve
6.5 Thermal Information
DLP2000
FQC (LGA)
42 PINS
8
THERMAL METRIC(1)
UNIT
Thermal resistance active area to test point 1 (TP1) (1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in 节6.4. The total heat load on the DMD is largely driven by the
incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 1.65 V
IOH = –2 mA
VOH
VOL
IIL
High level output voltage
1.20
V
VCC = 1.95 V
IOL = –2 mA
Low level output voltage
Low level input current(1) (2)
High level input current(1) (2)
0.45
52
V
VCC = 1.95 V
VI = 0 V
nA
nA
VCC = 1.95 V
VI = 1.95 V
IIH
41
CURRENT
ICC
Current at VCC = 1.95 V
DCLK Frequency = 77 MHz
30
1.5
1.3
1.2
mA
mA
mA
mA
IOFFSET
IBIAS
Current at VOFFSET = 8.75 V(3)
Current at VBIAS = 16.5 V(3) (4) Three global resets within time period = 200 µs
IRESET
POWER
PCC
Three global resets within time period = 200 µs
Current at VRESET = –10.5 V
Power at VCC = 1.95 V(5)
DCLK Frequency = 77 MHz
26
5
59
13
mW
mW
mW
mW
mW
POFFSET
PBIAS
PRESET
PTOTAL
CAPACITANCE
CIN Input capacitance
Power at VOFFSET = 8.75 V(5)
Power at VBIAS = 16.5 V(5)
Power at VRESET = –10.5 V(5)
Supply power dissipation total
Three global resets within time period = 200 µs
Three global resets within time period = 200 µs
9
22
4
13
44
107
f = 1 MHz
10
pF
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6.6 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COUT
Output capacitance
f = 1 MHz
10
pF
(1) Includes LVCMOS pins only
(2) LVCMOS input pins do not have pullup or pulldown configurations.
(3) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than 8.75 V.
(4) When DRC_OEZ = high, the internal reset drivers are tri-stated and IBIAS standby current is 3.8 mA.
(5) Nominal values are measured with VCC = 1.8 V, VOFFSET = 8.5 V, VBIAS = 16 V, and VRESET = –10 V.
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
ns
tr
tf
tr
Rise time(1)
Fall time(1)
Rise time(2)
20% to 80% DCLK
80% to 20% DCLK
2.5
2.5
2.5
ns
20% to 80% DATA(11:0), SCTRL,
LOADB
ns
tf
Fall time(2)
80% to 20% DATA(11:0), SCTRL,
LOADB
2.5
ns
tc
Cycle time(1)
50% to 50% DCLK
12.5
16.67
ns
ns
ns
ns
ns
tw
tw
tw
tsu
Pulse duration(1)
Pulse duration low(1)
Pulse duration high(1)
Setup time(1)
50% to 50% DCLK
5
7
7
1
50% to 50% LOADB
50% to 50% DRC_STROBE
DATA(11:0) before rising or falling edge
of DCLK
tsu
Setup time(1)
SCTRL before rising or falling edge of
DCLK
1
ns
tsu
tsu
Setup time(1)
Setup time(2)
LOADB low before rising edge of DCLK
1
2
ns
ns
SAC_BUS low before rising edge of
DCLK
tsu
tsu
th
Setup time(2)
Setup time(1)
Hold time(1)
Hold time(1)
DRC_BUS high before rising edge of
DCLK
2
2
1
1
ns
ns
ns
ns
DRC_STROBE high before rising edge
of DCLK
DATA(11:0) after rising or falling edge of
DCLK
th
SCTRL after rising or falling edge of
DCLK
th
th
th
th
Hold time(1)
Hold time(2)
Hold time(2)
Hold time(1)
LOADB low after falling edge of DCLK
SAC_BUS low after rising edge of DCLK
DRC_BUS after rising edge of DCLK
1
2
2
2
ns
ns
ns
ns
DRC_STROBE after rising edge of
DCLK
(1) Refer to 图6-2 and 图6-3.
(2) Refer to 图6-4 and 图6-5.
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tW
tW
tC
50%
50%
50%
50%
50%
DCLK
tH
tH
tSU
tSU
50%
50%
50%
50%
50%
DATA(11:0)
SCTRL
50%
50%
tSU
50%
50%
tH
50%
LOADB
tW(L)
Not To Scale
tH
tSU
50%
50%
DRC_ STROBE
tW(H)
图6-2. Switching Parameters 1
50%
50%
50%
50%
DCLK
tH
tSU
50%
50%
SAC_BUS
tSU
tH
50%
50%
DRC_BUS
tH
tSU
50%
50%
DRC_STROBE
tW(H)
图6-3. Switching Parameters 2
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VCC
80%
20%
DCLK, SCTRL, LOADB, DATA(11:0)
VSS
tR
tF
图6-4. Rise and Fall Timing Parameters 1
VCC
80%
Not To Scale
SAC_CLK, SAC_BUS, DRC_BUS
20%
VSS
tR
tF
图6-5. Rise and Fall Timing Parameters 2
Device Pin
Tester Channel
Output Under Test
CLOAD
图6-6. Test Load Circuit
See 节7.3.4 for more information.
6.8 System Mounting Interface Loads
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX UNIT
45
N
N
Connector area (See 图6-7.)
Maximum system mounting interface
load to be applied to the:
DMD mounting area uniformly distributed over 4 areas (See
图6-7.)
100
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Datum 'A' Area (3 places)
Datum 'E' Area (1 place)
DMD Mounting Area (4 places)
Connector Area
图6-7. System Interface Loads
6.9 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
640
UNIT
micromirrors
micromirrors
µm
M
N
P
Number of active columns(1)
Number of active rows(1)
See 图6-8.
See 图6-8.
See 图6-8.
M × P
360
Micromirror (pixel) pitch(1)
7.56
Micromirror active array width(1)
Micromirror active array height(1)
Micromirror active border(2) (3)
4.8384
2.7216
8
mm
N × P
mm
Pond of micromirrors (POM)
micromirrors, side
(1) See 图6-8.
(2) The structure and qualities of the border around the active array include a band of partially functional micromirrors called the “pond of
micromirrors”(POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or “on”state
but still require an electrical bias to tilt toward “off.”
(3) Out of the eight POM rows on the top and bottom, only the one POM row closest to the active array is electrically attached to that reset
group. The other seven POM rows are attached to a dedicated POM internal reset driver circuit.
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incident
illumination
M x P
N œ 1
N œ 2
N œ 3
N œ 4
DLP2000 DMD
Active Array
N x P
M x N Micromirrors
3
2
1
0
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
P
P
图6-8. Micromirror Array Physical Characteristics
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6.10 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Micromirror tilt—half angle, variation device to device (1)
11
12
13
°
Axis of rotation with respect to system datums, variation
device to device(2)
44
45
46
°
Bright pixel(s) in active area(4)
Bright pixel(s) in the POM(6)
Gray 10 screen(5)
Gray 10 screen(5)
0
1
4
0
0
Image performance(3)
Dark pixel(s) in the active area(7) White screen
Adjacent pixel(s)(8)
Any screen
Unstable pixel(s) in active area(9) Any screen
micromirrors
(1) Limits on variability of micromirror tilt half angle are critical in the design of the accompanying optical system. Variations in tilt angle
within a device may result in apparent non-uniformities, such as line pairing and image mottling, across the projected image. Variations
in the average tilt angle between devices may result in colorimetry and system contrast variations. The specified limits represent the
tolerances of the tilt angles within a device.
(2) See 图6-9.
(3) Conditions of acceptance: All DMD image quality returns are evaluated using the following projected image test conditions:
Test set degamma should be linear.
Test set brightness and contrast should be set to nominal.
The diagonal size of the projected image should be a minimum of 20 inches.
The projections screen should be 1X gain.
The projected image should be inspected from a 38-inch minimum viewing distance.
The image should be in focus during all image quality tests.
(4) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(5) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(6) POM definition: Rectangular border of off-state mirrors surrounding the active area
(7) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(8) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(9) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image.
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Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity. Not to scale.
incident
illumination
DLP2000 DMD
M x N Micromirrors
N œ 1
N œ 2
N œ 3
N œ 4
On-State
Tilt Direction
Off-State
Tilt Direction
45°
3
2
1
0
图6-9. Landed Pixel Orientation and Tilt
See 节6.9 for M and N specifications.
6.11 Window Characteristics
表6-1. DMD Window Characteristics
PARAMETER
VALUE
Corning Eagle XG
1.5119
UNIT
Window Material
Window Refractive Index at wavelength 546.1 nm
Window Transmittance, minimum within the wavelength range 420–680 nm. Applies to all angles
0–30° AOI. (1) (2)
97%
97%
Window Transmittance, average over the wavelength range 420–680 nm. Applies to all angles 30–
45° AOI. (1) (2)
(1) Single-pass through both surfaces and glass.
(2) AOI –Angle Of Incidence is the angle between an incident ray and the normal of a reflecting or refracting surface.
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6.12 Chipset Component Usage Specification
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
The DLP2000 is a component of one or more DLP chipsets. Reliable function and operation of the DLP2000
requires that it be used in conjunction with the other components of the applicable DLP chipset, including those
components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DLP2000 is a 0.2-inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 640
columns by 360 rows in a square grid pixel arrangement. The DMD is an electrical input, optical output micro-
electrical-mechanical system (MEMS). The electrical interface is a Double Data Rate (DDR) input data bus.
The DLP2000 is part of the chipset that includes the DLP2000 DMD, the DLPC2607 display controller, and the
DLPA1000 PMIC/LED driver. To ensure optimal performance, the DLP2000 DMD should be used with the
DLPC2607 display controller and the DLPA1000 PMIC/LED driver.
7.2 Functional Block Diagram
illumination
Orientation is not representative of optical system.
Scale is not representative of layout.
For informational purposes only.
Details omitted for clarity.
High Speed Interface
Misc
Column Write
Bit Lines
Control
(0,0)
Voltages
Word Lines
Voltage
Generators
SRAM
Row
(359, 639)
Control
Column Read
Control
Low Speed Interface
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7.3 Feature Description
7.3.1 Power Interface
For the DLP2000 DMD, the power management IC is the DLPA1000. This driver contains three regulated DC
supplies for the DMD reset circuitry: VBIAS, VRESET, and VOFFSET
.
7.3.2 Control Serial Interface
The control serial interface handles instructions that configure the DMD and control reset operation. DRC_BUS
is the reset control serial bus, DRC_OEZ is the active low, output enable signal for internal reset driver circuitry,
DRC_STROBE rising edge latches in the control signals, and SAC_BUS is the stepped address control serial
bus.
7.3.3 High Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high speed interface is composed of
LVCMOS signal receivers for inputs and a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. 图 6-6 shows an equivalent test load circuit for the output
under test. The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or
depiction of the actual load presented by a production test. System designers should use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Refer to the 节8 section.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC2607 controller. See the DLPC2607 controller data sheet or
contact a TI applications engineer.
7.5 Window Characteristics and Optics
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous components and system design parameters.
Optimizing system optical performance and image quality strongly relates to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance depends on compliance with the optical system operating conditions described in the following
sections.
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
7.5.1.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the display’s border as well as the active area, which may require additional system
apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
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7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the area outside the active array can create artifacts from the mechanical
features surrounding the active array and other surface anomalies that may be visible on the screen. The
illumination optical system should be designed to limit light flux incident anywhere outside more than 20 pixels
from the edge of the active array on all sides. Depending on the particular system’s optical architecture and
assembly tolerances, this amount of overfill light on the outside of the active array may still cause artifacts to still
be visible.
7.6 Micromirror Array Temperature Calculation
Window Edge
(4 surfaces)
TP1 (ceramic)
0.60
7.06
图7-1. DMD Thermal Test Point
The micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the package thermal resistance, the electrical power dissipation, and the illumination heat load. The
relationship between array temperature and the reference ceramic temperature is provided by the following
equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
)
(1)
(2)
(3)
• TARRAY = Computed DMD array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C), TP1 location in 图7-1
• RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W), specified in
节6.5
• QARRAY = Total DMD power; electrical plus absorbed (calculated) (W)
• QELECTRICAL = Nominal DMD electrical power dissipation (W)
• CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm)
• SL = Measured ANSI screen lumens (lm)
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.045 watts.
The absorbed power from the illumination source is variable and depends on the operating state of the mirrors
and the intensity of the light source. The equations shown previously are valid for a 1-Chip DMD system with a
total projection efficiency from DMD to screen of 87%.
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The conversion constant CL2W is based on DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lumens/watt for the projected light, and an illumination distribution of 83.7% on the DMD active
array and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be
0.00293 W/lm.
The following is a sample calculation for a typical projection application:
• SL = 20 lm
• TCeramic = 55°C
• QArray = QELECTRICAL + QILLUMINATION = 0.045 W + (0.00293 W/lm × 20 lm) = 0.1036 W
• TArray = 55°C + (0.1036 W × 8°C/W) = 55.8°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On state versus the amount of time the same
micromirror is landed in the Off state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the On state 75% of the
time (and in the Off state 25% of the time), whereas 25/75 would indicate that the pixel is in the On state 25% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric
landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a given long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
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Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
表7-1. Grayscale Value
and Landed Duty Cycle
Grayscale
Value
Landed Duty
Cycle
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (4)
×
Blue_Scale_Value)
where
• Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in 表7-2.
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表7-2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
Red Scale
Value
Green Scale
Blue Scale
Value
Landed Duty
Cycle
Value
0%
100%
0%
0%
0%
0%
0/100
50/50
20/80
30/70
6/94
0%
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
0%
7/93
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
0%
60%
60%
100%
12%
100%
100%
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into projection or collection optics. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the the DLPC2607
controller. Applications of interest include internet of things (IoT) devices such as control panels, and security
systems and thermostats, as well as projection embedded in display applications like smartphones, tablets,
cameras, and artificial intelligence (AI) assistance. Other applications include wearable (near-eye) displays,
micro digital signage, and ultra-low power smart accessory projectors.
DMD power-up and power-down sequencing is strictly controlled by the DLPA1000. Refer to 节 9 for power-up
and power-down specifications. The DLP2000 DMD reliability is only specified when used with the DLPC2607
controller and the DLPA1000 PMIC/LED Driver.
8.2 Typical Application
A common application for the DLP2000 chipset is creating a pico-projector embedded in a handheld product. For
example, a pico-projector embedded in a smart phone, camera, battery powered mobile accessory, micro digital
signage or IoT application. The DLPC2607 controller in the pico-projector receives images from a multimedia
front end within the product as shown below.
Projector Module Electronics
BAT
L5
2.3V-5.5V
DC
Supplies
1.8V
1.0V
Dual
Reg.
Connector
PWR_EN
MIC
On/Off
SYSPWR
PROJ_ON
L6
LCD
Panel
VDD
VLED
RESETZ
INTZ
L1
L2
PARKZ
RF
I/F
DLPA1000
Analog
RED
PROJ_ON
Flash
GREEN
BLUE
ASIC
INIT_DONE
GPIO4
SPI(4)
FLASH,
SDRAM,
etc.
BIAS, RST, OFS
3
Illumination
Optics
Host
Processor
Parallel or
BT.656
LED_SEL(2)
CLRL
4
DLPC2607
PWM_IN
RGB
28
24/16/8
DATA
CMP_OUT
DLP2000
Keypad
Thermistor
I2C
(.2nHD)
DMD
CTRL
DDR
DATA
1.8V
1.0V
VIO
VCORE
GPIO(5)
Motor
Driver
GPIO5
DDR
Drives Focus Lens
Stepper
Motor
Included in DLP® Chip Set along with DMD
Motor Position
Mobile SDRAM
8.2.1 Design Requirements
A pico-projector is created by using a DLP chip set comprised of the DLP2000 DMD, a DLPC2607 controller,
and a DLPA1000 PMIC/LED driver. The DLPC2607 controller does the digital image processing, the DLPA1000
provides the needed analog functions for the projector, and the DLP2000 DMD is the display device producing
the projected image.
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In addition to the three DLP chips in the chipset, other chips may be needed. This includes a Flash part needed
to store the software and firmware for controlling the DLPC2607 controller.
The illumination that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector.
When connecting the DLPC2607 controller to the multimedia front end to receive images, a parallel interface is
used. When using the parallel interface, the I2C should be connected to the multimedia front end to send
commands to the DLPC2607 controller and configure the DLPC2607 controller for different features.
8.2.2 Detailed Design Procedure
To connect the DLPC2607 controller, the DLPA1000, and the DLP2000 DMD, see the reference design
schematic. A small circuit board layout is possible when using this schematic. An example small board layout is
included in the reference design data base. Layout guidelines should be followed to achieve a reliable projector.
An optical OEM who specializes in designing optics for DLP projectors typically supplies the optical engine that
has the LED packages and the DMD mounted on it.
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in 图8-1. For the LED currents shown, it is assumed that
the same current amplitude is applied to the red, green, and blue LEDs.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300 400
Current (mA)
500
600
700
D001
图8-1. Luminance vs Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, and VRESET. DMD
power-up and power-down sequencing is strictly controlled by the DLPA1000 device.
VCC, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down
operations. Failure to meet any of the following requirements will result in a significant reduction in the DMD’s
reliability and lifetime. Refer to 图9-1.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect
device reliability.
VCC, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and
power-down operations. Failure to meet any of the following requirements will result in a significant
reduction in the DMD’s reliability and lifetime.
9.1 Power Supply Power-Up Procedure
• During Power-Up, VCC must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied
to the DMD.
• During Power-Up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta
between VBIAS and VOFFSET must be within ±8.75 V (Note 1).
• During Power-Up, the DMD’s LVCMOS input pins shall not be driven high until after VCC has settled at
operating voltage.
• During Power-Up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS
• Slew Rates for Power-Up are flexible, as long as the transient voltage levels follow the requirements listed
previously.
.
9.2 Power Supply Power-Down Procedure
• The power-down sequence is the reverse order of the previous power-up sequence. VCC must be supplied
until after VBIAS, VRESET and VOFFSET are discharged to within 4 V of ground.
• During Power-Down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within ±8.75 V (Note 1).
• During power-down, the DMD’s LVCMOS input pins must be less than VCC + 0.3 V.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS
.
• Slew rates for power-down are flexible, as long as the transient voltage levels follow the requirements listed
previously.
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Note 1
VBIAS, VOFFSET, and VRESET are disabled by DLP Display Controller software
Note 2
Power Off
Note 4
DMD_PWR_EN
Mirror Park Sequence
Note 3
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VOFFSET
VOFFSET
Note 6
VOFFSET
Note 5
VOFFSET < Specification
VSS
VSS
Note 5
ûV < Specification
VBIAS
ûV < Specification
VBIAS
Note 6
VBIAS
VBIAS < Specification
VSS
VSS
VSS
VSS
Refer to specifications listed in section Recommended Operating Conditions.
Note 6
Waveforms are not to scale. Details are omitted for clarity.
VRESET < Specification
VRESET > Specification
VRESET
VRESET
VCC
VRESET
VCC
LVCMOS
Inputs
VSS
VSS
图9-1. DMD Power Supply Sequencing Requirements
Note 1: Refer to specifications listed in 节6.4 . Waveforms are not to scale. Details are omitted for clarity.
Note 2: DMD_PWR_EN is not a package pin on the DMD. It is a signal from the DLP Display Controller
(DLPC2607) that enables the VRESET, VBIAS, and VOFFSET regulators on the system board.
Note 3: After the DMD micromirror park sequence is complete, the DLP display controller (DLPC2607) software
initiates a hardware power-down that disables VBIAS, VRESET and VOFFSET
.
Note 4: During the micromirror parking process, VCC, VBIAS, VOFFSET, and VRESET power supplies are all required
to be within the specification limits in 节 6.4 . Once the micromirrors are parked, VBIAS, VOFFSET, and VRESET
power supplies can be turned off.
Note 5: To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in 节
6.4 . It is critical to meet this requirement and that VBIAS not reach full power level until after VOFFSET is at almost
full power level. OEMs may find that the most reliable way to ensure this is to delay powering VBIAS until after
VOFFSET is fully powered on during power-up (and to remove VBIAS prior to VOFFSET during power down). In this
case, VOFFSET is run at its maximum allowable voltage level (8.75 V).
Note 6: Refer to specifications listed in 表9-1.
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表9-1. DMD Power-Down Sequence Requirements
PARAMETER
VBIAS
DESCRIPTION
Supply voltage level during power-down sequence
Supply voltage level during power-down sequence
Supply voltage level during power-down sequence
MIN
MAX
4.0
UNIT
V
V
V
VOFFSET
4.0
VRESET
0.5
–4.0
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD, however the DMD is typically connected using a board to
board connector with a flex cable. The flex cable provides an interface for data and control signals between the
DLPC2607 controller and the DLP2000 DMD. For detailed layout guidelines refer to the DLPC2607 controller
layout guidelines under PCB design and DMD interface considerations.
Some layout guidelines for the flex cable interface with the DMD are:
• Minimize the number of layer changes for DMD data and control signals.
• DMD data and control lines are DDR, whereas DMD_SAC and DMD_DRC lines are single data rate.
Matching the DDR lines is more critical and should take precedence over matching single data rate lines.
• 图10-1 and 图10-2 show the top and bottom layer of the DMD flex cable connections.
10.2 Layout Example
图10-1. DMD Flex Cable—Top Layer
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图10-2. DMD Flex Cable—Bottom Layer
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
DLP2000 A FQC
Package
TI Internal Numbering
Device Descriptor
图11-1. Part Number Description
11.2.2 Device Markings
•Device Marking includes the Human-Readable character string GHJJJJK VVVV
•GHJJJJK is the Lot Trace Code
•VVVV is a 4 character Encoded Device Part Number
GHJJJJK VVVV
图11-2. DMD Marking Location
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DLPC2607
DLPA1000
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.6 Trademarks
Pico™ and TI E2E™ are trademarks of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP2000AFQC
ACTIVE
CLGA
FQC
42
180
RoHS & Green
Call TI
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
DWG NO.
SH
8
5
3
6
1
7
4
1
2510560
REVISIONS
C
COPYRIGHT 2009 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
ECO 2100735 INITIAL RELEASE
DATE
BY
BMH
1
2
DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.
8/3/09
ECO 2102356 ADD DATUM E AND NOTE 9; UPDATE
SOLDER APPEARANCE; TIGHTEN NOTCH X-AXIS TOL'S
ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
10/22/09
B
BMH
1/4/10
C
ECO 2104056 CHG ENCAP MAX HEIGHT FROM TBD TO ZERO
ECO 2166625 ADD "FQC PACKAGE" TO DRAWING TITLE;
SHOW APERTURE CORNER RADII PICTORIALLY
BMH
BMH
3
4
5
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
DMD MARKING TO APPEAR IN CONNECTOR RECESS.
5/30/17
D
D
C
B
A
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
C
B
A
6
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C
(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
7
8
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING
TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).
(ILLUMINATION
DIRECTION)
9
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
5
4X R0.2 0.05
5
1.1760.05
5
+
0.2
-
0.1
2X 1.235
+
-
0.2
0.1
2.485
5
+
0.275
-
0.075
4.97
4X R0.40.1
5
5
5
90°1°
2X 2.50.075
(2.5)
A
A
B
8
C
5
+
0.2
-
0.1
(1)
0.8
12.320.08
5
+
0.3
14.12
-
0.1
7
6
0.4 0.03
D
2X ENCAPSULANT
0.703 0.057
0.038A
9
(1.483)
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
A
1
9
0.780.063
0.02D
1.2 0.1
ACTIVE ARRAY
5
(2.5)
0.05
(0.88)
0.35 MIN.
TYP.
F
F
(SHEET 3)
(SHEET 3)
0 MIN. TYP.
(PANASONIC AXT642124DD1, 42-CONTACT,
0.4 mm PITCH BOARD-TO-BOARD HEADER)
INTERFACE TO PANASONIC AXT542124DD1 SOCKET
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
TEXAS
8/3/2009
8/3/2009
8/3/2009
8/3/2009
8/3/2009
B. HASKETT
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
INSTRUMENTS
ENGINEER
Dallas Texas
B. HASKETT
QA/CE
ANGLES 1
TITLE
SECTION A-A
NOTCH OFFSETS
ICD, MECHANICAL, DMD,
.2 nHD DDR SERIES 230
(FQC PACKAGE)
2 PLACE DECIMALS 0.25
1 PLACE DECIMALS 0.50
P. KONRAD
CM
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
F. ARMSTRONG
THIRD ANGLE
PROJECTION
DWG NO
REV
SIZE
D
NONE
NEXT ASSY
0314DA
USED ON
J. GRIMMETT
2510560
D
APPROVED
SCALE
SHEET
OF
APPLICATION
25:1
1
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2510560
2
2X (1)
A2
2X 1.176
A3
2X 12.32
2X (0.8)
D
C
B
A
D
C
B
A
C
4X 1.485
(2.5)
2.5
B
(1.1)
4X (1)
8
E1
VIEW B
9
A1
DATUMS A, B, C, AND E
1.176
12.32
SCALE 20 : 1
(FROM SHEET 1)
C
2.585
(2.5)
5.17
(2.5)
B
6
VIEW C
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
SCALE 20 : 1
(FROM SHEET 1)
7
2X 0 MIN
VIEW D
ENCAPSULANT MAXIMUM HEIGHT
SCALE 20 : 1
DWG NO
REV
SIZE
DRAWN
DATE
8/3/2009
TEXAS
2510560
B. HASKETT
D
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
8
5
3
6
1
7
4
2510560
3
2
3
(4.8384)
ACTIVE ARRAY
4X (0.0605)
4.483 0.075
1.4380.075
0.862 0.05
D
C
B
A
D
C
B
A
0.242 0.0635
(2.7216)
ACTIVE ARRAY
3.0160.0635
(3.258)
(4.563)
WINDOW
(2.5)
APERTURE
(2.5)
B
3.701 0.05
C
0.244 0.0635
1.0190.05
5.0270.0635
(5.271)
APERTURE
6.727 0.05
(7.746 WINDOW)
VIEW E
WINDOW AND ACTIVE ARRAY
54X TEST PADS
(FROM SHEET 1)
0.2ABC
4
54X 0.5 0.1
0.1A
2X 0.836
20 X 0.66 = 13.2
(0.66) TYP.
0.33 TYP.
(0.572) TYP.
C
3 X 0.572 = 1.716
2X 0.93
(2.5)
1
5
10
15
20 21
(2.5)
2X 0.369
B
2X (1.86)
0.4ABC
(10.2)
2.6
0.4ABC
VIEW F-F
TEST PADS AND CONNECTOR
(FROM SHEET 1)
DWG NO
REV
SIZE
DRAWN
DATE
8/3/2009
TEXAS
2510560
B. HASKETT
D
3
D
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
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