DLP4500NIRAFQD_技术文档

DLP4500NIR

ZHCSJA3B – JANUARY 2019 – REVISED MAY 2022

DLP4500NIR 0.45 WXGA 近红外 DMD

1 特性

2 应用范围

•

0.45 英寸对角线微镜阵列

•

分光计（化学分析）：

– 过程分析仪

– 实验室设备

– 专用分析仪

压缩传感（单像素 NIR 摄像机）

3D 生物识别技术

机器视觉

– 分辨率为 912 × 1140 的阵列（微镜数超过一百

万）

– 菱形阵列定向支持侧面照明，以实现简化高效光

学设计

•

– 能够支持 WXGA 的显示分辨率

– 7.6µm 微镜间距

– ±12° 倾斜角度

红外场景投影

激光打标

– 5µs 微镜交叉时间（标称值）

高效控制近红外光

•

光学斩波器

显微镜

– 窗透射率标称值 96%（700 至 2000nm，单通

光纤网络

道，两个窗面）

– 窗透射率标称值 90%（2000 至 2500nm，单通

道，两个窗面）

3 说明

DLP4500NIR 数字微镜器件 (DMD) 可用作空间光调制

器 (SLM)，以快速、准确且高效地操控近红外 (NIR)

光以及生成图案。由于具有高分频率以及紧凑的外形，

DLP4500NIR DMD 通常与单元件探测器结合使用，可

取代昂贵的基于 InGaAs 阵列的检测器设计，从而提供

高性能、具有成本效益的便携式解决方案。

– 偏振无关型铝制微镜

– 阵列填充因子 92%（标称值）

针对可靠运行的专用 DLPC350 控制器

– 二进制图形速率高达 4kHz

– 图案序列模式，可对阵列内的每个微镜进行控制

集成微镜驱动器电路

•

对于便携式仪器为 9.1mm × 20.7mm

– FQD 封装，具备散热增强型接口

器件型号

封装⁽¹⁾

LCCC (98)

散热接口区域

DLP4500NIR

7.00mm x 7.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

DC Power

Lamp Driver

NIR Lamp

RGB Interface

LVDS Interface

Control

DMD Voltage

Supplies

Processor

USB Interface

I²C Interface

Hardware Triggers

GPIO Interface

FAN

Digital

Pattern

Creation

DLPC350

JTAG

System

Control

DLP4500NIR

Oscillator

Control

Data

简化版应用

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS147

DLP4500NIR

ZHCSJA3B – JANUARY 2019 – REVISED MAY 2022

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Table of Contents

1 特性................................................................................... 1

2 应用范围............................................................................ 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Chipset Component Usage Specification..................... 3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 Storage Conditions..................................................... 8

7.3 ESD Ratings............................................................... 9

7.4 Recommended Operating Conditions.........................9

7.5 Thermal Information..................................................10

7.6 Electrical Characteristics...........................................11

7.7 Timing Requirements................................................12

7.8 System Mounting Interface Loads............................ 14

7.9 Micromirror Array Physical Characteristics...............15

7.10 Micromirror Array Optical Characteristics............... 16

7.11 Typical Characteristics............................................ 17

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................18

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................21

8.5 Micromirror Array Temperature Calculation.............. 21

8.6 Micromirror Landed-on/Landed-Off Duty Cycle........ 23

9 Applications and Implementation................................26

9.1 Application Information............................................. 26

9.2 Typical Application.................................................... 26

10 Power Supply Recommendations..............................31

10.1 Power Supply Sequencing Requirements.............. 31

10.2 DMD Power Supply Power-Up Procedure..............31

10.3 DMD Power Supply Power-Down Procedure......... 31

11 Layout...........................................................................33

11.1 Layout Guidelines................................................... 33

11.2 Layout Example...................................................... 38

12 Device and Documentation Support..........................42

12.1 Device Support....................................................... 42

12.2 Documentation Support.......................................... 42

12.3 接收文档更新通知................................................... 43

12.4 支持资源..................................................................43

12.5 Trademarks.............................................................43

12.6 Electrostatic Discharge Caution..............................43

12.7 术语表..................................................................... 43

13 Mechanical, Packaging, and Orderable

Information.................................................................... 43

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (December 2021) to Revision B (May 2022)

Page

•

Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 8

Updated Micromirror Array Optical Characteristics ......................................................................................... 16

Added Third-Party Products Disclaimer ...........................................................................................................42

Changes from Revision * (January 2019) to Revision A (December 2021)

Page

更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

Updated |T_DELTA| MAX from 30°C to 15°C..........................................................................................................9

•

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5 Chipset Component Usage Specification

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

The DLP4500NIR is a component of one or more DLP^®chipsets. Reliable function and operation of the

DLP4500NIR requires that it be used in conjunction with the other components of the applicable DLP chipset,

including those components that contain or implement TI DMD control technology. TI DMD control technology is

the TI technology and devices for operating or controlling a DLP DMD.

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6 Pin Configuration and Functions

图 6-1. FQD Package LCCC (98) Bottom View

4

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表 6-1. Connector Pins for FQD

INTERNAL

DATA RATE ⁽¹⁾

PACKAGE NET

DESCRIPTION

TYPE

SIGNAL

TERMINATION

LENGTH (mm) ⁽²⁾

NAME

DATA INPUTS

DATA(0)

NO.

A1

A2

A3

A4

B1

B3

C1

C3

C4

D1

D4

E1

E4

F1

F3

G1

G2

G4

H1

H2

H4

J1

Input

LVCMOS

DDR

none

Input data bus, bit 0, LSB

3.77

3.73

3.74

3.79

3.75

3.72

3.75

3.78

3.75

3.77

3.75

3.71

3.76

3.73

3.72

3.77

3.73

3.74

3.76

3.70

3.77

3.76

3.77

3.74

DATA(1)

Input data bus, bit 1

Input data bus, bit 2

Input data bus, bit 3

Input data bus, bit 4

Input data bus, bit 5

Input data bus, bit 6

Input data bus, bit 7

Input data bus, bit 8

Input data bus, bit 9

Input data bus, bit 10

Input data bus, bit 11

Input data bus, bit 12

Input data bus, bit 13

Input data bus, bit 14

Input data bus, bit 15

Input data bus, bit 16

Input data bus, bit 17

Input data bus, bit 18

Input data bus, bit 19

Input data bus, bit 20

Input data bus, bit 21

Input data bus, bit 22

Input data bus, bit 23, MSB

Input data bus clock

DATA(2)

DATA(3)

DATA(4)

DATA(5)

DATA(6)

DATA(7)

DATA(8)

DATA(9)

DATA(10)

DATA(11)

DATA(12)

DATA(13)

DATA(14)

DATA(15)

DATA(16)

DATA(17)

DATA(18)

DATA(19)

DATA(20)

DATA(21)

DATA(22)

DATA(23)

DCLK

J3

J4

K1

DATA CONTROL INPUTS

LOADB

TRC

K2

K4

K3

Input

LVCMOS

DDR

none

Parallel-data load enable

Input-data toggle rate control

Serial-control bus

3.74

4.70

3.75

3.77

SCTRL

Stepped address-control serial-

bus data

SAC_BUS

SAC_CLK

C20

C22

Input

LVCMOS

—

none

Stepped address-control serial-

bus clock

1.49

MIRROR RESET CONTROL INPUTS

DRC_BUS

B21

Input

LVCMOS

—

none

DMD reset-control serial bus

3.73

3.74

Active-low output enable signal

for internal DMD reset driver

circuitry

DRC_OE

A20

Input

Strobe signal for DMD reset-

control inputs

3.73

DRC_STROBE

A22

Input

LVCMOS

—

none

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表 6-1. Connector Pins for FQD (continued)

NAME

INTERNAL

PACKAGE NET

TYPE

SIGNAL

DATA RATE ⁽¹⁾

DESCRIPTION

TERMINATION

LENGTH (mm) ⁽²⁾

NO.

POWER INPUTS ⁽³⁾

VBIAS

C19 Power

D19 Power

A19 Power

K19 Power

E19 Power

F19 Power

B19 Power

Mirror-reset bias voltage

Mirror-reset offset voltage

Mirror-reset voltage

VBIAS

VOFFSET

VRESET

VREF

Power supply for LVCMOS

double-data-rate (DDR)

interface

VREF

J19 Power

VCC

B22 Power

C2 Power

D21 Power

E2

Power

E20 Power

E22 Power

F21 Power

G3 Power

G19 Power

G20 Power

G22 Power

H19 Power

H21 Power

J20 Power

J22 Power

K21 Power

Power supply for LVCMOS logic

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表 6-1. Connector Pins for FQD (continued)

NAME

INTERNAL

PACKAGE NET

TYPE

SIGNAL

DATA RATE ⁽¹⁾

DESCRIPTION

TERMINATION

LENGTH (mm) ⁽²⁾

NO.

VSS

A21 Power

B2

B4

Power

B20 Power

C21 Power

D2 Power

D3 Power

D20 Power

D22 Power

E3

Power

E21 Power

Ground – Common return for all

power inputs

F2

F4

Power

F20 Power

F22 Power

G21 Power

H3 Power

H20 Power

H22 Power

J2

Power

J21 Power

K20 Power

(1)

•

DDR = Double data rate

SDR = Single data rate

Refer to 节 7.7 for specifications and relationships.

(2) Net trace lengths inside the package:

•

Relative dielectric constant for the FQD ceramic package is 9.8.

Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, VRESET.

表 6-2. Test Pads for FQD Package

NAME

SIGNAL

DESCRIPTION

A5, A18, B5, B18, C5, C18, D5, D18, E5,

E18, F5, F18, G5, G18, H5, H18, J5, J18,

K22

UNUSED

Test pads

Do not connect

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGES ⁽²⁾

VCC

Supply voltage for LVCMOS core logic

–0.5

–11

4

V

VREF

Supply voltage for LVCMOS DDR interface

Supply voltage for high voltage CMOS and micromirror electrode

Supply voltage for micromirror electrode

VOFFSET

VBIAS ⁽³⁾

VRESET

8.75

17

Supply voltage for micromirror electrode

0.5

8.75

|VBIAS - VOFFSET| ⁽³⁾Supply voltage delta (absolute value)

INPUT VOLTAGES ⁽²⁾

Input voltage to all other input pins

INPUT CURRENTS

–0.5

VREF + 0.5

V

Current required from a high-level output

Current required from a low-level output

CLOCKS

V_OH= 1.4 V

V_OL= 0.4 V

–9

18

mA

f_CLK

DCLK clock frequency

80

120

MHz

ENVIRONMENTAL

Case temperature - operational ⁽⁴⁾

–20

–40

90

81

95

°C

T_CASE

T_DP

Case temperature - non-operational ⁽⁴⁾

Dew Point (operation and non-operational)

Operating Relative Humidity (non-condensing)

°C

0

%RH

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are referenced to common ground VSS. Supply voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are all

required for proper DMD operation. VSS must also be connected.

(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.

(4) DMD Temperature is the worst-case of any test point shown in or 图 8-3, or the active array as calculated by the Micromirror Array

Temperature Calculation, or any point along the Window Edge as defined in or 图 8-3. The locations of thermal test point TP2 is

intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be

at a higher temperature, a test point should be added to that location.

7.2 Storage Conditions

applicable before the DMD is installed in the final product

MIN

–40

0

MAX

85

UNIT

°C

Storage temperature ⁽¹⁾

Storage humidity, non-condensing ⁽¹⁾

Long-term storage dew point ^{(1) (2)}

Short-term storage dew point ^{(1) (3)}

95%

24

RH

°C

T_stg

28

°C

(1) As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment.

(2) Long-term is defined as the average over the usable life.

(3) Short-term is defined as <60 cumulative days over the usable life of the device.

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7.3 ESD Ratings

VALUE

UNIT

Electrostatic

discharge

V_(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001^{(1) (2) (3)}

±2000

V

(1) ESD Ratings are applicable before the DMD is installed in final product.

(2) All CMOS devices require proper Electrostatic Discharge (ESD) handling procedures.

(3) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGES

VCC

Supply voltage for LVCMOS core logic

2.375

1.6

2.5

1.9

8.5

16

2.625

2

V

VREF

Supply voltage for LVCMOS DDR interface

Supply voltage for HVCMOS and micromirror electrode

Supply voltage for micromirror electrode

VOFFSET

VBIAS

8.25

15.5

–9.5

8.75

16.5

–10.5

VRESET

Supply voltage for micromirror electrode

–10

|VBIAS –

VOFFSET|

Supply voltage delta (absolute value)

8.75

V

VOLTAGE RANGE

V_T+

V_T–

V_hys

Positive-going threshold voltage

Negative-going threshold voltage

Hysteresis voltage (V_T+– V_T–

0.4 × VREF

0.3 × VREF

0.1 × VREF

0.7 × VREF

0.6 × VREF

0.4 × VREF

V

)

CLOCK FREQUENCY

ƒ_(CLK)

DCLK clock frequency

80

120

MHz

ENVIRONMENTAL

DMD temperature - operational, long-term

DMD temperature - operational, short-term

DMD window temperature - operational

10

–20

0

40 to 70

70

°C

T_DMD

T_Window

90

T_CERAMIC-

DMD |ceramic - window| temperature delta - operational

0

15

°C

WINDOW-DELTA

DMD long-term dewpoint (operational, non-operational)l

DMD short-term dewpoint (operational, non-operational)

24

28

°C

ILLUMINATION

ILL_UV-VIS

Illumination power - spectral region <700 nm

0.68 mW/cm²

Thermally

Limited

10 mW/cm²

Illumination power - spectral region 700 to 2500 nm, FQD

package

ILL_NIR

mW/cm²

ILL_MWIR

Illumination power - spectral region >2500 nm

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80

70

60

50

40

30

0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

100/0 95/5

D001

Micromirror Landed Duty Cycle

图 7-1. Maximum Recommended DMD Temperature – Derating Curve

7.5 Thermal Information

DLP4500NIR

FQD (LCCC)

98 PINS

2

THERMAL METRIC

UNIT

Thermal resistance - Active area to case ceramic ⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on

the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed

by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy

falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the

device.

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7.6 Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

I_IL

Low-level input current ⁽¹⁾

High-level input current ⁽¹⁾

VREF = 2.00 V, V_I= 0 V

–50

nA

I_IH

VREF = 2.00 V, V_I= VREF

50

nA

CURRENT

I_REF

Current into VREF pin

Current into VCC pin

VREF = 2.00 V, f_DCLK= 120 MHz

VCC = 2.75 V, f_DCLK= 120 MHz

2.15

125

2.75

160

mA

I_CC

VOFFSET = 8.75 V, Three global resets

within time period = 200 μs

I_OFFSET

I_BIAS

Current into VOFFSET pin ⁽²⁾

3

3.3

6.5

mA

VBIAS = 16.5 V, Three global resets within

time period = 200 μs

Current into VBIAS pin ^{(2) (3)}

Current into VRESET pin

2.55

I_RESET

I_TOTAL

POWER

P_REF

VRESET = –10.5 V

2.45

3.1

mA

135.15

175.65

Power into VREF pin ⁽⁴⁾

Power into VCC pin ⁽⁴⁾

VREF = 2.00 V, f_DCLK= 120 MHz

VCC = 2.75 V, f_DCLK= 120 MHz

4.15

5.5

mW

P_CC

343.75

440

P_OFFSET

VOFFSET = 8.75 V, Three global resets

within time period = 200 μs

Power into VOFFSET pin ⁽⁴⁾

26.25

42.1

28.9

58.6

mW

P_BIAS

VBIAS = 16.5 V, Three global resets within

time period = 200 μs

Power into VBIAS pin ⁽⁴⁾

Power into VRESET pin ⁽⁴⁾

P_RESET

P_TOTAL

CAPACITANCE

VRESET = –10.5 V

25.71

442

32.6

566

mW

C_I

Input capacitance

Output capacitance

ƒ = 1 MHz

10

pF

C_O

(1) Applies to LVCMOS pins only. LVCMOS pins do not have pullup or pulldown configurations.

(2) Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excess current draw. See

the 节 7.1 for further details.

(3) When DRC_OE = HIGH, the internal reset drivers are tri-stated and I_BIASstandby current is 6.5 mA.

(4) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the 节 8.5 for

further details.

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7.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted). This data sheet provides timing at the device pin.

MIN

0.7

1

NOM

MAX

UNIT

Setup time: DATA before rising or falling edge of DCLK ⁽¹⁾

Setup time: TRC before rising or falling edge of DCLK ⁽¹⁾

Setup time: SCTRL before rising or falling edge of DCLK ⁽¹⁾

Setup time: LOADB low before rising edge of DCLK ⁽¹⁾

Setup time: SAC_BUS low before rising edge of SAC_CLK ⁽¹⁾

Setup time: DRC_BUS high before rising edge of SAC_CLK ⁽¹⁾

Setup time: DRC_STROBE high before rising edge of SAC_CLK ⁽¹⁾

Hold time: DATA after rising or falling edge of DCLK ⁽¹⁾

Hold time: TRC after rising or falling edge of DCLK ⁽¹⁾

Hold time: SCTRL after rising or falling edge of DCLK ⁽¹⁾

Hold time: LOADB low after falling edge of DCLK ⁽¹⁾

Hold time: SAC_BUS low after rising edge of SAC_CLK ⁽¹⁾

Hold time: DRC_BUS after rising edge of SAC_CLK ⁽¹⁾

Hold time: DRC_STROBE after rising edge of SAC_CLK ⁽¹⁾

Rise time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V

Rise time (20% to 80%): DATA / TRC / SCTRL / LOADB, VREF = 1.8 V

Fall time (20% to 80%): DCLK / SAC_CLK, VREF = 1.8 V

Fall time (20% to 80%): DATA / TRC / SCTRL / LOADB

Clock cycle: DCLK

t_su(1)

ns

t_su(2)

t_su(3)

t_su(4)

t_su(5)

ns

1

2

0.7

1

t_h(1)

ns

t_h(2)

t_h(3)

t_h(4)

t_h(5)

ns

1

2

1.08

12.5

14.3

t_r

t_f

ns

t_c1

8.33

12.5

3.33

4.73

5

10

ns

t_c3

Clock cycle: SAC_CLK

13.33

t_w1

t_w2

t_w3

t_w5

Pulse width high or low: DCLK

Pulse width low: LOADB

Pulse width high or low: SAC_CLK

Pulse width high: DRC_STROBE

7

(1) Setup and hold times shown are for fast input slew rates >1 V/ns. For slow slew rates >0.5 V/ns and <1 V/ns, the setup and hold times

are longer. For every 0.1 V/ns decrease in slew rate from 1 V/ns, add 150 ps on setup and hold.

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图 7-2. Timing Diagram

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7.8 System Mounting Interface Loads

MIN

NOM

MAX

UNIT

Uniformly distributed over

Thermal Interface area

Load applied to the thermal interface area ⁽¹⁾

FQD

62

55

N

package

Load applied to the electrical interface areas (2)

Uniformly distributed over each of

the two areas

N

(1)

(1) See and 图 7-3 for diagrams.

(2) See Mounting Concepts DLP4500FQD.

Datum 'A' area (3 places)

Datum 'E' area (1 place)

Thermal Interface Area

Electrical Interface

Area Number 1

Electrical Interface

Area Number 2

图 7-3. System Interface Loads for FQD

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7.9 Micromirror Array Physical Characteristics

VALUE

1140

912

UNIT

micromirrors

µm

Number of active micromirror rows ⁽²⁾

Number of active micromirror columns ⁽²⁾

Micromirror pitch, diagonal ⁽²⁾

7.6

Micromirror pitch, vertical and horizontal ⁽²⁾

10.8

1140

6161.4

912

µm

micromirrors

µm

Micromirror active array height ⁽³⁾

micromirrors

µm

Micromirror active array width ⁽³⁾

Micromirror array border ⁽¹⁾

9855

10

mirrors/side

(1) The mirrors that form the array border are hard-wired to tilt in the –12° (“Off”) direction once power is applied to the DMD (see

Micromirror Array, Pitch, and Hinge-Axis Orientation and Micromirror Landed Positions and Light Paths).

(2) See Micromirror Array, Pitch, and Hinge-Axis Orientation.

(3) See Micromirror Active Area in 图 7-4.

图 7-4. DLP4500NIR Micromirror Active Area

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7.10 Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical

performance involves making trade-offs between numerous component and system design parameters. See the related

application reports in 节 12.2.1 for guidelines.

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DMD parked state ^{(1) (3) (4)}, see ⁽¹⁰⁾

DMD landed state ^{(1) (5) (6)}, see ⁽¹⁰⁾

0

α

β

Micromirror tilt angle

degrees

11

–1

12

13

Micromirror tilt angle variation ⁽¹⁾

See ⁽¹⁰⁾

1

degrees

(5) (7) (8) (9)

Micromirror crossover time ^{(2) (11)}

Micromirror switching time ⁽¹¹⁾

5

μs

16

Orientation of the micromirror

axis-of-rotation ⁽¹²⁾

89

90

92%

89%

91

degrees

Micromirror array fill factor ^{(13) (14)}f/3 illumination at 24 degree angle,

(17)

mirrors tilted toward illumination

Mirror metal specular reflectivity

700 nm to 2500 nm

(13) (14)

Window material

Corning Eagle XG

See ⁽¹⁵⁾

Window aperture

Illumination overfill ⁽¹⁶⁾

See ⁽¹⁶⁾

Window transmittance (single

pass through two window

surfaces) ^{(13) (14)}

2000 nm to 2500 nm, See 图 7-5

90%

Bright pixel(s) in active area ⁽¹⁹⁾

Bright pixel(s) in the POM ⁽²¹⁾

Gray 10 Screen ⁽²⁰⁾

0

1

4

0

Image

performance⁽¹⁸⁾

Dark pixel(s) in the active area ⁽²²⁾White Screen

micromirrors

Adjacent pixel(s) ⁽²³⁾

Any Screen

Unstable pixel(s) in active area

0

(24)

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.

(3) Parking the micromirror array returns all of the micromirrors to a relatively flat (0°) state (as measured relative to the plane formed by

the overall micromirror array).

(4) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.

(5) Additional variation exists between the micromirror array and the package datums.

(6) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS

memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular

position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.

(7) Represents the landed tilt angle variation relative to the nominal landed tilt angle

(8) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(9) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations or system contrast variations.

(10) See 图 8-2.

(11) Performance as measured at the start of life.

(12) Measured relative to the package datums B and C, shown in the Package Mechanical Data section in 节 13.

(13) The nominal DMD total optical efficiency results from the following four components:

•

Micromirror array fill factor

Micromirror array diffraction efficiency

Micromirror surface reflectivity (very similar to the reflectivity of bulk Aluminum)

Window Transmission (single pass through two surfaces for incoming light, and single pass through two surfaces for reflected light)

(14) The DMD diffraction efficiency and total optical efficiency observed in a specific application depends on numerous application-specific

design variables, such as:

•

Illumination wavelength, bandwidth or line-width, degree of coherence

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•

Illumination angle, plus angle tolerence

Illumination and projection aperture size, and location in the system optical path

Illumination overfill of the DMD micromirror array

Aberrations present in the illumination source or path, or both

Aberrations present in the projection path

Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle

represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical

projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array

update rate.

(15) See the Package Mechanical Characteristics in 节 13 for details regarding the size and location of the window aperture.

(16) The active area of the DLP4500NIR device is surrounded by an aperture on the inside of the DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light

illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the

DMD. Design the illumination optical system as to limit light flux incident outside the active array to less than 10% of the light flux level

in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the

outside of the active array may cause system performance degradation .

(17) The Micromirror array fill factor depends on numerous application-specific design variables, such as:

•

Illumination angle, plus angle tolerance

Illumination and projection aperture size, and location in the system optical path

(18) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

(19) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(20) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(21) POM definition: Rectangular border of off-state mirrors surrounding the active area

(22) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(23) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(24) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

7.11 Typical Characteristics

Angle of incidence = 0°

Single pass through two window surfaces

100

95

90

85

80

75

70

65

60

Nominal

Minimum

700 900 1100 1300 1500 1700 1900 2100 2300 2500

Wavelength (nm)

D001

图 7-5. DLP4500NIR DMD Window Transmittance

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8 Detailed Description

8.1 Overview

Electrically, the DLP4500NIR device consists of a two-dimensional array of 1-bit CMOS memory cells, organized

in a grid of 912 memory cell columns by 1140 memory cell rows. The CMOS memory array is addressed on a

column-by-column basis, over a 24-bit DDR bus. Addressing is handled through a serial control bus. The specific

CMOS memory access protocol is handled by the DLPC350 digital controller.

Optically, the DLP4500NIR device consists of 1039680 highly reflective, digitally switchable, micrometer-sized

mirrors (micromirrors) organized in a two-dimensional array. The micromirror array consists of 912 micromirror

columns by 1140 micromirror rows in diamond pixel configuration (图 8-1). Due to the diamond pixel

configuration, the columns of each odd row are offset by half a pixel from the columns of the even row.

8.2 Functional Block Diagram

High Speed Interface

Misc

Column Write

Control

Bit Lines

(0,0)

Word Lines

Voltages

Voltage

Generators

Micromirror Array

Row

(911,1139)

Control

Column Read

Control

Low Speed Interface

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8.3 Feature Description

Each aluminum micromirror is approximately 7.6 microns in size and arranged in row and columns as shown in

图 8-1. Due to the diamond pixel array of the DMD, the pixel data does not appear on the DMD exactly as it

would in an orthogonal pixel arrangement. Pixel arrangement and numbering for the DLP4500NIR is shown in 图

8-1.

Each micromirror is switchable between two discrete angular positions: –12° and 12°. The angular positions α

and β are measured relative to a 0° flat reference when the mirrors are parked in their inactive state, parallel

to the array plane (see 图 8-2). The parked position is not a latched position. Individual micromirror angular

positions are relatively flat, but do vary. The tilt direction is perpendicular to the hinge-axis. The on-state landed

position is directed toward the left side of the package (see 图 8-2).

图 8-1. Micromirror Array, Pitch, and Hinge-Axis Orientation

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图 8-2. Micromirror Landed Positions and Light Paths

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Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of

a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory

cell contents, after the mirror clocking pulse is applied. The angular position (–12° or 12°) of the individual

micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking

pulse results in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell

followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12° position.

Updating the angular position of the micromirror array consists of two steps.

1. Update the contents of the CMOS memory.

2. Applying a mirror clocking pulse to the entire micromirror array.

Mirror reset pulses are generated internally by the DLP4500NIR DMD, with initiation of the pulses being

coordinated by the DLPC350 controller. For timing specifications, see 节 7.7.

Around the perimeter of the 912 × 1140 array of micromirrors is a uniform band of border micromirrors. The

border micromirrors are not user-addressable. The border micromirrors land in the –12° position after power has

been applied to the device. There are 10 border micromirrors on each side of the 912 × 1140 active array.

8.4 Device Functional Modes

DLP4500NIR is part of the chipset comprising of the DLP4500NIR DMD and DLPC350 display controller. To

ensure reliable operation, the DLP4500NIR DMD must always be used with the DLPC350 display controller.

DMD functional modes are controlled by the DLPC350 digital display controller. See the DLPC350 data sheet

listed in 节 12.2.1.

8.4.1 Operating Modes

The DLPC350 is capable of sending patterns to the DLP4500NIR DMD in two different streaming modes.

The first mode is continuous streaming mode, where the DLPC350 uses the parallel RGB interface to stream

the 24-bit patterns to the DMD. The second mode is burst mode, where the DLPC350 loads up to 48 binary

patterns from flash storage into internal memory, and then streams those patterns to the DMD. 表 8-1 shows the

maximum pattern and data rates for both modes of operation.

表 8-1. Pattern and Data Rates

OPERATING MODE

Continuous Streaming⁽¹⁾

Burst⁽²⁾

PATTERN RATE (Hz)

DATA RATE (Gbps)

MAXIMUM BINARY PATTERNS

2880

4220

2.99

4.39

Unlimited

48

(1) Continuous streaming mode uses patterns from RGB interface.

(2) Burst mode uses patterns from internal memory.

8.5 Micromirror Array Temperature Calculation

Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the

maximum temperature of any individual micromirror in the active array, the maximum temperature of the window

aperture, and the temperature gradient between any two points on or within the package.

See the 节 7.1 and 节 7.4 for applicable temperature limits.

8.5.1 Package Thermal Resistance

The DMD is designed to conduct the absorbed and dissipated heat back to the package where it can be

removed by an appropriate thermal management system. The thermal management system must be capable of

maintaining the package within the specified operational temperatures at the Thermal test point location, see 图

8-3. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although

other contributions can include light energy absorbed by the window aperture, electrical power dissipation of the

array, and/or parasitic heating.

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8.5.2 Case Temperature

The temperature of the DMD case can be measured directly. For consistency, a thermal test point location TP1

representing the case temperature is defined as shown in and 图 8-3.

图 8-3. Thermal Test Point Location - FQD Package

8.5.2.1 Temperature Calculation

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically using one

or more of these conditions:

•

Thermal test point location (see or 图 8-3)

Package thermal resistance

Electrical power dissipation

Illumination heat load

The relationship between the micromirror array and the case temperature is provided by the following equations:

T_Array= T_Ceramic+ (Q_Array× R_{Array-To-Ceramic}

Q_Array= Q_Elec+ Q_Illum

Q_Illum= P_D× A × DMD Absorption Constant

)

(1)

(2)

(3)

where

•

T_Array= Computed micromirror array temperature (°C)

T_Ceramic= Ceramic case temperature (°C), located at TP1

Q_Array= Total (electrical + absorbed) DMD array power (W)

R_{Array-to-Ceramic}= Thermal resistance of DMD package from array to TP1 (°C/W)

Q_Elec= Nominal electrical power (W)

Q_Illum= Absorbed illumination heat (W)

P_D= Illumination power density

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•

A = Illumination area on DMD

An example calculation is provided in 方程式 4 and 方程式 5. DMD electrical power dissipation varies and

depends on the voltage, data rates, and operating frequencies. The nominal electrical power dissipation is

used in this calculation with a power density of 2 W/cm², an illumination area of 0.725

cm², and a ceramic case temperature at TP1 of 55°C. The DMD absorption constant of

0.42 assumes nominal operation with an illumination distribution of 83.7% on the

active array, 11.9% on the array border, and 4.4% on the window aperture. A system

aperture may be required to limit power incident on the package aperture since

this area absorbs much more efficiently than the array . Using these values in the previous

equations, the following values are computed:

Q_Array= Q_Elec+ Q_Illum= 0.442 W + (2 W/cm²× 0.725 cm²× 0.42) = 1.05 W

T_Array= T_Ceramic+ (Q_Array× R_{Array-To-Ceramic}) = 55°C + ( 1.05 W × 2°C/W) = 57.1°C

(4)

(5)

8.6 Micromirror Landed-on/Landed-Off Duty Cycle

8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On–state versus the amount of time the same

micromirror is landed in the Off–state.

As an example, a landed duty cycle of 75/25 indicates that the referenced micromirror is in the On–state 75%

of the time (and in the Off–state 25% of the time); whereas 25/75 would indicate that the micromirror is in the

On–state 25% of the time. Likewise, 50/50 indicates that the micromirror is On 50% of the time and Off 50% of

the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

8.6.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD’s usable life.

The symmetry of the landed duty cycle is determined by how close the On-state and Off-state percentages are

to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle

of 100/0 or 0/100 is perfectly asymmetrical.

For extended useful lifetime of the DMD, it is strongly recommended not to put any individual pixel in a 100/0 or

0/100 duty cycle for prolonged periods of time. It’s recommended as much as possible to put the DMD in a 50/50

duty cycle across the entire DMD mirror array, where all the mirrors are continuously flipped between the on and

off states. A few examples when the DMD could be in a 50/50 duty cycle mode include: when the system is idle,

the illumination is disabled, between sequential pattern exposures, or when the exposure pattern sequence is

stopped for any reason.

8.6.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life, and this interaction

can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s usable life. This

is quantified in the de-rating curve shown in 图 7-1. The importance of this curve is that:

•

All points along this curve represent the same usable life.

All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

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•

All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed

duty cycle.

8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given micromirror follows from the image content being

displayed by that micromirror.

For example, in the simplest case, when displaying pure-white on a given micromirror for a given time period,

that micromirror experiences a 100/0 landed duty cycle during that time period. Likewise, when displaying

pure-black, the micromirror experiences a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the linear gray scale value, as shown in 表 8-2.

表 8-2. Grayscale Value and Landed Duty Cycle

NOMINAL LANDED DUTY

GRAYSCALE VALUE

CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given micromirror as well as the

color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given micromirror can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%

(6)

×

Blue_Scale_Value)

where

•

Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,

Green, and Blue are displayed (respectively) to achieve the desired white point.

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue

color intensities would be as shown in 表 8-3.

When used with a single near-IR LED, the landed duty cycle of the DLP4500NIR device depends on the single

LED cycle time and the scale value.

For example, assume the LED cycle time is 100% and the scale value is 80%, then the landed duty cycle is

80/20.

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表 8-3. Example Landed Duty Cycle for Full-Color

RED CYCLE PERCENTAGE

50%

GREEN CYCLE PERCENTAGE

20%

BLUE CYCLE PERCENTAGE

NOMINAL LANDED DUTY

CYCLE

30%

RED SCALE VALUE

GREEN SCALE VALUE

BLUE SCALE VALUE

0%

100%

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

0%

60%

100%

12%

100%

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9 Applications and Implementation

备注

以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

For reliable operation, the DLP4500NIR DMD must be coupled with the DLPC350 controller. The DMD is a

spatial light modulator which reflects incoming light from an illumination source to one of two directions, with the

primary direction being into a projection or collection optic. Each application is derived primarily from the optical

architecture of the system and the format of the data coming into the DLPC350. Applications of interest include

3D measurement systems, spectrometers, medical systems, and compressive sensing.

9.2 Typical Application

图 9-1 shows a typical embedded system application using the DLPC350 controller and DLP4500NIR DMD.

In this configuration, the DLPC350 controller supports a 24-bit parallel RGB input from an external source or

processor. In this system, the external processor controls the near-IR lamp and sends structured light patterns

to the DLPC350. The near-IR radiation is projected through a liquid sample where the non-absorbed spectra

is transmitted through an entrance slit and onto a diffraction grating. Diffracted light of varying wavelengths is

then focused onto the DMD. The DLPC350 uses patterns to scan across the DMD thereby selecting specific

wavelengths of light which are then focused onto a single point InGaAs detector. The external processor

samples the outputs of the InGaAs detector to create an absorbance curve of the sample.

Lamp Enable

DC Power

Lamp Driver

NIR Lamp

RGB Interface

LVDS Interface

USB Interface

Control

Processor

Sample

DMD Voltage Supplies

Focusing Lens

Slit

I²C Interface

Hardware Triggers

GPIO Interface

Digital

Pattern

Creation

DLPC350

Colluminating Lens

System

Control

Oscillator

FLASH

DLP4500NIR

Control

Data

Diffraction Grating

Focusing

Lens

Selected Wavelength by DMD

Collecting Lens

FAN

JTAG

Single Point

InGaAs Detector

ADC

图 9-1. Typical Application Schematic

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9.2.1 Design Requirements

All applications using the DLP4500NIR chipset require both the controller and DMD components for operation.

The system also requires an external parallel flash memory device loaded with the DLPC350 configuration and

support firmware. The chipset has several system interfaces and requires some support circuitry. The following

interfaces and support circuitry are required:

•

DLPC350 system interfaces:

– Control interface

– Trigger interface

– Input data interface

– Illumination interface

•

DLPC350 support circuitry and interfaces:

– Reference clock

– PLL

– Program memory flash interface

DMD interfaces:

– DLPC350 to DMD digital data

– DLPC350 to DMD control interface

– DLPC350 to DMD micromirror reset control interface

9.2.2 Detailed Design Procedure

9.2.2.1 DLPC350 System Interfaces

The DLP4500NIR chipset supports a 30-bit parallel RGB interface for image data transfers from another device

and a 30-bit interface for video data transfers. The system input requires proper generation of the PWRGOOD

and POSENSE inputs to ensure reliable operation. The two primary output interfaces are the illumination driver

control interface and sync outputs.

9.2.2.1.1 Control Interface

The DLP4500NIR chipset accepts control interface commands via the I²C or USB input buses. The control

interface allows another master processor to send commands to the DLP4500NIR chipset to query system

status or perform realtime operations such as programming LED driver current settings.

The DLPC350 controller offers two different sets of slave addresses. The I2C_ADDR_SEL pin provides the

ability to select an alternate set of 7-bit I²C slave addresses only during power-up. If the I2C_ADDR_SEL pin is

set low (logic '0'), then the DLPC350 slave addresses are 0x34 and 0x35. If the I2C-ADDR_SEL pin is set high

(logic '1'), then the DLPC350 slave address is 0x3A and 0x3B. The I2C_ADDR_SEL pin also changes the serial

number for the USB device so that two DLPC350s can be connected to one computer through USB. Once the

system initialization is complete, this pin is available as a GPIO. See the DLPC350 Programmer's Guide (listed

in 节 12.2.1) for detailed information about these operations.

表 9-1 lists a description for active signals used by the DLPC350 to support the I²C interface.

表 9-1. Active Signals – I²C Interface

Signal Name

Description

I²C clock. Bidirectional open-drain signal. I²C slave clock input from the external

processor.

I2C1_SCL

I²C data. Bidirectional open-drain signal. I²C slave to accept command or transfer

data to and from the external processor.

I2C1_SDA

I2C0_SCL

I2C0_SDA

I²C bus 0, clock; I²C master for on-board peripherals

I²C bus 0, data; I²C master for on-board peripherals

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9.2.2.1.2 Input Data Interface

The data interface has two input data ports: a parallel RGB-input port and an FPD-Link LVDS input port. Both

input ports can support up to 30 bits and have a nominal I/O voltage of 3.3 V. See the DLPC350 controller data

sheet (listed in 节 12.2.1) for details relating to maximum and minimum input timing specifications.

The parallel RGB port can support up to 30 bits in video mode. In pattern mode, only the upper 8 bits of each

color are recognized, thereby creating a 24 bit bus from the 30 bit input bus.

The FPD-Link input port can be configured to connect to a video decoder device or an external processor

through a 24-, 27-, or 30-bit interface.

表 9-2 provides a description of the signals associated with the data interface.

表 9-2. Active Signals – Data Interface

SIGNAL NAME

RGB Parallel Interface

P1_(A, B, C)_[0:9]

DESCRIPTION

30-bit data inputs 10 bits for each of the red, green, and blue channels). If

interfacing to a system with less than 10-bits per color, connect the bus of the

red, green, and blue channels to the upper bits of the DLPC350 10-bit bus.

P1A_CLK

P1_VSYNC

P1_HSYNC

P1_DATAEN

FPD-Link LVDS Input

RCK

Pixel clock; all input signals on data interface are synchronized with this clock.

Vertical sync

Horizontal sync

Input data valid

Differential input signal for clock

RA_IN

Differential input signal for data channel A

Differential input signal for data channel B

Differential input signal for data channel C

Differential input signal for data channel D

Differential input signal for data channel E

RB_IN

RC_IN

RD_IN

RE_IN

The A, B, and C input data channels of Port 1 can be internally swapped for optimum board layout.

9.2.2.2 DLPC350 System Output Interfaces

9.2.2.2.1 Illumination Interface

An illumination interface is provided that supports an LED driver with up to 3 individual channels.

表 9-3 describes the active signals for the illumination interface.

When the DLP4500NIR is used with a single near-IR LED, then one of the three LED enables can be used to

drive the near-IR LED. The user can also disable all the LED enables and allow an external processor to control

the near-IR LED.

表 9-3. Active Signals – Illumination Interface

SIGNAL NAME

HEARTBEAT

FAULT_STATUS

LEDR_EN

DESCRIPTION

LED blinks continuously to indicate system is running fine

LED off indicates system fault

Red LED enable

LEDG_EN

Green LED enable

LEDB_EN

Blue LED enable

LEDR_PWM

LEDG_PWM

LEDB_PWM

Red LED PWM signal used to control the LED current

Green LED PWM signal used to control the LED current

Blue LED PWM signal used to control the LED current

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9.2.2.2.2 Trigger Interface (Sync Outputs)

The DLPC350 controller outputs a set of trigger signals for synchronizing displayed patterns with a camera,

sensor, or other peripherals. The DLPC350 also has input triggers, where an external processor controls when

the patterns are displayed.

表 9-4. Active Signals – Trigger and Sync Interface

SIGNAL NAME

P1_HSYNC

DESCRIPTION

Horizontal sync

Vertical sync

P1_VSYNC

Advances the pattern display or displays two alternating patterns, depending on

the mode

TRIG_IN_1

TRIG_IN_2

Pauses the pattern display or advances the pattern by two, depending on the

mode

TRIG_OUT_1

TRIG_OUT_2

Active high during pattern exposure

Active high to indicate first pattern display

9.2.2.3 DLPC350 System Support Interfaces

9.2.2.3.1 Reference Clock

The DLPC350 controller requires a 32-MHz 3.3-V external input from an oscillator. This signal serves as the

DLP4500NIR chipset reference clock from which the majority of the interfaces derive their timing. This includes

DMD interfaces and serial interfaces.

9.2.2.3.2 PLL

The DLPC350 controller contains two PLLs (PLLM and PLLD), each of which have dedicated 1.2-V digital and

1.8-V analog supplies. These 1.2-V PLL pins must be individually isolated from the main 1.2-V system supply via

a ferrite bead. The impedance of the ferrite bead must be much greater than the capacitor at frequencies where

noise is expected. The impedance of the ferrite bead must also be less than 0.5 Ω in the frequency range of 100

to 300 kHz and greater than 10 Ω at frequencies greater than 100 MHz.

Isolate the 1.8-V analog PLL power and ground pins as a minimum, using an LC filter with a ferrite bead serving

as the inductor and a 0.1-µF capacitor on the DLPC350 side of the ferrite bead. TI recommends that this 1.8-V

PLL power be supplied from a dedicated linear regulator and each PLL should be individually isolated from the

regulator. The same ferrite recommendations described for the 1.8-V analog PLL supply apply to the 1.2-V digital

PLL supply.

When designing the overall supply filter network, care must be taken to ensure that no resonances occur. Take

special care when using the 1- to 2-MHz band because this coincides with the PLL natural loop frequency.

9.2.2.3.3 Program Memory Flash Interface

The DLPC350 controller provides two external program memory chip selects:

•

PM_CS_1 must be used as the chip select for the boot flash device. (Standard NOR Flash ≤ 128 Mb).

PM_CS_2 is available for an optional flash device (≤128 Mb).

The flash access timing is fixed at 100.5 ns for read timing, and 154.1 ns for write timing. In standby mode, these

values change to 803.5 ns for read timing and 1232.1 ns for write timing.

These timing values assume a maximum single direction trace length of 75 mm. When an additional flash is

used in conjunction with the boot flash, stub lengths must be kept short and located as close as possible to the

flash end of the route.

The DLPC350 controller provides enough program memory address pins to support a flash device up to 128 Mb.

PM_ADDR_22 and PM_ADDR_21 are tri-stated GPIO pins during reset, so they require board-level pulldown

resistors to prevent the flash address bits from floating during initial bootload.

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9.2.2.4 DMD Interfaces

9.2.2.4.1 DLPC350 to DMD Digital Data

The DLPC350 controller provides the pattern data to the DMD over a double data rate (DDR) interface. Data is

clocked on both rising and falling edges of the DCLK.

表 9-5 describes the signals used for this interface.

表 9-5. Active Signals – DLPC350 to DMD Digital Data Interface

DLPC350 SIGNAL NAME

DMD SIGNAL NAME

DMD_D(23:0)

DATA(23:0)

DMD_DCLK

DCLK

9.2.2.4.2 DLPC350 to DMD Control Interface

The DLPC350 controller provides the control data to the DMD over a serial bus.

表 9-6 describes the signals used for this interface.

表 9-6. Active Signals – DLPC350 to DMD Control Interface

DLPC350

SIGNAL NAME

DMD

SIGNAL NAME

DESCRIPTION

DMD_SAC_BUS

DMD_SAC_CLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

SAC_BUS

SAC_CLK

LOADB

SCTRL

TRC

DMD stepped-address control (SAC) bus data

DMD stepped-address control (SAC) bus clock

DMD data load signal

DMD data serial control signal

DMD data toggle rate control

9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface

The DLPC350 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the

DMD.

表 9-7 describes the signals used for this interface.

表 9-7. Active Signals – DLPC350 to DMD Micromirror Reset Control Interface

DLPC350

SIGNAL NAME

DMD

SIGNAL NAME

DESCRIPTION

DMD_DRC_BUS

DMD_DRC_OE

DRC_BUS

DRC_OE

DMD reset control serial bus

DMD reset control output enable

DMD reset control strobe

DMD_DRC_STRB

DRC_STRB

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10 Power Supply Recommendations

10.1 Power Supply Sequencing Requirements

The DLP4500NIR DMD includes five voltage-level supplies (V_CC, V_REF, V_OFFSET, V_BIAS, and V_RESET), all

referenced to VSS ground. For reliable operation of the DLP4500NIR DMD, the following power supply

sequencing requirements must be followed.

CAUTION

Reliable performance of the DMD requires that the following conditions be met:

1. The V_CC, V_REF, V_OFFSET, V_BIAS, and V_RESETpower supply inputs must all be present during

operation. All voltages must be referenced to DMD ground (VSS).

2. The V_CC, V_REF, V_OFFSET, V_BIAS, and V_RESETpower supplies must be sequenced on and off in the

manner prescribed.

Repeated failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability

10.2 DMD Power Supply Power-Up Procedure

1. Power up V_CCand V_REFin any order.

2. Wait for V_CCand V_REFto each reach a stable level within their respective recommended operating ranges.

3. Power up V_BIAS, V_OFFSET, and V_RESETin any order, provided that the maximum delta-voltage between V_BIAS

and V_OFFSETis not exceeded (see 节 7.1 for details).

备注

During the power-up procedure, the DMD LVCMOS inputs should not be driven high until after

step 2 is complete.

备注

Power supply slew rates during power up are unrestricted, provided that all other conditions

are met.

10.3 DMD Power Supply Power-Down Procedure

1. Command the chipset controller to execute a mirror-parking sequence. See the controller data sheet (listed

in 节 12.2.1) for details.

2. Power down V_BIAS, V_OFFSET, and V_RESETin any order, provided that the maximum delta voltage between

V_BIASand V_OFFSETis not exceeded (see 节 7.1 for details).

3. Wait for V_BIAS, V_OFFSET, and V_RESETto each discharge to a stable level within 4 V of the reference ground.

4. Power down V_CCand V_REFin any order.

备注

During the power-down procedure, the DMD LVCMOS inputs should be held at a level less than

V_REF+ 0.3 V.

备注

Power-supply slew rates during power down are unrestricted, provided that all other

conditions are met.

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图 10-1. Power-Up and Power-Down Timing

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11 Layout

11.1 Layout Guidelines

11.1.1 DMD Interface Design Considerations

The DMD interface is modeled after the low-power DDR-memory (LPDDR) interface. To minimize power

dissipation, the LPDDR interface is defined to be unterminated. As a result, PCB signal-integrity management

is imperative. Impedance control and crosstalk mitigation is critical to robust operation. LPDDR board design

recommendations include trace spacing that is three times the trace width, impedance control within 10%, and

signal routing directly over a neighboring reference plane (ground or 1.9-V plane).

DMD interface performance is also a function of trace length; therefore the length of the trace limits performance.

The DLPC350 controller only works over a narrow range of DMD signal routing lengths at 120 MHz. Ensuring

positive timing margins requires attention to many factors.

As an example, the DMD interface system timing margin can be calculated as follows.

Setup Margin = (DLPC350 Output Setup) – (DMD Input Setup) – (PCB Routing Mismatch) – (PCB SI Degradation)

Hold-Time Margin = (DLPC350 Output Hold) – (DMD Input Hold) – (PCB Routing Mismatch) – (PCB SI Degradation)

(7)

(8)

PCB signal integrity degradation can be minimized by reducing the affects of simultaneously switching output

(SSO) noise, crosstalk, and inter-symbol interface (ISI). Additionally, PCB routing mismatch can be budgeted via

controlled PCB routing.

In an attempt to minimize the need for signal integrity analysis that would otherwise be required, the following

PCB design guidelines are provided. They describe an interconnect system that satisfies both waveform quality

and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from

these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements.

11.1.2 DMD Termination Requirements

表 11-1 lists the termination requirements for the DMD interface. These series resistors should be placed as

close to the DLPC350 pins as possible while following all PCB guidelines.

表 11-1. Termination Requirements for DMD Interface

SIGNALS

SYSTEM TERMINATION

DMD_D(23:0), DMD_TRC, DMD_SCTRL,

DMD_LOADB, DMD_DRC_STRB,

DMD_DRC_BUS, DMD_SAC_CLK, and

DMD_SAC_BUS

External 5-Ω series termination at the transmitter

DMD_DCLK

External 5-Ω series termination at the transmitter

External 0-Ω series termination. This signal must

be externally pulled-up to VDD_DMD via a 30-kΩ

to 51-kΩ resistor

DMD_DRC_OE

DMD_CLK and DMD_SAC_CLK clocks should be equal lengths, as shown in 图 11-1.

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图 11-1. Series-Terminated Clocks

11.1.3 Decoupling Capacitors

The decoupling capacitors should be given placement priority. The supply voltage pin of the capacitor should be

located close to the DLPC350 supply voltage pin or pins. Decoupling capacitors should have two vias connecting

the capacitor to ground and two vias connecting the capacitor to the power plane, but if the trace length is less

than 0.05 inches, the device can be connected directly to the decoupling capacitor. The vias should be located

on opposite sides of the long side of the capacitor, and those connections should be less than 0.05 inches as

well.

11.1.4 Power Plane Recommendations

For best performance, TI recommends the following:

•

Two power planes

– One solid plane for ground (GND)

– One split plane for other voltages with no signal routing on the power planes

Power and ground pins should be connected to these planes through a via for each pin.

All device pin and via connections to these planes should use a thermal relief with a minimum of four spokes.

Trace lengths for the component power and ground pins should be minimized to 0.03 inches or less.

Vias should be spaced out to avoid forming slots on the power planes.

High speed signals should not cross over a slot in the adjacent power planes.

Vias connecting all the digital layers should be placed around the edge of the rigid PCB regions 0.03 inches

from the board edges with 0.1 inch spacing prior to routing.

•

Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of

devices.

All signal routing and signal vias should be inside the perimeter ring of ground vias.

11.1.5 Signal Layer Recommendations

The PCB signal layers should follow typical good practice guidelines including:

•

Layer changes should be minimized for single-ended signals.

Individual differential pairs can be routed on different layers, but the signals of a given pair should not change

layers.

•

Stubs should be avoided.

Only voltage or low-frequency signals should be routed on the outer layers, except as noted previously in this

document.

•

Double data rate signals should be routed first for best impedance and trace length matching.

The PCB should have a solder mask on the top and bottom layers. The mask should not cover the vias.

•

Except for fine pitch devices (pitch ≤ 0.032 inches), the copper pads and the solder mask cutout should be of

the same size.

•

Solder mask between pads of fine pitch devices should be removed.

In the BGA package, the copper pads and the solder mask cutout should be of the same size.

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11.1.6 General Handling Guidelines for CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused

input pins be tied through a pullup resistor to its associated power supply, or a pulldown to ground. For inputs

with internal pullup or pulldown resistors, adding an external pullup or pulldown resistor is unnecessary unless

specified in the Pin Configuration and Functions section. Note that internal pullup and pulldown resistors are

weak and should not be expected to drive an external line.

After power-up or device reset, bidirectional pins are configured as inputs as a reset default until directed

otherwise.

Unused output-only pins can be left open.

11.1.7 PCB Manufacturing

The DLPC350 Controller and DMD are a high-performance (high-frequency and high-bandwidth) set of

components. This section provides PCB guidelines to help ensure proper operation of these components.

The DLPC350 controller board will be a multi-layer PCB with surface mount components on both sides. The

majority of large surface mount components are placed on the top side of the PCB. Circuitry is high speed digital

logic. The high speed interfaces include:

•

120-MHz DDR interface from DLPC350 to DMD

150-MHz LVTTL interface from a video decoder to the DLPC350

150-MHz pixel clock supporting 30-bit parallel RGB interface

LVTTL parallel memory interface between the DLPC350 controller and flash with 70-ns access time

LVDS flat panel display port to DLPC350

The PCB should be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to

IPC6011 and IPC6012, Class 2.

11.1.7.1 General Guidelines

表 11-2. PCB General Recommendations

DESCRIPTION

RECOMMENDATION

Asymmetric dual stripline

1.0-oz. (1.2-mil thick) copper

50 Ω (±10%)

Configuration

Etch thickness (T)

Single-ended signal impedance

Differential signal impedance

100 Ω differential (±10%)

11.1.7.2 Trace Widths and Minimum Spacings

For best performance, TI recommends the trace widths and minimum spacings shown in 表 11-3.

表 11-3. Trace Widths and Minimum Spacings

MINIMUM TRACE SPACING

SIGNAL NAME

TRACE WIDTH (inches)

(inches)

P1P2, P1P2V_PLLM, P1P2V_PLLD,

P2P5V, P3P3V, P1P9V, A1P8V,

A1P8V_PLLD, A1P8V_PLLM

0.02

0.010

VRST, VBIAS, VOFFSET

VSS (GND)

0.02

0.010

0.005

0.020

0.030

FANx_OUT

DMD_DCLK

P1A_CLK, P1B_CLK, P1C_CLK

MOSC, MOSCN

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11.1.7.3 Routing Constraints

In order to meet the specifications listed in the following tables, typically the PCB designer must route these

signals manually (not using automated PCB routing software). In case of length matching requirements, routing

traces in a serpentine fashion may be required. Keep the number of turns to a minimum and the turn angles

no sharper than 45°. Traces must be 0.1 inches from board edges when possible; otherwise they must be 0.05

inches minimum from the board edges. Avoid routing long traces all around the PCB. PCB layout assumes

adjacent trace spacing is twice the trace width. However, three times the trace width will reduce crosstalk and

significantly help performance.

The maximum and minimum signal routing trace lengths include escape routing.

表 11-4. Signal Length Routing Constraints for DMD Interface

MINIMUM SIGNAL

MAXIMUM SIGNAL

SIGNALS

ROUTING LENGTH⁽¹⁾

ROUTING LENGTH⁽²⁾

DMD_D(23:0), DMD_DCLK, DMD_TRC,

DMD_SCTRL, DMD_LOADB,

2480 mil

(63 mm)

2953 mil

(75 mm)

DMD_OE, DMD_DRC_STRB, DMD_DRC_BUS,

DMD_SAC_CLK, and DMD_SAC_BUS

512 mil

(13 mm)

5906 mil

(150 mm)

(1) Signal lengths below the stated minimum will likely result in overshoot or undershoot.

(2) DMD-DDR maximum signal length is a function of the DMD_DCLK rate.

Each high-speed, single-ended signal should be routed in relation to its reference signal, such that a constant

impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping total

trace lengths to a minimum. The following signals should follow the signal matching requirements described in 表

11-5.

表 11-5. High-Speed Signal Matching Requirements for DMD Interface

SIGNALS

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD_D(23:0), DMD_TRC, DMD_SCTRL,

DMD_LOADB

±200

(±5.08)

mil

(mm)

DMD_DCLK

DMD_DRC_STRB, DMD_DRC_BUS,

DMD_SAC_BUS, DMD_OE

±200

(±5.08)

mil

(mm)

DMD_SAC_CLK

The values in 表 11-5 apply to the PCB routing only. They do not include any internal package routing mismatch

associated with the DLPC350 or DMD. Additional margin can be attained if internal DLPC350 package skew

is taken into account. Additionally, to minimize EMI radiation, serpentine routes added to facilitate trace length

matching should only be implemented on signal layers between reference planes.

Both the DLPC350 output timing parameters and the DMD input timing parameters include a timing budget to

account for their respective internal package routing skew. Thus, additional system margin can be attained by

comprehending the package variations and compensating for them in the PCB layout. To increase the system

timing margin, TI recommends that the DLPC350 package variation be compensated for (by signal group),

but it may not be desirable to compensate for DMD package skew. This is due to the fact that each DMD

has a different skew profile, making the PCB layout DMD specific. To use a common PCB design for different

DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB, or the

package lengths for all applicable DMDs being considered. 表 11-6 provides the DLPC350 package output delay

at the package ball for each DMD interface signal.

The total length of all the traces in 表 11-6 should be matched to the DMD_DCLK trace length. Total trace length

includes package skews, PCB length, and DMD flex cable length.

表 11-6. DLPC350 Package Skew and Routing Trace Length for the DMD

Interface

TOTAL DELAY (Package Skews)

SIGNAL

PACKAGE PIN

(ps)

25.9

19.6

(mil)

DMD_D0

DMD_D1

152.35

115.29

A8

B8

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表 11-6. DLPC350 Package Skew and Routing Trace Length for the DMD

Interface (continued)

TOTAL DELAY (Package Skews)

SIGNAL

PACKAGE PIN

(ps)

13.4

7.4

(mil)

78.82

43.53

106.47

65.29

25.88

0.00

DMD_D2

DMD_D3

C8

D8

DMD_D4

18.1

11.1

4.4

B11

C11

D11

E11

C7

DMD_D5

DMD_D6

DMD_D7

0.0

DMD_D8

14.8

18.4

6.4

87.06

108.24

37.65

28.24

175.29

151.18

111.76

68.82

27.65

126.47

145.88

48.82

140.59

9.41

DMD_D9

B10

E7

DMD_D10

DMD_D11

DMD_D12

DMD_D13

DMD_D14

DMD_D15

DMD_D16

DMD_D17

DMD_D18

DMD_D19

DMD_D20

DMD_D21

DMD_D22

DMD_D23

DMD_DCLK

DMD_LOADB

DMD_SCTRL

DMD_TRC

4.8

D10

A6

29.8

25.7

19.0

11.7

4.7

A12

B12

C12

D12

B7

21.5

24.8

8.3

A10

D7

23.9

1.6

B6

E9

10.7

16.7

24.8

18.0

11.4

4.6

62.94

98.24

145.88

105.88

67.06

27.06

C10

C6

A9

B9

C9

D9

表 11-7. Routing Priority

ROUTING

PRIORITY

ROUTING

LAYER

MATCHING REFERENCE

SIGNAL

DMD_DCLK^{(1) (2) (3)}

TOLERANCE

–

SIGNAL

1

3

–

DMD_D[23:0], DMD_SCTRL, DMD_TRC,

DMD_LOADB^{(1) (2) (3) (4)}

1

3, 4

DMD_DCLK

P1X_CLK

±150 mils

P1_A[9:0], P1_B[9:0], P1_C[9:0],

P1_HSYNC, P1_VSYNC, P1_DATAEN,

P1X_CLK

3, 4

±0.1 inches

±150 mils

Differential signals need to be

matched within ±12 mils

R[A-E]_IN_P, R[A-E]_IN_N, RCK_IN_P,

RCK_IN_N

2

RCK

(1) Total signal length from the DLPC350 and the DMD, including flex cable traces and PCB signal trace lengths must be held to the

lengths specified in 表 11-4.

(2) Switching routing layers is not permitted except at the beginning and end of a trace.

(3) Minimize vias on DMD traces.

(4) Matching includes PCB trace length plus the DLPC350 package length plus the DMD flex cable length.

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11.1.7.4 Fiducials

Fiducials for automatic component insertion should be 0.05 inch diameter copper with a 0.1-inch cutout

(antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

11.1.7.5 Flex Considerations

表 11-8 shows the general DMD flex design recommendations. 表 11-9 lists the minimum flex design

requirements.

表 11-8. Flex General Recommendations

DESCRIPTION

RECOMMENDATION

Configuration

Two-layer micro strip

Reference plane 1

Vias

Ground plan for proper return

Maximum two per signal

4-mil minimum

Single trace width

Etch thickness (T)

Single-ended signal impedance

0.5-oz. (0.6 mil thick) copper

50 Ω (± 10%)

表 11-9. Minimum Flex Design Requirements

PARAMETER

APPLICATION

SINGLE-ENDED SIGNALS

UNIT

4

(0.1)

mil

(mm)

Escape routing in ball field

5

mil

(mm)

Line width (W)⁽¹⁾

PCB etch data and control

PCB etch clocks

(0.13)

7

mil

(mm)

(0.18)

4

(0.1)

mil

(mm)

Escape routing in ball field

PCB etch data and control

PCB etch clocks

Minimum line spacing to

other signals (S)

mil

(mm)

2x the line width⁽²⁾

mil

(mm)

3x the line width

(1) Line width is expected to be adjusted to achieve impedance requirements.

(2) Three times the line spacing is recommended for all signals to help achieve the desired signal

integrity.

11.1.7.6 DLPC350 Thermal Considerations

The underlying thermal limitation for the DLPC350 controller is that the maximum operating junction temperature

(T_J) must not be exceeded (see Recommended Operating Conditions in Specifications). This temperature is

dependent on operating ambient temperature, airflow, PCB design (including the component layout density and

the amount of copper used), power dissipation of the DLPC350 controller, and power dissipation of surrounding

components. The DLPC350 package is designed to extract heat through the power and ground planes of the

PCB, thus copper content and airflow over the PCB are important factors.

11.2 Layout Example

11.2.1 Printed Circuit Board Layer Stackup Geometry

The DLPC350 PCB is targeted at six layers with layer stack up shown in 图 11-2. The PCB layer stack may

vary depending on system design. However, careful attention is required to meet design considerations. Layers

one and six should consist of the components layers. Low-speed routing and power splits are allowed on these

layers. Layer two should consist of a solid ground plane. Layer five should be a split voltage plane. Layers three

and four should be used as the primary routing layers. Routing on external layers should be less than 0.25

inches for priority one and two signals. Refer to 表 11-7 for signal priority groups.

Board material should be FR-370HR or similar. PCB should be designed for lead-free assembly with the stackup

geometry shown in 图 11-2.

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图 11-2. Layer Stackup

表 11-10. PCB Layer Stackup Geometry

PARAMETER

DESCRIPTION

RECOMMENDATION

Reference plane 1

Ground plane for proper return

Reference plane 2

1.9-V DMD I/O power plane or ground

Er

Dielectric FR4

4.3 at 1 GHz (nominal)

5 mil (0.127 mm)

30.4 mil

H1

H2

Signal trace distance to reference plane 1

Signal trace distance to reference plane 2

11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration

The DLPC350 controller requires an external reference clock to feed its internal PLL. This reference may be

supplied via a crystal or oscillator. The DLPC350 controller accepts a reference clock of 32 MHz with a maximum

frequency variation of 100 ppm (including aging, temperature, and trim component variation). When a crystal is

used, several discrete components are also required, as shown in 图 11-3.

MOSC

MOSCN

R_FB

R_S

(Crystal)

C_L1

C_L2

C_L= crystal load capacitance in F

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C_L1= 2 × (C_L– C_stray-MOSC

)

C_L2= 2 × (C_L– C_stray-MOSCN

C_stray-MOSC= sum of package and PCB capacitance at the crystal pin associated withe ASIC signal MOSC

C_stray-MOSCN= sum of package and PCB capacitance at the crystal pin associated withe ASIC signal MOSCN

图 11-3. Recommended Crystal Oscillator Configuration

表 11-11. Crystal Port Electrical Characteristics

PARAMETER

NOM

3.9

UNIT

pF

MOSC to GND capacitance

MOSCN to GND capacitance

3.8

pF

表 11-12. Recommended Crystal Configuration

PARAMETER

Crystal circuit configuration

RECOMMENDED

Parallel resonant

Fundamental (first harmonic)

32

UNIT

Crystal type

Crystal nominal frequency

MHz

PPM

Crystal frequency tolerance (including accuracy,

temperature, aging and trim sensitivity)

±100

Crystal equivalent series resistance (ESR)

Crystal load

50 maximum

Ω

pF

10

Crystal shunt load

7 maximum

pF

Crystal frequency temperature stability

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

±30

100

1

PPM

Ω

MΩ

Typical drive level with TCX9C3207001 crystal

(ESRmax = 30 Ω) = 160 µW. See 图 11-3

C_L1external crystal load capacitor (MOSC)

pF

Typical drive level with TCX9C3207001 crystal

(ESRmax = 30 Ω) = 160 µW. See 图 11-3

C_L2external crystal load capacitor (MOSCN)

PCB layout

A ground isolation ring around the crystal

If an external oscillator is used, then the oscillator output must drive the MOSC pin on the DLPC350 controller,

and the MOSCN pin should be left unconnected. Note that the DLPC350 controller can only accept a triangular

waveform.

Similar to the crystal option, the oscillator input frequency is limited to 32 MHz.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.

11.2.3 Recommended DLPC350 PLL Layout Configuration

High-frequency decoupling is required for both 1.2-V and 1.8-V PLL supplies and should be provided as close as

possible to each of the PLL supply package pins as shown in the example layout in 图 11-4. TI recommends that

decoupling capacitors be placed under the package on the opposite side of the board. High quality, low-ESR,

monolithic, surface mount capacitors should be used. Typically 0.1 µF for each PLL supply should be sufficient.

The length of a connecting trace increases the parasitic inductance of the mounting and thus, where possible,

there should be no trace, allowing the via to butt up against the land itself. Additionally, the connecting trace

should be made as wide as possible. Further improvement can be made by placing vias to the side of the

capacitor lands or doubling the number of vias.

The location of bulk decoupling depends on the system design. Typically, a good ceramic capacitor in the 10-µF

range is adequate.

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图 11-4. PLL Filter Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.1.2 Device Nomenclature

图 12-1 provides a legend for reading the complete device name for any DLP device.

表 12-1. Package-Specific Information

PACKAGE TYPE

PACKAGE DRAWING

BODY SIZE

CONNECTOR

LCCC

FQD

9.1 mm x 20.7 mm

Neoconix FBX0040CMFF6AU00

DLP4500NIRAFQD

Package Type

Near-IR DMD

Device Descriptor

图 12-1. Device Nomenclature

12.1.3 Device Markings

The device marking consists of the fields shown in 图 12-2.

Two Dimensional Matrix Code

(DMD part number and lot trace code)

Lot Trace Code

DMD Device Name

图 12-2. Device Markings for FQD

12.2 Documentation Support

12.2.1 Related Documentation

The following documents contain additional information related to the use of the DLP4500NIR device:

•

DLPC350 Digital Controller Data Sheet, DLPS029 DLPS029

DLPC350 Software Programmer's Guide, DLPU010

DLP® LightCrafter™ 4500 Evaluation Module User's Guide, DLPU011

Geometric Optics Application Note, DLPA044

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12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP4500NIRAFQD
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.45 WXGA NIR DMD \| FQD \| 98 \| 10 to 70
文件：	总48页 (文件大小：2300K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP4500NIRAFQD [TI]

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