DLP470TE [TI]
0.47 英寸 4K UHD 2XLVDS DLP® 数字微镜器件 (DMD);
| 型号： | DLP470TE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.47 英寸 4K UHD 2XLVDS DLP® 数字微镜器件 (DMD) |
| 文件： | 总47页 (文件大小：1692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP470TE
ZHCSQC3B –APRIL 2019 –REVISED MARCH 2023
DLP470TE 0.47 4K UHD 数字微镜器件
1 特性
3 说明
• 0.47 英寸对角线微镜阵列
TI DLP470TE 数字微镜器件 (DMD) 是一款数控微机电
系统 (MEM) 空间光调制器 (SLM)，可用于实现明亮的
全 4K UHD 显示解决方案。与适当的光学系统配合使
用时，DLP470TE DMD 可以显示真正的 4K 超高清分
辨率（屏幕像素超过 800 万像素），并且能够向各种
显示介质投射准确且清晰的图像。DLP470TE DMD 通
过与DLPC4420 显示控制器、DLPA100 控制器电源和
电机驱动器配合使用，可实现高性能系统，而且非常适
合采用更小封装的4K UHD 高亮度显示应用。
– 4K 超高清(3840 × 2160) 显示分辨率
– 5.4 微米微镜间距
– ±17° 微镜倾斜度（相对于平坦表面）
– 底部照明
• 2xLVDS 输入数据总线
• DLP470TE 芯片组包括：
– DLP470TE DMD
– DLPC4420 控制器
器件信息
封装(1)
– DLPA100 控制器电源管理和电机驱动器IC
封装尺寸（标称值）
器件型号
DLP470TE
2 应用
FXJ (257)
32.2mm × 22.3mm
• 4K 超高清显示
• 激光电视
• 商业和教育
• 数字标牌
• 游戏
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 家庭影院
DLP470TE 简化应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS161
DLP470TE
ZHCSQC3B –APRIL 2019 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................25
7.5 Optical Interface and System Image Quality
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings...................................... 10
6.2 Storage Conditions................................................... 10
6.3 ESD Ratings..............................................................11
6.4 Recommended Operating Conditions.......................11
6.5 Thermal Information..................................................15
6.6 Electrical Characteristics...........................................15
6.7 Capacitance at Recommended Operating
Conditions................................................................... 16
6.8 Timing Requirements................................................16
6.9 System Mounting Interface Loads............................ 20
6.10 Micromirror Array Physical Characteristics.............21
6.11 Micromirror Array Optical Characteristics............... 22
6.12 Window Characteristics.......................................... 23
6.13 Chipset Component Usage Specification............... 23
7 Detailed Description......................................................24
7.1 Overview...................................................................24
7.2 Functional Block Diagram.........................................24
7.3 Feature Description...................................................25
Considerations............................................................ 25
7.6 Micromirror Array Temperature Calculation.............. 26
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 27
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application ................................................... 30
8.3 DMD Die Temperature Sensing................................ 32
9 Power Supply Recommendations................................34
9.1 DMD Power Supply Power-Up Procedure................34
9.2 DMD Power Supply Power-Down Procedure........... 34
10 Layout...........................................................................37
10.1 Layout Guidelines................................................... 37
10.2 Layout Example...................................................... 37
11 Device and Documentation Support..........................39
11.1 Device Support........................................................39
11.2 第三方产品免责声明................................................39
11.3 Documentation Support ......................................... 40
11.4 Trademarks............................................................. 40
11.5 静电放电警告...........................................................40
11.6 术语表..................................................................... 40
12 Mechanical, Packaging, and Orderable
Information.................................................................... 41
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2022) to Revision B (September 2022)
Page
• 将控制器更改为 DLPC4420，将芯片组元件链接到产品页面............................................................................. 1
• 将控制器更改为 DLPC4420，更新了应用图.......................................................................................................1
• Changed the controller to DLPC4420, added the lamp illumination section.....................................................11
• Added the DMD efficiency specification............................................................................................................22
• Changed the controller to DLPC4420...............................................................................................................24
• Changed the controller to DLPC4420...............................................................................................................25
• Changed the controller to DLPC4420, added a table with legacy part numbers and mechanical ICD.............30
• Changed the controller to DLPC4420, updated the application diagrams........................................................30
• Changed the controller to DLPC4420...............................................................................................................31
• Changed the controller to DLPC4420...............................................................................................................32
• Changed the controller to DLPC4420...............................................................................................................32
• Changed the controller to DLPC4420...............................................................................................................37
• Changed the controller to DLPC4420, updated the link................................................................................... 40
Changes from Revision * (April 2019) to Revision A (June 2022)
Page
• 根据最新的德州仪器 (TI) 和行业数据表标准对本文档进行了更新...................................................................... 1
• Updated SCP Specifications ............................................................................................................................16
• Updated 图6-3 ................................................................................................................................................ 18
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS161
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ZHCSQC3B –APRIL 2019 –REVISED MARCH 2023
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5 Pin Configuration and Functions
12 14
26
28 30
2
4
6
8
10
16 18 20 22 24
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29
Z
V
T
W
U
R
N
L
P
M
K
H
F
J
G
E
C
A
D
B
图5-1. Series 410 Package. 257-pin FXJ. Bottom View.
CAUTION
To ensure reliable, long-term operation of the .47-inch 4K UHD S410 DMD, it is critical to properly
manage the layout and operation of the signals identified in the table below. For specific details and
guidelines, refer to the PCB Design Requirements for TI DLP Standard TRP Digital Micromirror
Devices application report before designing the board.
表5-1. Pin Functions
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
D_AN(0)
NO.
C6
C3
E1
C4
D1
B8
F4
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AN(8)
D_AN(9)
D_AN(10)
D_AN(11)
D_AN(12)
D_AN(13)
D_AN(14)
D_AN(15)
E3
C11
F3
I
LVDS
DDR Differential
Data negative
805.0
K4
H3
J3
C13
A5
A3
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English Data Sheet: DLPS161
DLP470TE
ZHCSQC3B –APRIL 2019 –REVISED MARCH 2023
www.ti.com.cn
表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
D_AP(0)
NO.
C7
C2
E2
B4
C1
B7
E4
D3
C12
F2
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_AP(8)
D_AP(9)
D_AP(10)
D_AP(11)
D_AP(12)
D_AP(13)
D_AP(14)
D_AP(15)
D_BN(0)
D_BN(1)
D_BN(2)
D_BN(3)
D_BN(4)
D_BN(5)
D_BN(6)
D_BN(7)
D_BN(8)
D_BN(9)
D_BN(10)
D_BN(11)
D_BN(12)
D_BN(13)
D_BN(14)
D_BN(15)
I
LVDS
DDR Differential
Data positive
805.0
J4
G3
J2
C14
A6
A4
N4
Z11
W4
W10
L1
V8
W6
M1
R4
W1
U4
V2
Z5
I
LVDS
DDR Differential
Data negative
805.0
N3
Z2
L4
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English Data Sheet: DLPS161
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
D_BP(0)
NO.
M4
Z12
Z4
D_BP(1)
D_BP(2)
D_BP(3)
D_BP(4)
D_BP(5)
D_BP(6)
D_BP(7)
D_BP(8)
D_BP(9)
D_BP(10)
D_BP(11)
D_BP(12)
D_BP(13)
D_BP(14)
D_BP(15)
D_CN(0)
D_CN(1)
D_CN(2)
D_CN(3)
D_CN(4)
D_CN(5)
D_CN(6)
D_CN(7)
D_CN(8)
D_CN(9)
D_CN(10)
D_CN(11)
D_CN(12)
D_CN(13)
D_CN(14)
D_CN(15)
Z10
L2
V9
W7
N1
I
LVDS
DDR Differential
Data positive
805.0
P4
V1
T4
V3
Z6
N2
Z3
L3
H27
A20
H28
K28
K30
C23
G27
J30
B24
A21
A27
C29
A26
C25
A29
C30
I
LVDS
DDR Differential
Data negative
805.0
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English Data Sheet: DLPS161
DLP470TE
ZHCSQC3B –APRIL 2019 –REVISED MARCH 2023
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
D_CP(0)
NO.
J27
A19
H29
K27
K29
C22
F27
H30
B25
B21
B27
C28
A25
C24
A28
B30
V25
V28
T30
V27
U30
W23
R27
T28
V20
R28
L27
N28
M28
V18
Z26
Z28
D_CP(1)
D_CP(2)
D_CP(3)
D_CP(4)
D_CP(5)
D_CP(6)
D_CP(7)
D_CP(8)
D_CP(9)
D_CP(10)
D_CP(11)
D_CP(12)
D_CP(13)
D_CP(14)
D_CP(15)
D_DN(0)
D_DN(1)
D_DN(2)
D_DN(3)
D_DN(4)
D_DN(5)
D_DN(6)
D_DN(7)
D_DN(8)
D_DN(9)
D_DN(10)
D_DN(11)
D_DN(12)
D_DN(13)
D_DN(14)
D_DN(15)
I
LVDS
DDR Differential
Data positive
805.0
805.0
I
LVDS
DDR Differential
Data negative
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English Data Sheet: DLPS161
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
D_DP(0)
NO.
V24
V29
T29
W27
V30
W24
T27
U28
V19
R29
M27
P28
M29
V17
Z25
Z27
G1
805.0
D_DP(1)
D_DP(2)
D_DP(3)
D_DP(4)
D_DP(5)
D_DP(6)
D_DP(7)
I
LVDS
DDR Differential
Data positive
D_DP(8)
D_DP(9)
D_DP(10)
D_DP(11)
D_DP(12)
D_DP(13)
D_DP(14)
D_DP(15)
SCTRL_AN
SCTRL_AP
SCTRL_BN
SCTRL_BP
SCTRL_CN
SCTRL_CP
SCTRL_DN
SCTRL_DP
DCLK_AN
DCLK_AP
DCLK_BN
DCLK_BP
DCLK_CN
DCLK_CP
DCLK_DN
DCLK_DP
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR Differential
DDR Differential
DDR Differential
DDR Differential
DDR Differential
DDR Differential
DDR Differential
DDR Differential
Differential
Serial control negative(2)
Serial control negative(2)
Serial control negative(2)
Serial control negative(2)
Serial control negative(2)
Serial control positive(2)
Serial control negative(2)
Serial control positive(2)
Clock negative(2)
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
805.0
F1
V5
V4
C26
C27
P30
R30
H2
H1
Differential
Clock positive(2)
V6
Differential
Clock negative(2)
V7
Differential
Clock positive(2)
D27
E27
N29
N30
Differential
Clock negative(2)
Differential
Clock positive(2)
Differential
Clock negative(2)
Differential
Clock positive(2)
Serial communications port clock. Active only
when SCPENZ is logic low(2)
SCPCLK
SCPDI
A10
A12
C10
I
I
LVCMOS
LVCMOS
Pulldown
Serial communications port data input.
Synchronous to SCPCLK rising edge(2)
SDR Pulldown
Serial communications port enable active
low(2)
SCPENZ
I
LVCMOS
LVCMOS
Pulldown
SDR
SCPDO
A11
Z13
O
Serial communications port output
RESET_ADDR(0)
RESET_ADDR(1)
RESET_ADDR(2)
RESET_ADDR(3)
W13
V10
W14
I
LVCMOS
Pulldown
Reset driver address select(2)
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English Data Sheet: DLPS161
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
NO.
RESET_MODE(0)
RESET_SEL(0)
RESET_SEL(1)
W9
V14
Z8
Reset driver mode select(2)
I
LVCMOS
Pulldown
Reset driver level select(2)
Reset driver level select(2)
Rising edge latches in RESET_ADDR,
RESET_MODE, and RESET_SEL.(2)
RESET_STROBE
PWRDNZ
Z9
A8
I
I
I
LVCMOS
LVCMOS
LVCMOS
Pulldown
Pulldown
Pullup
Active low device reset.(2)
Active low output enable for internal reset
driver circuits.(2)
RESET_OEZ
W15
Active low output interrupt to the DLP® display
controller
RESET_IRQZ
EN_OFFSET
PG_OFFSET
V16
C9
O
O
I
LVCMOS
LVCMOS
LVCMOS
Active high enable for external VOFFSET
regulator
Active low fault from external VOFFSET
regulator(2)
A9
Pullup
TEMP_N
TEMP_P
B18
B17
Analog
Analog
Temperature sensor diode cathode
Temperature sensor diode anode
D12, D13,
D14, D15,
D16, D17,
D18, D19,
U12, U13,
U14, U15
RESERVED
**MUST VERIFY
WITH SRC DATA
SHEET
Do not connect on the DLP® system board.
No connect. No electrical connections from
CMOS bond pad to package pin
NC
Analog
Pulldown
U16, U17,
U18, U19
No connect. No electrical connection from the
CMOS bond pad to package pin
No Connect
NC
O
RESERVED_BA
RESERVED_BB
RESERVED_BC
RESERVED_BD
RESERVED_PFE
RESERVED_TM
RESERVED_TP0
RESERVED_TP1
RESERVED_TP2
W11
B11
Z20
C18
A18
C8
LVCMOS
Do not connect on the DLP system board.
I
I
LVCMOS
Analog
Pulldown
Connect to ground on the DLP system board.
Do not connect on the DLP system board.
Z19
W20
W19
C15, C16,
V11, V12
Supply voltage for positive bias level of
micromirror reset signal
(3)
VBIAS
P
P
Analog
Analog
G4, H4,
J1, K1
Supply voltage for negative reset level of
micromirror reset signal
(3)
VRESET
Supply voltage for HVCMOS logic. Supply
voltage for positive offset level of micromirror
reset signal. Supply voltage for stepped high
voltage at micromirror address electrodes
A30, B2,
M30, Z1,
Z30
(3)
VOFFSET
P
Analog
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English Data Sheet: DLPS161
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH
(mil)
DATA
INTERNAL
I/O(1)
SIGNAL
DESCRIPTION
RATE TERMINATION
NAME
NO.
A24, A7,
B10, B13,
B16, B19,
B22, B28,
B5, C17,
C20, D4,
J29, K2,
L29, M2,
N27, U27,
V13, V15,
V22, W17,
W21,
Supply voltage for LVCMOS core. Supply
voltage for positive offset level of micromirror
reset signal during power down. Supply
voltage for normal high level at micromirror
address electrodes
(3)
VCC
P
Analog
W26,
W29, W3,
Z18, Z23,
Z29, Z7
A13, A22,
A23, B12,
B14, B15,
B20, B23,
B26, B29,
B3, B6,
B9, C19,
C21, C5,
D2, G2,
J28, K3,
L28, L30,
M3, P27,
P29, U29,
V21, V23,
V26, W12,
W16,
(4)
VSS
G
Device ground. Common return for all power
W18, W2,
W22,
W25,
W28,
W30, W5,
W8, Z21,
Z22, Z24
(1) I = Input, O = Output, P = Power, G = Ground, NC = No connect
(2) These signals are very sensible to noise or intermittent power connections, which can cause irreversible DMD micromirror array
damage or, to a lesser extent, image disruption. Consider this precaution during DMD board design and manufacturer handling of the
DMD subassemblies.
(3) VBIAS, VCC, VOFFSET, and VRESET power supplies must be connected for proper DMD operation.
(4) VSS must be connected for proper DMD operation.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under 节 6.1
may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device is not implied at these or any other conditions beyond those indicated under Recommended Operating
Conditions. Exposure above or below the Recommended Operating Conditions. Exposure above or below the
Recommended Operating Conditions for extended periods may affect device reliability.
MIN
MAX
UNIT
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic(1)
2.3
11
V
V
V
V
V
V
–0.5
–0.5
–0.5
–15
VOFFSET
VBIAS
Supply voltage for HVCMOS and micromirror electrode(1) (2)
Supply voltage for micromirror electrode(1)
Supply voltage for micromirror electrode(1)
Supply voltage difference (absolute value)(3)
Supply voltage difference (absolute value)(4)
19
VRESET
–0.3
11
|VBIAS –VOFFSET
|VBIAS –VRESET
|
34
|
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins(1)
Input voltage for all other LVDS input pins (1) (5)
Input differential voltage (absolute value)(6)
Input differential current(5)
VCC + 0.5
VCC + 0.5
500
V
V
–0.5
–0.5
|VID|
mV
mA
IID
6.3
Clocks
ƒCLOCK
Clock frequency for LVDS interface, DCLK_A
Clock frequency for LVDS interface, DCLK_B
Clock frequency for LVDS interface, DCLK_C
Clock frequency for LVDS interface, DCLK_D
400
400
400
400
MHz
MHz
MHz
MHz
ƒCLOCK
ƒCLOCK
ƒCLOCK
ENVIRONMENTAL
Temperature, operating(7)
0
90
90
°C
°C
TARRAY and
TWINDOW
Temperature, non–operating(7)
–40
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1 (8)
|TDELTA
TDP
|
30
81
°C
°C
Dew point temperature, operating and non–operating (non-condensing)
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD
operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(4) Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
(5) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in 图7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the
highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,
use that location.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, use that location.
Applicable for the DMD as a component or non-operating in a system.
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6.2 Storage Conditions
MIN
MAX
80
UNIT
°C
TDMD
DMD storage temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature (non-condensing) (1)
Elevated dew point temperature range (non-condensing) (2)
Cumulative time in elevated dew point temperature range
28
°C
28
36
°C
24 months
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Limit the exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of
CTELR
.
6.3 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
discharge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device
specified in this data sheet is achieved when operating the device within the limits defined by this table. No level
of performance is implied when operating the device above or below these limits.
6.4 Recommended Operating Conditions
MIN NOM
MAX
UNIT
VOLTAGE SUPPLY
VCC
LVCMOS logic supply voltage(1)
1.65
9.5
1.8
10
18
1.95
10.5
V
V
V
V
VOFFSET
VBIAS
Mirror electrode and HVCMOS voltage(1) (2)
Mirror electrode voltage(1)
17.5
18.5
VRESET
Mirror electrode voltage(1)
–14.5 –14
–13.5
|VBIAS
VOFFSET
–
|
Supply voltage difference (absolute value)(3)
Supply voltage difference (absolute value)(4)
10.5
33
V
V
|VBIAS
VRESET
–
|
LVCMOS INTERFACE
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
tPWRDNZ
DC input high voltage(5)
0.7 × VCC
VCC + 0.3
0.3 × VCC
VCC + 0.3
0.2 × VCC
V
V
DC input low voltage(5)
AC input high voltage(5)
AC input low voltage(5)
PWRDNZ pulse duration(6)
–0.3
0.8 × VCC
–0.3
V
V
10
ns
SCP INTERFACE
SCP clock frequency(7)
500
900
kHz
ns
ƒSCPCLK
Propagation delay, clock to Q, from rising-edge of SCPCLK to valid
SCPDO(8)
tSCP_PD
0
tSCP_NEG_ENZ Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK
tSCP_POS_ENZ Time between falling-edge of SCPCLK and the rising-edge of SCPENZ
1
1
µs
µs
tSCP_DS
tSCP_DH
tSCP_PW_ENZ
ƒCLOCK
SCPDI clock setup time (before SCPCLK falling edge)(8)
SCPDI hold time (after SCPCLK falling edge)(8)
SCPENZ inactive pulse duration (high level)
800
900
2
ns
ns
µs
Clock frequency for LVDS interface (all channels), DCLK(9)
Input differential voltage (absolute value)(10)
400
440
MHz
mV
|VID|
150
300
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6.4 Recommended Operating Conditions (continued)
MIN NOM
1100 1200
880
MAX
UNIT
mV
mV
ns
VCM
Common mode voltage(10)
1300
1520
2000
120
VLVDS
tLVDS_RSTZ
ZIN
LVDS voltage(10)
Time required for LVDS receivers to recover from PWRDNZ
Internal differential termination resistance
Line differential impedance (PWB/trace)
80
90
100
100
Ω
ZLINE
110
Ω
ENVIRONMENTAL
Array temperature, long-term operational(11) (12) (13) (23)
10
0
40 to 70(23)
°C
°C
°C
TARRAY
Array temperature, short-term operational(12) (15)
10
85
Window temperature –operational(16) (17)
TWINDOW
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1(18) (19)
|TDELTA
|
14
°C
Average dew point temperature (non–condensing)(20)
Elevated dew point temperature range (non-condensing)(21)
Cumulative time in elevated dew point temperature range
TDP-AVG
TDP-ELR
CTELR
28
36
°C
°C
28
24 months
MIN NOM
MAX
UNIT
VOLTAGE SUPPLY
VCC
LVCMOS logic supply voltage(1)
1.65
9.5
1.8
10
18
1.95
10.5
V
V
V
V
VOFFSET
VBIAS
Mirror electrode and HVCMOS voltage(1) (2)
Mirror electrode voltage(1)
17.5
18.5
VRESET
Mirror electrode voltage(1)
–14.5 –14
–13.5
|VBIAS
VOFFSET
–
|
Supply voltage difference (absolute value)(3)
Supply voltage difference (absolute value)(4)
10.5
33
V
V
|VBIAS
VRESET
–
|
LVCMOS INTERFACE
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
tPWRDNZ
DC input high voltage(5)
0.7 × VCC
VCC + 0.3
0.3 × VCC
VCC + 0.3
0.2 × VCC
V
V
DC input low voltage(5)
AC input high voltage(5)
AC input low voltage(5)
PWRDNZ pulse duration(6)
–0.3
0.8 × VCC
–0.3
V
V
10
ns
SCP INTERFACE
SCP clock frequency(7)
500
900
kHz
ns
ƒSCPCLK
Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid
tSCP_PD
0
SCPDO(8)
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6.4 Recommended Operating Conditions (continued)
MIN NOM
MAX
UNIT
µs
tSCP_NEG_ENZ Time between falling-edge of SCPENZ and the first rising- edge of SCPCLK
tSCP_POS_ENZ Time between falling-edge of SCPCLK and the rising-edge of SCPENZ
1
1
µs
tSCP_DS
SCPDI Clock setup time (before SCPCLK falling edge)(8)
SCPDI Hold time (after SCPCLK falling edge)(8)
SCPENZ inactive pulse duration (high level)
800
900
2
ns
tSCP_DH
ns
tSCP_PW_ENZ
µs
LVDS INTERFACE
Clock frequency for LVDS interface (all channels), DCLK(10)
400
440
MHz
mV
mV
mV
ns
ƒCLOCK
|VID|
Input differential voltage (absolute value)(11)
Common mode voltage(11)
150
300
VCM
1100 1200
880
1300
1520
2000
120
VLVDS
tLVDS_RSTZ
ZIN
LVDS voltage(11)
Time required for LVDS receivers to recover from PWRDNZ
Internal differential termination resistance
Line differential impedance (PWB/trace)
80
90
100
100
Ω
ZLINE
110
Ω
ENVIRONMENTAL
10
0
40 to 70(15)
°C
°C
°C
Array temperature, long–term operational(13) (14) (16)
TARRAY
Array temperature, short–term operational(14) (17)
Window temperature –operational(21) (23)
10
85
TWINDOW
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1(18) (19)
|TDELTA
|
14
°C
TDP -AVG
TDP-ELR
CTELR
Average dew point temperature (non-condensing)(20)
Elevated dew point temperature range (non-condensing)(22)
Cumulative time in elevated dew point temperature range
28
36
°C
°C
28
24 Months
ILLUMINATION (Lamp)
L
Operating system luminance(19)
4000
lm
2.00 mW/cm2
mW/cm2
ILLUV
ILLVIS
ILLIR
ILLθ
Illumination wavelengths < 395 nm(13)
Illumination wavelengths between 395 nm and 800 nm
Illumination wavelengths > 800 nm
0.68
Thermally limited
10 mW/cm2
Illumination marginal ray angle(23)
55
deg
ILLUMINATION (Solid State)
L
Operating system luminance(19)
5500
lm
ILLUV
ILLVIS
ILLIR
ILLθ
Illumination wavelengths < 436 nm(13)
Illumination wavelengths between 436 nm and 800 nm
Illumination wavelengths > 800 nm
0.45 mW/cm2
mW/cm2
Thermally Limited
10 mW/cm2
Illumination marginal ray angle(23)
55
deg
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD
operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than the specified limit. See Power Supply
Recommendations, 图9-1, and 表9-1.
(4) To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than the specified limit. See Power Supply
Recommendations, 图9-1, and 表9-1.
(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, "Low-Power Double Data Rate (LPDDR)" JESD209B. Tester conditions for VIH and VIL.
•
•
Frequency = 60 MHz. Maximum rise time = 2.5 ns at 20/80
Frequency = 60 MHz. Maximum fall time = 2.5 ns at 80/20
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the
SCPDO output pin.
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(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(8) See 图6-2.
(9) See LVDS timing requirements in Timing Requirements.
(10) See LVDS waveform requirements in the specifications.
(11) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination
reduces device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in 图7-1 and the package thermal resistance (Thermal Information) using the Micromirror Array Temperature Calculation.
(13) Long-term is defined as the usable life of the device.
(14) CP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as the cumulative time over the usable life of the device and is less than 500 hours.
(16) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 10 are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, use that location.
(17) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of
micromirrors (POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not
necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance
has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array
(including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(18) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta temperature. If a
particular application causes another point on the window edge to result in a larger delta in temperature, that point needs to be used.
(19) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of
these limits has not been tested.
(20) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(21) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of
CTELR
.
(22) Supported for video applications only
(23) Per the Maximum Recommended Array Temperature - Derating Curve, the maximum operational array temperature is derated based
on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-On/Landed-Off Duty
Cycle for a definition of micromirror landed duty cycle.
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80
70
60
50
40
30
0/100
100/0
5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
65/35
95/5
90/10
85/15
80/20
75/25
70/30
60/40
55/45
50/50
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature - Derating Curve
6.5 Thermal Information
DLP470TE
FXJ Package
257 PINS
0.90
THERMAL METRIC
UNIT
Thermal resistance, active area to test point 1 (TP1)(1)
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include
light energy absorbed by the window aperture and electrical power dissipation of the array.
Optical systems need to be designed to minimize the light energy falling outside the window clear aperture since any additional thermal
load in this area can significantly degrade the reliability of the device.
Over operating free-air temperature range (unless otherwise noted).
6.6 Electrical Characteristics
PARAMETER
TEST CONDITIONS
VCC = 1.8 V, IOH = –2 mA
VCC = 1.95 V, IOL = 2 mA
MIN
TYP
MAX
UNIT
V
VOH
VOL
High level output voltage
Low level output voltage
0.8 × VCC
0.2 × VCC
25
V
High impedance output
current
IOZ
IIL
VCC = 1.95 V
µA
µA
–40
–1
Low level input current
VCC = 1.95 V, VI = 0
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6.6 Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
IIH
High level input current(1)
VCC = 1.95 V, VI = VCC
110
1500
13.2
(2)
ICC
Supply current VCC
VCC = 1.95 V
mA
mA
mA
mA
mW
(3)
IOFFSET
IBIAS
IRESET
PCC
Supply current VOFFSET
VOFFSET = 10.5 V
VBIAS = 18.5 V
VRESET = –14.5 V
(3) (4)
Supply current VBIAS
Supply current VRESET
3.6
(4)
–9
Supply power dissipation VCC VCC = 1.95 V
Supply power dissipation
2925.0
POFFSET
PBIAS
PRESET
PTOTAL
VOFFSET = 10.5 V
138.6
66.6
mW
mW
mW
mW
(3)
VOFFSET
Supply power dissipation
VBIAS = 18.5 V
(3) (4)
VBIAS
Supply power dissipation
130.5
3260.7
VRESET = –14.5 V
(4)
VRESET
Supply power dissipation
VTOTAL
(1) Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.
(2) See the Pin Functions table for pull–up and pull–down configuration per device pin.
(3) To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than the specified limits listed in the
Recommended Operating Conditions table.
(4) To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than specified limit in Recommended
Operating Conditions.
6.7 Capacitance at Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ƒ= 1 MHz
MIN
TYP
MAX
UNIT
CI_lvds
LVDS input capacitance 2xLVDS
20
pF
Non-LVDS input capacitance
2xLVDS
CI_nonlvds
20
pF
ƒ= 1 MHz
Temperature diode input capacitance
2xLVDS
CI_tdiode
CO
30
20
pF
pF
ƒ= 1 MHz
ƒ= 1 MHz
Output capacitance
6.8 Timing Requirements
MIN
NOM
MAX
UNIT
SCP(1)
tr
Rise time
Fall time
20% to 80% reference points
30
30
ns
ns
tf
80% to 20% reference points
LVDS(2)
tr
tf
Rise slew rate
Fall slew rate
20% to 80% reference points
80% to 20% reference points
DCLK_A, LVDS pair
DCLK_B, LVDS pair
DCLK_C, LVDS pair
DCLK_D, LVDS pair
DCLK_A, LVDS pair
DCLK_B, LVDS pair
DCLK_C, LVDS pair
DCLK_D, LVDS pair
0.7
0.7
1
1
V/ns
V/ns
ns
2.5
2.5
ns
tC
Clock cycle
2.5
ns
2.5
ns
1.19
1.19
1.19
1.19
1.25
1.25
1.25
1.25
ns
ns
tW
Pulse duration
ns
ns
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6.8 Timing Requirements (continued)
MIN
0.275
0.275
0.275
0.275
0.275
0.275
0.275
0.275
0.195
0.195
0.195
0.195
0.195
0.195
0.195
0.195
–1.25
–1.25
NOM
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D_A(15:0) before DCLK_A, LVDS pair
D_B(15:0) before DCLK_B, LVDS pair
D_C(15:0) before DCLK_C, LVDS pair
D_D(15:0) before DCLK_D, LVDS pair
SCTRL_A before DCLK_A, LVDS pair
SCTRL_B before DCLK_B, LVDS pair
SCTRL_C before DCLK_C, LVDS pair
SCTRL_D before DCLK_D, LVDS pair
D_A(15:0) after DCLK_A, LVDS pair
D_B(15:0) after DCLK_B, LVDS pair
D_C(15:0) after DCLK_C, LVDS pair
D_D(15:0) after DCLK_D, LVDS pair
SCTRL_A after DCLK_A, LVDS pair
SCTRL_B after DCLK_B, LVDS pair
SCTRL_C after DCLK_C, LVDS pair
SCTRL_D after DCLK_D, LVDS pair
Channel B relative to channel A (3) (4)
Channel D relative to channel C(5) (6), LVDS pair
tSu
Setup time
th
Hold time
tSKEW
tSKEW
Skew time
Skew time
1.25
1.25
(1) See the specifications for rise time and fall time for SCP.
(2) See the specifications the for timing requirements for LVDS.
(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and
D_AP(15:0).
(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and
D_BP(15:0).
(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and
D_CP(15:0).
(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and
D_DP(15:0).
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6.8.1 Timing Diagrams
SCPCLK falling–edge capture for SCPDI.
SCPCLK rising–edge launch for SCPDO.
tSCP_NEG_ENZ
tSCP_POS_ENZ
50%
50%
SCPENZ
tSCP_DS
tSCP_DH
50%
50%
DI
SCPDI
tC
fSCPCLK = 1 / tC
50%
50%
50%
50%
SCPCLK
tSCP_PD
50%
DO
SCPDO
See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH and tSCP_PD specifications.
图6-2. SCP Timing Requirements
SCPCLK, SCPDI,
SCPDO, SCPENZ
100%
80%
20%
0%
tf
tr
Time
See Timing Diagrams for tr and tf specifications and conditions.
图6-3. SCP Requirements for Rise and Fall
Device pin
output under test
Tester channel
CLOAD
For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers use
IBIS or other simulation tools to correlate the timing reference load to a system environment.
图6-4. Test Load Circuit for Output Propagation Measurement
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VLVDS max = VCM max + | 1/2 * VID max
|
tf
VCM
VID
tr
VLVDS min = VCM min œ | 1/2 * VID max
|
See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions.
图6-5. LVDS Waveform Requirements
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t
c
t
w
t
w
DCLK_P
DCLK_N
50%
t
t
t
t
h
h
h
h
t
t
t
t
su
su
su
su
D_P(?:0)
D_N(?:0)
50%
SCTRL_P
SCTRL_N
50%
t
skew
t
c
t
w
t
w
DCLK_P
DCLK_N
50%
t
t
t
t
h
h
h
h
t
t
t
t
su
su
su
su
D_P(?:0)
D_N(?:0)
50%
SCTRL_P
SCTRL_N
50%
See Timing Diagrams for timing requirements and LVDS pairs per channel (bus) defining D_P(?:0) and D_N(?:0).
图6-6. Timing Requirements
6.9 System Mounting Interface Loads
表6-1. System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
12
UNIT
kg
Thermal interface area(1)
Electrical interface area(1)
25
kg
(1) Uniformly distributed within area shown in 图6-7.
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Electrical Interface Area
Thermal Interface Area
图6-7. System Mounting Interface Loads
6.10 Micromirror Array Physical Characteristics
表6-2. Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
VALUE
1920
1080
5.4
UNIT
micromirrors
micromirrors
µm
Number of active columns (1)
M
N
P
Number of active rows (1)
Micromirror (pixel) pitch (1)
Micromirror active array width (1)
Micromirror active array height (1)
Micromirror active border (top / bottom) (2)
Micromirror active border (right / left) (2)
Micromirror pitch × number of active columns
Micromirror pitch × number of active rows
Pond of micromirrors (POM)
10.368
5.832
80
mm
mm
micromirrors/side
micromirrors/side
Pond of micromirrors (POM)
84
(1) See 图6-8.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the
pond of micromirrors (POM). These micromirrors are prevented from tilting toward the bright or “on”state but still require an
electrical bias to tilt toward “off.”
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Off-State
Light Path
0
1
2
3
Active Micromirror Array
M x N Micromirrors
N x P
Nœ 4
Nœ 3
Nœ 2
Nœ 1
M x P
P
Incident
Illumination
Light Path
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity. Not to scale.
P
图6-8. Micromirror Array Physical Characteristics
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
6.11 Micromirror Array Optical Characteristics
表6-3. Micromirror Array Optical Characteristics
PARAMETER
MIN
NOM
17.0
MAX
UNIT
Mirror tilt angle, variation device to device(1) (2) (3) (4)
15.6
18.4
0
degrees
Adjacent micromirrors
Number of out-of-specification micromirrors (5)
micromirrors
%
Non-Adjacent
micromirrors
10
68
DMD Efficiency (420 nm –680 nm)
(1) Measured relative to the plane formed by the overall micromirror array
(2) Variation can occur between any two individual mircromirrors located on the same device or located on different devices.
(3) Additional variation exists between the micromirror array and the package datums. See package drawing.
(4) See 图6-9.
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(5) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states.
Border micromirrors omitted for clarity
Off State
Light Path
Details omitted for clarity.
Not to scale.
0
1
2
3
Tilted Axis of
Pixel Rotation
Off-State
Landed Edge
On-State
Landed Edge
Nœ 4
Nœ 3
Nœ 2
Nœ 1
Incident
Illumination
Light Path
A. Pond of micromirrors (POM) omitted for clarity.
B. Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
图6-9. Micromirror Landed Orientation and Tilt
6.12 Window Characteristics
表6-4. DMD Window Characteristics
DESCRIPTION
MIN
NOM
Corning Eagle XG
1.5119
Window material
Window refractive index at 546.1 nm
Window transmittance, minimum within the wavelength range 420-680 nm. Applies to all angles 0°-30°
AOI. (1) (2)
97%
97%
Window transmittance, average over the wavelength range 420-680 nm. Applies to all angles 30°-45° AOI.
(1) (2)
(1) Single-pass through both surfaces and glass.
(2) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP470TE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DMD is a 0.47-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The
electrical interface is low voltage differential signaling (LVDS). The DMD consists of a two-dimensional array of
1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows.
Refer to the Functional Block Diagram. The positive or negative deflection angle of the micromirrors can be
individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror
reset signals (MBRST).
The DLP470TE DMD is part of the chipset that comprises the DLP470TE DMD, the DLPC4420 display
controller, and the DLPA100 power and motor driver. To ensure reliable operation, the DLP470TE DMD must
always be used with the DLPC4420 display controller and the DLPA100 power and motor driver.
7.2 Functional Block Diagram
Channel A Interface
Column Read and Write
Control
Control
(0,0)
Voltages
Word Lines
Voltage
Generators
Micromirror Array
Row
(M-1, N-1)
Column Read and Write
Channel B Interface
Control
Control
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备注
Channels C and D not shown. For pin details on channels A, B, C, and D, refer to the Pin
Configurations and Functions table and the LVDS interface section of Timing Diagrams.
RESET_CTRL is utilized in applications when an external reset signal is required.
7.3 Feature Description
7.3.1 Power Interface
The DMD requires five DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V is
created by the DLPA100 power and motor driver and is used on the DMD board to create the other 4 DMD
voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators). DMD_P1P8V is
created by the TI PMIC LP38513S and provides the VCC voltage required by the DMD. VOFFSET (10 V), VRESET
(–14 V), and VBIAS (18 V) are made by the TI PMIC TPS65145 and are supplied to the DMD to control the
micromirrors.
7.3.2 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. The specifications show an equivalent test load circuit for
the output under test. Timing reference loads are not intended as a precise representation of any particular
system environment or depiction of the actual load presented by a production test. System designers use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance
value stated is only for characterization and measurement of AC timing signals. This load capacitance value
does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC4420 display controller. For more information, see the
DLPC4420 Display Controller Data Sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
System optical performance and image quality strongly relate to optical system design parameter trade offs.
Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
needs to be the same. This angle cannot exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and projection pupils to block out flat-state and stray light from the
projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle, contrast degradation, and objectionable artifacts in the display
border or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border or active area, which may require additional system apertures to control, especially
if the numerical aperture of the system exceeds the pixel tilt angle.
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7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical
system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the
average flux level in the active area. Depending on the particular system optical architecture, overfill light may
have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
Array
TP2
2X 11.75
TP5
TP4
TP3
2X 16.10
Window Edge
(4 surfaces)
TP3 (TP2)
TP5
TP4
TP1
5.05
16.10
TP1
图7-1. DMD Thermal Test Points
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Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship
between micromirror array temperature and the reference ceramic temperature is provided by the following
equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
(1)
(2)
QARRAY = QELECTRICAL + QILLUMINATION
)
where
• TARRAY = computed array temperature (°C)
• TCERAMIC = measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = thermal resistance of package from array to ceramic TP1 (°C/Watt)
• QARRAY = Total DMD power on the array (Watts) (electrical + absorbed)
• QELECTRICAL = nominal electrical power
• QILLUMINATION = (CL2W × SL)
• CL2W = Conversion constant for screen lumens to power on DMD (Watts/Lumen)
• SL = measured screen lumens
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.9 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a 1-Chip DMD system with
projection efficiency from the DMD to the screen of 87%.
The conversion constant CL2W is based on array characteristics. It assumes a spectral efficiency of 300 lumens/
Watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array
border.
Sample calculations for typical projection application:
QELECTRICAL = 0.9 W
(3)
(4)
(5)
(6)
(7)
(8)
CL2W = 0.00266
SL = 4000 lm
TCERAMIC = 55.0°C
QARRAY = 0.9 W + (0.00266 × 4000 lm) = 11.54 W
TARRAY = 55.0°C + (11.54 W × 0.90°C/W) = 65.39°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the
time (and in the OFF state 0% of the time), whereas 0/100 indicate that the pixel is in the OFF state 100% of the
time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing the landed duty cycle, the time spent switching from one state (ON or OFF) to the
other state (OFF or ON) is considered negligible and is thus ignored.
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Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD usable life.
Note that it is the symmetry or asymmetry of the landed duty cycle that is of relevance. The symmetry of the
landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a
landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD usable life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD usable life. This is
quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature at a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the; gray scale value, as shown in 表7-1.
表7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, or blue) for the given pixel as well as the color cycle
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time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
Use the following equation to calculate the landed duty cycle of a given pixel during a specified time period
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
where
• Red_Cycle_% represents the percentage of the frame time that red is displayed to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
• Blue_Cycle_% represents the percentage of the frame time that blue is displayed to achieve the desired
white point
For example, assume that the red, green, and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, and
blue color intensities are as shown in 表7-2 and 表7-3.
表7-2. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
RED
GREEN
BLUE
50%
20%
30%
表7-3. Example Landed Duty Cycle for Full-Color
SCALE VALUE
GREEN
0%
LANDED DUTY
CYCLE
RED
0%
BLUE
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
7/93
0%
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
60%
60%
100%
12%
100%
0%
100%
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8 Application and Implementation
备注
Information in the following application section is not part of the TI component specifications, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Texas Instruments DLP® technology is a micro-electro-mechanical systems (MEMS) technology that modulates
light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light
from an illumination source to one of two directions, towards the projection optics or collection optics. The new
TRP pixel with a higher tilt angle increases brightness performance and enables smaller system electronics for
size constrained applications. Typical applications using the DLP470NE include home theater, digital signage,
interactive displays, low-latency gaming displays, and portable smart displays.
The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology
called TRP. With a smaller pixel pitch of 5.4 µm and increased tilt angle of 17 degrees, TRP chipsets enable
higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical
efficiency. DLP® chipsets are a great fit for any system that requires high resolution and high brightness displays.
The following orderables have been replaced by the DLP470TE.
Device Information
PART NUMBER
1910-5532B
PACKAGE
BODY SIZE (NOM)
Mechanical ICD
FXJ (257)
FXJ (257)
FXJ (257)
32.2 mm × 22.3 mm
2516207
2516207
2516207
32.2 mm × 22.3 mm
32.2 mm × 22.3 mm
1910-5537B
1910-553AB
8.2 Typical Application
The DLP470TE DMD combined with two DLPC4420 display controllers, an FPGA, a power management device
DLPA100, and other electrical, optical, and mechanical components, enables bright, affordable, full 4K UHD
display solutions. 图8-1 shows a typical 4K UHD system application using the DLP470TE DMD.
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1.1V
1.15V
1.8V
2.5V
3.3V
FPGA
Voltage
Regulators
12V
PWM Driver
Flash
EPROM
I2C
1.1V
1.8V
3.3V
(23) (16)
DLPA100
Controller
PMIC
ADDR
DATA
12V
RGB_EN
(3)
CTRL
RGB_PWM
(3)
FE CTRL
DDR3
USB CTRL
DATA
GPIO
3.3 V
CTRL
DDR3
DLPC4420
Controller
Primary
VBIAS, VOFFSET, VRESET
ADDR
(3)
DMD PMIC
(Power Management IC)
DATA
Front End Device
3D
L/R
SCP CTRL
I2C
2xLVDS
SPI
HBT
4K UHD DMD
Vx1:
XPR FPGA
Vx1
3840 × 2160 @ 60Hz
2xLVDS
I2C
1.8 V
DATA
GPIO
DLPC4420
Controller
Secondary
SPI
Flash
JTAG
ACTUATOR CTRL
Actuator
Driver
4-Position
Actuator
CTRL
1.1V
1.8V
3.3V
DLPA100
Controller
PMIC
ADDR
DATA
I2C
(23) (16)
12V
TI DLP chipset
Flash
EPROM
Third party component
1.1V
12V
12V
1.21V
1.8V
3.3V
1.21V
FPGA
Voltage
Regulators
1.15V
1.8V
2.5V
3.3V
DLPA100
Controller PMIC
CW Driver
DLPA100
Controller PMIC
CW Driver
1.8V
3.3V
5V
12V
Flash
EPROM
I2C
5V
(23) (16)
ADDR
DATA
CTRL
GPIO
Wheel Motor #2
Wheel Motor #1
CTRL
FE CTRL
DDR3
USB CTRL
DATA
DDR3
DLPC4420
Controller
Primary
VBIAS, VOFFSET, VRESET
(3)
3.3 V
ADDR
1.1V
DMD PMIC
(Power Management IC)
CTRL
1.8V
3.3V
DATA
Front End Device
3D
L/R
SCP CTRL
2xLVDS
I2C
SPI
HBT
Vx1:
4K UHD DMD
XPR FPGA
Vx1
3840 × 2160 @ 60Hz
2xLVDS
I2C
1.8 V
DATA
GPIO
DLPC4420
Controller
Secondary
SPI
Flash
JTAG
ACTUATOR CTRL
Actuator
Driver
4-Position
Actuator
1.1V
1.8V
3.3V
ADDR
DATA
I2C
(23) (16)
TI DLP chipset
Flash
EPROM
Third party component
图8-1. Typical DLPC4420 4K UHD Application (LED, Top; LPCW, Bottom)
8.2.1 Design Requirements
A DLP470TE projection system is created by using the DMD chipset, including the DLP470TE digital micromirror
device (DMD), the DLPC4420 controller, and the DLPA100 power management and motor driver. The
DLP470TE is used as the core imaging device in the display system and contains a 0.47-inch array of
micromirrors. The DLPC4420 controller is the digital interface between the DMD and the rest of the system,
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taking digital input from a front-end receiver and driving the DMD over a high-speed interface. The DLPA100
power management device provides voltage regulators for the DMD, controller, and illumination functionality.
Other core components of the display system include an FPGA, illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The illumination
source options include lamp, LED, laser, or laser phosphor. The type of illumination used and desired brightness
will have a major effect on the overall system design and size.
8.2.2 Detailed Design Procedure
For a complete DLP® system, an optical module or light engine is required that contains the DLP470TE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DLP470TE DMD must always be used with the DLPC4420 display controller
and the DLPA100 PMIC driver. Refer to the PCB design requirements to see DLP standard TRP digital
micromirror devices for the DMD board design and manufacturer handling of the DMD sub-assemblies.
8.2.3 Application Curves
When LED illumination is utilized, the typical LED-current-to-luminance relationship is shown in 图8-2.
图8-2. Luminance vs. Current
8.3 DMD Die Temperature Sensing
The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the
micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in 图8-3.
The serial bus from the TMP411 can be connected to the DLPC4420 display controller to enable its temperature
sensing features. See the DLPC4420 Programmers’ Guide for instructions on installing the DLPC4420
controller support firmware bundle and obtaining the temperature readings.
The software application contains functions to configure the TMP411 to read the DMD temperature sensor diode.
This data can be leveraged to incorporate additional functionality in the overall system design such as adjusting
illumination, fan speeds, and so forth. All communication between the TMP411 and the DLPC4420 controller will
be completed using the I2C interface. The TMP411 connects to the DMD via pins B17 and B18 as outlined in Pin
Configuration and Functions.
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3.3V
R1
R2
TMP411
DLP470TE
SCL
VCC
D+
R3
R5
TEMP_P
SDA
ALERT
THERM
GND
C1
R4
R6
D-
TEMP_N
GND
A. Details omitted for clarity, see the TI Reference Design for connections to the DLPC4420 controller.
B. See the TMP411 data sheet for system board layout recommendation.
C. See the TMP411 data sheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.
D. R5 = 0 Ω. R6 = 0 Ω. Zero ohm resistors need to be located close to the DMD package pins.
图8-3. TMP411 Sample Schematic
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VCC
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the ®DLP display controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See 图9-1.
VBIAS, VCC, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-
down operations. Failure to meet any of the below requirements will result in a significant reduction
in the DMD reliability and lifetime. Common ground VSS must also be connected.
9.1 DMD Power Supply Power-Up Procedure
• During power-up, VCC must always start and settle before VOFFSET plus Delay1 specified in 表9-1, VBIAS, and
VRESET voltages are applied to the DMD.
• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Recommended Operating Conditions.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in the Absolute Maximum Ratings, in the Recommended Operating Conditions, and in
图9-1.
• During power-up, LVCMOS input pins must not be driven high until after VCC have settled at operating
voltages listed in the Recommended Operating Conditions.
9.2 DMD Power Supply Power-Down Procedure
• During power-down, VCC must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the
specified limit of ground. See 表9-1.
• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in the Recommended Operating Conditions.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in the Absolute Maximum Ratings, in the Recommended Operating Conditions, and in
图9-1.
• During power-down, LVCMOS input pins must be less than specified in the Recommended Operating
Conditions.
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Not to scale. Details omitted for clarity
Note 1
VCC
VSS
VSS
Note 2
ûV < Specification
VOFFSET
Note 4
Delay 1
VBIAS
VSS
VSS
Note 3
ûV < Specification
VRESET
EN_OFFSET
VSS
Note 9
Delay 2
Note 5
PG_OFFSET
Note 7
VSS
RESET_OEZ
VSS
Note 6
Note 8
PWRDNZ
and RESETZ
VSS
A. See Recommended Operating Conditions, and the Pin Functions table.
B. To prevent excess current, the supply voltage difference |VOFFSET –VBIAS| must be less than the specified limit in the Recommended
Operating Conditions
C. To prevent excess current, the supply difference |VBIAS –VRESET| must be less than the specified limit in the Recommended Operating
Conditions.
D. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in 表9-1
E. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in 表9-1.
F. ®DLP controller software enables the DMD power supplies VBIAS, VRESET, VOFFSET with VCC active after RESET_OEZ is at logic high.
G. ®DLP controller software initiates the global VBIAS command.
H. After the DMD micromirror park sequence is complete, the ®DLP controller software initiates a hardware power-down that activates
PWRDNZ and disables VBIAS, VRESET, and VOFFSET
.
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I.
Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the ®DLP controller hardware,
EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to PG_OFFSET turning off to indicate the
DMD micromirror has completed the emergency park procedures.
图9-1. DMD Power Supply Requirements
表9-1. DMD Power-Supply Requirements
PARAMETER
Delay1
Delay2
DESCRIPTION
MIN
1
NOM
MAX
UNIT
ms
Delay from VOFFSET settled at recommended operating voltage to
VBIAS and VRESET power up
2
PG_OFFSET hold time after EN_OFFSET goes low
100
ns
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10 Layout
10.1 Layout Guidelines
The DLP470TE DMD is part of a chipset that is controlled by the DLPC4420 display controller in conjunction with
the DLPA100 power and motor driver. These guidelines are targeted to help design a PCB board with the
DLP470TE DMD. The DLP470TE DMD board is a high-speed multilayer PCB, with primarily high-speed digital
logic using dual-edge clock rates up to 400 MHz for DMD LVDS signals. The remaining traces are comprised of
low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and
VBIAS. Solid planes are required for DMD_P3P3V(3.3 V), DMD_P1P8V and Ground. The target impedance for
the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10% differential. TI recommends using an 8-layer
stack-up, as described in 表10-1.
10.2 Layout Example
10.2.1 Layers
The layer stack-up and copper weight for each layer is shown in 表10-1. Small sub-planes are allowed on signal
routing layers to connect components to major sub-planes on top/bottom layers if necessary.
表10-1. Layer Stack-Up
LAYER
NO.
LAYER NAME
Side A - DMD only
COPPER WT. (oz.)
COMMENTS
1
1.5
1
DMD, escapes, low frequency signals, power sub-planes.
Solid ground plane (net GND).
2
Ground
3
Signal
0.5
1
50 Ωand 100 Ωdifferential signals
4
Ground
Solid ground plane (net GND)
5
DMD_P3P3V
1
+3.3-V power plane (net DMD_P3P3V)
50 Ωand 100 Ωdifferential signals
6
Signal
0.5
1
7
Ground
Solid ground plane (net GND).
8
Side B - All other Components
1.5
Discrete components, low frequency signals, power sub-planes
10.2.2 Impedance Requirements
TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed
in 表10-2.
表10-2. Special Impedance Requirements
Signal Type
Signal Name
Impedance (ohms)
D_AP(0:15), D_AN(0:15)
DCLKA_P, DCLKA_N
SCTRL_AP, SCTRL_AN
D_BP(0:15), D_BN(0:15)
DCLKB_P, DCLKB_N
SCTRL_BP, SCTRL_BN
D_CP(0:15), D_CN(0:15)
DCLKC_P, DCLKC_N
SCTRL_CP, SCTRL_CN
D_DP(0:15), D_DN(0:15)
DCLKD_P, DCLKD_N
SCTRL_DP, SCTRL_DN
100 ±10% differential across
each pair
A channel LVDS differential pairs
100 ±10% differential across
each pair
B channel LVDS differential pairs
C channel LVDS differential pairs
D channel LVDS differential pairs
100 ±10% differential across
each pair
100 ±10% differential across
each pair
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10.2.3 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005-inch/0.005-inch design rule.
Minimum trace clearance from the ground ring around the PWB has a 0.1-inch minimum. An analysis of
impedance and stack-up requirements determine the actual trace widths and clearances.
10.2.3.1 Voltage Signals
表10-3. Special Trace Widths, Spacing Requirements
MINIMUM TRACE WIDTH TO
SIGNAL NAME
GND
LAYOUT REQUIREMENT
Maximize trace width to connecting pin
PINS (MIL)
15
15
15
15
15
15
DMD_P3P3V
DMD_P1P8V
VOFFSET
VRESET
Maximize trace width to connecting pin
Maximize trace width to connecting pin
Create mini plane from U2 to U3
Create mini plane from U2 to U3
Create mini plane from U2 to U3
VBIAS
All U3 control
connections
10
Use 10 mil etch to connect all signals/voltages to DMD pads
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP470TE AA FXJ
Package
TI Internal Numbering
Device Descriptor
图11-1. Part Number Description
11.1.2 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in 图11-2. The 2-dimensional matrix code is an alpha-numeric character string
that contains the DMD part number, part 1 of the serial number, and part 2 of the serial number. The first
character of the DMD serial number (part 1) is the manufacturing year. The second character of the DMD serial
number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias
voltage bin letter.
Example: *1910-553AB GHXXXXX LLLLLLM
2-Dimension Matrix Code
(Part Number and Serial Number)
DMD Part Number
*1910-553xB
GHXXXXX LLLLLLM
Part 1 of Serial Number
(7 characters)
Part 2 of Serial Number
(7 characters)
图11-2. DMD Marking Locations
11.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
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11.3 Documentation Support
11.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the
DLP470TE.
• DLPC4420 Display Controller Data Sheet
• DLPA100 Power Management and Motor Driver Data Sheet
11.3.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP470TEAAFXJ
ACTIVE
CLGA
FXJ
257
33
RoHS & Green
Call TI
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DLP470TEAAFXJ
0.47-inch, 4K UHD, 2XLVDS DLP® digital micromirror device (DMD) | FXJ | 257 | 0 to 70
TI
DLP471TEA0FYN
0.47-inch, 4K UHD, HSSI DLP® digital micromirror device (DMD) | FYN | 149 | 0 to 70
TI
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