DLP471TP [TI]
0.47-inch 4K UHD DLP® digital micromirror device (DMD);型号: | DLP471TP |
厂家: | TEXAS INSTRUMENTS |
描述: | 0.47-inch 4K UHD DLP® digital micromirror device (DMD) |
文件: | 总48页 (文件大小:1895K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DLP471TP
ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
DLP471TP 0.47 4K 超高清DMD
1 特性
3 说明
• 0.47 英寸对角线微镜阵列
DLP471TP 数字微镜器件 (DMD) 是一款数控微机电系
统 (MEMS) 空间照明调制器 (SLM),可用于实现高亮
的 4K 超高清显示系统。TI DLP® 产品 0.47 英寸 4K
UHD 芯片组由 DMD、DLPC6540 显示控制器以及
DLPA3005 PMIC 和 LED 驱动器组成。芯片组的外形
紧凑,为体型小巧的 4K 超高清显示器提供完整的系统
解决方案。
– 4K 超高清(3840 × 2160) 显示分辨率
– 5.4 µm 微镜间距
– ±17° 微镜倾斜度(相对于平坦表面)
– 底部照明
• 高速串行接口(HSSI) 输入数据总线
• 支持4K UHD (60Hz)
• 支持1080p(高达240Hz)
• 由DLPC6540 显示控制器、DLPA3005 电源管理
IC (PMIC) 和LED 驱动器支持LED 正常运行
器件信息(1)
封装尺寸(标称值)
器件型号
DLP471TP
封装
FQQ (270)
25.65mm × 16.9mm
2 应用
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 移动智能电视
• 移动投影仪
• 数字标牌
LS_Interface
HSSI Macro A Data Pair
DMD DCLKA
8
8
HSSI Macro B Data Pair
DMD DCLKB
DLPC6540
Display Controller
DLP471TP
HSSI DMD
Vx1
V
V
V
OFFSET
BIAS
2
I C/SPI
Power
Management
RESET
1.8 V
VREG
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: DLPS173
DLP471TP
ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
www.ti.com.cn
Table of Contents
7.7 Micromirror Power Density Calculation.....................25
7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 28
8 Application and Implementation..................................31
8.1 Application Information............................................. 31
8.2 Typical Application.................................................... 31
8.3 Temperature Sensor Diode.......................................32
9 Power Supply Recommendations................................33
9.1 DMD Power Supply Power-Up Procedure................33
9.2 DMD Power Supply Power-Down Procedure........... 33
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Impedance Requirements.......................................35
10.3 Layers..................................................................... 35
10.4 Trace Width, Spacing..............................................36
10.5 Power......................................................................36
10.6 Trace Length Matching Recommendations............ 37
11 Device and Documentation Support..........................38
11.1 第三方产品免责声明................................................38
11.2 Device Support........................................................38
11.3 Documentation Support.......................................... 39
11.4 支持资源..................................................................39
11.5 Trademarks............................................................. 39
11.6 静电放电警告...........................................................39
11.7 术语表..................................................................... 39
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 Storage Conditions..................................................... 9
6.3 ESD Ratings............................................................... 9
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information..................................................11
6.6 Electrical Characteristics...........................................12
6.7 Switching Characteristics..........................................13
6.8 Timing Requirements................................................14
6.9 System Mounting Interface Loads............................ 17
6.10 Micromirror Array Physical Characteristics.............18
6.11 Micromirror Array Optical Characteristics............... 19
6.12 Window Characteristics.......................................... 21
6.13 Chipset Component Usage Specification............... 21
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................23
7.5 Optical Interface and System Image Quality
Considerations............................................................ 23
7.6 Micromirror Array Temperature Calculation.............. 24
Information.................................................................... 40
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2022) to Revision B (July 2023)
Page
• Added section "ILLUMINATION" to Recommended Operating Conditions ....................................................... 9
• Updated Micromirror Array Temperature Calculation ...................................................................................... 24
• Added Micromirror Power DensityCalculation ................................................................................................. 25
Changes from Revision * (August 2020) to Revision A (June 2022)
Page
• 根据最新的德州仪器 (TI) 和行业标准对本文档进行了更新.................................................................................1
• Updated |TDELTA| MAX from 14°C to 15°C..........................................................................................................9
• Updated Micromirror Array Optical Characteristics ......................................................................................... 19
• Updated 图9-1 ................................................................................................................................................ 33
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
2
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5 Pin Configuration and Functions
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11
13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24
图5-1. FQQ Package 270-Pin CLGA (Bottom View)
表5-1. Pin Functions
PIN(2)
TRACE
LENGTH
(mm)
TYPE(1)
DESCRIPTION
TERMINATION
NAME
PAD ID
A8
D_AP(0)
D_AN(0)
D_AP(1)
D_AN(1)
D_AP(2)
D_AN(2)
D_AP(3)
D_AN(3)
D_AP(4)
D_AN(4)
D_AP(5)
D_AN(5)
D_AP(6)
D_AN(6)
D_AP(7)
D_AN(7)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
High-speed Differential Data Pair lane A0
High-speed Differential Data Pair lane A0
High-speed Differential Data Pair lane A1
High-speed Differential Data Pair lane A1
High-speed Differential Data Pair lane A2
High-speed Differential Data Pair lane A2
High-speed Differential Data Pair lane A3
High-speed Differential Data Pair lane A3
High-speed Differential Data Pair lane A4
High-speed Differential Data Pair lane A4
High-speed Differential Data Pair lane A5
High-speed Differential Data Pair lane A5
High-speed Differential Data Pair lane A6
High-speed Differential Data Pair lane A6
High-speed Differential Data Pair lane A7
High-speed Differential Data Pair lane A7
High-speed Differential Clock A
2.15873
2.16135
8.33946
8.34121
6.41271
6.41305
1.8959
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
A7
B2
C2
A6
A5
A10
A9
1.8959
D1
E1
12.11543
12.11539
12.01561
12.0164
12.98403
12.98177
2.29773
2.29773
11.75367
11.57432
2.10786
2.10711
D3
E3
F3
G3
A12
A11
A3
DCLK_AP
DCLK_AN
D_BP(0)
A4
High-speed Differential Clock A
A14
A15
High-speed Differential Data Pair lane B0
High-speed Differential Data Pair lane B0
D_BN(0)
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English Data Sheet: DLPS173
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ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
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表5-1. Pin Functions (continued)
PIN(2)
TRACE
LENGTH
(mm)
TYPE(1)
DESCRIPTION
TERMINATION
NAME
PAD ID
F23
D_BP(1)
D_BN(1)
D_BP(2)
D_BN(2)
D_BP(3)
D_BN(3)
D_BP(4)
D_BN(4)
D_BP(5)
D_BN(5)
D_BP(6)
D_BN(6)
D_BP(7)
D_BN(7)
I
I
High-speed Differential Data Pair lane B1
High-speed Differential Data Pair lane B1
High-speed Differential Data Pair lane B2
High-speed Differential Data Pair lane B2
High-speed Differential Data Pair lane B3
High-speed Differential Data Pair lane B3
High-speed Differential Data Pair lane B4
High-speed Differential Data Pair lane B4
High-speed Differential Data Pair lane B5
High-speed Differential Data Pair lane B5
High-speed Differential Data Pair lane B6
High-speed Differential Data Pair lane B6
High-speed Differential Data Pair lane B7
High-speed Differential Data Pair lane B7
High-speed Differential Clock B
High-speed Differential Clock B
LVDS Data
12.79448
12.79438
13.00876
13.00932
11.21886
11.21881
10.79038
10.78946
5.75986
5.75928
9.01461
9.01416
2.08767
2.08767
2.12928
2.30933
0
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
Differential 100 Ω
G23
E24
E23
A22
A23
D25
D24
A20
A21
B24
B25
A18
A19
A17
A16
T16
R16
T14
R14
R18
T20
C21
R20
T18
R12
T12
I
I
I
I
I
I
I
I
I
I
I
I
DCLK_BP
I
DCLK_BN
I
LS_WDATA_P
LS_WDATA_N
LS_CLK_P
I
I
LVDS Data
0.27407
2.43086
2.40852
2.00263
4.61261
3.03604
2.88361
1.89945
4.02546
3.62598
I
LVDS CLK
LS_CLK_N
I
LVDS CLK
LS_RDATA_A_BISTA
BIST_B
O
O
O
O
I
LVCMOS Output
LVCMOS Output
AMUX_OUT
DMUX_OUT
DMD_DEN_ARSTZ
TEMP_N
Analog Test Mux
Digital Test Mux
ARSTZ
17.5-kΩpulldown
I
Temp Diode N
TEMP_P
I
Temp Diode P
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
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表5-1. Pin Functions (continued)
PIN(2)
TRACE
TYPE(1)
DESCRIPTION
TERMINATION
LENGTH
(mm)
NAME
PAD ID
B13, C5,
C9, C12,
C15, C18,
C22, D6,
D7, D14,
D16, D19,
D20, E21,
G21, J4,
J21, J23,
K3, K22,
L2, L4,
L22, M1,
M3, M21,
M23, M25,
N2, N4, N6,
N8, N16,
N18, N20,
N22, N24,
P3, P5, P7,
P9, P11,
VDD
P
Digital core supply voltage
Plane
P13, P15,
P17, P19,
P21, P23,
P25, R2,
R4, R6, R8,
R10, T3,
T5, T7, T9,
T11, T13,
T15, T17,
T19, T21,
T23
A24, B3,
B5, B7, B9,
B11, B14,
B16, B18,
B20, B22,
C1, C24,
D4, D23,
E2, F4,
VDDA
P
HSSI supply voltage
Plane
F22, H3,
H22
Supply voltage for negative bias of
micromirror reset signal
VRESET
VBIAS
A2, R1
B1, P1
P
P
P
Plane
Plane
Plane
Supply voltage for positive bias of
micromirror reset signal
A1, A25,
T1, T25
Supply voltage for HVCMOS logic, stepped
up logic level
VOFFSET
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English Data Sheet: DLPS173
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ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
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表5-1. Pin Functions (continued)
PIN(2)
TRACE
LENGTH
(mm)
TYPE(1)
DESCRIPTION
TERMINATION
NAME
PAD ID
C4, C6, C8,
C10, C13,
C14, C17,
C19, C23,
D5, D8,
D15, D17,
D18, D21,
D22, F21,
H4, H21,
J3, J22, K4,
K21, K23,
L3, L21,
L23, M2,
M4, M22,
M24, N1,
N3, N5, N7,
N17, N19,
N21, N23,
N25, P2,
VSS
G
Ground
Plane
P4, P6, P8,
P10, P12,
P14, P16,
P18, P20,
P22, P24,
R3, R5, R7,
R9, R11,
R13, R15,
R17, R19,
R21, R23,
R25, T2,
T4, T8, T10
A13, B4,
B6, B8,
B10, B12,
B15, B17,
B19, B21,
B23, C3,
C7, C11,
C16, C20,
C25, D2,
E4, E22,
E25, F2,
G4, G22,
H23
VSSA
G
Ground
Plane
None
DMD_Detect
T6
NC
DMD detection
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
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表5-1. Pin Functions (continued)
PIN(2)
TRACE
TYPE(1)
DESCRIPTION
TERMINATION
LENGTH
(mm)
NAME
PAD ID
D9, D10,
D11, D12,
D13, E10,
E11, E12,
E13, E14,
E15, E16,
E17, E18,
F24, G2,
K2, L24,
M12, M13,
M14, M15,
M16, M17,
M18, N9,
N10, N11,
N12, N13,
N14, N15,
R22,
N/C
NC
No connect pin
None
R24 ,T22,
T24
(1) I=Input, O=Output, P=Power, G=Ground, NC = No Connect
(2) Only 238 pins are electrically connected for functional use.
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6 Specifications
6.1 Absolute Maximum Ratings
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating
Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN
MAX UNIT
SUPPLY VOLTAGE
Supply voltage for LVCMOS core logic and LVCMOS low speed interface
(LSIF)(1)
VDD
2.3
V
–0.5
VDDA
Supply voltage for high speed serial interface (HSSI) receivers(1)
Supply voltage for HVCMOS and micromirror electrode(1) (2)
Supply voltage for micromirror electrode(1)
2.2
11
V
V
V
V
V
V
V
–0.3
–0.5
–0.5
–15
VOFFSET
VBIAS
19
0.5
0.3
11
VRESET
Supply voltage for micromirror electrode(1)
Supply voltage delta (absolute value)(3)
| VDDA –VDD
|
Supply voltage delta (absolute value)(4)
| VBIAS –VOFFSET
|
Supply voltage delta (absolute value)(5)
34
| VBIAS –VRESET
|
INPUT VOLTAGE
Input voltage for other inputs –LSIF and LVCMOS(1)
Input voltage for other inputs –HSSI(1) (6)
–0.5
–0.2
2.45
V
V
VDDA
LOW SPEED INTERFACE (LSIF)
fCLOCK LSIF clock frequency (LS_CLK)
130 MHz
| VID
IID
|
LSIF differential input voltage magnitude(6)
810
10
mV
mA
LSIF differential input current
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK HSSI clock frequency (DCLK)
1.65 GHz
| VID
| VID
|
|
HSSI differential input voltage magnitude Data Lane(6)
HSSI differential input voltage magnitude Clock Lane(6)
700
700
mV
mV
ENVIRONMENTAL
Temperature, operating(7)
0
90
90
°C
°C
TWINDOW and TARRAY
Temperature, non-operating(7)
–40
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1(8)
|TDELTA
TDP
|
30
81
°C
°C
Dew point temperature, operating and non–operating (noncondensing)
(1) All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper
DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI
differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in 图7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in 图7-1 are intended to measure the
highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,
that point should be used.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
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6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
85
24
36
6
UNIT
°C
TDMD
DMD temperature
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature, non-condensing(1)
Elevated dew point temperature range, non-condensing(2)
Cumulative time in elevated dew point temperature range
°C
28
°C
months
(1) The average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew point
temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC specification ANSI/ESDA/JEDEC
JS-002(2)
±500
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGES (1) (2)
Supply voltage for LVCMOS core logic and low speed
interface (LSIF)
VDD
1.71
1.8
1.95
V
VDDA
Supply voltage for high speed serial interface (HSSI) receivers
Supply voltage for HVCMOS and micromirror electrode(3)
Supply voltage for micromirror electrode
Supply voltage for micromirror electrode
Supply voltage delta, absolute value(4)
1.71
9.5
1.8
10
1.95
10.5
V
V
V
V
V
VOFFSET
VBIAS
17.5
18
18.5
VRESET
–14.5
–14
–13.5
0.3
| VDDA –VDD
|
| VBIAS –VOFFSET
|
Supply voltage delta, absolute value(5)
Supply voltage delta, absolute value
|
10.5
33
V
V
| VBIAS –VRESET
LVCMOS INPUT
VIH
VIL
High level input voltage(6)
Low level input voltage(6)
0.7 × VDD
V
V
0.3 × VDD
LOW SPEED SERIAL INTERFACE (LSIF)
fCLOCK
DCDIN
LSIF clock frequency (LS_CLK)(7)
108
44%
150
575
700
90
120
350
130
56%
440
MHz
LSIF duty cycle distortion (LS_CLK)
LSIF differential input voltage magnitude(7)
LSIF voltage(7)
| VID
|
mV
mV
mV
Ω
VLVDS
VCM
ZLINE
ZIN
1520
1300
110
Common mode voltage(7)
900
100
100
Line differential impedance (PWB/trace)
Internal differential termination resistance
80
120
Ω
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6.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
TYP
MAX
UNIT
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK
HSSI clock frequency (DCLK)(8)
1.2
44
1.6
56
GHz
%
DCDIN
HSSI duty cycle distortion (DCLK)
50
| VID | Data
| VID | CLK
VCMDC Data
VCMDC CLK
HSSI differential input voltage magnitude Data Lane(8)
HSSI differential input voltage magnitude Clock Lane(8)
Input common mode voltage (DC) Data Lane(8)
Input common mode voltage (DC) Clk Lane(8)
100
295
200
200
600
600
800
800
mV
mV
mV
mV
600
600
AC peak to peak (ripple) on common mode voltage of Data
Lane and Clock Lane(8)
VCMACp-p
100
mV
ZLINE
Line differential impedance (PWB/trace)
100
100
Ω
Ω
ZIN
Internal differential termination resistance. ( RXterm
)
80
120
ENVIRONMENTAL
Array temperature, long–term operational(9) (10) (11) (12)
Array temperature, short-term operational, 500 hr max(10) (13)
Window temperature, operational(14)
10
0
40 to 70 (11)
°C
°C
°C
TARRAY
10
85
TWINDOW
Absolute temperature delta between any point on the window
edge and the ceramic test point TP1(15)
|TDELTA
|
15
°C
Average dew point temperature (non–condensing)(16)
Elevated dew point temperature range (non-condensing)(17)
Cumulative time in elevated dew point temperature range
TDP-AVG
TDP-ELR
CTELR
24
36
6
°C
°C
28
months
ILLUMINATION
ILLUV
Illumination power at wavelengths < 410 nm(9)
10 mW/cm2
ILLVIS
20.5
W/cm2
Illumination power at wavelengths ≥410 nm and ≤800
nm(19)
ILLIR
Illumination power at wavelengths > 800 nm
10 mW/cm2
ILLBLU
6.5
1.2
55
W/cm2
W/cm2
deg
Illumination power at wavelengths ≥410 nm and ≤475
nm(19)
ILLBLU1
ILLθ
Illumination power at wavelengths ≥410 nm and ≤445
nm(19)
Illumination marginal ray angle(18)
(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the VSS ground pins.
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta | VDDA –VDD | must be less than specified limit.
(5) To prevent excess current, the supply voltage delta | VBIAS –VOFFSET | must be less than specified limit.
(6) LVCMOS input pin is DMD_DEN_ARSTZ.
(7) See the low speed interface (LSIF) timing requirements in Timing Requirements.
(8) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.
(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in 图7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.
(11) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(12) Long-term is defined as the usable life of the device.
(13) Short-term is the total cumulative time over the useful life of the device.
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(14) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
图7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta
temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point
should be used.
(16) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(19) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength
range specified and the micromirror array temperature (TARRAY).
80
70
60
50
40
30
0/100
100/0
5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
65/35
95/5
90/10
85/15
80/20
75/25
70/30
60/40
55/45
50/50
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature—Derating Curve
6.5 Thermal Information
DLP471TP
FQQ PACKAGE
270 PIN
THERMAL METRIC
Unit
Thermal Resistance, active area to test point 1 (TP1)(1)
1.0
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the 节6.4. The total heat load on the DMD is largely driven by the
incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
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MAX UNIT
6.6 Electrical Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1) (2)
TEST CONDITIONS (1)
MIN
TYP
CURRENT –TYPICAL
(3)
IDD
Supply current VDD
Supply current VDDA
800
1000
20
1200 mA
1200 mA
25 mA
4.0 mA
mA
(3)
IDDA
(4) (5)
IOFFSET
IBIAS
Supply current VOFFSET
(4) (5)
Supply current VBIAS
Supply current VRESET
2.5
(5)
IRESET
-9.3
-6.9
POWER –TYPICAL
(3)
PDD
Supply power dissipation VDD
1440
1620
230
2437.5 mW
2340 mW
(3)
PDDA
Supply power dissipation VDDA
Supply power dissipation VOFFSET
(4) (5)
(4) (5)
POFFSET
367.5 mW
70.3 mW
PBIAS
Supply power dissipation VBIAS
Supply power dissipation VRESET
Supply power dissipation Total
43.2
(5)
PRESET
107.8
3441
152.25 mW
5367.55 mW
PTOTAL
LVCMOS INPUT
IIL
Low level input current (6)
High level input current (6)
VDD = 1.95 V, VI = 0 V
nA
–100
0.8 x VDD
100
IIH
VDD = 1.95 V, VI = 1.95 V
135 uA
LVCMOS OUTPUT
VOH
VOL
DC output high voltage (7)
DC output low voltage (7)
IOH = -2 mA
IOL = 2 mA
V
0.2 x VDD
V
RECEIVER EYE CHARACTERISTICS
A1
A2
X1
X2
Minimum data eye opening (8) (9)
400
600 mV
600 mV
Maximum data signal swing (8) (9)
Maximum data eye closure (8)
Maximum data eye closure (8)
0.275
UI
UI
0.4
20
Drift between Clock and Data between
Training Patterns
| tDRIFT
|
ps
CAPACITANCE
CIN
Input capacitance LVCMOS
f = 1 MHz
f = 1 MHz
10 pF
20 pF
Input capacitance LSIF (low speed
interface)
CIN
Input capacitance HSSI (high speed serial
interface)
CIN
f = 1 MHz
f = 1 MHz
20 pF
10 pF
COUT
Output capacitance
(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDA –VDD | must be less than specified limit.
(4) To prevent excess current, the supply voltage delta | VBIAS –VOFFSET | must be less than specified limit.
(5) Supply power dissipation based on 3 global resets in 200 µs.
(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
(8) Refer to 图6-11, Receiver Eye Mask (1e-12 BER).
(9) Defined in Recommended Operating Conditions.
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6.7 Switching Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output propagation, Clock to Q (C2Q), rising edge of
LS_CLK (differential clock signal) input to LS_RDATA
output. (1)
CL = 5 pF
11.1
11.3
ns
ns
tpd
CL = 10 pF
Slew rate, LS_RDATA
0.5
V/ns
20%–80%, CL <10pF
Output duty cycle distortion, LS_RDATA_A and
LS_RDATA_B
50-(C2Q rise –C2Q fall )
×130e6×100
40%
60%
(1) See 图6-2.
LS_CLK_P
1
0
1
0
1
0
1
0
1
0
LS_CLK_N
1 period
LS_WDATA_P
LS_WDATA_N
Stop (1)
Start (0)
tPD
LS_RDATA_A
BIST_A
Acknowledge
图6-2. Switching Characteristics
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MAX UNIT
6.8 Timing Requirements
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
LVCMOS
tr
tf
Rise time(1)
Fall time(1)
20% to 80% reference points
25
25
ns
ns
80% to 20% reference points
LOW SPEED INTERFACE (LSIF)
tr
Rise time(2)
20% to 80% reference points
450
450
ps
ps
ns
ns
tf
Fall time(2)
80% to 20% reference points
tW(H)
tW(L)
Pulse duration high(3)
Pulse duration low(3)
LS_CLK. 50% to 50% reference points
LS_CLK. 50% to 50% reference points
3.1
3.1
LS_WDATA valid before rising edge of LS_CLK
(differential)
tsu
th
Setup time(4)
Hold time(4)
1.5
1.5
ns
ns
LS_WDATA valid after rising edge of LS_CLK
(differential)
HIGH SPEED SERIAL INTERFACE (HSSI)
Rise time - data(5) (6)
50
50
115
135
115
135
ps
ps
ps
ps
ns
ns
From –A1 to A1 minimum eye height specification
From –A1 to A1 minimum eye height specification
From A1 to –A1 minimum eye height specification
From A1 to –A1 minimum eye height specification
DCLK. 50% to 50% reference points
tr
Rise time - clock(5) (6)
Fall time —data(5) (6)
50
tf
Fall time —clock(5) (6)
50
tW(H)
tW(L)
Pulse duration high(7)
Pulse duration low(7)
0.275
0.275
DCLK. 50% to 50% reference points
(1) See 图6-9 for rise time and fall time for LVCMOS.
(2) See 图6-4 for rise time and fall time for LSIF.
(3) See 图6-4 for pulse duration high and low time for LSIF.
(4) See 图6-4 for setup and hold time for LSIF.
(5) See 图6-11 for rise time and fall time for HSSI Eye Characteristics.
(6) See 图6-12 for rise time and fall time for HSSI.
(7) See 图6-12 for pulse duration high and low for HSSI.
1.255 V
V
LVDS(max)
V
V
CM
ID
V
LVDS(min)
0.575 V
A. See 方程式1 and 方程式2
图6-3. LSIF Waveform Requirements
1
VLVDS max = V
:
; + , × V
,
;
ID max
;
:
CM max
:
2
(1)
(2)
1
VLVDS min = V
:
; F , × V
,
;
ID max
;
:
CM min
:
2
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t
t
W(H)|
W(L)|
LS_CLK_P
50%
LS_CLK_N
t
t
H|
SU|
LS_WDATA_P
50%
LS_WDATA_N
t
WINDOW|
图6-4. LSIF Timing Requirements
V
, V
, V
LS_CLK_P LS_CLK_N LS_WDATA_P LS_WDATA_N
, V
100
90
80
70
60
50
40
30
20
10
0
tr
tf
图6-5. LSIF Rise, Fall Time Slew
+
(VIP + VIN
)
VCM
=
œ
2
LS_CLK_P,
LS_WDATA_P
VID
LS_CLK_N,
LS_WDATA_N
LVDS
Receiver
VCM
VIP
VIN
图6-6. LSIF Voltage Requirements
LS_CLK_P
LS_WDATA_P
Internal
Termination
ESD
ESD
(ZIN
)
LVDS
Receiver
LS_CLK_N
LS_WDATA_N
图6-7. LSIF Equivalent Input
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V
IH
V
T+
DV
T
V
Tœ
V
IL
DMD_DEN_ARTZ
Time
图6-8. LVCMOS Input Hysteresis
DMD_DEN_ARSTZ
100
90
80
V
OH
70
60
50
40
30
20
V
OL
10
0
tr
t
f
图6-9. LVCMOS Rise, Fall Time Slew Rate
t
f
V
HSSI(max)
V
V
ID
CM
V
HSSI(min)
t
r
A. See 方程式3 and 方程式4
图6-10. HSSI Waveform Requirements
1
VHSSI max = V
:
; + , × V
,
;
ID max
;
:
CM max
:
2
(3)
1
VHSSI min = V
:
; F , × V
,
;
ID max
;
:
CM min
:
2
(4)
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A2
A1
0V
-A1
-A2
X1
1-X1
X2 1-X2
0
1 UI
图6-11. HSSI Eye Characteristics
t
C|
t
t
W(H)|
W(L)|
DCLK_?P
50%
DCLK_?N
图6-12. HSSI CLK Characteristics
6.9 System Mounting Interface Loads
PARAMETER
Thermal interface area(1)
MIN
TYP
MAX
100
UNIT
N
Electrical interface area(1)
245
N
(1) The load should be uniformly applied within the area shown in 图6-13.
Electrical Interface Area
Thermal Interface Area
图6-13. System Mounting Interface Loads
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6.10 Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
VALUE
1920
1080
5.4
UNIT
Number of active columns(1) (2)
Number of active rows(1) (2)
Micromirror (pixel) pitch (1)
M
micromirrors
micromirrors
μm
N
P
Micromirror active array width(1)
Micromirror active array height(1)
Micromirror active border(3)
Micromirror pitch × number of active columns
Micromirror pitch × number of active rows
Pond of micromirror (POM)
10.368
5.832
20
mm
mm
micromirrors/side
(1) See 图6-14.
(2) The fast switching speed of the DMD micromirrors combined with advanced DLP image processing algorithms enables each
micromirror
to display four distinct pixels on the screen during every frame, resulting in a full 3840 × 2160 pixel image being displayed.
(3) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the
Pond Of Micromirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state
but still require an electrical bias to tilt toward the OFF state.
Off-State
Light Path
0
1
2
3
Active Micromirror Array
N x P
M x N Micromirrors
Nœ 4
Nœ 3
Nœ 2
Nœ 1
M x P
P
Incident
Illumination
Light Path
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
图6-14. Micromirror Array Physical Characteristics
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6.11 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Micromirror tilt angle
Landed state (1)
17
1.4
°
°
°
°
Micromirror tilt angle tolerance(2) (3) (4) (5)
Micromirror tilt direction (6) (7)
Micromirror tilt direction (6) (7)
Micromirror crossover time (8)
Micromirror switching time (9)
–1.4
Landed ON state
Landed OFF state
Typical performance
Typical performance
Gray 10 Screen (12)
Gray 10 Screen (12)
White Screen
270
180
1
3
μs
6
Bright pixel(s) in active area (11)
0
1
4
0
0
Bright pixel(s) in the POM (13)
Dark pixel(s) in the active area (14)
Adjacent pixel(s) (15)
Image
micromirrors
performance(10)
Any Screen
Unstable pixel(s) in active area (16)
Any Screen
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction. See 图6-15.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° degree reference
which is aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror.
(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(13) POM definition: Rectangular border of off-state mirrors surrounding the active area
(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image
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Border micromirrors omitted for clarity
Off State
Light Path
Details omitted for clarity.
Not to scale.
0
1
2
3
Tilted Axis of
Pixel Rotation
Off-State
Landed Edge
On-State
Landed Edge
Nœ 4
Nœ 3
Nœ 2
Nœ 1
Incident
Illumination
Light Path
图6-15. Micromirror Landed Orientation and Tilt
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6.12 Window Characteristics
DESCRIPTION(1)
MIN
TYP MAX
Corning Eagle XG
1.5119
Window material
Window refractive index
Window aperture (2)
Illumination overfill (3)
At wavelength 546.1 nm
See (2)
See (3)
.
.
Minimum within the wavelength range 420 nm to
680 nm. Applies to all angles 0° to 30° AOI(4)
97%
97%
Window transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420 nm to 680
nm. Applies to all angles 30° to 45° AOI(4)
(1) See 节7.5 for more information.
(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(3) The active area of the DLP471TP device is surrounded by an aperture on the inside of the DMD window surface that masks structures
of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The
illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux
level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light
on the outside of the active array may cause system performance degradation.
(4) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP471TP DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
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7 Detailed Description
7.1 Overview
The DMD is a 0.47-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system
(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing
algorithms enables each micromirror to display four distinct pixels on the screen during every frame, resulting in
a full 3840 × 2160 pixel image being displayed. The electrical interface is low voltage differential signaling
(LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram. The positive or
negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of
underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
The DLP 0.47” 4K UHD chipset is comprised of the DLP471TP DMD, DLPC6540 display controller, and the
DLPA3005 PMIC and the LED driver. To ensure reliable operation, the DLP471TP DMD must always be used
with the DLP display controller and the PMIC specified in the chipset.
7.2 Functional Block Diagram
Channel A Interface
Control
Control
Column Read/Write
Bit Lines
(0,0)
Word
Lines
Voltages
Voltage
Generators
Micromirror
Array
Row
(M-1,N-1)
Bit Lines
Control
Column Read/Write
Control
Channel B Interface
.
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7.3 Feature Description
7.3.1 Power Interface
The DMD requires 4 DC voltages: 1.8 V source, VOFFSET, VRESET, and VBIAS. In a typical LED-based system, 1.8
V is provided by a TPS54320 and the VOFFSET, VRESET, and VBIAS is managed by the DLPA3005 PMIC and LED
driver.
7.3.2 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be considered. Timing reference loads are not intended to be precise
representations of any particular system environment or depiction of the actual load presented by a production
test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a
system environment. The load capacitance value stated is only for characterization and measurement of AC
timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC6540 display controller. See the DLPC6540 display controller
data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
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7.6 Micromirror Array Temperature Calculation
TP2
Array
2X 7.37
TP4
TP5
2X 12.43
TP3
TP3 (TP2)
Window Edge
(4 surfaces)
TP4
TP5
TP1
5.45
12.43
TP1
图7-1. DMD Thermal Test Points
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Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in 图7-1) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
QARRAY = QELECTRICAL + QILLUMINATION
where
•
•
•
•
•
•
•
•
TARRAY = Computed array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = Thermal resistance of package specified in 节6.5 from array to ceramic TP1 (°C/Watt)
QARRAY = Total DMD power on the array (W) (electrical + absorbed)
QELECTRICAL = Nominal electrical power (W)
QINCIDENT = Incident illumination optical power (W)
QILLUMINATION = (DMD average thermal absorptivity × QINCIDENT) (W)
DMD average thermal absorptivity = 0.4
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 2.5 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD
system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.
The sample calculation for a typical projection application is as follows:
QINCIDENT = 9.4 W (measured)
TCERAMIC = 55.0°C (measured)
QELECTRICAL = 2.5 W
QARRAY = 2.5 W + (0.40 × 9.4 W) = 6.26 W
TARRAY = 55.0°C + (6.26 W × 1.0°C/W) = 61.3°C
7.7 Micromirror Power Density Calculation
The calculation of the optical power density of the illumination on the DMD in the different wavelength bands
uses the total measured optical power on the DMD, percent illumination overfill, area of the active array, and
ratio of the spectrum in the wavelength band of interest to the total spectral optical power.
• ILLUV = [OPUV-RATIO × QINCIDENT] × 1000 ÷ AILL (mW/cm2)
• ILLVIS = [OPVIS-RATIO × QINCIDENT] ÷ AILL (W/cm2)
• ILLIR = [OPIR-RATIO × QINCIDENT] × 1000 ÷ AILL (mW/cm2)
• ILLBLU = [OPBLU-RATIO × QINCIDENT] ÷ AILL (W/cm2)
• ILLBLU1 = [OPBLU1-RATIO × QINCIDENT] ÷ AILL (W/cm2)
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• AILL = AARRAY ÷ (1 - OVILL) (cm2)
where:
• ILLUV = UV illumination power density on the DMD (mW/cm2)
• ILLVIS = VIS illumination power density on the DMD (W/cm2)
• ILLIR = IR illumination power density on the DMD (mW/cm2)
• ILLBLU = BLU illumination power density on the DMD (W/cm2)
• ILLBLU1 = BLU1 illumination power density on the DMD (W/cm2)
• AILL = illumination area on the DMD (cm2)
• QINCIDENT = total incident optical power on DMD (W) (measured)
• AARRAY = area of the array (cm 2) (data sheet)
• OVILL = percent of total illumination on the DMD outside the array (%) (optical model)
• OPUV-RATIO = ratio of the optical power for wavelengths <410 nm to the total optical power in the illumination
spectrum (spectral measurement)
• OPVIS-RATIO = ratio of the optical power for wavelengths ≥410 and ≤800 nm to the total optical power in the
illumination spectrum (spectral measurement)
• OPIR-RATIO = ratio of the optical power for wavelengths >800 nm to the total optical power in the illumination
spectrum (spectral measurement)
• OPBLU-RATIO = ratio of the optical power for wavelengths ≥410 and ≤475 nm to the total optical power in the
illumination spectrum (spectral measurement)
• OPBLU1-RATIO = ratio of the optical power for wavelengths ≥410 and ≤445 nm to the total optical power in the
illumination spectrum (spectral measurement)
The illumination area varies and depends on the illumination overfill. The total illumination area on the DMD is
the array area and overfill area around the array. The optical model is used to determine the percent of the total
illumination on the DMD that is outside the array (OVILL) and the percent of the total illumination that is on the
active array. From these values the illumination area (AILL) is calculated. The illumination is assumed to be
uniform across the entire array.
From the measured illumination spectrum, the ratio of the optical power in the wavelength bands of interest to
the total optical power is calculated.
Sample calculation:
QINCIDENT = 9.40 W (measured)
AARRAY = (1.0368 × 0.5832) = 0.6047 cm2 (data sheet)
OVILL = 16.3% (optical model)
OPUV-RATIO = 0.00021 (spectral measurement)
OPVIS-RATIO = 0.99977 (spectral measurement)
OPIR-RATIO = 0.00002 (spectral measurement)
OPBLU-RATIO = 0.28100 (spectral measurement)
OPBLU1-RATIO = 0.03200 (spectral measurement)
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AILL = 0.6047 ÷ (1 - 0.163) = 0.7224 cm2
ILLUV = [0.00021 × 9.40W] × 1000 ÷ 0.7224 cm2 = 2.732 mW/cm2
ILLVIS = [0.99977 × 9.40W] ÷ 0.7224 cm2 = 13.01 W/cm2
ILLIR = [0.00002 × 9.40W] × 1000 ÷ 0.7224 cm2 = 0.260 mW/cm2
ILLBLU = [0.28100 × 9.40W] ÷ 0.7224 cm2 = 3.66 W/cm2
ILLBLU1 = [0.03200 × 9.40W] ÷ 0.7224 cm2 = 0.42 W/cm2
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7.8 Micromirror Landed-On/Landed-Off Duty Cycle
7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the percentage of time that an
individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the
OFF state.
For example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the time
(and in the OFF state 0% of the time); whereas 0/100 would indicate that the pixel is in the OFF state 100% of
the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.8.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD useful life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.8.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD useful life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD useful life. This is
quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same useful life.
• All points above this curve represent lower useful life (and the further away from the curve, the lower the
useful life).
• All points below this curve represent higher useful life (and the further away from the curve, the higher the
useful life).
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a given long-term average landed duty cycle.
7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
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表7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
Use 方程式5 to calculate the landed duty cycle of a given pixel during a given time period
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (5)
×
Blue_Scale_Value)
where
• Red_Cycle_%, represents the percentage of the frame time that red is displayed to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired
white point
For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue
color intensities would be as shown in 表7-2 and 表7-3.
表7-2. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
RED
GREEN
BLUE
30%
50%
20%
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表7-3. Example Landed Duty Cycle for Full-Color
SCALE VALUE
GREEN
0%
LANDED DUTY
CYCLE
RED
0%
BLUE
0%
0/100
50/50
20/80
30/70
6/94
100%
0%
0%
0%
100%
0%
0%
0%
100%
0%
12%
0%
0%
35%
0%
7/93
0%
0%
60%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
0%
35%
35%
60%
60%
100%
12%
100%
0%
100%
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLPC6540 controller, the gamma function affects the landed duty cycle.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC6540 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical
gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.
100
90
80
Gamma = 2.2
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90 100
D002
图7-2. Example of Gamma = 2.2
From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale
value will be 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact
displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
Consideration must also be given to any image processing which occurs before the DLPC6540 controller.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC6540
controller. The high tilt pixel in the bottom-illuminated DMD increases brightness performance and enables a
smaller system footprint for thickness constrained applications. Typical applications using the DLP471TP include
mobile smart TV and digital signage.
DMD power-up and power-down sequencing is strictly controlled by the DLPA3005. Refer to 节 9 for power-up
and power-down specifications. To ensure reliable operation, the DLP471TP DMD must always be used with
DLPC6540 controller and a DLPA3005 PMIC/LED driver.
8.2 Typical Application
The DLP471TP DMD combined with DLPC6540 digital controller and a power management device provides full
4K UHD resolution for bright, colorful display applications. See Typical 4K UHD LED Application Diagram , which
shows the system components needed along with the LED configuration of the DLP 0.47”4K UHD chipset. The
components include the DLP471TP DMD, DLPC6540 display controller and the DLPA3005 PMIC and LED
driver.
Fan or
programmable DC supply
DC
Supply
SYSPWR (14.5 V to 20 V)
DC
Reg
L5
L4
L3
VSPI
1.8 V
1.8 V @ 3 A for
DMD and DLPC6540
GPIO (PROJ_ON)
Flash (2)
1.8
Reg
ADDR
DATA
1.1 V @ 3 A
(23) (18)
SYSPWR
1.1
Reg
L2
VLED
PROJ_ON
L1
Front End
Device
I2C BUSY
DLPA3005
I2C
LED_SEL (2)
POSENSE
Vx1
Vx1:
3840 × 2160
@ 60Hz
EEPROM
I2C
RESETZ
INITZ
3.3 V @ 2 A
2.5 V
LDO 1
LDO 2
DLPC6540
Master
3D L/R
SPI (2)
PWRGOOD
(3)
VBIAS, VOFFSET, VRESET
RLIM current sense
SPI BUS (Ctrl) (4)
1.15 V
1.21 V
1.8 V
3.3 V
2-Port HSSI
USB Mux
GPIO
DLPC471TP
.47 4K UHD DMD
LS Interface
1.8 V
USB 2.0
TI DLP chipset
Actuator
Driver
4-Position
Actuator
USB Camera
Third party component
图8-1. Typical 4K UHD LED Application Diagram
8.2.1 Design Requirements
Other core components of the display system include an illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The type of
illumination used and desired brightness will have a major effect on the overall system design and size.
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The display system uses the DLP471TP as the core imaging device and contains a 0.47-inch array of
micromirrors. The DLPC6540 controller is the digital interface between the DMD and the rest of the system,
taking digital input from front end receiver and driving the DMD over a high-speed interface. The DLPA3005
PMIC serves as a voltage regulator for the DMD, controller, and LED illumination functionality.
8.2.2 Detailed Design Procedure
For a complete DLP system, an optical module or light engine is required that contains the DLP471TP DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DMD must always be used with DLPC6540 display controller and the
DLPA3005 PMIC and LED driver . Refer to PCB Design Requirements for TI DLP Pico TRP Digital Micromirror
Devices for the DMD board design and manufacturing handling of the DMD sub assemblies.
8.2.3 Application Curves
The typical LED-current-to-luminance relationship when LED illumination is utilized is shown in 图8-2.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
LED CURRENT (A)
8
9
10 11 12
D001
图8-2. Luminance vs. Current
8.3 Temperature Sensor Diode
The software application provides functions to configure the TMP411 to read the DLP471TP DMD temperature
sensor diode. Customers can use this data to incorporate additional functionality in the overall system design,
such as adjusting illumination, fan speeds, and so on. All communication between the TMP411 and the
DLPC6540 controller is completed using the I2C interface. The TMP411 connects to the DMD through the pins
outlined in 节5.
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VDD
• VDDA
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in 图9-1.
VBIAS, VDD, VDDA, VOFFSET, and VRESET power supplies must be coordinated during power-up and
power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.
表9-1. Power Supply Sequence Requirements
SYMBOL
tDELAY
PARAMETER
Delay requirement
DESCRIPTION
MIN
TYP
MAX UNIT
from VOFFSET power up to VBIAS power up
at beginning of power-up sequence delay(1)
at end of power-up sequence delay(1)
2
ms
VOFFSET
VBIAS
Supply voltage level
Supply voltage level
6
6
V
V
(1) See 图9-1, Power-Up Sequence Delay Requirement.
9.1 DMD Power Supply Power-Up Procedure
• During power-up, VDD and VDDA must always start and settle before VOFFSET plus Delay1 specified in 表9-2,
VBIAS, and VRESET voltages are applied to the DMD.
• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in 节6.4.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1.
• During power-up, LVCMOS input pins must not be driven high until after VDD have settled at operating
voltages listed in 节6.4.
9.2 DMD Power Supply Power-Down Procedure
• During power-down, VDD and VDDA must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to
within the specified limit of ground. See 表9-2.
• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in 节6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1.
• During power-down, LVCMOS input pins must be less than specified in 节6.4.
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Note A
...
...
...
VDD and VDDA
VSS
VSS
Note I
tDELAY3
Note B
ûV < Specification
VOFFSET
Note D
tDELAY1
VBIAS
VSS
VSS
Note C
ûV < Specification
VRESET
Note E
...
...
Note G
tDELAY2
Note H
DMD_EN_ARSTZ
Note F
VSS
Time
A. See 节5 for the Pin Functions Table.
B. To prevent excess current, the supply voltage difference |VOFFSET –VBIAS| must be less than the specified limit in 节6.4.
C. To prevent excess current, the supply difference |VBIAS –VRESET| must be less than the specified limit in 节6.4.
D. VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in 表9-2.
E. DLP controller software initiates the global VBIAS command.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates
DMD_EN_ARSTZ and disables VBIAS, VRESET , and VOFFSET
.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware
DMD_EN_ARSTZ will go low.
H. VDD must remain high until after VOFFSET, VBIAS, VRESET go low, per Delay2 specification in 表9-2.
I.
To prevent excess current, the supply voltage delta |VDDA –VDD| must be less than specified limit in 节6.4.
图9-1. DMD Power Supply Requirements
表9-2. DMD Power-Supply Requirements
PARAMETER
Delay1(1)
DESCRIPTION
MIN
NOM
MAX
UNIT
Delay from VOFFSET settled at recommended operating voltage to
VBIAS and VRESET power up
1
2
ms
Delay VDD must be held high from VOFFSET, VBIAS and VRESET
powering down.
Delay2(1)
50
us
(1) See 图9-1.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
34
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10 Layout
10.1 Layout Guidelines
The DLP471TP DMD is part of a chipset that is controlled by DLPC6540 display controller in conjunction with the
DLPA3005 PMIC and LED driver. These guidelines are targeted at designing a PCB board with the DLP471TP
DMD. The DMD board is a high-speed multi-layer PCB, with primarily high-speed digital logic including double
data rate 3.2 Gbps and 250 Mbps differential data buses run to the DMD. TI recommends that full or mini power
planes are used for VOFFSET, VRESET, and VBIAS. Solid planes are required for ground (VSS). The target
impedance for the PCB is 50 Ω ±10% with exceptions listed in 表 10-1. TI recommends a 10 layer stack-up as
described in 表10-2. TI recommends manufacturing the PCB with a high quality FR-4 material.
10.2 Impedance Requirements
TI recommends a target impedance for the PCB of 50 Ω ±10% for all signals. The exceptions are listed in 表
10-1.
表10-1. Special Impedance Requirements
Signal Type
Signal Name
Impedance (ohms)
DMD_HSSI0_N_(0…7),
DMD_HSSI0_P_(0…7),
DMD_HSSI1_N_(0…7),
DMD_HSSI1_P_(0…7),
DMD_HSSI0_CLK_N,
DMD_HSSI0_CLK_P,
DMD_HSSI1_CLK_N,
DMD_HSSI1_CLK_P
100-Ω differential (50-Ω single
DMD High Speed Data Signals
ended)
DMD_LS0_WDATA_N,
DMD_LS0_WDATA_P,
DMD_LS0_CLK_N,
DMD_LS0_CLK_P
DMD Low Speed Interface
Signals
100-Ω differential (50-Ω single
ended)
10.3 Layers
The layer stack-up and copper weight for each layer is shown in 表10-2.
表10-2. Layer Stack-Up
LAYER
NO.
LAYER NAME
COPPER WT. (oz.)
COMMENTS
DMD and escapes. Two data input connectors. Top components including
power generation and two-data input connectors. Low frequency signals
routing. Should have copper fill (GND) plated up to 1 oz.
Side A –DMD, primary
components, power mini-
planes
0.5 oz. (before
plating)
1
2
3
Ground
0.5
0.5
Solid ground plane (net GND) reference for signal layers #1, 3
High-speed signal layer. High-speed differential data buses from input
connector to DMD.
Signal (high frequency)
4
5
6
7
Ground
Power
Power
Ground
0.5
0.5
0.5
0.5
Solid ground plane (net GND) reference for signal layers #3, #5
Primary split power planes for 1.8 V, 10 V, –14 V, 18 V
Primary split power planes for 1.8 V, 10 V, –14 V, 18 V
Solid ground plane (net GND) reference for signal layer #8
High-speed signal layer. High-speed differential data buses from input
connector to DMD
8
9
Signal (high frequency)
Ground
0.5
0.5
Solid ground plane (net GND) reference for signal layers #8, 10
Side B –secondary
components, power mini-
planes
0.5 oz. (before
plating)
Discrete components if necessary. Low-frequency signals routing. Should
have copper fill plated up to 1 oz.
10
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English Data Sheet: DLPS173
DLP471TP
ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
www.ti.com.cn
10.4 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.015” (Trace-Width/Spacing)
design rule. Actual trace widths and clearances should be determined and calculated based on an analysis of
impedance and stack-up requirements.
The width of all voltage signals shall be maximized as space permits. In particular, the following width and
spacing requirements shall be observed for the specific signals listed in 表10-3.
表10-3. Special Trace Widths, Spacing Requirements
MINIMUM TRACE
WIDTH (MIL)
SIGNAL NAME
MINIMUM TRACE SPACING (MIL)
LAYOUT REQUIREMENT
GND
MAXIMIZE
5
Maximize trace width to connecting pin as a minimum.
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary with multiple
vias.
P1P8V
100
15
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
VOFFSET
VRESET
VBIAS
40
40
40
15
15
15
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
10.5 Power
TI strongly discourages signal routing on power planes or on planes adjacent to power planes. If signals must be
routed on layers adjacent to power planes, they must not cross splits in power planes to prevent EMI and
preserve signal integrity.
Have all internal digital ground (GND) planes connected together in as many places as possible. If possible, all
internal ground planes should be connected together with a minimum distance between connections of 0.5”.
Extra vias may not be required if there are sufficient ground vias due to normal ground connections of devices.
The power and ground pins of each component should be connected to the power and ground planes with at
least one via for each pin. Trace lengths for component power and ground pins should be minimized (ideally,
less than 0.100”).
Ground plane slots are strongly discouraged.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
36
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10.6 Trace Length Matching Recommendations
Recommended signal trace length matching requirements can be found in 表 10-4 and 表 10-5. When length
matching traces, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a
minimum and the turn angles no sharper than 45 degrees as opposed to running long traces over large areas of
the PCB.
Signals in 表 10-4 should be routed for data rate operation at up to 3.2 Gbps. Layer changes for these signals
should be minimized, the number of vias should be minimized. Avoid sharp turns and layer switching while
keeping lengths to a minimum. When layer changes are necessary, GND vias should be placed around the
signal vias to provide a signal return path. The distance from one pair of differential signals to another shall be at
least 2 times the distance within the pair.
表10-4. HSSI High Speed DMD Data Signals
SIGNAL NAME
DMD_HSSI0_N(0...7),
REFERENCE SIGNAL
Routing Spec
Unit
DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P
+/- 0.25
inch
DMD_HSSI0_P(0...7)
DMD_HSSI1_N(0...7),
DMD_HSSI1_P(0...7)
DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P
+/- 0.25
inch
DMD_HSSI0_CLK_P
Intra-pair P
DMD_HSSI1_CLK_P
Intra-pair N
+/- 0.05
+/- 0.01
inch
inch
表10-5. Other Timing Critical Signals
SIGNAL NAME
Constraints
Routing Layers
LS_CLK_P, LS_CLK_N
LS_WDATA_P,
LS_WDATA_N
Intra-pair (P to N)
Matched to 0.01 inches
Signal-to-signal
Layers 3, 8
LS_RDATA_A
Matched to +/- 0.25 inches
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: DLPS173
DLP471TP
ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
www.ti.com.cn
11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
DLP471TP FQQ
Package
Device Descriptor
图11-1. Part Number Description
11.2.2 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in 图 11-2 and includes the legible character string GHJJJJK DLP471TPFQQ.
GHJJJJK is the lot trace code and DLP471TPFQQ is the device marking.
Example: GHJJJJK DLP471TPFQQ
Two-Dimensional Matrix Code
(Part Number and Lot Trace Code)
DMD Part Number
Lot Trace Code
图11-2. DMD Marking Locations
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
38
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11.3 Documentation Support
11.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the DMD.
• DLPC6540 Display Controller Data Sheet
• DLPA3005 PMIC/LED Driver Data Sheet
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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English Data Sheet: DLPS173
DLP471TP
ZHCSNH4B –AUGUST 2020 –REVISED JULY 2023
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS173
40
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLP471TPFQQ
ACTIVE
CLGA
FQQ
270
54
RoHS & Green
NI/AU
N / A for Pkg Type
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DLP471TPFQQ
FQQ
CLGA
270
54
6 x 9
150
315 135.9 12190 31.5
31.5
16.2
Pack Materials-Page 1
DWG NO.
SH
5
8
3
6
1
7
4
1
2516402
REVISIONS
COPYRIGHT 2018 TEXAS INSTRUMENTS
UN-PUBLISHED, ALL RIGHTS RESERVED.
C
NOTES UNLESS OTHERWISE SPECIFIED:
REV
A
DESCRIPTION
ECO 2178176: INITIAL RELEASE
ECO: 2187413: CHANGE SHORT APERTURE SLOTS TO
ALL-AROUND
DATE
BY
BMH
12/11/2018
1
DIE PARALLELISM TOLERANCES APPLY TO DMD ACTIVE ARRAY ONLY.
4/29/2020
B
PPC
2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.
4
(1.3)
24.454B0.1
3
4
BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.
+
-
0.1
0.2
(OFF-STATE
DIRECTION)
0.104
NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,
AS SHOWN IN SECTION A-A.
D
C
B
A
4X (R0.2)
D
C
B
A
4
5
ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW D
(SHEET 3). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.
6
7
8
ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.
SEE DETAIL B FOR "V-NOTCH" DIMENSIONS.
WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED
FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,
TO SUPPORT MECHANICAL LOADS.
FRONT SIDE
INDEX MARK
7
B
4
P2.5
4
2X R0.4B0.1
4
(1.25)
+
-
0.3
0.1
2X 3B0.075
16.9
C
1.5
4
A
A
45 B1
4
R1B0.1
+
-
0.2
0.1
4
8.45
(3)
+
-
0.2
0.1
6.95
4
45 B1
2X ENCAPSULANT
(ILLUMINATION
DIRECTION)
5
6
DETAIL B
+
-
0.3
0.1
25.65
V-NOTCH
SCALE 30 : 1
D
1.403B0.077
1.1B0.05
(2.183)
3 SURFACES INDICATED
IN VIEW B (SHEET 2)
1 8
0.042A
A
4
H
8
0.02D
ACTIVE ARRAY
(3)
0.78B0.063
1.925B0.1
H
H
0.35 MIN TYP
0 MIN TYP
(SHEET 3)
(SHEET 3)
DATE
DRAWN
UNLESS OTHERWISE SPECIFIED
TEXAS
12/11/2018
B. HASKETT
ENGINEER
DIMENSIONS ARE IN MILLIMETERS
TOLERANCES:
INSTRUMENTS
Dallas Texas
SECTION A-A
12/11/2018 TITLE
12/12/2018
B. HASKETT
QA/CE
ANGLES B1`
(ROTATED 90)
ICD, MECHANICAL, DMD,
.47 4K HSSI SERIES 317
(FQQ PACKAGE)
2 PLACE DECIMALS B0.25
1 PLACE DECIMALS B0.50
K. DICKERSON
CM
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME
Y14.5M-1994
REMOVE ALL BURRS AND SHARP EDGES
PARENTHETICAL INFORMATION FOR REFERENCE ONLY
12/19/2018
B. HASKETT
REV
THIRD ANGLE
PROJECTION
DWG NO
SDIZE
0314DA
USED ON
12/18/2018
J. MCKINLEY
APPROVED
2516402
B
NEXT ASSY
12/18/2018
SHEET
OF
SCALE
APPLICATION
HERMOSILLO
15:1
1
5
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
5
8
3
6
1
7
4
2
2516402
D
C
B
A
D
C
B
A
4X (1.5)
2X 1.604
2X 22.65
A3
4X (5)
A2
2X 3.45
P2.5
C
1.5
2X 3.45
B
8
E1
A1
VIEW C
DATUMS A AND E
(FROM SHEET 1)
REV
DWG NO
SIZE
DATE
DRAWN
TEXAS
2516402
12/11/2018 D
B. HASKETT
B
5
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
2
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
5
8
3
6
1
7
4
3
2516402
D
C
B
A
D
C
B
A
2X 2.374
2X 21.11
C
1.5
P2.5
B
6
2X 0 MIN
VIEW D
VIEW E
MAXIMUM ENCAPSULANT HEIGHT
ENCAPSULANT MAXIMUM X/Y DIMENSIONS
5
(FROM SHEET 1)
6
REV
DWG NO
SIZE
DATE
DRAWN
TEXAS
2516402
12/11/2018 D
B. HASKETT
B
5
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
3
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
5
8
3
6
1
7
4
4
2516402
(0.075) TYP.
D
C
B
A
D
C
B
A
(0.068) TYP.
(42) TYP.
S
2
(OFF-STATE
DIRECTION)
(10.368)
ACTIVE ARRAY
4X (0.108)
7.29B0.075
3
DETAIL F
APERTURE TOP EDGE
(GLASS OMITTED FOR CLARITY)
SCALE 60 : 1
0.754B0.0635
2.633B0.05
F
S
2
2.91B0.075
7.155B0.0635
(11.085)
WINDOW
(5.832)
ACTIVE ARRAY
(7.909)
C
APERTURE
1.5
P2.5
(0.15) TYP.
8.452B0.05
B
(42) TYP.
(42) TYP.
S
S
G
(0.068) TYP.
DETAIL G
APERTURE BOTTOM EDGE
(ILLUMINATION
DIRECTION)
(GLASS OMITTED FOR CLARITY)
SCALE 60 : 1
1.127
0.0635
11.574B0.0635
(12.701) APERTURE
14.63B0.05
3.34B0.05
(17.97) WINDOW
VIEW E
WINDOW AND ACTIVE ARRAY
(FROM SHEET 1)
REV
DWG NO
SIZE
DATE
DRAWN
TEXAS
2516402
12/11/2018 D
B. HASKETT
B
5
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
4
INV11-2006a
5
3
6
1
2
7
8
4
DWG NO.
SH
5
8
3
6
1
7
4
5
2516402
D
C
B
A
D
C
B
A
0.929
24 X 1 = 24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
T
R
P
N
M
L
7.5
K
J
1.5
C
15 X 1
= 15
H
G
F
P2.5
32X CIRCULAR TEST PADS
(P0.75)
B
BACK SIDE
INDEX MARK
E
D
C
B
A
SYMBOLIZATION PAD
(7 X 3)
238X SQUARE LGA PADS
0.750.05 X 0.750.05
0.2ABC
0.1A
VIEW H-H
L
BACK SIDE METALIZATION
(FROM SHEET 1)
REV
DWG NO
SIZE
DATE
DRAWN
TEXAS
2516402
12/11/2018 D
B. HASKETT
B
5
INSTRUMENTS
Dallas Texas
SCALE
SHEET
OF
5
INV11-2006a
5
3
6
1
2
7
8
4
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
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