DLP500YX_技术文档

DLP500YX

ZHCSKV7A –NOVEMBER 2020 –REVISED JULY 2022

DLP500YX 0.50 2048×1200 DMD

1 特性

2 应用

• 高分辨率2048 × 1200 阵列

• 工业

– 用于机器视觉的3D 扫描仪

– 大于2.4M 微镜

– 3D 无接触计量和质量控制

– 3D 打印

– 0.50 英寸微镜阵列对角线

– 5.4 微米微镜间距

• 医疗

– ±17.5° 微镜倾斜角（相对于平面）

– 设计用于底部照明

– 集成微镜驱动器电路

– 眼科

– 针对四肢和皮肤测量的3D 扫描仪

– 高光谱扫描和成像

• 设计用于宽带可见光(420nm–700nm)

• 显示器

– 窗透射率为97%（单通，两个窗面）

– 微镜反射率为88%

– 阵列衍射效率84% (@f/2.4)

– 阵列填充系数为93%

– 3D 成像显微镜

– 智能和自适应照明

3 说明

• 四条16 位低压差分信令(LVDS)、双倍数据速率

(DDR) 输入数据总线

• 由双DLPC900 数字控制器驱动

DLP500YX 数字微镜器件 (DMD) 是一种空间光调制器

(SLM)，调制入射光的振幅、方向和/或相位。此 DMD

与四条 2xLVDS 输入数据总线相结合，能够以超快的

图形更新速率显示高分辨率图形。DLP500YX 提供的

高分辨率和快速图形速率使其非常适合支持各种工业、

医疗和高级成像应用。DLP500YX 与双 DLPC900 数

字控制器配合使用时可实现可靠功能和操作。此专用芯

片组以满足各种终端设备解决方案要求所需的高图形速

率提供灵活且易于编程的图形流。

– 高达16.1kHz 1 位图形/秒

– 在预存储图形模式下相当于39.6 千兆位/秒像素

数据速率

– 高达2016Hz 8 位灰度图形速率（预存储图形模

式，具有照明调制）

– 高达1008Hz 16 位灰度图形速率（预存储图形

模式，具有照明调制）

– 高达247Hz 8 位图形速率（外部视频图形输

入）

表3-1. 器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DLP500YX

FXK (257)

32.2mm × 22.3mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS193

DLP500YX

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ZHCSKV7A –NOVEMBER 2020 –REVISED JULY 2022

Table of Contents

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications................................................................ 11

6.1 Absolute Maximum Ratings...................................... 11

6.2 Storage Conditions................................................... 12

6.3 ESD Ratings............................................................. 12

6.4 Recommended Operating Conditions.......................12

6.5 Thermal Information..................................................14

6.6 Electrical Characteristics...........................................15

6.7 Capacitance at Recommended Operating

Conditions................................................................... 15

6.8 Timing Requirements................................................16

6.9 Typical Characteristics..............................................19

6.10 System Mounting Interface Loads.......................... 20

6.11 Micromirror Array Physical Characteristics............. 20

6.12 Micromirror Array Optical Characteristics............... 22

6.13 Window Characteristics.......................................... 24

6.14 Chipset Component Usage Specification............... 24

7 Detailed Description......................................................25

7.1 Overview...................................................................25

7.2 Functional Block Diagram.........................................25

7.3 Feature Description...................................................26

7.4 Device Functional Modes..........................................26

Considerations............................................................ 26

7.6 Micromirror Array Temperature Calculation.............. 27

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 29

8 Application and Implementation..................................32

8.1 Application Information............................................. 32

8.2 Typical Application.................................................... 32

8.3 DMD Die Temperature Sensing................................ 34

9 Power Supply Recommendations................................35

9.1 DMD Power Supply Power-Up Procedure................35

9.2 DMD Power Supply Power-Down Procedure........... 35

9.3 Restrictions on Hot Plugging and Hot Swapping...... 37

10 Layout...........................................................................37

10.1 Layout Guidelines................................................... 37

10.2 Layout Example...................................................... 40

11 Device and Documentation Support..........................42

11.1 第三方产品免责声明................................................42

11.2 Device Support........................................................42

11.3 Documentation Support.......................................... 43

11.4 接收文档更新通知................................................... 43

11.5 支持资源..................................................................43

11.6 Trademarks............................................................. 43

11.7 Electrostatic Discharge Caution..............................43

11.8 术语表..................................................................... 43

12 Mechanical, Packaging, and Orderable

Information.................................................................... 44

4 Revision History

Changes from Revision * (November 2020) to Revision A (July 2022)

Page

• This document is updated per the latest Texas Instruments and industry data sheet standards......................11

• Updated Timing Requirements ........................................................................................................................ 16

2

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5 Pin Configuration and Functions

图5-1. FXK Package 257-Pin CLGA Bottom View

CAUTION

To ensure reliable, long-term operation of the DLP500YX DMD, it is critical to properly manage the layout and operation of

the signals identified in Pin Functions . For specific details and guidelines, refer to 节10.1 section before designing the

board.

表5-1. Pin Functions

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

D_AN(0)

NO.

C6

C3

E1

C4

D1

B8

F4

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

E3

C11

F3

Input

LVDS

DDR

Differential

Data negative

805

K4

H3

J3

C13

A5

A3

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

D_AP(0)

NO.

C7

C2

E2

B4

C1

B7

E4

D3

C12

F2

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

Input

LVDS

DDR

Differential

Data positive

805

J4

G3

J2

C14

A6

A4

N4

Z11

W4

W10

L1

V8

W6

M1

R4

W1

U4

V2

Z5

Input

LVDS

DDR

Differential

Data negative

805

N3

Z2

L4

4

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

D_BP(0)

NO.

M4

Z12

Z4

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

D_BP(8)

D_BP(9)

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

D_BP(15)

D_CN(0)

D_CN(1)

D_CN(2)

D_CN(3)

D_CN(4)

D_CN(5)

D_CN(6)

D_CN(7)

D_CN(8)

D_CN(9)

D_CN(10)

D_CN(11)

D_CN(12)

D_CN(13)

D_CN(14)

D_CN(15)

Z10

L2

V9

W7

N1

Input

LVDS

DDR

Differential

Data positive

805

P4

V1

T4

V3

Z6

N2

Z3

L3

H27

A20

H28

K28

K30

C23

G27

J30

B24

A21

A27

C29

A26

C25

A29

C30

Input

LVDS

DDR

Differential

Data negative

805

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

D_CP(0)

NO.

J27

A19

H29

K27

K29

C22

F27

H30

B25

B21

B27

C28

A25

C24

A28

B30

V25

V28

T30

V27

U30

W23

R27

T28

V20

R28

L27

N28

M28

V18

Z26

Z28

D_CP(1)

D_CP(2)

D_CP(3)

D_CP(4)

D_CP(5)

D_CP(6)

D_CP(7)

D_CP(8)

D_CP(9)

D_CP(10)

D_CP(11)

D_CP(12)

D_CP(13)

D_CP(14)

D_CP(15)

D_DN(0)

D_DN(1)

D_DN(2)

D_DN(3)

D_DN(4)

D_DN(5)

D_DN(6)

D_DN(7)

D_DN(8)

D_DN(9)

D_DN(10)

D_DN(11)

D_DN(12)

D_DN(13)

D_DN(14)

D_DN(15)

Input

LVDS

DDR

Differential

Data positive

805

Input

LVDS

DDR

Differential

Data negative

805

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

D_DP(0)

NO.

V24

V29

T29

W27

V30

W24

T27

U28

V19

R29

M27

P28

M29

V17

Z25

Z27

G1

D_DP(1)

D_DP(2)

D_DP(3)

D_DP(4)

D_DP(5)

D_DP(6)

D_DP(7)

Input

LVDS

DDR

Differential

Data positive

805

D_DP(8)

D_DP(9)

D_DP(10)

D_DP(11)

D_DP(12)

D_DP(13)

D_DP(14)

D_DP(15)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

SCTRL_CN

SCTRL_CP

SCTRL_DN

SCTRL_DP

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

DCLK_CN

DCLK_CP

DCLK_DN

DCLK_DP

Input

LVDS

DDR

Differential

Serial control negative⁽³⁾

Serial control positive⁽³⁾

Serial control negative⁽³⁾

Serial control positive⁽³⁾

Serial control negative⁽³⁾

Serial control positive⁽³⁾

Serial control negative⁽³⁾

Serial control positive⁽³⁾

Clock negative⁽³⁾

805

F1

V5

V4

C26

C27

P30

R30

H2

H1

Clock positive⁽³⁾

V6

Clock negative⁽³⁾

V7

Clock positive⁽³⁾

D27

E27

N29

N30

Clock negative⁽³⁾

Clock positive⁽³⁾

Clock negative⁽³⁾

Clock positive⁽³⁾

Serial communications port clock.

Active only when SCPENZ is

logic low⁽³⁾

SCPCLK

SCPDI

A10

A12

Input

LVCMOS

Pull down

Serial communications port data

input. Synchronous to SCPCLK

rising edge⁽³⁾

SDR

Pull down

Serial communications port

enable active low⁽³⁾

SCPENZ

SCPDO

C10

A11

Input

LVCMOS

Serial communications port

output

Output

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

NO.

RESET_ADDR(

0)

Z13

RESET_ADDR(

1)

W13

V10

W14

W9

Input

LVCMOS

Pull down

Reset driver address select⁽³⁾

Reset driver mode select⁽³⁾

RESET_ADDR(

2)

RESET_ADDR(

3)

RESET_MOD

E(0)

Input

LVCMOS

Pull down

RESET_SEL(0)

RESET_SEL(1)

V14

Z8

Reset driver level select⁽³⁾

Reset driver level select.⁽³⁾

Rising edge latches in

RESET_ADDR, RESET_MODE,

& RESET_SEL.⁽³⁾

RESET_STRO

BE

Z9

PWRDNZ

A8

Input

LVCMOS

Pull down

Pull up

Active low device reset.⁽³⁾

Active low output enable for

internal reset driver circuits.⁽³⁾

RESET_OEZ

W15

Active low output interrupt to DLP

controller

RESET_IRQZ

EN_OFFSET

PG_OFFSET

V16

C9

Output

Input

LVCMOS

Active high enable for external

V_OFFSETregulator

Active low fault from external

V_OFFSETregulator⁽³⁾

A9

Pull up

Temperature sensor diode

cathode

TEMP_N

TEMP_P

B18

B17

Input

Analog

Temperature sensor diode anode

D12,

D13,

D14,

RESERVED

**MUST

VERIFY WITH

SRC DATA

SHEET

D15,

D16,

D17,

D18,

Do not connect on DLP system

board. No connect. No electrical

connections from CMOS bond

pad to package pin.

NC

Analog

Pull Down

D19,

U12,

U13,

U14, U15

U16,

U17,

U18, U19

No connect. No electrical

connection from CMOS bond pad

to package pin

No Connect

NC

RESERVED_B

A

W11

B11

Z20

C18

A18

C8

RESERVED_B

B

Do not connect on DLP system

board.

Output

LVCMOS

RESERVED_B

C

RESERVED_B

D

RESERVED_P

FE

Do not connect on DLP system

board.

Input

Pull down

RESERVED_T

M

8

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

NO.

RESERVED_T

P0

Z19

RESERVED_T

P1

Do not connect on DLP system

board.

W20

Input

Analog

RESERVED_T

P2

W19

C15,

Supply voltage for positive bias

level of micromirror reset signal

(4)

V_BIAS

C16, V11, Power

V12

Analog

G4, H4,

Power

J1, K1

Supply voltage for negative reset

level of micromirror reset signal

(4)

V_RESET

Supply voltage for HVCMOS

logic. Supply voltage for positive

offset level of micromirror reset

signal. Supply voltage for

A30, B2,

M30, Z1,

Z30

(4)

V_OFFSET

Power

Analog

stepped high voltage at

micromirror address electrodes

A24, A7,

B10, B13,

B16, B19,

B22, B28,

B5, C17,

C20, D4,

J29, K2,

L29, M2,

N27,

Supply voltage for LVCMOS

core. Supply voltage for positive

offset level of micromirror reset

signal during power down.

Supply voltage for normal high

level at micromirror address

electrodes

(4)

V_CC

Power

Analog

U27,

V13, V15,

V22,

W17,

W21,

W26,

W29, W3,

Z18, Z23,

Z29, Z7

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表5-1. Pin Functions (continued)

TRACE

DATA

INTERNAL

TYPE⁽²⁾

SIGNAL

DESCRIPTION⁽¹⁾

LENGTH

RATE⁽⁶⁾

TERMINATION⁽⁷⁾

(mil⁽⁸⁾

)

NAME

NO.

A13, A22,

A23, B12,

B14, B15,

B20, B23,

B26, B29,

B3, B6,

B9, C19,

C21, C5,

D2, G2,

J28, K3,

L28, L30,

M3, P27,

P29,

Device ground. Common return

for all power.

(5)

V_SS

Ground

U29,

V21, V23,

V26,

W12,

W16,

W18, W2,

W22,

W25,

W28,

W30, W5,

W8, Z21,

Z22, Z24

(1) The DLP500YX DMD is a component of a DLP chipset. Reliable function and operation of the DLP500YX DMD requires that it be used

in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD.

(2) I = Input, O = Output, P = Power, G = Ground, NC = No connect

(3) These signals are very sensitive to noise or intermittent power connections, which can cause irreversible DMD micromirror array

damage or, to a lesser extent, image disruption. Consider this precaution during DMD board design and manufacturer handling of the

DMD sub-assemblies.

(4) The following power supplies are required to operate the DMD: V_CC, V_OFFSET, V_BIAS, and V_RESET

(5) V_SSmust be connected for proper DMD operation.

.

(6) DDR = Double Data Rate, SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.

(7) Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions for differential termination specification.

(8) Dielectric Constant for the DMD FXK (S410) ceramic package is approximately 9.6. For the package trace lengths shown: Propagation

Speed = 11.8 sqrt (9.60 = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGES

V_CC

Supply voltage for LVCMOS core logic⁽²⁾

2.3

11

V

–0.5

–15

V_OFFSET

V_BIAS

Supply voltage for HVCMOS and micromirror electrode^{(2) (3)}

Supply voltage for micromirror electrode⁽²⁾

Supply voltage difference (absolute value)⁽⁴⁾

Supply voltage difference (absolute value)⁽⁵⁾

19

V_RESET

–0.3

11

|V_BIAS–V_OFFSET

|

34

|V_BIAS–V_RESET

|

INPUT VOLTAGES

Input voltage for all other LVCMOS input pins⁽²⁾

Input voltage for all other LVDS input pins ^{(2) (6)}

Input differential voltage (absolute value)⁽⁷⁾

Input differential current⁽⁶⁾

V_CC+ 0.5

500

V

–0.5

|V_ID|

mV

mA

I_ID

6.3

CLOCKS

Clock frequency for LVDS interface, DCLK_A, DCLK_B, DCLK_C,

DCLK_D

400

MHz

ƒ_CLOCK

ENVIRONMENTAL

Array temperature: operational⁽⁸⁾

0

90

°C

T_ARRAYand T_WINDOW

Array temperature: non–operational⁽⁸⁾

–40

Absolute temperature delta between any point on the window edge and

the ceramic test point TP1 ⁽⁹⁾

|T_DELTA

T_DP

|

30

81

°C

Dew point temperature, operating and non–operating (non-condensing)

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies are all required for proper DMD

operation. V_SSmust also be connected.

(3) V_OFFSETsupply transients must fall within specified voltages.

(4) Exceeding the recommended allowable voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(5) Exceeding the recommended allowable voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(8) The highest temperature of the active array (as calculated using 节7.6) or of any location along the window edge as defined in 图7-2.

The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-2 are intended to measure the highest window edge temperature.

If a particular application causes another location on the window edge to be at a higher temperature, use that location.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-2. The window test points TP2, TP3, TP4, and TP5 shown in 图7-2 are intended to result in the worst case delta. If a particular

application causes another location on the window edge to result in a larger delta temperature, use that location.

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6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

°C

T_DMD

DMD storage temperature

80

28

36

–40

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature (non-condensing) ⁽¹⁾

Elevated dew point temperature range (non-condensing) ⁽²⁾

Cumulative time in elevated dew point temperature range

°C

28

°C

24 Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Limit the exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of

CT_ELR

.

6.3 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN

NOM

MAX

UNIT

VOLTAGE SUPPLY

V_CC

LVCMOS logic supply voltage⁽¹⁾

1.65

9.5

1.8

10

1.95

10.5

18.5

–13.5

10.5

33

V

V_OFFSET

V_BIAS

Mirror electrode and HVCMOS voltage^{(1) (2)}

Mirror electrode voltage⁽¹⁾

17.5

18

V_RESET

Mirror electrode voltage⁽¹⁾

–14.5

–14

Supply voltage difference (absolute value)⁽³⁾

Supply voltage difference (absolute value)⁽⁴⁾

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

|

LVCMOS INTERFACE

V_IH(DC)

DC input high voltage⁽⁵⁾

DC input low voltage⁽⁵⁾

AC input high voltage⁽⁵⁾

AC input low voltage⁽⁵⁾

PWRDNZ pulse duration⁽⁶⁾

0.7 × V_CC

–0.3

V_CC+ 0.3

0.3 × V_CC

V_CC+ 0.3

0.2 × V_CC

V

V_IL(DC)

V_IH(AC)

0.8 × V_CC

–0.3

V

V_IL(AC)

V

t_PWRDNZ

10

ns

SCP INTERFACE

ƒ_SCPCLK

SCP clock frequency⁽⁷⁾

500

900

kHz

ns

Propagation delay, clock to Q, from rising-edge of SCPCLK to

valid SCPDO⁽⁸⁾

t_{SCP_PD}

0

1

Time between falling-edge of SCPENZ and the first rising-

edge of SCPCLK

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

µs

Time between falling-edge of SCPCLK and the rising-edge of

SCPENZ

t_{SCP_DS}

SCPDI clock setup time (before SCPCLK falling edge)⁽⁸⁾

SCPDI hold time (after SCPCLK falling edge)⁽⁸⁾

SCPENZ inactive pulse duration (high level)

800

900

2

ns

µs

t_{SCP_DH}

t_{SCP_PW_ENZ}

LVDS INTERFACE

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN

NOM

MAX

UNIT

MHz

mV

ns

Clock frequency for LVDS interface (all channels), DCLK⁽⁹⁾

Input differential voltage (absolute value)⁽¹⁰⁾

Common mode voltage⁽¹⁰⁾

400

ƒ_CLOCK

|V_ID|

150

1100

880

300

440

V_CM

1200

1300

1520

2000

120

V_LVDS

LVDS voltage⁽¹⁰⁾

t_{LVDS_RSTZ}

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

Line differential impedance (PWB/trace)

Z_IN

80

90

100

Ω

Z_LINE

110

Ω

ENVIRONMENTAL

Array temperature, long–term operational^{(11) (12) (13) (14)}

Array temperature, short–term operational^{(12) (15)}

Window temperature –operational⁽¹⁶⁾

10

0

40 to 70⁽¹³⁾

°C

T_ARRAY

10

85

T_WINDOW

Absolute temperature delta between any point on the window

edge and the ceramic test point TP1^{(16) (17)}

|T_DELTA

|

14

°C

T_DP-AVG

T_DP-ELR

CT_ELR

ILL_θ

Average dew point temperature (non-condensing)⁽¹⁸⁾

Elevated dew point temperature range (non-condensing)⁽¹⁹⁾

Cumulative time in elevated dew point temperature range

Illumination marginal ray angle⁽²⁰⁾

28

36

°C

28

24 Months

55 deg

For Illumination Source Between 420 nm and 700 nm

ILL_VIS

Illumination power density on array⁽²¹⁾

31 W/cm²

22

ILL_VISTP

Illumination total power on array

W

For Illumination Source <420 nm and >700 nm

ILL_IR

Illumination wavelengths > 700 nm

Illumination wavelengths < 420 nm⁽¹¹⁾

10 mW/cm²

ILL_UV

(1) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies are all required for proper DMD

operation. V_SSmust also be connected.

(2) V_OFFSETsupply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage difference |V_BIAS–V_OFFSET| must be less than the specified limit. See 节9 , 图9-1, and

表9-1.

(4) To prevent excess current, the supply voltage difference |V_BIAS–V_RESET| must be less than the specified limit. See 节9 , 图9-1, and

表9-1.

(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, “Low-Power Double Data Rate (LPDDR)”JESD209B. Tester conditions for V_IHand V_IL.

•

Frequency = 60 MHz. Maximum rise time = 2.5 ns at 20/80

Frequency = 60 MHz. Maximum fall time = 2.5 ns at 80/20

(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the

SCPDO output pin.

(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(8) See 图6-2.

(9) See LVDS timing requirements in 节6.8 and 图6-6.

(10) See LVDS waveform requirements in 图6-5.

(11) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination reduces device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-2 and the package thermal resistance 节7.6 .

(13) Per 图6-1, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. See 节7.7 for a definition of micromirror landed duty cycle.

(14) Long-term is defined as the usable life of the device.

(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is

defined as the cumulative time over the usable life of the device and is less than 500 hours.

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(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-2. The window test points TP2, TP3, TP4, and TP5 shown in 图7-2 are intended to result in the worst case delta temperature. If a

particular application causes another location on the window edge to result in a larger delta in temperature, use that location.

(17) DMD is qualified at the maximum temperature specified. Operation of the DMD outside of these limits has not been tested.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of

CT_ELR

.

(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of

micromirrors (POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not

necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance

has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array

(including POM) contributes to thermal limitations described in this document, and may negatively affect lifetime.

(21) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror

array temperature.

80

70

60

50

40

30

0/100

100/0

5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

65/35

95/5

90/10

85/15

80/20

75/25

70/30

60/40

55/45

50/50

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature—Derating Curve

6.5 Thermal Information

DLP500YX

FXK Package

257 PINS

0.90

THERMAL METRIC

UNIT

Thermal resistance, active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4 .

The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include

light energy absorbed by the window aperture and electrical power dissipation of the array.

Optical systems must be designed to minimize the light energy falling outside the window clear aperture since any additional thermal

load in this area can significantly degrade the reliability of the device.

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6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT VOLTAGES

V_OH

High level output voltage

Low level output voltage

0.8 x V_CC

V

V_CC= 1.8 V, I_OH= –2 mA

V_OL

V_CC= 1.95 V, I_OL= 2 mA

0.2 x V_CC

CURRENTS

High impedance output

current

I_OZ

V_CC= 1.95 V

25

µA

–40

–1

I_IL

Low level input current

High level input current ⁽¹⁾

Supply current V_CC

V_CC= 1.95 V, V_I= 0

V_CC= 1.95 V, V_I= V_CC

V_CC= 1.95 V

µA

I_IH

110

1500

13

I_CC

mA

(2)

I_OFFSET

I_BIAS

Supply current V_OFFSET

V_OFFSET= 10.5 V

V_BIAS= 18.5 V

(2) (3)

Supply current V_BIAS

4

(3)

I_RESET

Supply current V_RESET

V_RESET= –14.5 V

–9

SUPPLY POWER

P_CC

Supply power dissipation V_CCV_CC= 1.95 V

Supply power dissipation

2925

139

mW

P_OFFSET

P_BIAS

P_RESET

P_TOTAL

V_OFFSET= 10.5 V

(2)

V_OFFSET

Supply power dissipation

V_BIAS

V_BIAS= 18.5 V

67

131

mW

(2) (3)

Supply power dissipation

V_RESET

V_RESET= –14.5 V

(3)

Supply power dissipation

V_TOTAL

3261

(1) Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.

(2) To prevent excess current, the supply voltage difference |V_BIAS–V_OFFSET| must be less than the specified limits listed in the 节6.4

table.

(3) To prevent excess current, the supply voltage difference |V_BIAS–V_RESET| must be less than specified limit in 节6.4.

6.7 Capacitance at Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

20

UNIT

pF

C_{I_lvds}

C_{I_nonlvds}

C_{I_tdiode}

C_O

LVDS input capacitance 2xLVDS

Non-LVDS input capacitance

Temperature diode input capacitance

Output capacitance

ƒ= 1 MHz

20

pF

ƒ= 1 MHz

30

pF

20

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6.8 Timing Requirements

MIN

NOM

MAX

UNIT

SCP INTERFACE⁽¹⁾

t_r

Rise time

20% to 80% reference points

80% to 20% reference points

1

3

V/ns

t_f

Fall time

LVDS INTERFACE⁽²⁾

t_r

t_f

Rise slew rate

20% to 80% reference points

0.7

1

V/ns

ns

Fall slew rate

80% to 20% reference points

DCLK_A, LVDS pair

2.5

DCLK_B, LVDS pair

2.5

t_C

Clock cycle

DCLK_C, LVDS pair

2.5

DCLK_D, LVDS pair

2.5

DCLK_A, LVDS pair

1.19

1.25

DCLK_B, LVDS pair

1.19

t_W

Pulse duration

DCLK_C, LVDS pair

1.19

DCLK_D, LVDS pair

1.19

D_A(15:0) before DCLK_A, LVDS pair

D_B(15:0) before DCLK_B, LVDS pair

D_C(15:0) before DCLK_C, LVDS pair

D_D(15:0) before DCLK_D, LVDS pair

SCTRL_A before DCLK_A, LVDS pair

SCTRL_B before DCLK_B, LVDS pair

SCTRL_C before DCLK_C, LVDS pair

SCTRL_D before DCLK_D, LVDS pair

D_A(15:0) after DCLK_A, LVDS pair

D_B(15:0) after DCLK_B, LVDS pair

D_C(15:0) after DCLK_C, LVDS pair

D_D(15:0) after DCLK_D, LVDS pair

SCTRL_A after DCLK_A, LVDS pair

SCTRL_B after DCLK_B, LVDS pair

SCTRL_C after DCLK_C, LVDS pair

SCTRL_D after DCLK_D, LVDS pair

Channel B relative to channel A ^{(3) (4)}

Channel D relative to channel C^{(5) (6)}, LVDS pair

0.275

0.195

–1.25

t_Su

Setup time

t_h

Hold time

t_SKEW

Skew time

1.25

(1) See 图6-3 for rise time and fall time for SCP.

(2) See 图6-5 for timing requirements for LVDS.

(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and

D_AP(15:0).

(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and

D_BP(15:0).

(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and

D_CP(15:0).

(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and

D_DP(15:0).

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t

SCP_NEG_ENZ

SCP_POS_ENZ

SCPENZ

50%

...

t

SCP_DS

SCP_DH

...

SCPDI

DI

t_C

50%

...

50%

t_{SCP_PD}

50%

SCPCLK

SCPDO

...

DO

图6-2. SCP Timing Requirements

A. See 节6.4 for f_SCPCLK, t_{SCP_DS}, t_{SCP_DH}and t_{SCP_PD}specifications.

B. SCPCLK falling–edge capture for SCPDI.

C. SCPCLK rising–edge launch for SCPDO.

D. See 方程式1

1

f_SCPCLK

=

t_C

(1)

V

CC

80

50

20

V

CM

t

FALL

t

RISE

Time

图6-3. SCP Requirements for Rise and Fall

See 节6.8 for t_rand t_fspecifications and conditions.

Device pin

output under test

Tester channel

C_LOAD

图6-4. Test Load Circuit for Output Propagation Measurement

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For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

System designers must use IBIS or other simulation tools to correlate the timing reference load to a system

environment.

t

f

V

LVDS(max)

V

ID

CM

V

LVDS(min)

t

r

A. See 方程式2 and 方程式3

图6-5. LVDS Waveform Requirements

1

V_{LVDS max}= V

:

_;+ , × V

,

;

ID max

;

:

CM max

:

2

(2)

(3)

1

V_{LVDS min}= V

:

_;F , × V

,

;

ID max

;

:

CM min

:

2

See 节6.4 for V_CM, V_ID, and V_LVDSspecifications and conditions.

t

C .

t

W .

DCLK_P

DCLK_N

50%

t

H.

t

SU.

D_P(15:0)

D_N(15:0)

50%

t

H.

SU.

SCTRL_P

SCTRL_N

图6-6. Timing Requirements

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DCLK_P

DCLK_N

50%

D_P(15:0)

D_N(15:0)

SCTRL_P

SCTRL_N

50%

t

SKEW .

DCLK_P

DCLK_N

50%

D_P(15:0)

D_N(15:0)

SCTRL_P

SCTRL_N

50%

图6-7. LVDS Interface Channel Skew Definition

See 节6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(15:0) and D_N(15:0).

6.9 Typical Characteristics

When the DMD is controlled by the DLPC900, the digital controller has four modes of operation:

A. Video mode

B. Video pattern mode

C. Pre-stored pattern mode

D. Pattern on-the-fly mode

In video mode (A), the 24-bit frames displayed on the DMD are the same as the input 24-bit video frame rates. In

video pattern mode (B), the V_SYNCrates displayed on the DMD are linked to the incoming video source V_SYNC

rates but the overall pattern rates depend upon the configured bit depth. In modes B, C, and D, the pattern rates

depend on the bit depth as shown in 表6-1.

表6-1. DLP500YX Pattern Rate versus Bit Depth using DLPC900

PRE-STORED or PATTERN

ON-THE-FLY MODE (Hz)

BIT DEPTH

VIDEO PATTERN MODE (Hz)

1

2

2880

1440

960

720

480

360

247

16129

5434

3717

2183

1466

1239

923

441

96

3

4

5

6

7

8

10

12

14

16

24

6

1

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6.10 System Mounting Interface Loads

表6-2. System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

When loads are applied to the electrical and thermal interface areas

Maximum load to be applied to the electrical interface area⁽¹⁾

Maximum load to be applied to the thermal interface area⁽¹⁾

When loads are applied to only the electrical interface area

Maximum load to be applied to the electrical interface area⁽¹⁾

Maximum load to be applied to the thermal interface area⁽¹⁾

111

N

222

0

N

(1) Apply the load uniformly in the corresponding areas shown in 图6-8.

Electrical Interface Area

Thermal Interface Area

图6-8. System Mounting Interface Loads

6.11 Micromirror Array Physical Characteristics

表6-3. Micromirror Array Physical Characteristics

PARAMETER DESCRIPTION

VALUE

2048

1200

5.4

UNIT

Number of active columns⁽¹⁾

Number of active rows⁽¹⁾

M

micromirrors

µm

N

Micromirror (pixel) pitch⁽¹⁾

P

Micromirror active array width⁽¹⁾

Micromirror active array height⁽¹⁾

Micromirror Pitch × number of active columns

Micromirror Pitch × number of active rows

11.0592

6.4800

20

mm

Micromirror active border (All four sides) ⁽²⁾

Pond of micromirrors (POM)

micromirrors/side

(1) See 图6-9

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the

pond of micromirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state

but still require an electrical bias to tilt toward the OFF state.

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Off-State

Light Path

0

1

2

3

Active Micromirror Array

M x N Micromirrors

N x P

Nœ 4

Nœ 3

Nœ 2

Nœ 1

M x P

P

Incident

Illumination

Light Path

P

Pond Of Micromirrors (POM) omitted for clarity.

Details omitted for clarity.

Not to scale.

P

图6-9. Micromirror Array Physical Characteristics

Refer to 节6.11 table for M, N, and P specifications.

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6.12 Micromirror Array Optical Characteristics

表6-4. Micromirror Array Optical Characteristics

PARAMETER

Mirror tilt angle ^{(1) (2) (3) (4)}

Micromirror crossover time⁽⁵⁾

Micromirror switching time⁽⁶⁾

TEST CONDITION

MIN

NOM

17.5

1

MAX

18.4

3

UNIT

Landed State

15.6

degrees

Typical Performance

Adjacent micromirrors

Non-Adjacent micromirrors

420 - 700 nm

µs

6

0

Number of out-of-specification

micromirrors⁽⁷⁾

micromirrors

10

DMD Photopic Efficiency⁽⁸⁾

65%

(1) Measured relative to the plane formed by the overall micromirror array

(2) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(3) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations or system contrast variations.

(4) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State

direction. A binary value of 0 results in a micromirror landing in the OFF State direction. See 图6-10.

(5) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(6) The minimum time between successive transitions of a micromirror.

(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the

specified MICROMIRROR SWITCHING Time.

(8) Efficiency numbers assume 35-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and

uniform pupil illumination.

•

Window Transmission 94% (double Pass, Through Two Window Surfaces)

Micromirror Reflectivity 88%

Array Diffraction Efficiency 84% (@f/2.4)

Array Fill Factor 93%

Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this number is specified

under conditions described above and deviations from the specified conditions could result in decreased efficiency.

22

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Oﬀ-State

Light Direction

Incident

Light Direction

B

Tilted Rotation

Axis

Tilted Mirror

On-State

Mirror

Landed Edge

Tilt Angle

Oﬀ-State

Mirror

B

View B-B

On-State Mirror - Tilted Position

Landed Edge

A

Tilt Angle

Tilted Mirror

Landed Edge

View A-A

Off-State Mirror - Tilted Position

图6-10. Micromirror Landed Orientation and Tilt

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6.13 Window Characteristics

表6-5. DMD Window Characteristics

CONDITIONS

PARAMETER⁽¹⁾

MIN

NOM MAX UNIT

Window material

Corning Eagle XG

at wavelength 546.1 nm

See Note ⁽²⁾

Window refractive index

Window aperture

Illumination overfill

1.5119

Refer to 节7.5.3

Minimum within the wavelength range 420 nm to 680 nm.

Applies to all angles 0° to 30° AOI.

97%

Window transmittance, single–pass

through both surfaces and glass ⁽³⁾

Average over the wavelength range 420 nm to 680 nm.

Applies to all angles 30° to 45° AOI.

(1) See 节7.5 for more information.

(2) For details on the size and location of the window aperture, see the Mechanical ICD in the Mechanical, Packaging, and Orderable

Information section of this data sheet.

(3) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP^®DMD Window.

6.14 Chipset Component Usage Specification

Reliable function and operation of the DLP500YX DMD requires that it be used in conjunction with the other

components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology consists of the TI technology and devices used for operating or

controlling a DLP DMD.

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7 Detailed Description

7.1 Overview

The DLP500YX DMD is a 0.50-inch diagonal spatial light modulator which consists of an array of highly reflective

aluminum micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system

(MEMS). The electrical interface is low voltage differential signaling (LVDS). The DMD consists of a two-

dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N

memory cell rows. Refer to 节 7.2 . The positive or negative deflection angle of the micromirrors can be

individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror

reset signals (MBRST).

The DMD is one part of a chipset comprising of the DLP500YX DMD and the DLPC900 Controller. To ensure

reliable operation, the DLPC900 Controller must always be used to control the DLP500YX DMD.

7.2 Functional Block Diagram

Channel A Interface

Column Read and Write

Control

(0,0)

Voltages

Word Lines

Voltage

Generators

Micromirror Array

Row

(M-1, N-1)

Column Read and Write

Channel B Interface

Control

Channels C and D not shown. For pin details on channels A, B, C, and D, refer to the Pin Configurations and Functions table and the

LVDS interface section of 节6.8.

图7-1. Functional Block Diagram

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7.3 Feature Description

7.3.1 Power Interface

The DMD requires 5 DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V

is a filtered version of the 3.3VDS supply received over the flex cables from the DLPC910 Controller Board.

DMD_P3P3V is used on the DMD Board to create the other DMD voltages (DMD_P1P8V, VOFFSET, VRESET,

and VBIAS) required for proper DMD operation. TI provides a DMD board reference design on TI.com to enable

customers to see how these voltages are created as well and how the DMD board design is accomplished.

7.3.2 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-4 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers need to use IBIS

or other simulation tools to correlate the timing reference load to a system environment. The load capacitance

value stated is only for characterization and measurement of AC timing signals. This load capacitance value

does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC900 controller. See the DLPC900 controller data sheet or

contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, the projected image quality and the

optical performance are contingent on compliance to the optical system operating conditions described in the

following sections.

7.5.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

needs to be the same. This angle cannot exceed the nominal device micromirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation, and objectionable artifacts

in the display border and/or active area could occur.

7.5.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border or active area, which may require additional system apertures to control, especially

if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

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conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical

system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the

average flux level in the active area. Depending on the particular system optical architecture, overfill light may

have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Array

TP2

2X 11.75

TP5

TP4

TP3

2X 16.10

Window Edge

(4 surfaces)

TP3 (TP2)

TP5

TP4

TP1

5.05

16.10

TP1

图7-2. DMD Thermal Test Points

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Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship

between micromirror array temperature and the reference ceramic temperature is provided by the following

equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

where

• T_ARRAY= Computed array temperature (°C)

• T_CERAMIC= Measured ceramic temperature (°C) (measured at TP1 location)

• R_{ARRAY-TO-CERAMIC}= Thermal resistance of package specified in Thermal Information from array to ceramic

TP1 (°C/Watt)

• Q_ARRAY= Total DMD power on the array (W) (electrical + absorbed)

• Q_ELECTRICAL= Nominal electrical power (W)

• Q_ILLUMINATION= Illumination power absorbed (W)

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 3.26 W. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The factors used in determining the illumination power absorbed is shown in

each of the examples below. Examples are included where the optical power has been determined by measuring

the illumination power density, total illumination power, and screen lumens. The examples assume illumination

distribution is 83.7% on the active array and 16.3% on the area outside the array.

7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density

The equations below are valid for each DMD in a single chip or multi-chip DMD system.

• Q_ILLUMINATION= (Q_INCIDENT× DMD average thermal absorptivity) (W)

• Q_INCIDENT= ILL_DENSITY× ILL_AREA(W)

• ILL_DENSITY= measured illumination optical power density at DMD (W/cm²)

• ILL_AREA= illumination area on DMD (cm²)

• DMD average thermal absorptivity = 0.40

Q_ELECTRICAL= 3.26 W

Array size = 11.0592 mm × 6.4800 mm = 0.72 cm²

ILL_DENSITY= 31 W/cm²(measured)

T_CERAMIC= 50.0 °C (measured)

ILL_AREA= 0.72 cm²/ (83.7%) = 0.86 cm²

Q_INCIDENT= 31 W/cm²× 0.86 cm²=26.66 W

Q_ARRAY= 3.26 W + (0.40 × 26.66 W) = 13.92 W

T_ARRAY= 50.0 °C + (13.92 W × 0.90 °C/W) = 62.53 °C

7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power

The equations below are valid for each DMD in a single chip or multi-chip DMD system.

• Q_ILLUMINATION= (Q_INCIDENT× DMD average thermal absorptivity) (W)

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• Q_INCIDENT= measured total illumination optical power at DMD (W)

• DMD average thermal absorptivity = 0.40

Q_ELECTRICAL= 3.26 W

Q_INCIDENT=26.66 W (measured)

T_CERAMIC= 50.0 °C (measured)

Q_ARRAY= 3.26 W + (0.40 × 26.66 W) = 13.92 W

T_ARRAY= 50.0 °C + (13.92 W × 0.90 °C/W) = 62.53 °C

7.6.3 Micromirror Array Temperature Calculation using Screen Lumens

The equations below are valid for a single chip DMD system with spectral efficiency of 300 lumens/Watt.

• Q_ILLUMINATION= SL × C_L2W(W)

• SL = measured ANSI screen lumens (lm)

• C_L2W= Conversion constant for screen lumens to power absorbed on DMD (Watts/Lumen)

Q_ELECTRICAL= 3.26 W

C_L2W= 0.00266 W/lm

SL = 4000 lm (measured)

T_CERAMIC= 50.0 °C (measured)

Q_ARRAY= 3.26 W + (0.00266 W/lm × 4000 lm) = 13.9 W

T_ARRAY= 50.0 °C + (13.9 W × 0.90 °C/W) = 62.51 °C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the

time (and in the OFF state 0% of the time), whereas 0/100 would indicate that the pixel is in the OFF state 100%

of the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).

Note that when assessing the landed duty cycle, the time spent switching from one state (ON or OFF) to the

other state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

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7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD usable life.

Note that it is the symmetry or asymmetry of the landed duty cycle that is of relevance. The symmetry of the

landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a

landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect DMD usable life, and this interaction can

be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD usable life. This is

quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the maximum operating DMD temperature at a given long-term average landed

duty cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the

pixel operates under a 0/100 landed duty cycle.

If the use case involves inputting Grayscale input images, between the two extremes (ignoring for the moment

color), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, or blue) for the given pixel as well as the color cycle

time for each primary color, where “color cycle time” is the total percentage of the frame time that a given

primary must be displayed in order to achieve the desired white point.

Use the following equation to calculate the landed duty cycle of a given pixel during a specified time period

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%

×

Blue_Scale_Value)

where

• Red_Cycle_% represents the percentage of the frame time that red is displayed to achieve the desired white

point

• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired

white point

• Blue_Cycle_% represents the percentage of the frame time that blue is displayed to achieve the desired

white point

For example, assume that the red, green, and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, and

blue color intensities would be as shown in 表7-2 and 表7-3.

表7-2. Example Landed Duty Cycle for Full-Color,

Color Percentage

CYCLE PERCENTAGE

RED

GREEN

BLUE

50%

20%

30%

表7-3. Example Landed Duty Cycle for Full-Color

SCALE VALUE

GREEN

0%

LANDED DUTY

CYCLE

RED

0%

BLUE

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

60%

100%

12%

100%

0%

100%

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The DMD is a spatial light modulator, which reflects incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data being used.

The DLP500YX DMD is controlled by two DLPC900 controllers. The DMD itself receives bit planes through a

2xLVDS input data bus and, when input control commands dictate, activates the controls which update the

mechanical state of the DMD mirrors. In combination with the DLPC900 Controllers, the chipset enables four

unique modes of system level operation:

• Video Mode - 24 bit video signals presented to inputs of the DLPC900 Controllers appear on the DMD. The

DMD mirrors are updated in a PWM fashion to construct the 24 bit video data. This mode is similar to

standard DLP Display projector use cases.

• Video Pattern Mode - the user can define periods of time for specific patterns to be displayed on the DMD.

Those patterns are provided via the input video interface and are constrained to input video timing

parameters. This mode is optimal for when the data to be presented is not known in advance of operation, or

input data needs to be streamed or updated based on real-time processing conditions.

• Pre-stored Pattern Mode - the user can define the patterns in advance and build the pattern data into an on-

board flash memory. Upon power up, the DLPC900 controllers immediately start reading and displaying those

patterns. This mode is typically used in applications where the patterns to be used are known in advance and

the patterns can all fit in the external flash memory. This mode typically provides the fastest pattern update

rates.

• Pattern-on-the-Fly Pattern Mode - the user can download and update pattern data over the DLPC900 input

USB data interface. This allows an external processor to modify and update patterns based on external

processing decisions. This mode also provides streaming capability similar to the Video Pattern Mode except

that the user would need to take into account delays involved with USB transmission of pattern data and

control information.

The DLP500YX provides solutions for many varied applications including structured light (3-D machine vision),

3-D printing, information projection, and lithography.

The DLP500YX contains the most recent breakthrough micromirror technology called the TRP pixel. With a

smaller pixel pitch of 5.4 μm and increased tilt angle of 17 degrees, TRP chipsets enable higher resolution in a

smaller form factor while maintaining high optical efficiency. DLP chipsets are a great fit for any system that

requires high resolution and high output projection imaging.

8.2 Typical Application

3D machine vision is a typical embedded system application for the DLP500YX DMD. In this application, two

DLPC900 devices control the pattern data being imaged from a DLP500YX DMD onto the object being

measured while an external camera system monitors the projected patterns as they appear on the object. An

external microprocessor can then geometrically determine all 3D points of the object using the knowledge of the

projected pattern provided to the object, the actual distorted pattern as captured by the camera, and the angle

between the projector line-of-sight and the camera line-of-sight. This type of application diagram is shown in 图

8-1. In this configuration, the DLPC900 controller supports a 24-bit parallel RGB video input from an external

source computer or processor. The video input FPGA splits each 2048 x 1200 image frame into a left half and a

right half with the left half feeding the Primary DLPC900 and the right half feeding the Secondary DLPC900.

Each half consists of 1024 columns by 1200 rows plus any horizontal and vertical blanking at half the pixel clock

rate. This system configuration supports still and motion video as well as sequential pattern modes. For more

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information, refer to the DLPC900 digital controller data sheet, found on the DLPC900 Product Folder listed

under 节11.3.1.

图8-1. Typical DLP500YX Application Diagram

8.2.1 Design Requirements

At the high level, typical DLP500YX DMD systems include an illumination source (Lamp, LED, or Laser), an

optical light engine containing both illumination and projection optics, mechanics, electronic components, power

supplies, cooling systems, and software. The designer must first choose an illumination source and design the

optical engine taking into consideration the optical relationship from the illumination source to the DMD, and from

the DMD to the location of the projected image. The designer must then understand the electronic components

of a DLP500YX DMD system, part of which includes one or more PCBs which contain the DMD and Controllers.

In the TI DLP500YX based evaluation module design, the DLPC900 Controller board provides power, bit plane

data, and control information to the DMD mounted on the DLP500YX DMD board. The DLPC900 Controller

board also interfaces to the user system, accepting image data based on user provided timing (software or

hardware triggered) and providing that data in bit plane format to the DMD to be projected on the imaging target.

8.2.2 Detailed Design Procedure

A TI evaluation module design exists which shows how to connect the DLPC900 controller to the DMD. In

creating a new board specific to a customer application, layout guidelines need to be followed to achieve a

functional and reliable projection system. To complete the system, an optical module or light engine is required

that contains the DLP500YX DMD, associated illumination sources, optical elements, and necessary mechanical

components. Care must be taken to understand and implement wise design decisions regarding the engineering

aspects of illumination and projection optics, digital and analog electronics, software, and mechanical and

thermal design principles.

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8.3 DMD Die Temperature Sensing

The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the

micromirror array. The DMD thermal diode pins B17 and B18 can be connected to the TMP411 temperature

sensor as shown in 图 8-2, and an external processor can interface with the TMP411 temperature sensor over

I²C bus to allow monitoring of the DMD temperature. This temperature data can be leveraged to incorporate

additional functionality in the overall system design such as adjusting illumination, fan speeds, and so forth, all

with the idea of maintaining appropriate temperature control of the DMD.

3.3V

R1

R2

TMP411

DLP500YX

SCL

VCC

D+

R3

R5

TEMP_P

SDA

ALERT

THERM

GND

C1

R4

R6

D-

TEMP_N

GND

A. Details omitted for clarity, see the DLPLCR500YXEVM evaluation module design for connections.

B. See the TMP411 datasheet for system board layout recommendation.

C. See the TMP411 datasheet and the DLPLCR500YXEVM evaluation module design for suggested component values for R1, R2, R3,

R4, and C1.

D. R5 = 0 Ω. R6 = 0 Ω. Zero ohm resistors need to be located close to the DMD package pins.

图8-2. TMP411 Sample Schematic

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• V_SS

• V_BIAS

• V_CC

• V_OFFSET

• V_RESET

DMD power-up and power-down sequencing is strictly controlled by the DLP^®controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See 图9-1.

V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies must be coordinated during power-up and power-

down operations. Failure to meet any of the below requirements results in a significant reduction in

the DMD reliability and lifetime. Common ground V_SSmust also be connected.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, V_CCmust always start and settle before V_OFFSETplus Delay1 specified in 表9-1, V_BIAS, and

V_RESETvoltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节6.4.

• During power-up, there is no requirement for the relative timing of V_RESETwith respect to V_BIAS

.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-up, LVCMOS input pins must not be driven high until after V_CChave settled at operating

voltages listed in 节6.4.

9.2 DMD Power Supply Power-Down Procedure

• During power-down, V_CCmust be supplied until after V_BIAS, V_RESET, and V_OFFSETare discharged to within the

specified limit of ground. See 表9-1.

• During power-down, it is a strict requirement that the voltage difference between V_BIASand V_OFFSETmust be

within the specified limit shown in 节6.4.

• During power-down, there is no requirement for the relative timing of V_RESETwith respect to V_BIAS

.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-down, LVCMOS input pins must be less than specified in 节6.4.

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图9-1. DMD Power Supply Requirements

A. See 节6.4, and the Pin Functions 表5-1.

B. To prevent excess current, the supply voltage difference |VOFFSET –VBIAS| must be less than the specified limit in the 节6.4

C. To prevent excess current, the supply difference |VBIAS –VRESET| must be less than the specified limit in the 节6.4.

D. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in 表9-1.

E. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in 表9-1.

F. DLP^®controller software enables the DMD power supplies VBIAS, VRESET, VOFFSET with VCC active after RESET_OEZ is at logic

high.

G. DLP^®controller software initiates the global VBIAS command.

H. After the DMD micromirror park sequence is complete, the DLP^®controller software initiates a hardware power-down that activates

PWRDNZ and disables VBIAS, VRESET, and VOFFSET.

I.

Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP^®controller hardware,

EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to PG_OFFSET turning off to indicate the

DMD micromirror has completed the emergency park procedures.

36

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表9-1. DMD Power-Supply Requirements

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

ms

Delay from VOFFSET settled at recommended operating voltage to

VBIAS power up

Delay1

Delay2

1

2

PG_OFFSET hold time after EN_OFFSET goes low

100

ns

9.3 Restrictions on Hot Plugging and Hot Swapping

The DLP500YX uses a state of the art pixel node which enables smaller optics, higher resolution, and overall

great performance and reliability as long as certain design-for-assembly methods are used. To maximize DMD

reliability, Hot Plugging and/or Hot Swapping DMDs voids the DMD warranty conditions and must be

avoided at all times.

9.3.1 No Hot Plugging

Avoid hot plugging, the act of connecting the DMD to power supplies and/or data inputs which are already

energized, to ensure maximum reliability of the DMD. Do not add or remove the DMD from a DMD socket unless

all input power supplies of the DMD are at a potential equal to the local ground potential (VSS). This applies to a

DMD incoming test station, a partially assembled product, a completed product under test, and a product in the

field. This also applies to any cables, flex cables, or PCB connections which provide power to the DMD. Provide

power as defined in the power-up scenario detailed in 节9.1. Perform power down as defined in 节9.2.

9.3.2 No Hot Swapping

Avoid hot swapping, the act of removing and replacing the DMD with DMD power supplies and/or data inputs

which are already energized, to ensure maximum reliability of the DMD. Never add or remove the DMD from a

DMD socket unless all input power supplies of the DMD are at a potential equal to the local ground potential

(VSS). This applies to a DMD incoming test station, a partially assembled product, a completed product under

test, and a product in the field. This also applies to any cables, flex cables, or PCB connections which provide

power to the DMD. Provide power as defined in the power-up scenario detailed in 节 9.1. Perform power down

as defined in 节9.2

9.3.3 Intermittent or Voltage Power Spike Avoidance

When DMD power and/or data and clock inputs are energized, twisting of the DMD, DMD socket, or DMD board

must be avoided when trying to align the DMD within an optical engine. This twisting motion can create power

intermittences and/or voltage spikes exceeding input power and data specifications of the DMD which may

ultimately affect the DMD reliability. PCB power/data/clock/control circuits must be de-energized before making

or removing connections, including cables, connectors, probes and bed-of-nails connections.

PCB and System design considerations must take into account ways to prevent external influence of DMD input

power clock, data and control signals. Robust connectors must be used which are resistant to intermittent

connections or noise spikes if jostled or vibrated. Connectors must be used which are rated to exceed the

number of insertion/removal cycles expected in the application. External electromagnetic emitters must not be

placed nearby these sensitive circuits unless adequate EMI shielding is properly used. Sufficient bulk decoupling

and component decoupling capacitance as well as appropriate PCB layout techniques must be available for all

electrical components within the DMD based "system" such that ground bounce does not occur. See the section

on 节10.1 for more layout information.

10 Layout

10.1 Layout Guidelines

10.1.1 Critical Signal Guidelines

The DLP500YX DMD is one device in a chipset controlled by the DLPC900 Controller. The following guidelines

are targeted at designing a functioning PCB using this DLP500YX DMD chipset. The DLP500YX DMD board

must be a high-speed multi-layer PCB containing high-speed digital logic utilizing dual edge (DDR) LVDS signals

at 400 MHz clock rates. 图 10-1 shows the DLP500YX signals and the recommendations needed from/to the

DLPC900 Controller devices. The DLPC900 device provides the data and control to the DMD. The TPS65145

and LP38513 devices supply power to the DMD.

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DD_AP0

DD_AN0

DD_AP1

DD_AN1

DD_AP0

DD_AN0

DD_AP1

DD_AN1

DD_AP15

DD_AN15

DCLK_AP

DCLK_AN

SCTRL_AP

DD_AP15

DD_AN15

DCLK_AP

DCLK_AN

SCTRL_AP

SCTRL_AN

DLPC900

Secondary

DD_BP0

DD_BN0

DD_BP1

DD_BN1

DD_BN0

DD_BP1

DD_BN1

DD_BP15

DD_BN15

DCLK_BP

DCLK_BN

SCTRL_BP

SCTRL_BN

DD_BP15

DD_BN15

DCLK_BP

DCLK_BN

SCTRL_BP

SCTRL_BN

A

DD_CP0

DD_CN0

DD_CP1

DD_CN1

DD_CP0

DD_CN0

DD_CP1

DD_CN1

DLP500YX

DMD

DD_CP15

DD_CN15

DCLK_CP

DCLK_CN

SCTRL_CP

SCTRL_CN

DD_CP15

DD_CN15

DCLK_CP

DCLK_CN

SCTRL_CP

SCTRL_CN

Flex Cables

DD_DP0

DD_DN0

DD_DP1

DD_DN1

DD_DP0

DD_DN0

DD_DP1

DD_DN1

DLPC900

Primary

DD_DP15

DD_DN15

DCLK_DP

DCLK_DN

SCTRL_DP

SCTRL_DN

DD_DN15

DCLK_DP

DCLK_DN

SCTRL_DP

SCTRL_DN

DADSTRB

DADMODE0

DADADDR_0..3

DADSEL_0..1

DADOEZ

DADSTRB

DADMODE0

DADADDR_0..3

DADSEL_0..1

DADOEZ

B

SCP_CLK

SCP_DI

SCP_CLK

SCP_DI

SCP_DMD_CSZ

SCP_DO

DMD_RSTZ

DADIRQZ

SCP_DO

DMD_RSTZ

DADIRQZ

C

B

3.3 V

VSS

LP38513

3.3 V

TPS65145

图10-1. DLP500YX DMD System Connections and Layout Restrictions

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表10-1. Layout Restriction Notes for 图10-1

Signal Type

Guideline

Prevent signal noise

Route 100 ±10-Ωresistor

Intra-pair (P-to-N) length tolerance is ±12-mils

DD and SCTRL must be matched to the DCLK within ±150-mils

DCLK_C must be matched to DCLK_D within ±1.25-ns

DCLK_A must be matched to DCLK_B within ±1.25-ns

Do not switch routing layers except at the beginning and end of trace

Signal routing length must not exceed 375-mm

Prevent signal noise

A

Differential

B

C

Single-ended

Route single-ended signals 50 ±5-Ω

No length match requirement

VRESET, VOFFSET, VBIAS, and VCC at the DMD must be kept within the operating limits

specified in the data sheet

Power

Provide proper amount of decoupling capacitance for each voltage at the DMD

10.1.2 Power Connection Guidelines

The following are recommendations for the power connections to the DMD or DMD PCB:

• Solid planes are required for DMD_P3P3V(3.3V), DMD_P1P8V and Ground.

• TI strongly recommends partial power planes are used for VOFFSET, VRESET, and VBIAS.

• VOFFSET, VBIAS, VRESET, VCC, and VCCI power rails must be kept within the specified operating range.

This includes effects from ripple and DC error.

• To accommodate power supply transient current requirements, adequate decoupling capacitance must be

placed as near the DMD VOFFSET, VBIAS, VRESET, VCC, and VCCI pins as possible.

• Do not swap DMDs while the DMD is still powered on (this is called hot swapping). All DMD power supply

rails and signals must be 0 volts (not driven) before connecting or disconnecting the DMD physical interface.

• Do not allow power to be applied to the DMD when one or more signal pins are not being driven.

• Decoupling capacitor locations for the DMD must be as close as possible to the DMD. The pads of the

capacitors must be connected to at least two or three vias to get a very low impedance to ground as shown in

图10-3. Furthermore, the capacitor must be in the flow of the power trace as it goes to the input of the DMD.

• It is extremely important to adhere to the 节9.1 and 节9.2 and do not allow the DMD power-supply levels to

be outside of the recommended operating conditions specified in the DMD data sheet.

These figures show examples of bypass decoupling capacitor layout.

图10-3. Good Layout

图10-2. Poor Layout

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10.1.3 Noise Coupling Avoidance

During operation, it is critical to prevent the coupling of noise or intermittent power connections onto the following

signals because irreversible DMD micromirror array damage or lesser effects of image disruption can occur:

• SCTRL_DN, STRL_DP

• DCLK_DN, DCLK_DP

• SCPCLK

• SCPDI

• SCP_DMD_CSZ

• DADADDR_0, DADADDR1_1, DADADDR_2, DADADDR_3

• DADMODE0

• DADSEL_0, DADSEL_1, DADSEL_2, DADSEL_3

• DADSTRB

• DMD_RSTZ

• DADOEZ

• PG_OFFSET

In this context, the following conditions are considered noise:

• Shorting to another signal

• Shorting to power

• Shorting to ground

• Intermittent connection (includes hot swapping)

• An electrical open condition

• An electrical floating condition

• Inducing electromagnetic interference that is strong enough to affect the integrity of the signals

• Unstable inputs (conditions outside of the specified operating range) to any of the device power rails

• Voltage fluctuations on the device ground pins

10.2 Layout Example

10.2.1 Layers

The layer stack-up and copper weight for each layer is shown in 表10-2. Small sub-planes are allowed on signal

routing layers to connect components to major sub-planes on top/bottom layers if necessary.

表10-2. Layer Stack-Up

LAYER

NO.

LAYER NAME

Side A - DMD only

COPPER WT. (oz.)

COMMENTS

1

1.5

1

DMD, escapes, low frequency signals, power sub-planes.

Solid ground plane (net GND).

2

Ground

3

Signal

0.5

1

50 Ωand 100 Ωdifferential signals

4

Ground

Solid ground plane (net GND)

5

DMD_P3P3V

1

+3.3-V power plane (net DMD_P3P3V)

50 Ωand 100 Ωdifferential signals

6

Signal

0.5

1

7

Ground

Solid ground plane (net GND).

8

Side B - All other Components

1.5

Discrete components, low frequency signals, power sub-planes

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10.2.2 Impedance Requirements

TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed

in 图10-1 and repeated for convenience in 表10-3.

表10-3. Special Impedance Requirements

Signal Type

Signal Name

Impedance (ohms)

D_AP(0:15), D_AN(0:15)

DCLK_AP, DCLK_AN

SCTRL_AP, SCTRL_AN

D_BP(0:15), D_BN(0:15)

DCLK_BP, DCLK_BN

SCTRL_BP, SCTRL_BN

D_CP(0:15), D_CN(0:15)

DCLK_CP, DCLK_CN

SCTRL_CP, SCTRL_CN

D_DP(0:15), D_DN(0:15)

DCLK_DP, DCLK_DN

SCTRL_DP, SCTRL_DN

100 ±10% differential across

each pair

A channel LVDS differential pairs

100 ±10% differential across

each pair

B channel LVDS differential pairs

C channel LVDS differential pairs

100 ±10% differential across

each pair

100 ±10% differential across

each pair

D channel LVDS differential pairs

10.2.3 Trace Width, Spacing

Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.005” design rule. Minimum

trace clearance from the ground ring around the PWB has a 0.1” minimum. An analysis of impedance and

stack-up requirements determine the actual trace widths and clearances.

10.2.3.1 Voltage Signals

Below are additional voltage supply layout examples from the power planes to the individual DMD pins. In

general, power supply trace widths must be as wide as possible to reduce impedances.

表10-4. Special Trace Widths, Spacing Requirements

MINIMUM TRACE WIDTH TO

SIGNAL NAME

GND

LAYOUT REQUIREMENT

Maximize trace width to connecting pin

PINS (MIL)

15

DMD_P3P3V

DMD_P1P8V

VOFFSET

VRESET

Maximize trace width to connecting pin

Create mini plane from the power generation to the DMD input

VBIAS

All DMD control input/

output connections

10

Use 10 mil etch to connect all signals/voltages to DMD pads

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP500YX

FXK

Package

TI Internal Numbering

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking includes both human-readable information and a 2-dimensional matrix code. The human-

readable information is described in 图11-2. The 2-dimensional matrix code is an alpha-numeric character string

that contains the DMD part number, part 1 of the serial number, and part 2 of the serial number. The first

character of the DMD serial number (part 1) is the manufacturing year. The second character of the DMD serial

number (part 1) is the manufacturing month.

Example: DLP500YXFXK GHXXXXX LLLLLLM

2-Dimension Matrix Code

(Part Number and Serial Number)

DMD Part Number

DLP500YX FXK

GHXXXXX LLLLLLM

Part 1 of Serial Number

(7 characters)

Part 2 of Serial Number

(7 characters)

图11-2. DMD Marking Locations

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11.3 Documentation Support

11.3.1 Related Documentation

The following documents contain additional information related to the chipset components used with the

DLP500YX.

• DLP500YX Product Folder

• DLPC900 Product Folder

• DLPC900 Programmers Guide

11.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP500YX
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.50 英寸、2048x1200 阵列、S410 数字微镜器件 (DMD)
文件：	总50页 (文件大小：2209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP500YX [TI]

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