DLP480REAAFXG_技术文档

DLP480RE

ZHCSQB5B –APRIL 2019 –REVISED FEBRUARY 2023

DLP480RE 0.48 WUXGA DMD

1 特性

3 说明

• 0.48 英寸对角线微镜阵列

TI DLP480RE 数字微镜器件 (DMD) 是一款数控微机电

系统 (MEMS) 空间照明调制器 (SLM)，可用于实现高

分辨率 WUXGA 显示系统。DLP480RE DMD 通过与

DLPC4430 显示控制器、DLPA100 控制器电源和电机

驱动器配合使用，可提供实现高性能系统的能力，是需

要在更小封装中实现更高分辨率及 16:10 宽高比、高

亮度和系统简单性的显示应用的理想之选。

– WUXGA（1920 × 1200）显示分辨率

– 5.4 微米微镜间距

– ±17° 微镜倾斜度（相对于平坦表面）

– 底部照明

• 2xLVDS 输入数据总线

• DLP480RE 芯片组包括：

器件信息

封装⁽¹⁾

– DLP470TE DMD

– DLPC4430 控制器

– DLPA100 控制器电源管理和电机驱动器IC

封装尺寸（标称值）

器件型号

DLP480RE

FXG (257)

32mm × 22mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• WUXGA 显示屏

• 智能显示屏

• 数字标牌

• 企业投影仪

• 教育投影仪

DLP480RE 简化应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS160

DLP480RE

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ZHCSQB5B –APRIL 2019 –REVISED FEBRUARY 2023

Table of Contents

7.4 Device Functional Modes..........................................24

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications................................................................ 10

6.1 Absolute Maximum Ratings...................................... 10

6.2 Storage Conditions................................................... 10

6.3 ESD Ratings..............................................................11

6.4 Recommended Operating Conditions.......................11

6.5 Thermal Information..................................................14

6.6 Electrical Characteristics...........................................14

6.7 Capacitance at Recommended Operating

Conditions................................................................... 14

6.8 Timing Requirements................................................15

6.9 System Mounting Interface Loads............................ 18

6.10 Micromirror Array Physical Characteristics.............19

6.11 Micromirror Array Optical Characteristics............... 21

6.12 Window Characteristics.......................................... 22

6.13 Chipset Component Usage Specification............... 22

7 Detailed Description......................................................23

7.1 Overview...................................................................23

7.2 Functional Block Diagram.........................................23

7.3 Feature Description...................................................24

Considerations............................................................ 24

7.6 Micromirror Array Temperature Calculation.............. 25

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 26

8 Application and Implementation..................................29

8.1 Application Information............................................. 29

8.2 Typical Application.................................................... 29

8.3 DMD Die Temperature Sensing................................ 31

9 Power Supply Recommendations................................33

9.1 DMD Power Supply Power-Up Procedure................33

9.2 DMD Power Supply Power-Down Procedure........... 33

10 Layout...........................................................................35

10.1 Layout Guidelines................................................... 35

10.2 Layout Example...................................................... 35

11 Device and Documentation Support..........................36

11.1 第三方产品免责声明................................................36

11.2 Device Support........................................................36

11.3 Documentation Support.......................................... 37

11.4 Receiving Notification of Documentation Updates..37

11.5 支持资源..................................................................37

11.6 Trademarks............................................................. 37

11.7 静电放电警告...........................................................37

11.8 术语表..................................................................... 37

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (June 2022) to Revision B (February 2023)

Page

• 将控制器更改为DLPC4430，更新了应用图.......................................................................................................1

• 通篇将控制器更改为DLPC4430.........................................................................................................................1

• Added the lamp illumination section..................................................................................................................11

• Added DMD efficiency specification..................................................................................................................21

Changes from Revision * (April 2019) to Revision A (June 2022)

Page

• 根据最新的德州仪器(TI) 和行业数据表标准对本文档进行了更新.......................................................................1

• Updated Timing Requirements ........................................................................................................................ 15

• Updated 图6-3 ................................................................................................................................................ 15

2

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5 Pin Configuration and Functions

12 14

26

28 30

2

4

6

8

10

16 18 20 22 24

1

3

5

7

9 11 13 15 17 19 21 23 25 27 29

Z

V

T

W

U

R

N

L

P

M

K

H

F

J

G

E

C

A

D

B

图5-1. Series 410 257-pin FXG Bottom View

CAUTION

To ensure reliable, long-term operation of the .48-inch WUXGA S410 DMD, it is critical to properly manage the layout and

operation of the signals identified in the table below. For specific details and guidelines, refer to the PCB Design

Requirements for TI DLP Standard TRP Digital Micromirror Devices application report before designing the board.

表5-1. Pin Functions

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

D_AN(0)

NO.

C6

C3

E1

C4

D1

B8

F4

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

E3

C11

F3

NC

LVDS

DDR Differential

No connect

805.0

K4

H3

J3

C13

A5

A3

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

D_AP(0)

NO.

C7

C2

E2

B4

C1

B7

E4

D3

C12

F2

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

NC

LVDS

DDR Differential

No connect

805.0

J4

G3

J2

C14

A6

A4

N4

Z11

W4

W10

L1

V8

W6

M1

R4

W1

U4

V2

Z5

NC

LVDS

DDR Differential

No connect

805.0

N3

Z2

L4

4

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

D_BP(0)

NO.

M4

Z12

Z4

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

D_BP(8)

D_BP(9)

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

D_BP(15)

D_CN(0)

D_CN(1)

D_CN(2)

D_CN(3)

D_CN(4)

D_CN(5)

D_CN(6)

D_CN(7)

D_CN(8)

D_CN(9)

D_CN(10)

D_CN(11)

D_CN(12)

D_CN(13)

D_CN(14)

D_CN(15)

Z10

L2

V9

W7

N1

NC

LVDS

DDR Differential

No connect

805.0

P4

V1

T4

V3

Z6

N2

Z3

L3

H27

A20

H28

K28

K30

C23

G27

J30

B24

A21

A27

C29

A26

C25

A29

C30

I

LVDS

DDR Differential

Data negative

805.0

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

D_CP(0)

NO.

J27

A19

H29

K27

K29

C22

F27

H30

B25

B21

B27

C28

A25

C24

A28

B30

V25

V28

T30

V27

U30

W23

R27

T28

V20

R28

L27

N28

M28

V18

Z26

Z28

D_CP(1)

D_CP(2)

D_CP(3)

D_CP(4)

D_CP(5)

D_CP(6)

D_CP(7)

D_CP(8)

D_CP(9)

D_CP(10)

D_CP(11)

D_CP(12)

D_CP(13)

D_CP(14)

D_CP(15)

D_DN(0)

D_DN(1)

D_DN(2)

D_DN(3)

D_DN(4)

D_DN(5)

D_DN(6)

D_DN(7)

D_DN(8)

D_DN(9)

D_DN(10)

D_DN(11)

D_DN(12)

D_DN(13)

D_DN(14)

D_DN(15)

I

LVDS

DDR Differential

Data positive

805.0

I

LVDS

DDR Differential

Data negative

6

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

D_DP(0)

NO.

V24

V29

T29

W27

V30

W24

T27

U28

V19

R29

M27

P28

M29

V17

Z25

Z27

G1

805.0

D_DP(1)

D_DP(2)

D_DP(3)

D_DP(4)

D_DP(5)

D_DP(6)

D_DP(7)

I

LVDS

DDR Differential

Data positive

D_DP(8)

D_DP(9)

D_DP(10)

D_DP(11)

D_DP(12)

D_DP(13)

D_DP(14)

D_DP(15)

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

SCTRL_CN

SCTRL_CP

SCTRL_DN

SCTRL_DP

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

DCLK_CN

DCLK_CP

DCLK_DN

DCLK_DP

F1

NC

LVDS

DDR Differential

No connect

805.0

V5

V4

C26

C27

P30

R30

H2

I

LVDS

DDR Differential

Serial control negative

Serial control positive

Serial control negative

Serial control positive

805.0

H1

NC

LVDS

Differential

No connect

805.0

V6

V7

D27

E27

N29

N30

I

LVDS

Differential

Clock negative

Clock positive

Clock negative

Clock positive

805.0

Serial communications port clock. Active only

when SCPENZ is logic low

SCPCLK

SCPDI

A10

A12

I

LVCMOS

Pulldown

Serial communications port Data Input.

Synchronous to SCPCLK rising edge

SDR Pulldown

SCPENZ

C10

A11

Z13

W13

V10

W14

W9

I

LVCMOS

Pulldown

SDR

Serial communications port enable active low

Serial communications port output

SCPDO

O

RESET_ADDR(0)

RESET_ADDR(1)

RESET_ADDR(2)

RESET_ADDR(3)

RESET_MODE(0)

RESET_SEL(0)

RESET_SEL(1)

I

LVCMOS

Pulldown

Reset driver address select

Reset driver mode select

Reset driver level select

V14

Z8

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

NO.

Rising edge latches in RESET_ADDR,

RESET_MODE, and RESET_SEL

RESET_STROBE

PWRDNZ

Z9

A8

I

LVCMOS

Pulldown

Pullup

Active low device reset

Active low output enable for internal reset

driver circuits

RESET_OEZ

W15

Active low output interrupt to DLP^®display

controller

RESET_IRQZ

EN_OFFSET

PG_OFFSET

V16

C9

O

I

LVCMOS

Active high enable for external VOFFSET

regulator

Active low fault from external VOFFSET

regulator

A9

Pullup

TEMP_N

TEMP_P

B18

B17

Analog

Temperature sensor diode cathode

Temperature sensor diode anode

D12, D13,

D14, D15,

D16, D17,

D18, D19,

U12, U13,

U14, U15

Do not connect on the printed circuit board

(PCB). No connect. No electrical connections

from CMOS bond pad to package pin

RESERVED

NC

Analog

Pulldown

U16, U17,

U18, U19

No connect. No electrical connection from

CMOS bond pad to package pin

No Connect

NC

O

RESERVED_BA

RESERVED_BB

RESERVED_BC

RESERVED_BD

RESERVED_PFE

RESERVED_TM

RESERVED_TP0

RESERVED_TP1

RESERVED_TP2

W11

B11

Z20

C18

A18

C8

Do not connect on the printed circuit board

(PCB)

LVCMOS

Connect to ground on the printed circuit board

(PCB)

I

LVCMOS

Analog

Pulldown

Z19

W20

W19

Do not connect on the printed circuit board

(PCB)

C15, C16,

V11, V12

Supply voltage for positive bias level of

micromirror reset signal

VBIAS⁽¹⁾

P

Analog

G4, H4,

J1, K1

Supply voltage for negative reset level of

micromirror reset signal

VRESET⁽¹⁾

Supply voltage for HVCMOS logic. Supply

voltage for positive offset level of micromirror

reset signal. Supply voltage for stepped high

voltage at micromirror address electrodes

A30, B2,

M30, Z1,

Z30

VOFFSET⁽¹⁾

P

Analog

A24, A7,

B10, B13,

B16, B19,

B22, B28,

B5, C17,

C20, D4,

J29, K2,

L29, M2,

N27, U27,

V13, V15,

V22, W17,

W21,

Supply voltage for LVCMOS core. Supply

voltage for positive offset level of micromirror

reset signal during Power down. Supply

voltage for normal high level at micromirror

address electrodes

VCC⁽¹⁾

P

Analog

W26,

W29, W3,

Z18, Z23,

Z29, Z7

8

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表5-1. Pin Functions (continued)

TRACE

LENGTH

(mil)

DATA

INTERNAL

I/O⁽³⁾

SIGNAL

DESCRIPTION

RATE TERMINATION

NAME

NO.

A13, A22,

A23, B12,

B14, B15,

B20, B23,

B26, B29,

B3, B6,

B9, C19,

C21, C5,

D2, G2,

J28, K3,

L28, L30,

M3, P27,

P29, U29,

V21, V23,

V26, W12,

W16,

VSS⁽²⁾

G

Device ground. Common return for all power

W18, W2,

W22,

W25,

W28,

W30, W5,

W8, Z21,

Z22, Z24

(1) V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies must be connected for proper DMD operation.

(2) V_SSmust be connected for proper DMD operation.

(3) I = Input, O = Output, P = Power, G = Ground, NC = No connect

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

SUPPLY VOLTAGES

V_CC

Supply voltage for LVCMOS core logic⁽²⁾

2.3

11

V

–0.5

–15

V_OFFSET

V_BIAS

Supply voltage for HVCMOS and micromirror electrode^{(2) (3)}

Supply voltage for micromirror electrode⁽²⁾

Supply voltage difference (absolute value)⁽⁴⁾

Supply voltage difference (absolute value)⁽⁵⁾

19

V_RESET

-0.3

11

|V_BIAS–V_OFFSET

|

34

|V_BIAS–V_RESET

|

INPUT VOLTAGES

Input voltage for all other LVCMOS input pins⁽²⁾

Input differential voltage (absolute value)⁽⁶⁾

Input differential current⁽⁷⁾

V_CC+ 0.5

500

V

–0.5

|V_ID|

mV

mA

I_ID

6.3

Clocks

Clock frequency for LVDS interface, DCLK_C

Clock frequency for LVDS interface, DCLK_D

400

MHz

ƒ_CLOCK

ENVIRONMENTAL

Temperature, operating⁽⁸⁾

0

90

°C

T_ARRAYand

T_WINDOW

Temperature, non–operating⁽⁸⁾

–40

Absolute Temperature difference between any point on the window edge and

the ceramic test point TP1 ⁽⁹⁾

|T_DELTA

T_DP

|

30

81

°C

Dew Point Temperature, operating and non–operating (noncondensing)

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies are all required for proper DMD

operation. V_SSmust also be connected.

(3) V_OFFSETsupply transients must fall within specified voltages.

(4) Exceeding the recommended allowable voltage difference between V_BIASand V_OFFSETmay result in excessive current draw.

(5) Exceeding the recommended allowable voltage difference between V_BIASand V_RESETmay result in excessive current draw.

(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated using 节7.6) or of any point along the window edge as defined in 图7-1.

The locations of thermal test points TP2, TP3, TP4 and TP5 in 图7-1 are intended to measure the highest window edge temperature.

If a particular application causes another point on the window edge to be at a higher temperature, use that point.

(9) Temperature difference is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown

in 图7-1. The window test points TP2, TP3, TP4 and TP5 shown in 图7-1 are intended to result in the worst case difference. If a

particular application causes another point on the window edge to result in a larger difference temperature, use that point.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system

MIN

MAX

80

UNIT

°C

T_stg

DMD storage temperature

–40

T_DP-AVGAverage dew point temperature, (non-condensing) ⁽¹⁾

28

°C

T_DP-ELRElevated dew point temperature range , (non-condensing) ⁽²⁾

28

36

°C

CT_ELR

Cumulative time in elevated dew point temperature range

24 Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

10

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(2) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of

CT_ELR

.

6.3 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN

NOM

MAX

UNIT

VOLTAGE SUPPLY

V_CC

LVCMOS logic supply voltage⁽¹⁾

1.65

9.5

1.8

10

1.95

10.5

V

V_OFFSET

V_BIAS

Mirror electrode and HVCMOS voltage^{(1) (2)}

Mirror electrode voltage⁽¹⁾

17.5

18

18.5

V_RESET

Mirror electrode voltage⁽¹⁾

–14.5

–14

–13.5

|V_BIAS

V_OFFSET

–

|

Supply voltage difference (absolute value)⁽³⁾

Supply voltage difference (absolute value)⁽⁴⁾

10.5

33

V

|V_BIAS

V_RESET

–

|

LVCMOS INTERFACE

V_IH(DC)

DC input high voltage⁽⁵⁾

0.7 × V_CC

–0.3

V_CC+ 0.3

0.3 × V_CC

V_CC+ 0.3

0.2 × V_CC

V

V_IL(DC)

DC input low voltage⁽⁵⁾

AC input high voltage⁽⁵⁾

AC input low voltage⁽⁵⁾

PWRDNZ pulse duration⁽⁶⁾

V_IH(AC)

0.8 × V_CC

–0.3

V

V_IL(AC)

V

t_PWRDNZ

SCP INTERFACE

ƒ_SCPCLK

10

ns

SCP clock frequency⁽⁷⁾

500

900

kHz

ns

Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid

t_{SCP_PD}

0

1

SCPDO⁽⁸⁾

Time between falling-edge of SCPENZ and the first rising- edge of

SCPCLK

t_{SCP_NEG_ENZ}

µs

t_{SCP_POS_ENZ}

t_{SCP_DS}

Time between falling-edge of SCPCLK and the rising-edge of SCPENZ

SCPDI Clock setup time (before SCPCLK falling edge)⁽⁸⁾

SCPDI Hold time (after SCPCLK falling edge)⁽⁸⁾

1

800

900

2

µs

ns

µs

t_{SCP_DH}

t_{SCP_PW_ENZ}

SCPENZ inactive pulse duration (high level)

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN

NOM

MAX

UNIT

LVDS INTERFACE

Clock frequency for LVDS interface (all channels), DCLK⁽⁹⁾

400

440

MHz

mV

ns

ƒ_CLOCK

|V_ID|

Input differential voltage (absolute value)⁽¹⁰⁾

Common mode voltage⁽¹⁰⁾

150

1100

880

300

V_CM

1200

1300

1520

2000

120

V_LVDS

t_{LVDS_RSTZ}

Z_IN

LVDS voltage⁽¹⁰⁾

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

Line differential impedance (PWB/trace)

80

90

100

Ω

Z_LINE

110

Ω

ENVIRONMENTAL

40 to

70⁽¹³⁾

Array temperature, Long–term operational^{(11) (12) (13) (14)}

10

0

°C

T_ARRAY

Array temperature, Short–term operational^{(12) (15)}

Window temperature –operational^{(19) (21)}

10

85

°C

T_WINDOW

Absolute temperature difference between any point on the window edge

and the ceramic test point TP1^{(16) (17)}

|T_DELTA

|

14

°C

Average dew point temperature (non–condensing)⁽¹⁸⁾

Elevated dew point temperature range (non-condensing)⁽²⁰⁾

Cumulative time in elevated dew point temperature range

T_{DP -AVG}

T_DP-ELR

CT_ELR

28

36

°C

28

24 Months

ILLUMINATION (Lamp)

L

Operating system luminance⁽¹⁷⁾

4000

lm

2.00 mW/cm²

mW/cm²

ILL_UV

ILL_VIS

ILL_IR

ILL_θ

Illumination Wavelengths < 395 nm⁽¹¹⁾

Illumination Wavelengths between 395 nm and 800 nm

Illumination Wavelengths > 800 nm

0.68

Thermally limited

10 mW/cm²

Illumination Marginal Ray Angle⁽²¹⁾

55

deg

lm

ILLUMINATION (Solid State)

L

Operating system luminance⁽¹⁷⁾

6000

ILL_UV

ILL_VIS

ILL_IR

Illumination Wavelengths < 436 nm⁽¹¹⁾

0.45 mW/cm²

Illumination Wavelengths between 436 nm and 800 nm

Illumination Wavelengths > 800 nm

Thermally limited mW/cm²

10 mW/cm²

ILL_θ

Illumination Marginal Ray Angle⁽²¹⁾

55

lm

(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper

DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than specified limit. See 节9, 图9-1, and

表9-1.

(4) To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than specified limit. See 节9, 图9-1, and 表

9-1.

(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, “Low-Power Double Data Rate (LPDDR)”JESD209B.Tester Conditions for VIH and VIL.

•

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% –80%)

Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% –20%)

(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the

SCPDO output pin.

(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(8) See 图6-2.

(9) See LVDS Timing Requirements in 节6.8 and 图6-6.

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(10) See 图6-5 LVDS Waveform Requirements.

(11) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination reduces device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the package thermal resistance 节7.6.

(13) Per 图6-1, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. See 节7.7 for a definition of micromirror landed duty cycle.

(14) Long-term is defined as the usable life of the device.

(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is

defined as cumulative time over the usable life of the device and is less than 500 hours.

(16) Temperature difference is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown

in 图7-1. The window test points TP2, TP3, TP4 and TP5 shown in 图7-1 are intended to result in the worst case difference

temperature. If a particular application causes another point on the window edge to result in a larger difference in temperature, use that

point.

(17) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of

these limits has not been tested.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) The locations of Thermal Test Points TP2, TP3, TP4 and TP5 in Figure 10 are intended to measure the highest window edge

temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular

application causes additional points on the window edge to be at a higher temperature, add those test points

(20) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of

CT_ELR

.

(21) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

80

70

60

50

40

30

0/100

100/0

5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

65/35

95/5

90/10

85/15

80/20

75/25

70/30

60/40

55/45

50/50

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature - Derating Curve

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6.5 Thermal Information

DLP480RE

FXG Package

257 PINS

0.90

THERMAL METRIC

UNIT

Thermal resistance, active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by

the window aperture and electrical power dissipation of the array. Optical systems must be designed to minimize the light energy falling

outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC= 1.8 V, I_OH= –2 mA

V_CC= 1.95 V, I_OL= 2 mA

MIN

TYP

MAX

UNIT

V

V_OH

V_OL

High level output voltage

Low level output voltage

0.8 × V_CC

0.2 x V_CC

25

V

High impedance output

current

I_OZ

V_CC= 1.95 V

µA

–40

–1

I_IL

Low level input current

V_CC= 1.95 V, V_I= 0

V_CC= 1.95 V, V_I= V_CC

V_CC= 1.95 V

µA

I_IH

High level input current ^{(1) (2)}

110

715

I_CC

Supply current VCC

mA

mW

I_OFFSET

I_BIAS

I_RESET

P_CC

Supply current VOFFSET ⁽²⁾

Supply current VBIAS ^{(2) (3)}

Supply current VRESET ⁽³⁾

V_OFFSET= 10.5 V

V_BIAS= 18.5 V

7

2.75

-5

V_RESET= –14.5 V

Supply power dissipation V_CCV_CC= 1.95 V

Supply power dissipation

1394.25

P_OFFSET

P_BIAS

P_RESET

P_TOTAL

V_OFFSET= 10.5 V

73.50

50.87

mW

(2)

V_OFFSET

Supply power dissipation

V_BIAS= 18.5 V

(2) (3)

V_BIAS

Supply power dissipation

72.5

V_RESET= –14.5 V

(3)

V_RESET

Supply power dissipation

V_TOTAL

1591.12

(1) Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.

(2) To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than the specified limits listed in the 节6.4

table.

(3) To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than specified limit in Recommended

Operating Conditions.

6.7 Capacitance at Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_{I_lvds}

LVDS input capacitance 2× LVDS

20

pF

ƒ= 1 MHz

Non-LVDS input capacitance 2×

LVDS

C_{I_nonlvds}

20

pF

ƒ= 1 MHz

Temperature diode input capacitance

2× LVDS

C_{I_tdiode}

C_O

30

20

pF

ƒ= 1 MHz

Output capacitance

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6.8 Timing Requirements

MIN

NOM

MAX

UNIT

SCP⁽¹⁾

t_r

Rise time

Fall time

20% to 80% reference points

80% to 20% reference points

30

ns

t_f

LVDS⁽²⁾

t_r

t_f

Rise slew rate

Fall slew rate

20% to 80% reference points

80% to 20% reference points

DCLK_C,LVDS pair

0.7

1

V/ns

ns

2.5

t_C

Clock cycle

DCLK_D, LVDS pair

2.5

ns

DCLK_C LVDS pair

1.19

1.25

ns

t_W

Pulse duration

DCLK_D LVDS pair

1.19

ns

D_C(15:0) before DCLK_C, LVDS pair

D_D(15:0) before DCLK_D, LVDS pair

SCTRL_C before DCLK_C, LVDS pair

SCTRL_D before DCLK_D, LVDS pair

D_C(15:0) after DCLK_C, LVDS pair

D_D(15:0) after DCLK_D, LVDS pair

SCTRL_C after DCLK_C, LVDS pair

SCTRL_D after DCLK_D, LVDS pair

0.275

0.195

ns

t_Su

Setup time

ns

t_h

Hold time

Skew time

ns

LVDS⁽²⁾

t_SKEW

Channel D relative to Channel C^{(3) (4)}, LVDS pair

1.25

ns

–1.25

(1) See 图6-3 for rise time and fall time for SCP.

(2) See 图6-5 for timing requirements for LVDS.

(3) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and

D_CP(15:0).

(4) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and

D_DP(15:0).

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SCPCLK falling–edge capture for SCPDI.

SCPCLK rising–edge launch for SCPDO.

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

50%

SCPENZ

t_{SCP_DS}

t_{SCP_DH}

50%

DI

SCPDI

t_C

f_SCPCLK= 1 / t_C

50%

SCPCLK

t_{SCP_PD}

50%

DO

SCPDO

图6-2. SCP Timing Requirements

See 节6.4 for f_SCPCLK, t_{SCP_DS}, t_{SCP_DH}and t_{SCP_PD}specifications.

SCPCLK, SCPDI,

SCPDO, SCPENZ

100%

80%

20%

0%

t_f

t_r

Time

图6-3. SCP Requirements for Rise and Fall

See 节6.8 for t_rand t_fspecifications and conditions.

Device pin

output under test

Tester channel

C_LOAD

图6-4. Test Load Circuit for Output Propagation Measurement

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For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

System designers use IBIS or other simulation tools to correlate the timing reference load to a system

environment.

V_{LVDS max}= V_{CM max}+ | 1/2 * V_{ID max}

|

t_f

V_CM

V_ID

t_r

V_{LVDS min}= V_{CM min}œ | 1/2 * V_{ID max}

|

图6-5. LVDS Waveform Requirements

See 节6.4 for V_CM, V_ID, and V_LVDSspecifications and conditions.

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t

c

t

w

t

w

DCLK_P

DCLK_N

50%

t

h

t

su

D_P(?:0)

D_N(?:0)

50%

SCTRL_P

SCTRL_N

50%

t

skew

t

c

t

w

t

w

DCLK_P

DCLK_N

50%

t

h

t

su

D_P(?:0)

D_N(?:0)

50%

SCTRL_P

SCTRL_N

50%

图6-6. Timing Requirements

See 节6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(?:0) and D_N(?:0).

6.9 System Mounting Interface Loads

表6-1. System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

12

UNIT

kg

Thermal interface area⁽¹⁾

Electrical interface area⁽¹⁾

25

kg

(1) Uniformly distributed within area shown in 图6-7

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Electrical Interface Area

Thermal Interface Area

图6-7. System Mounting Interface Loads

6.10 Micromirror Array Physical Characteristics

表6-2. Micromirror Array Physical Characteristics

PARAMETER DESCRIPTION

VALUE

1920

1200

5.4

UNIT

micromirrors

µm

Number of active columns ⁽¹⁾

M

N

P

Number of active rows ⁽¹⁾

Micromirror (pixel) pitch ⁽¹⁾

Micromirror active array width ⁽¹⁾

Micromirror active array height ⁽¹⁾

Micromirror active border (Top / Bottom) ⁽²⁾

Micromirror active border (Right / Left) ⁽²⁾

Micromirror Pitch × number of active columns

Micromirror Pitch × number of active rows

Pond of micromirrors (POM)

10.368

6.48

20

mm

micromirrors/side

Pond of micromirrors (POM)

84

(1) See 图6-8.

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the

Pond Of Mirrors (POM). These micromirrors are structurally and electrically prevented from tilting toward the bright or ON state but still

require an electrical bias to tilt toward the OFF state.

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Off-State

Light Path

0

1

2

3

Active Micromirror Array

M x N Micromirrors

N x P

Nœ 4

Nœ 3

Nœ 2

Nœ 1

M x P

P

Incident

Illumination

Light Path

P

Pond Of Micromirrors (POM) omitted for clarity.

Details omitted for clarity. Not to scale.

P

图6-8. Micromirror Array Physical Characteristics

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6.11 Micromirror Array Optical Characteristics

表6-3. Micromirror Array Optical Characteristics

PARAMETER

MIN

NOM

17.0

MAX

18.4

UNIT

Mirror Tilt angle, variation device to device^{(1) (2)}

15.6

degrees

Adjacent micromirrors

0

10

68

Number of out-of-specification micromirrors ⁽³⁾

micromirrors

%

Non-Adjacent

micromirrors

DMD Efficiency (420 nm–680 nm)

(1) Limits on variability of micromirror tilt angle are critical in the design of the accompanying optical system. Variations in tilt angle within a

device may result in apparent non-uniformities, such as line pairing and image mottling, across the projected image. Variations in the

average tilt angle between devices may result in colorimetric and system contrast variations.

(2) See Micromirror Landed Orientation and Tilt.

(3) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the

specified micromirror switching time.

Border micromirrors omitted for clarity

Off State

Light Path

Details omitted for clarity.

Not to scale.

0

1

2

3

Tilted Axis of

Pixel Rotation

Off-State

Landed Edge

On-State

Landed Edge

Nœ 4

Nœ 3

Nœ 2

Nœ 1

Incident

Illumination

Light Path

A. Pond of Mirrors (POM) omitted for clarity

B. Refer to Micromirror Array Physical Characteristics table for M, N, and P specifications.

图6-9. Micromirror Landed Orientation and Tilt

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6.12 Window Characteristics

表6-4. DMD Window Characteristics

DESCRIPTION

MIN

NOM

Corning

Eagle XG

Window Material Designation

Window Refractive Index at 546.1 nm

1.5119

Window Transmittance, minimum within the wavelength range 420–680 nm. Applies to all angles 0–30°

97%

AOI. ^{(1) (2)}

Window Transmittance, average over the wavelength range 420–680 nm. Applies to all angles 30–45° AOI.

(1) (2)

(1) Single-pass through both surfaces and glass.

(2) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.

6.13 Chipset Component Usage Specification

Reliable function and operation of the DLP480RE DMD requires that it be used in conjunction with the other

components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology is the TI technology and devices for operating or controlling a

DLP DMD.

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7 Detailed Description

7.1 Overview

The DMD is a 0.48-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum

micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system

(MOEMS). The electrical interface is Low Voltage Differential Signaling (LVDS). The DMD consists of a two-

dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N

memory cell rows. Refer to the Function Block Diagram. The positive or negative deflection angle of the

micromirrors can be individually controlled by changing the address voltage of underlying CMOS addressing

circuitry and micromirror reset signals (MBRST).

The DLP480RE DMD is part of the chipset comprising the DLP480RE DMD, the DLPC4430 display controller

and the DLPA100 power and motor driver. To ensure reliable operation, the DLP480RE DMD must always be

used with the DLPC4430 display controller and the DLPA100 power and motor driver.

7.2 Functional Block Diagram

Channel C Interface

Column Read and Write

Control

(0,0)

Voltages

Word Lines

Voltage

Generators

Micromirror Array

Row

(M-1, N-1)

Column Read and Write

Channel D Interface

Control

For pin details on Channels C, and D, refer to Pin Functions and the LVDS Interface section of 节6.8. RESET_CTRL is used in

applications when an external reset signal is required.

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7.3 Feature Description

7.3.1 Power Interface

The DMD requires 5 DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V

is created by the DLPA100 power and motor driver and is used on the DMD board to create the other 4 DMD

voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators). DMD_P1P8V is

created by the TI PMIC LP38513S and provides the VCC voltage required by the DMD. VOFFSET (10V),

VRESET (-14V), and VBIAS(18V) are made by the TI PMIC TPS65145 and are supplied to the DMD to control

the micromirrors.

7.3.2 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-4 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers use IBIS or other

simulation tools to correlate the timing reference load to a system environment. The load capacitance value

stated is only for characterization and measurement of AC timing signals. This load capacitance value does not

indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC4430 display controller. See the DLPC4430 Display Controller

Data Sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

needs to be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate

apertures are added in the illumination and projection pupils to block out flat-state and stray light from the

projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle, objectionable artifacts may occur in the display border or active

area.

7.5.1.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display border and active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.1.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical

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system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the

average flux level in the active area. Depending on the particular system optical architecture, overfill light may

have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Array

TP2

2X 11.75

TP5

TP4

TP3

2X 16.10

Window Edge

(4 surfaces)

TP3 (TP2)

TP5

TP4

TP1

5.05

16.10

TP1

图7-1. DMD Thermal Test Points

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Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship

between micromirror array temperature and the reference ceramic temperature is provided by the following

equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY-TO-CERAMIC}

)

Q_ARRAY= Q_ELECTRICAL+ (Q_ILLUMINATION

)

where

• T_ARRAY= computed array temperature (°C)

• T_CERAMIC= measured ceramic temperature (°C) (TP1 location)

• R_{ARRAY-TO-CERAMIC}= thermal resistance of package from array to ceramic TP1 (°C/Watt)

• Q_ARRAY= Total DMD power on the array (Watts) (electrical + absorbed)

• Q_ELECTRICAL= nominal electrical power

• Q_ILLUMINATION= (C_L2W× SL)

• C_L2W= Conversion constant for screen lumens to power on DMD (Watts/Lumen)

• SL = measured screen lumens

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.9 Watts. The

absorbed power from the illumination source is variable and depends on the operating state of the micromirrors

and the intensity of the light source. The equations shown above are valid for a 1-Chip DMD system with

projection efficiency from the DMD to the screen of 87%.

The conversion constant CL2W is based on array characteristics. It assumes a spectral efficiency of 300 lumens/

Watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array

border.

Sample calculations for typical projection application:

Q_ELECTRICAL= 0.9 W

C_L2W= 0.00266

SL = 4000 lm

T_CERAMIC= 55.0°C

Q_ARRAY= 0.9 W + (0.00266 × 4000 lm) = 11.54 W

T_ARRAY= 55.0°C + (11.54 W × 0.90°C/W) = 65.39°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the

time (and in the Off state 0% of the time); whereas 0/100 indicate that the pixel is in the OFF state 100% of the

time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

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7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD usable life.

Note that it is the symmetry or asymmetry of the landed duty cycle that is of relevance. The symmetry of the

landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a

landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect DMD usable life, and this interaction can

be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD usable life. This is

quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD operates at for a given

long-term average Landed Duty Cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

operates under a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel operates under a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

Use 方程式1 to calculate the landed duty cycle of a given pixel during a given time period

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (1)

×

Blue_Scale_Value)

where

• Red_Cycle_%, represents the percentage of the frame time that red s displayed to achieve the desired white

point

• Green_Cycle_% represents the percentage of the frame time that green s displayed to achieve the desired

white point

• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired

white point

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

blue color intensities are as shown in 表7-2 and 表7-3.

表7-2. Example Landed Duty Cycle for Full-Color,

Color Percentage

CYCLE PERCENTAGE

RED

GREEN

BLUE

50%

20%

30%

表7-3. Example Landed Duty Cycle for Full-Color

SCALE VALUE

GREEN

0%

LANDED DUTY

CYCLE

RED

0%

BLUE

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

60%

100%

12%

100%

0%

100%

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

Texas Instruments DLP^®technology is a micro-electro-mechanical systems (MEMS) technology that modulates

light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light

from an illumination source to one of two directions, towards the projection optics or collection optics. The new

TRP pixel with a higher tilt angle increases brightness performance and enables smaller system electronics for

size constrained applications. Typical applications using the DLP480RE include business, education, and large

venue projectors, interactive displays, and portable smart displays.

The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology,

called TRP. With a smaller pixel pitch of 5.4 μm and increased tilt angle of 17 degrees, TRP chipsets enable

higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical

efficiency. DLP^®chipsets are a great fit for any system that requires high resolution and high brightness displays.

The following orderables have been replaced by the DLP480RE.

Device Information

PART NUMBER

DLP480RETA

PACKAGE

BODY SIZE (NOM)

Mechanical ICD

FXG (257)

32 mm × 22 mm

2516206

1912-5132B

1912-5137B

1912-543AB

32 mm × 22 mm

8.2 Typical Application

The DLP480RE DMD combined with a DLPC4430 digital controller and DLPA100 power management device

provides full HD resolution for bright, colorful display applications. 图 8-1 shows a typical display system using

the DLP480RE, as well as additional system components.

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12V

1.21V

1.8V

3.3V

5V

1.21V

1.8V

3.3V

5V

DLPA100

Controller

PMIC

DLPA100

Controller

PMIC

Flash

(23) (16)

CW Driver

ADDR

DATA

Wheel Motor #2

CTRL

Wheel Motor #1

CTRL

CW_INDEX1

FE CTRL

DATA

3D L/R

CTRL

2xLVDS

SCP CTRL

DLPC4430

Controller

Front End Device

DLP DMD

1.8 V

USB CTRL

GPIO

1.15V

1.8V

3.3V

V_BIAS

V_OFFSET

V_RESET

CTRL

3.3V

DMD PMIC

(Power Management IC)

(3)

I²C

EEPROM

TI DLP chipset

Third party component

图8-1. Typical DLPC4430 Application (LED, Top; LPCW, Bottom)

8.2.1 Design Requirements

A DLP480RE projection system is created by using the DMD chipset, including the DLP480RE, DLPC4430, and

DLPA100. The DLP480RE is used as the core imaging device in the display system and contains a 0.48-inch

array of micromirrors. The DLPC4430 controller is the digital interface between the DMD and the rest of the

system, taking digital input from front end receiver and driving the DMD over a high speed interface. The

DLPA100 power management device provides voltage regulators for the DMD, controller, and illumination

functionality.

Other core components of the display system include an illumination source, an optical engine for the

illumination and projection optics, other electrical and mechanical components, and software. The illumination

source options include lamp, LED, laser or laser phosphor. The type of illumination used and desired brightness

will have a major effect on the overall system design and size.

8.2.2 Detailed Design Procedure

For connecting the DLPC4430 display controller and the DLP480RE DMD, see the reference design schematic.

For a complete the DLP^®system, an optical module or light engine is required that contains the DLP480RE

DMD, associated illumination sources, optical elements, and necessary mechanical components.

To ensure reliable operation, the DLP480RE DMD must always be used with the DLPC4430 display controllers

and a DLPA100 PMIC driver. Refer to PCB Design Requirements for DLP^®Standard TRP Digital Micromirror

Devices for the DMD board design and manufacturing handling of the DMD sub assemblies.

8.2.3 Application Curve

When LED illumination is utilized, typical LED-current-to-Luminance relationship is shown in 图8-2.

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图8-2. Luminance vs. Current

8.3 DMD Die Temperature Sensing

The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the

micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in 图8-3.

The serial bus from the TMP411 can be connected to the display controller to enable its temperature sensing

features. See the DLPC4430 Programmers’ Guide for instructions on installing the controller support firmware

bundle and obtaining the temperature readings.

The software application contains functions to configure the TMP411 to read the DMD temperature sensor diode.

This data can be leveraged to incorporate additional functionality in the overall system design such as adjusting

illumination, fan speeds, and so forth. All communication between the TMP411 and the DLPC4430 controller will

be completed using the I²C interface. The TMP411 connects to the DMD via pins B17 and B18 as outlined in 节

5.

3.3V

R1

R2

TMP411

DLP480RE

SCL

VCC

D+

R3

R5

TEMP_P

SDA

ALERT

THERM

GND

C1

R4

R6

D-

TEMP_N

GND

A. Details omitted for clarity, see the TI Reference Design for connections to the DLPC4430 controller.

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B. See the TMP411 datasheet for system board layout recommendation.

C. See the TMP411 datasheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.

D. R5 = 0 Ω. R6 = 0 Ω. Zero ohm resistors need be located close to the DMD package pins.

图8-3. TMP411 Sample Schematic

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• VSS

• VBIAS

• VCC

• VOFFSET

• VRESET

DMD power-up and power-down sequencing is strictly controlled by the DLP^®display controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See 图9-1 DMD Power Supply Sequencing Requirements.

VBIAS, VCC, VOFFSET, and VRESET power supplies must be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements will result in a significant

reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, VCC must always start and settle before VOFFSET plus Delay1 specified in 表9-1, VBIAS,

and VRESET voltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be

within the specified limit shown in 节6.4.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-up, LVCMOS input pins must not be driven high until after VCC have settled at operating

voltages listed in 节6.4.

9.2 DMD Power Supply Power-Down Procedure

• During power-down, VCC must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to

within the specified limit of ground. See 表9-1.

• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must

be within the specified limit shown in 节6.4.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in 节6.1, in 节6.4, and in 图9-1.

• During power-down, LVCMOS input pins must be less than specified in 节6.4.

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Not to scale. Details omitted for clarity

Note 1

VCC

VSS

Note 2

ûV < Specification

VOFFSET

Note 4

Delay 1

VBIAS

VSS

Note 3

ûV < Specification

VRESET

EN_OFFSET

VSS

Note 9

Delay 2

Note 5

PG_OFFSET

Note 7

VSS

RESET_OEZ

VSS

Note 6

Note 8

PWRDNZ

and RESETZ

VSS

A. See 节6.4, and Pin Functions .

B. To prevent excess current, the supply voltage difference |VOFFSET –VBIAS| must be less than specified limit in 节6.4.

C. To prevent excess current, the supply voltage difference |VBIAS –VRESET| must be less than specified limit in 节6.4.

D. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in 表9-1

E. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in 表9-1.

F. DLP^®controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.

G. DLP^®controller software initiates the global VBIAS command.

H. After the DMD micromirror park sequence is complete, the DLP^®controller software initiates a hardware power-down that activates

PWRDNZ and disables VBIAS, VRESET and VOFFSET.

I.

Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP^®controller hardware,

EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to PG_OFFSET turning off to indicate the

DMD micromirror has completed the emergency park procedures.

图9-1. DMD Power Supply Requirements

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表9-1. DMD Power-Supply Requirements

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

ms

Delay from VOFFSET settled at recommended operating voltage to

VBIAS and VRESET power up

Delay1

Delay2

1

2

PG_OFFSET hold time after EN_OFFSET goes low

100

ns

10 Layout

10.1 Layout Guidelines

The DLP480RE DMD is part of a chipset that is controlled by the DLPC4430 display controller in conjunction

with the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the

DLP480RE DMD. The DLP480RE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital

logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The remaining traces are comprised of

low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and

VBIAS. Solid planes are required for DMD_P3P3V(3.3V), DMD_P1P8V and Ground. The target impedance for

the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10% differential. TI recommends using an 8 layer

stack-up as described in 表10-1.

10.2 Layout Example

10.2.1 Layers

The layer stack-up and copper weight for each layer is shown in 表10-1. Small sub-planes are allowed on signal

routing layers to connect components to major sub-planes on top or bottom layers if necessary.

表10-1. Layer Stack-Up

LAYER

NO.

LAYER NAME

Side A - DMD only

COPPER WT. (oz.)

COMMENTS

1

1.5

1

DMD, escapes, low frequency signals, power sub-planes.

Solid ground plane (net GND).

2

Ground

3

Signal

0.5

1

50 Ωand 100 Ωdifferential signals

4

Ground

Solid ground plane (net GND)

5

DMD_P3P3V

1

+3.3-V power plane (net DMD_P3P3V)

50 Ωand 100 Ωdifferential signals

6

Signal

0.5

1

7

Ground

Solid ground plane (net GND).

8

Side B - All other Components

1.5

Discrete components, low frequency signals, power sub-planes

10.2.2 Impedance Requirements

TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed

in 表10-2.

表10-2. Special Impedance Requirements

Signal Type

Signal Name

Impedance (ohms)

DDCP(0:15), DDCN(0:15)

DCLKC_P, DCLKC_N

SCTRL_CP, SCTRL_CN

DDDP(0:15), DDDN(0:15)

DCLKD_P, DCLKD_N

SCTRL_DP, SCTRL_DN

100 ±10% differential across

each pair

C channel LVDS differential pairs

100 ±10% differential across

each pair

D channel LVDS differential pairs

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10.2.3 Trace Width, Spacing

Unless otherwise specified, TI recommends that all signals follow the 0.005-inch/0.005-inch design rule.

Minimum trace clearance from the ground ring around the PWB has a 0.1-inch minimum. An analysis of

impedance and stack-up requirements determine the actual trace widths and clearances.

10.2.3.1 Voltage Signals

表10-3. Special Trace Widths, Spacing Requirements

MINIMUM TRACE WIDTH TO

SIGNAL NAME

GND

LAYOUT REQUIREMENT

Maximize trace width to connecting pin

PINS (MIL)

15

DMD_P3P3V

DMD_P1P8V

VOFFSET

VRESET

Maximize trace width to connecting pin

Create mini plane from U2 to U3

VBIAS

All U3 control

connections

10

Use 10 mil etch to connect all signals/voltages to DMD pads

11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Device Support

11.2.1 Device Nomenclature

DLP480RE AA FXG

Package

TI Internal Numbering

Device Descriptor

图11-1. Part Number Description

11.2.2 Device Markings

The device marking includes both human-readable information and a 2-dimensional matrix code. The human-

readable information is described in 图11-2. The 2-dimensional matrix code is an alpha-numeric character string

that contains the DMD part number, part 1 of serial number, and part 2 of serial number. The first character of the

DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number (part 1)

is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin letter.

Example: *1912-513AB GHXXXXX LLLLLLM

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2-Dimension Matrix Code

(Part Number and Serial Number)

DMD Part Number

*1912-513xB

GHXXXXX LLLLLLM

Part 1 of Serial Number

(7 characters)

Part 2 of Serial Number

(7 characters)

图11-2. DMD Marking Locations

11.3 Documentation Support

11.3.1 Related Documentation

The following documents contain additional information related to the chipset components used with the

DLP480RE.

• DLPC4430 Display Controller Data Sheet

• DLPA100 Power and Motor Driver Data Sheet

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

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型号：	DLP480REAAFXG
厂家：	TEXAS INSTRUMENTS
描述：	0.48-inch, WUXGA DLP® digital micromirror device (DMD) \| FXG \| 257 \| 0 to 70
文件：	总44页 (文件大小：1626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP480REAAFXG [TI]

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