DLP550JE_技术文档

DLP550JE

ZHCSN33B –NOVEMBER 2017 –REVISED FEBRUARY 2023

DLP550JE 0.55 XGA 数字微镜器件

1 特性

3 说明

• 0.55 英寸微镜阵列对角线

TI DLP550JE 数字微镜器件 (DMD) 是一款数控微机电

系统 (MEMS) 空间照明调制器 (SLM)，能够实现明

亮、经济实惠的 DLP^®0.55 XGA 显示解决方案。

DLP550JE DMD 通过与 DLPC4430 显示控制器、

DLPA100 电源和电机驱动器及 DLPA200 DMD 微镜驱

动器配合使用，可提供实现高性能系统的能力，是需要

4:3 纵横比、高亮度和系统简单性的显示应用的理想之

选。

– XGA (1024 × 768)

– 10.8 微米微镜间距

– ±12° 微镜倾斜角

（相对于平面状态）

– 角落照明

• 2xLVDS 输入数据总线

• DLP550JE 芯片组包括：

器件信息

封装⁽¹⁾

– DLP470TE DMD

– DLPC4430 控制器

– DLPA100 控制器电源管理和电机驱动器IC

– DLPA200

封装尺寸（标称值）

器件型号

DLP550JE

FYA (149)

32.20 mm × 22.30 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 数字标牌

• 教育投影仪

• 企业投影仪

DLP550JE 简化应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS101

DLP550JE

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ZHCSN33B –NOVEMBER 2017 –REVISED FEBRUARY 2023

Table of Contents

7.2 Feature Description...................................................19

7.3 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 Storage Conditions..................................................... 6

6.3 ESD Ratings............................................................... 7

6.4 Recommended Operating Conditions.........................7

6.5 Thermal Information....................................................9

6.6 Electrical Characteristics...........................................10

6.7 Timing Requirements................................................10

6.8 Window Characteristics............................................ 14

6.9 System Mounting Interface Loads............................ 14

6.10 Micromirror Array Physical Characteristics.............15

6.11 Micromirror Array Optical Characteristics............... 17

6.12 Chipset Component Usage Specification............... 17

7 Detailed Description......................................................18

7.1 Overview...................................................................18

Considerations............................................................ 19

7.4 Micromirror Array Temperature Calculation.............. 20

7.5 Micromirror Landed-on/Landed-Off Duty Cycle........ 21

8 Application and Implementation..................................24

8.1 Application Information............................................. 24

8.2 Typical Application.................................................... 24

9 Power Supply Recommendations................................27

9.1 DMD Power-Up and Power-Down Procedures.........27

10 Device and Documentation Support..........................28

10.1 Device Support....................................................... 28

10.2 支持资源..................................................................28

10.3 接收文档更新通知................................................... 29

10.4 Trademarks.............................................................29

10.5 静电放电警告.......................................................... 29

10.6 术语表..................................................................... 29

11 Mechanical, Packaging, and Orderable

Information.................................................................... 29

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (September 2022) to Revision B (February 2023)

Page

• 将控制器更新为DLPC4430，所有芯片组元件均为有效链接..............................................................................1

• 将控制器更新为DLPC4430，将DMD 链接到文档.............................................................................................1

• Updated this section......................................................................................................................................... 24

• Updated controller to DLPC4430, updated the application diagram.................................................................24

• Updated controller to DLPC4430......................................................................................................................25

• Updated controller to DLPC4430......................................................................................................................27

Changes from Revision * (November 2017) to Revision A (September 2022)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将文档状态从：“预告信息”更改为：量产数据................................................................................................ 1

• 更新了措辞，将“MOEMS”替换为“MEMS”.................................................................................................1

• Updated wording in "Input Voltages" in 节6.1 ...................................................................................................6

2

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5 Pin Configuration and Functions

1

3

5

7

9

11 13 15 17 19

12 14 16 18 20

2

4

6

8

10

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

图5-1. FYA Package 149-Pin Bottom View

表5-1. Pin Functions

PIN⁽¹⁾

NAME

TYPE

(I/O/P )

DATA

INTERNAL

TERM⁽³⁾

TRACE

(mils)⁽⁴⁾

SIGNAL

CLOCK

DESCRIPTION

RATE⁽²⁾

NO.

DATA INPUTS

D_AN1

G20

H20

H19

G19

F18

G18

E18

D18

C20

D20

B18

A18

A20

B20

B19

A19

Input

LVCMOS

DDR

Differential

DCLK_A

760.78

760.86

760.73

760.76

760.73

760.81

760.77

760.81

760.67

760.74

760.68

760.77

760.82

760.77

760.79

760.75

D_AP1

D_AN3

D_AP3

D_AN5

D_AP5

D_AN7

D_AP7

Input data bus A (LVDS)

D_AN9

D_AP9

D_AN11

D_AP11

D_AN13

D_AP13

D_AN15

D_AP15

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表5-1. Pin Functions (continued)

PIN⁽¹⁾

NAME

TYPE

(I/O/P )

DATA

INTERNAL

TERM⁽³⁾

TRACE

(mils)⁽⁴⁾

SIGNAL

CLOCK

DESCRIPTION

RATE⁽²⁾

NO.

K20

J20

D_BN1

D_BP1

Input

LVCMOS

DDR

—

Differential

DCLK_B

—

760.72

760.80

760.79

760.82

760.77

760.85

760.78

760.81

760.76

760.83

760.78

760.80

760.78

760.72

760.80

760.77

760.73

760.80

760.72

760.80

D_BN3

J19

D_BP3

K19

L18

K18

M18

N18

P20

N20

R18

T18

T20

R20

R19

T19

D19

E19

N19

M19

D_BN5

D_BP5

D_BN7

D_BP7

Input data bus B (LVDS)

D_BN9

D_BP9

D_BN11

D_BP11

D_BN13

D_BP13

D_BN15

D_BP15

DCLK_AN

DCLK_AP

DCLK_BN

DCLK_BP

Input data bus A Clock

(LVDS)

—

Input data bus B Clock

(LVDS)

—

DATA CONTROL INPUTS

SCTRL_AN

SCTRL_AP

SCTRL_BN

SCTRL_BP

F20

Input

LVCMOS

DDR

Differential

DCLK_A

DCLK_B

760.74

760.70

760.83

760.78

E20

L20

M20

Data Control (LVDS)

SERIAL COMMUNICATION (SCP) AND CONFIGURATION

SCP_CLK

SCP_DO

SCP_DI

A8

A9

A5

B7

B9

Input

Output

Input

LVCMOS

Pulldown

—

SCP_CLK

—

Pulldown

SCP_EN

PWRDN

Input

—

MICROMIRROR BIAS CLOCKING PULSE

MODE_A

MBRST0

MBRST1

MBRST2

MBRST3

MBRST4

MBRST5

MBRST6

MBRST7

MBRST8

MBRST9

MBRST10

MBRST11

MBRST12

MBRST13

MBRST14

MBRST15

A4

C3

D2

D3

E2

G3

E1

G2

G1

N3

M2

M3

L2

Input

LVCMOS

Analog

Pulldown

—

Micromirror Bias

Clocking Pulse

—

"MBRST" signals "clock"

micromirrors into state of

LVCMOS memory cell

associated with each

mirror.

—

J3

—

L1

—

J2

—

J1

—

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表5-1. Pin Functions (continued)

PIN⁽¹⁾

NAME

POWER

TYPE

(I/O/P )

DATA

INTERNAL

TERM⁽³⁾

TRACE

(mils)⁽⁴⁾

SIGNAL

CLOCK

DESCRIPTION

RATE⁽²⁾

NO.

B11, B12,

B13, B16,

R12, R13,

R16, R17

Power for LVCMOS

Logic

V_CC

Power

Analog

—

A12, A14,

A16, T12,

T14, T16

Power supply for LVDS

Interface

V_CCI

Power

Analog

—

C1, D1,

M1, N1

Power for High Voltage

CMOS Logic

V_OFFSET

A6, A11,

A13, A15,

A17, B4,

B5, B8,

B14, B15,

B17, C2,

C18, C19,

F1, F2,

F19, H1,

H2, H3,

Common return for all

power inputs

V_SS

Power

Analog

—

H18, J18,

K1, K2,

L19, N2,

P18, P19,

R4, R9,

R14, R15,

T7, T13,

T15, T17

RESERVED SIGNALS (Not for use in system)

RESERVED_FC

RESERVED_FD

RESERVED_PFE

RESERVED_STM

R7

R8

T8

B6

Input

LVCMOS

Pulldown

—

Pins should be

connected to V_SS

.

A3, A7,

A10, B2,

B3, B10,

E3, F3,

K3, L3,

P1, P2,

P3, R1,

R2, R3,

R5, R6,

R10, R11,

T1, T2,

T3, T4,

T5, T6,

T9, T10,

T11

NO_CONNECT

Do not connect.

—

(1) The following power supplies are required to operate the DMD: V_CC, V_CCI, V_OFFSET. V_SSmust also be connected.

(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Timing Requirements for specifications and relationships.

(3) Refer to Electrical Characteristics for differential termination specification.

(4) Internal Trace Length (mils) refers to the Package electrical trace length. See the DLP 0.55 XGA Chip-Set Data Manual for details

regarding signal integrity considerations for end-equipment designs.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).⁽⁷⁾

MIN

MAX

UNIT

SUPPLY VOLTAGES

V_CC

Supply voltage for LVCMOS core logic⁽¹⁾

Supply voltage for LVDS Interface⁽¹⁾

Micromirror Electrode and HVCMOS voltage^{(1) (2)}

Voltage applied to MBRST[0:15] Input Pins

Supply voltage change⁽³⁾

4

V

–0.5

–28

V_CCI

V_OFFSET

V_MBRST

|V_CC–V_CCI

9

28

0.3

|

INPUT VOLTAGES

Input voltage for all other input pins⁽¹⁾

V_CC+ 0.3

700

V

–0.5

|V_ID

|

Input differential voltage (absolute value) ⁽⁴⁾

mV

CLOCKS

Clock frequency for LVDS interface, DCLK_A

Clock frequency for LVDS interface, DCLK_B

400

MHz

ƒ_clock

ENVIRONMENTAL

T_ARRAYand T_WINDOW

Temperature, operating⁽⁵⁾

0

90

30

°C

Temperature, non-operating ⁽⁵⁾

–40

|T_DELTA

T_DP

|

Absolute Temperature delta between any point on the window

edge and the ceramic test point TP1⁽⁶⁾

Dew Point Temperature, operating and non-operating (non-

condensing)

81

°C

(1) All voltages are referenced to common ground V_SS. Voltages V_CC, V_CCI, and V_OFFSETare required for proper DMD operation. V_SSmust

also be connected.

(2) V_OFFSETsupply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_CCand V_CCImay result in excess current draw.

(4) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(5) The highest temperature of the active array (as calculated by the 节7.4) or of any point along the Window Edge as defined in 图7-1.

The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature.

If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(6) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst-case delta. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(7) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节6.4. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operational in a system.

MIN

MAX

80

UNIT

°C

T_DMD

DMD storage temperature

–40

T_DP-AVGAverage dew point temperature (non-condensing)⁽¹⁾

28

°C

T_DP-ELRElevated dew point temperature range (non-condensing)⁽²⁾

28

36

°C

CT_ELR

Cumulative time in elevated dew point temperature range

24

Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

.

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6.3 ESD Ratings

VALUE

±2000

<250

UNIT

All pins except MBRST(15:0)

Pins MBRST(15:0)

Electrostatic

V_(ESD)

Human-body model (HBM), per ANSI/

ESDA/JEDEC JS-001⁽¹⁾

V

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN NOM

MAX UNIT

VOLTAGE SUPPLY

V_CC

Supply voltage for LVCMOS core logic⁽¹⁾

Supply voltage for LVDS receivers⁽¹⁾

Mirror Electrode and HVCMOS voltage^{(1) (2)}

Micromirror clocking pulse voltages⁽¹⁾

Supply voltage delta (absolute value)⁽³⁾

3.0

3.3

8.5

3.6

V

V_CCI

V_OFFSET

V_MBRST

|V_CCI–V_CC

8.25

–27

8.75

26.5

0.3

|

LVCMOS INTERFACE

V_IH

High level input voltage

1.7

2.5

VCC + 0.3

0.7

V

V_IL

Low level input voltage

–0.3

I_OH

High level output current at V_OH= 2.4 V

Low level output current at V_OL= 0.4 V

PWRDNZ pulse width⁽⁴⁾

mA

ns

–20

I_OL

15

t_PWRDNZ

10

SCP INTERFACE

f_SCPCLK

SCP clock frequency⁽⁵⁾

50

0

500

900

kHz

ns

Propagation delay, clock to Q, from rising-edge of SCPCLK to valid

SCPDO⁽⁶⁾

t_{SCP_PD}

t_{SCP_DS}

t_{SCP_DH}

SCPDI clock setup time (before SCPCLK falling-edge)⁽⁶⁾

SCPDI hold time (after SCPCLK falling-edge)⁽⁶⁾

800

900

ns

Time between falling-edge of SCPENZ and the first rising-edge of

SCPCLK

t_{SCP_NEG_ENZ}

1

us

t_{SCP_POS_ENZ}

t_{SCP_PW_ENZ}

t_{r_SCP}

Time between falling-edge of SCPCLK and the rising-edge of SCPENZ

SCPENZ inactive pulse width (high level)

Rise time for SCP signals

1

us

1/f_SCPCLK

ns

200

t_fP

Fall time for SCP signals

ns

LVDS INTERFACE

f_CLOCK

Clock frequency for LVDS interface (all channels), DCLK⁽⁷⁾

Input differential voltage (absolute difference)⁽⁸⁾

Common mode voltage⁽⁸⁾

320

400

330

600

MHz

mV

ps

|V_ID

|

100

V_CM

1200

V_LVDS

LVDS voltage⁽⁸⁾

0

100

2000

400

10

t_r

Rise time (20% to 80%)

t_r

Fall time (80% to 20%)

ps

t_{LVDS_RSTZ}

Z_IN

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

ns

95

105

Ω

ENVIRONMENTAL

Array temperature, long-term operational^{(9) (10) (11)}

Array temperature, short-term operational^{(10) (13)}

10

0

40 to 70⁽¹²⁾

10

°C

T_ARRAY

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN NOM

MAX UNIT

Window temperature –operational⁽¹⁴⁾

T_WINDOW

T_{|DELTA |}

85

26

°C

Absolute temperature delta between any point on the window edge and

the ceramic test point TP1⁽¹⁵⁾

T_DP-AVG

T_DP-ELR

CT_ELR

ILL_UV

Average dew point temperature (non-condensing)⁽¹⁶⁾

Elevated dew point temperature range (non-condensing)⁽¹⁷⁾

Cumulative time in elevated dew point temperature range

Illumination wavelengths < 395 nm⁽⁹⁾

28

36

°C

28

24 Months

2.00 mW/cm²

mW/cm²

0.68

ILL_VIS

ILL_IR

Illumination wavelengths between 395 nm and 800 nm

Illumination wavelengths > 800 nm

Thermally limited

10 mW/cm²

(1) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESETpower supplies are all required for proper DMD

operation. V_SSmust also be connected.

(2) V_OFFSETsupply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |V_CCI–V_CC| must be less than specified limit. See 节9.

(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the

SCPDO output pin.

(5) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(6) See 图6-2.

(7) See LVDS Timing Requirements in 节6.7 and 图6-5.

(8) Refer to 图6-7, 图6-8, and 图6-9.

(9) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination reduces device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the package 节6.5 using the calculation in 节7.4 .

(11) Long-term is defined as the average over the usable life.

(12) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. See 节7.5 for a definition of micromirror landed duty cycle.

(13) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (for example, power-up).

Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.

(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in 图7-1 are intended to measure the highest window edge temperature.

For most applications, the locations shown are representative of the highest window edge temperature. If a particular application

causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst-case delta temperature. If a

particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(16) The average over time (including storage and operating) that the device is not in the "elevated dew point temperature range."

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

.

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80

70

60

50

40

30

0/100

100/0

5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

65/35

95/5

90/10

85/15

80/20

75/25

70/30

60/40

55/45

50/50

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended DMD Temperature—Derating Curve

6.5 Thermal Information

DLP550JE

THERMAL METRIC

FYA PACKAGE

149 PINS

0.60

UNIT

Thermal resistance, active array to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the 节6.4.

The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include

light energy absorbed by the window aperture and electrical power dissipation of the array.

Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal

load in this area can significantly degrade the reliability of the device.

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6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

V_CC= 3.0 V, I_OH= –20 mA

V_CC= 3.6 V, I_OL= 15 mA

V_CC= 3.6 V

MIN

TYP

MAX

UNIT

V

V_OH

V_OL

I_OZ

High-level output voltage

Low-level output voltage

High impedance output current

Low-level input current

High-level input current⁽¹⁾

Current into V_CCpin

2.4

0.4

10

V

µA

mA

Ω

I_IL

V_CC= 3.6 V, V_I= 0 V

V_CC= 3.6 V, V_I= V_CC

V_CC= 3.6 V

–60

200

531

374

25

I_IH

I_CC

I_CCI

I_OFFSET

Z_IN

Current into V_CC1pin⁽²⁾

Current into V_OFFSETpin⁽³⁾

Internal Differential Impedance

V_CCI= 3.6 V

V_OFFSET= 8.75 V

95

90

105

Line Differential Impedance (PWB or

Trace)

Z_LINE

100

110

Ω

C_I

Input capacitance⁽¹⁾

Output capacitance⁽¹⁾

f = 1 MHz

10

pF

C_O

C_IM

Input capacitance for MBRST[0:15] pins f = 1 MHz

160

210

(1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins

(2) To prevent excess current, the supply voltage change |V_CCI–V_CC| must be less than specified limits listed in the 节6.4.

(3) To prevent excess current, the supply voltage delta |V_BIAS–V_OFFSET| must be less than the specified limit in 节6.4.

6.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted).

MIN

NOM

MAX

UNIT

LVDS ⁽¹⁾

t_c

Clock Cycle for DLCK_A

3.03

1.36

0.35

–1.51

ns

t_c

Clock Cycle for DCLKC_B

t_w

Pulse Duration DCLK_A

1.52

t_w

Pulse Duration for DCLK_B

t_SU

t_H

Setup Time, D_A[0:15] before DCLK_A

Setup Time, D_B[0:15] before DCLK_B

Setup Time, SCTRL_A before DCLK_A

Setup Time, SCTRL_B before DCLK_B

Hold Time, D_A[0:15] after DCLK_A

Hold Time, D_B[0:15] after DCLK_B

Hold Time, SCTRL_A after DCLK_A

Hold Time, SCTRL_B after DCLK_B

Channel B relative to Channel A^{(2) (3)}

t_H

t_skew

1.51

(1) See 图6-5 for timing requirements for LVDS.

(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and

D_AP(15:0).

(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and

D_BP(15:0).

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SCPCLK falling–edge capture for SCPDI.

SCPCLK rising–edge launch for SCPDO.

t_{SCP_NEG_ENZ}

t_{SCP_POS_ENZ}

50%

SCPENZ

t_{SCP_DS}

t_{SCP_DH}

50%

DI

SCPDI

t_C

f_SCPCLK= 1 / t_C

50%

SCPCLK

t_{SCP_PD}

50%

DO

SCPDO

图6-2. SCP Timing Parameters

LVDS Interface

SCP Interface

1.0 * VCC

1.0 * V

ID

V

CM

0.0 * VCC

0.0 * V

ID

t_r

t_f

t_r

t_f

Not to scale

Refer to 节6.7.

Refer to 节5 for list of LVDS pins and SCP pins.

图6-3. Rise Time and Fall Time

Device pin

output under test

Tester channel

C_LOAD

图6-4. Test Load Circuit for Output Propagation Measurement

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For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

System design should use IBIS or other simulation tools to correlate the timing reference load to a system

environment. See 图6-4.

图6-5. Timing Requirements

t_{f_SCP}

t_{r_SCP}

Input Controller V_CC

SCP_CLK,

SCP_DI,

SCP_EN

V_CC/2

0 v

图6-6. Serial Communications Bus Waveform Requirements

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Refer to LVDS Interface section of 节6.4.

Refer to 节5 for list of LVDS pins.

图6-7. LVDS Voltage Definitions (References)

V_LVDS(v)

V_LVDSmax= V_CM+ |½V_ID|

V_LVDSmax

T_f(20% - 80%)

V_LVDS= V_CM+/- | 1/2 V_ID

|

V_CM

V_ID

T_r(20% - 80%)

V_{LVDS min}

V_{LVDS min}= 0

Time

Not to scale

Refer to LVDS Interface section of the 节6.4.

图6-8. LVDS Voltage Parameter

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Refer to LVDS Interface section of the 节6.4.

Refer to 节5 for list of LVDS pins.

图6-9. LVDS Equivalent Input Circuit

6.8 Window Characteristics

PARAMETER

MIN

NOM

Corning Eagle

XG

Window material

Window refractive index at wavelength 546.1 nm

1.5119

Window Transmittance, minimum within the wavelength range 420–680 nm. Applies to all angles 0°–30°

97%

AOI.^{(1) (2)}

Window Transmittance, average over the wavelength range 420–680 nm. Applies to all angles 30°–45°

AOI.^{(1) (2)}

(1) Single-pass through both surfaces and glass.

(2) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.

6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

UNIT

Condition 1:

•

Thermal Interface area⁽¹⁾

11.3

kg

Electrical Interface area⁽¹⁾

Condition 2:

•

Thermal Interface area⁽¹⁾

0

kg

Electrical Interface area⁽¹⁾

22.6

(1) Uniformly distributed within the area shown in 图6-10

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Electrical Interface Area

Thermal Interface Area

图6-10. System Interface Loads

6.10 Micromirror Array Physical Characteristics

PARAMETER

Number of active columns⁽¹⁾

VALUE

1024

768

UNIT

M

N

P

micromirrors

Number of active rows⁽¹⁾

Micromirror (pixel) pitch⁽¹⁾

10.8

µm

mm

Micromirror active array width⁽¹⁾

Micromirror active array height ⁽¹⁾

Micromirror active array border⁽²⁾

Micromirror pitch × number of active columns

Pond of Micromirror (POM)

11.059

8.294

10

mm

micromirrors/side

(1) See 图6-11.

(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the

Pond Of Mirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but

still require an electrical bias to tilt toward OFF.

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Refer to the 节6.10 for M, N, and P specifications.

图6-11. Micromirror Array Physical Characteristics

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6.11 Micromirror Array Optical Characteristics

PARAMETER

MIN

NOM

MAX

13

UNIT

Micromirror tilt angle, variation device to device ^{(1) (2) (3) (4)}

11

12

degrees

Adjacent micromirrors

0

Number of out-of-specification micromirrors ⁽⁵⁾

micromirrors

Non-adjacent

micromirrors

10

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Variation can occur between any two individual micromirrors located on the same device or located on different devices.

(3) Additional variation exists between the micromirror array and the package datums. See package drawing.

(4) See 图6-12.

(5) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states.

illumination

Not To Scale

0

1

2

3

On-State

Tilt Direction

Off-State

45°

Tilt Direction

N œ 4

N œ 3

N œ 2

N œ 1

Refer to section 节6.10 table for M, N, and P specifications.

图6-12. Micromirror Landed Orientation and Tilt

6.12 Chipset Component Usage Specification

Reliable function and operation of the DLP550JE DMD requires that it be used in conjunction with the other

components of the applicable DLP chipset, including those components that contain or implement TI DMD

control technology. TI DMD control technology consists of the TI technology and devices used for operating or

controlling a DLP DMD.

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7 Detailed Description

7.1 Overview

The DLP550JE is a 0.55 inch diagonal spatial light modulator which consists of an array of highly reflective

aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in 图6-11.

The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical

interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).

The DLP550JE DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in

a grid of M memory cell columns by N memory cell rows.

The positive or negative deflection angle of the micromirrors can be individually controlled by changing the

address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).

Each cell of the M × N memory array drives its true and complement (‘Q’and ‘QB’) data to two electrodes

underlying one micromirror, one electrode on each side of the diagonal axis of rotation. The micromirrors are

electrically tied to the micromirror reset signals (MBRST) and the micromirror array is divided into reset groups.

Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt

toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or

out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative

(–) tilt angle state corresponds to an 'off' pixel.

Refer to 节 6.11 for the ± tilt angle specifications. Refer to the 节 5 for more information on micromirror clocking

pulse (reset) control.

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7.2 Feature Description

7.2.1 Power Interface

The DMD requires 3 DC voltages: DMD_P3P3V, V_OFFSET, and MBRST. DMD_P3P3V is created by the DLPA100

power and motor driver and the DLPA200 DMD micromirror driver. Both the DLPA100 and DLPA200 create the

main DMD voltages, as well as powering various peripherals (TMP411, I²C, and TI level translators).

DMD_P3P3V provides the V_CCvoltage required by the DMD. V_OFFSET(8.5V) and MBRST are made by the

DLPA200 and are supplied to the DMD to control the micromirrors.

7.2.2 Timing

The data sheet provides timing analysis as measured at the device pin. For output timing analysis, the tester pin

electronics and its transmission line effects must be considered. 图 6-4 shows an equivalent test load circuit for

the output under test. Timing reference loads are not intended as a precise representation of any particular

system environment or depiction of the actual load presented by a production test. TI suggests that system

designers use IBIS or other simulation tools to correlate the timing reference load to a system environment. The

load capacitance value stated is only for characterization and measurement of AC timing signals. This load

capacitance value does not indicate the maximum load the device is capable of driving.

7.3 Optical Interface and System Image Quality Considerations

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

System optical performance and image quality strongly relate to optical system design parameter trade offs.

Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.3.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light

path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt

angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle (and vice versa), contrast degradation, and objectionable artifacts in the display’s

border and/or active area could occur.

7.3.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display’s border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.3.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately

10% of the average flux level in the active area. Depending on the particular system’s optical architecture,

overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.

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7.4 Micromirror Array Temperature Calculation

TP2

Array

2X 12.0

TP5

TP4

2X 16.7

TP3

Window Edge

(4 surfaces)

TP4

TP3 (TP2)

TP1

TP5

4.5

16.1

TP1

图7-1. Thermal Test Point Location

7.4.1 Micromirror Array Temperature Calculation

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from

measurement points on the outside of the package, the package thermal resistance, the electrical power, and

the illumination heat load. The relationship between array temperature and the reference ceramic temperature

(thermal test TP1 in 图7-1) is provided by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

Q_ILLUMINATION= (C_L2W× SL)

)

where

• T_ARRAY= Computed array temperature (°C)

• T_CERAMIC= Measured ceramic temperature (°C), TP1 location in 图7-1

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• R_{ARRAY–TO–CERAMIC}= Thermal resistance of package (specified in 节6.5) from array to ceramic TP1(°C/

Watts).

• Q_ARRAY= Total DMD Power (electrical + absorbed) on array (Watts).

• Q_ELECTRICAL= Nominal electrical power

• C_L2W= Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below

• SL = Measured ANSI screen lumens (lm)

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 1.4 W. The

absorbed optical power from the illumination source is variable and depends on the operating state of the

micromirrors and the intensity of the light source. The equations shown above are valid for a 1-chip DMD system

with total projection efficiency through the projection lens from DMD to the screen of 87%.

The conversion constant C_L2Wis based on the DMD micromirror array characteristics. It assumes a spectral

efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and

16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00274

W/lm.

Sample calculations:

T_CERAMIC= 55°C

SL = 3000 lm

Q_ELECTRICAL= 1.4 W

C_L2W= 0.00274 W/lm

Q_ARRAY= 1.4 W + (0.00274 × 3000) = 9.62 W

T_ARRAY= 55°C + (9.62 W × 0.6 C/W) = 60.8°C

7.5 Micromirror Landed-on/Landed-Off Duty Cycle

7.5.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On–state versus the amount of time the same

micromirror is landed in the Off–state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the

time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of

the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

7.5.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric

landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

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7.5.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the maximum operating DMD Temperature at a given long-term average Landed

Duty Cycle.

7.5.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in 表7-1.

表7-1. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (1)

×

Blue_Scale_Value)

where

• Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,

Green, and Blue are displayed (respectively) to achieve the desired white point.

For example, assume that the red, green, and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

and blue color intensities would be as shown in 表7-2.

表7-2. Example Landed Duty Cycle for Full-Color

Red Cycle Percentage

50%

Green Cycle Percentage

20%

Blue Cycle Percentage

30%

Landed Duty Cycle

Red Scale Value

Green Scale Value

Blue Scale Value

0%

100%

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

0%

60%

100%

12%

100%

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

Texas Instruments DLP technology is a micro-electromechanical system (MEMS) technology that modulates light

using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light from

an illumination source to one of two directions, either towards the projection optics or the collection optics. The

large micromirror array size and ceramic package provides great thermal performance for bright display

applications. Typical applications using the DLP550JE include digital signage, educational projector, and

business projector.

The following orderables have been replaced by the DLP650JE:

Device Information

PART NUMBER

DLP550JET

1076-6434B

1076-6438B

1076-6439B

1076-643AB

PACKAGE

FYA (149)

BODY SIZE (NOM)

32.20 mm × 22.30 mm

MECHANICAL ICD

2512194

8.2 Typical Application

The DLP550JE digital micromirror device (DMD), combined with a DLPC4430 digital controller and a DLPA100

power management or a DLPA200 power management device, provides XGA resolution for bright, colorful

display applications. A typical display system using the DLP550JE and additional system components is shown

in Typical DLPC4430 Application (LED Top, LPCW Bottom).

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12V

1.21V

1.8V

3.3V

5V

1.21V

1.8V

3.3V

5V

DLPA100

Controller

PMIC

DLPA100

Controller

PMIC

Flash

(23) (16)

CW Driver

ADDR

DATA

Wheel Motor #2

CTRL

Wheel Motor #1

CTRL

CW_INDEX1

FE CTRL

DATA

3D L/R

CTRL

2xLVDS

SCP CTRL

DLPC4430

Controller

Front End Device

DLP DMD

1.8 V

USB CTRL

GPIO

1.15V

1.8V

3.3V

V_BIAS

V_OFFSET

V_RESET

CTRL

3.3V

DMD PMIC

(Power Management IC)

(3)

I²C

EEPROM

TI DLP chipset

Third party component

图8-1. Typical DLPC4430 Application (LED Top, LPCW Bottom)

8.2.1 Design Requirements

The DLP550JE projection system is created by using the DMD chipset, including the DLP550JE, DLPC4430,

DLPA100, and the DLPA200. The DLP550JE is used as the core imaging device in the display system and

contains a 0.55-inch array of micromirrors. The DLPC4430 controller is the digital interface between the DMD

and the rest of the system, taking digital input from front end receiver that converts the data from the source and

using the converted data for driving the DMD over a high speed interface. The DLPA100 power management

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device provides voltage regulators for the controller and illumination functionality. The DLPA200 provides the

power and sequencing to drive the DLP550JE.

Other core components of the display system include an illumination source, an optical engine for the

illumination and projection optics, other electrical and mechanical components, and software. The illumination

source options include a lamp, LED, laser, or laser phosphor. The type of illumination used and desired

brightness will have a major effect on the overall system design and size.

8.2.2 Detailed Design Procedure

For connecting the DLPC4430 display controller and the DLP550JE DMD, see the reference design schematic.

For a complete DLP system, an optical module or light engine is required that contains the DLP550JE DMD,

associated illumination sources, optical elements, and necessary mechanical components. The optical module is

typically supplied by an OMM (optical module manufacturer) who specializes in designing optics for DLP

projectors.

To ensure reliable operation, the DLP550JE DMD must always be used with the DLPC4430 display controller, a

DLPA100 PMIC driver, and a DLPA200 DMD micromirror driver.

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9 Power Supply Recommendations

9.1 DMD Power-Up and Power-Down Procedures

The DLP550JE power-up and power-down procedures are defined by the DLPC4430 data sheet. The power

supply guidelines are defined in the DLPA200 DMD Micromirror Driver Data Sheet. These procedures must be

followed to ensure reliable operation of the device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability. V_CC, V_CCI, V_OFFSET, and V_MBRSTpower supplies have to be coordinated during

power-up and power-down operations. V_SSmust also be connected. Failure to meet any of these

requirements results in a significant reduction in the DMD’s reliability and lifetime.

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10 Device and Documentation Support

10.1 Device Support

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

10.1.2 Device Nomenclature

DLP550JE FYA

Package Type

Device Descriptor

图10-1. Device Number Description

10.1.3 Device Markings

The device marking includes both human-readable information and a 2-dimensional matrix code. The human

readable information is described in 图10-2. The 2-dimensional matrix code is an alpha-numeric character string

that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first character of

the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number

(part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin

letter.

Example: *1076-643AB GHXXXXX LLLLLLM

TI Internal Numbering

Part 2 of Serial Number

(7 characters)

Part 1 of Serial Number

(7 characters)

DMD Part Number

2-Dimension Matrix Code

(Part Number and Serial Number)

图10-2. DMD Marking (Device Top View)

10.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

28

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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.2.1 Related Documentation

The following documents contain additional information related to the chipset components used with the

DLP470NE.

• DLPC4430 Display Controller Data Sheet

• DLPA100 Power and Motor Driver Data Sheet

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

DLP^®is a registered trademark of TI.

所有商标均为其各自所有者的财产。

10.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP550JE
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.55 XGA DMD
文件：	总35页 (文件大小：1433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP550JE [TI]

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DLP550JEFYA

DLP5530-Q1

DLP5530AFYKQ1

DLP5530S-Q1

DLP5530SAFYSQ1

DLP5531-Q1

DLP5531A-Q1

DLP5531AAFYSQ1

DLP5531AFYKQ1

DLP5532-Q1

DLP5532AFYSQ1

DLP5533A-Q1