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DLP9000

DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

DLP9000 Family of 0.9 WQXGA Type A DMDs

1 Features

2 Applications

1

•

High Resolution 2560×1600 (WQXGA) Array

•

Industrial

–

> 4 Million Micromirrors

–

Machine Vision and Quality Control

7.56-µm Micromirror Pitch

0.9-Inch Micromirror Array Diagonal

3D Printing

Direct Imaging Lithography

Laser Marking and Repair

±12° Micromirror Tilt Angle (Relative to Flat

State)

Medical

–

Designed for Corner Illumination

Integrated Micromirror Driver Circuitry

Two High Speed Options

–

Ophthalmology

3D Scanners for Limb and Skin Measurement

Hyper-Spectral Imaging

•

DLP9000X With a Single DLPC910 Digital

Controller

Hyper-Spectral Scanning

Displays

–

480 MHz Input Data Clock Rate

–

3D Imaging Microscopes

Intelligent and Adaptive Lighting

Up to 61 Giga-Bits Per Second (with

Continuous Streaming Input Data)

–

Up to 14989 Hz (1-Bit Binary Patterns)

3 Description

Featuring over

resolution DLP9000

micromirror devices (DMDs) are spatial light

modulators (SLMs) that modulate the amplitude,

direction, and/or phase of incoming light. This

advanced light control technology has numerous

applications in the industrial, medical, and consumer

markets. The streaming nature of the DLP9000X and

its DLPC910 controller enable very high speed

Up to 1873 Hz (8-Bit Gray Patterns With

Illumination Modulation)

4

million micromirrors, the high

and DLP9000X digital

DLP9000 with Dual DLPC900 Digital Controllers

–

400 MHz Input Data Clock Rate

Up to 38 Giga-Bits per Second (With Up to 400

Pre-Stored Binary Patterns)

–

Up to 9523 Hz (1-Bit Binary Patterns)

Up to 1031 Hz (8-Bit Gray Patterns Pre-

Loaded With Illumination Modulation), External

Input Up to 360 Hz

continuous

data

streaming

for

lithographic

applications. Both DMDs enable large build sizes and

fine resolution for 3D printing applications. The high

resolution provides the direct benefit of scanning

larger objects for 3D machine vision applications.

Designed for Use With Broad Wavelength Range

–

400 nm to 700 nm

Device Information⁽¹⁾

Window Transmission 95% (Single Pass,

Through Two Window Surfaces)

PART NUMBER

DLP9000

PACKAGE

BODY SIZE (NOM)

–

Micromirror Reflectivity 88%

Array Diffraction Efficiency 86%

Array Fill Factor 92%

42.20 mm x 42.20 mm x

7.00 mm

CLGA (355)

DLP9000X

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

SPACE

Typical DLP9000X Application

Typical DLP9000 Application

Illumination

Driver

LED

Driver

PCLK, DE

[ë5{ Lnterface

Red,Green,Blue PWM

LED Strobes

FAN

HSYNC, VSYNC

woꢂ and .lock {ignals

/ontrol {ignals

Illumination

Sensor

24-bit RGB Data

USB

DLPC900

I²C

[950

[951

{tatus {ignals

[ë5 Lnterface

Flash

OSC

DMD CTL, DATA

DLPC910

WÇ!D(3:0)

w9{9Ç {ignals

{/ꢀ Lnterface

DLP9000XFLS

I²C

SCP

DLPR910

ꢀDꢁ(4:0)

SCP

DMD DATA

/Çw[_w{Çù

DLP9000FLS

L2/

OSC

50 MHz

ë[950

ë[951

24-bit RGB Data

[950

[951

DLPC900

Flash

Voltage

Power Management

Supplies

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLP9000

DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

www.ti.com

Table of Contents

9.3 Feature Description................................................. 29

9.4 Device Functional Modes........................................ 32

9.5 Window Characteristics and Optics ....................... 32

9.6 Micromirror Array Temperature Calculation............ 33

9.7 Micromirror Landed-On/Landed-Off Duty Cycle ..... 34

10 Application and Implementation........................ 37

10.1 Application Information.......................................... 37

10.2 Typical Applications .............................................. 37

11 Power Supply Requirements ............................. 40

11.1 DMD Power Supply Requirements ...................... 40

11.2 DMD Power Supply Power-Up Procedure ........... 40

11.3 DMD Mirror Park Sequence Requirements .......... 41

11.4 DMD Power Supply Power-Down Procedure ...... 41

12 Layout................................................................... 44

12.1 Layout Guidelines ................................................. 44

12.2 Layout Example .................................................... 46

13 Device and Documentation Support ................. 50

13.1 Device Support...................................................... 50

13.2 Documentation Support ........................................ 51

13.3 Community Resources.......................................... 51

13.4 Trademarks........................................................... 52

13.5 Electrostatic Discharge Caution............................ 52

13.6 Glossary................................................................ 52

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 4

Pin Configuration and Functions......................... 4

Specifications....................................................... 11

7.1 Absolute Maximum Ratings .................................... 11

7.2 Storage Conditions.................................................. 12

7.3 ESD Ratings............................................................ 12

7.4 Recommended Operating Conditions..................... 12

7.5 Thermal Information................................................ 14

7.6 Electrical Characteristics......................................... 14

7.7 Timing Requirements.............................................. 16

7.8 Capacitance at Recommended Operating

Conditions ................................................................ 21

7.9 Typical Characteristics............................................ 21

7.10 System Mounting Interface Loads ........................ 22

7.11 Micromirror Array Physical Characteristics .......... 22

7.12 Micromirror Array Optical Characteristics ............. 24

7.13 Optical and System Image Quality........................ 25

7.14 Window Characteristics......................................... 25

7.15 Chipset Component Usage Specification ............. 25

Parameter Measurement Information ................ 26

Detailed Description ............................................ 27

9.1 Overview ................................................................. 27

9.2 Functional Block Diagram ....................................... 28

14 Mechanical, Packaging, and Orderable

8

9

Information ........................................................... 52

14.1 Thermal Characteristics ........................................ 52

14.2 Package Thermal Resistance ............................... 52

14.3 Case Temperature ................................................ 52

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2015) to Revision B

Page

•

Separated TCASE into TARRAY and TWINDOW. Changed TGRADIENT to TDELTA. Reduce DCLK_A,B,C,D for

DLP9000 in Absolute Maximum Ratings.............................................................................................................................. 11

•

Separated Tstg into Tdmd and RH in Storage Conditions................................................................................................... 12

Changed TDMD to TARRAY and TGRADIENT to TDELTA, added short term operational, and updated temperature

values in Recommended Operating Conditions. .................................................................................................................. 13

•

Added the four modes of operation...................................................................................................................................... 21

Removed the column showing the pixel data rate and added the pattern mode pattern rates............................................ 21

Updated CL2w constant in Micromirror Array Temperature Calculation.............................................................................. 33

Added recommended idle mode operation for maximizing mirror useful life. ...................................................................... 34

Updated Micromirror Derating Curve.................................................................................................................................... 34

Added mirror park sequence requirements. ......................................................................................................................... 41

Updated device nomenclature and markings. ...................................................................................................................... 51

Changes from Original (September 2014) to Revision A

Page

•

Updated title .......................................................................................................................................................................... 1

Updated Features, Description, and Device Information to include DLP9000XFLS DMD..................................................... 1

Added DLP9000XFLS application diagram............................................................................................................................ 1

2

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DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

•

Updated Absolute Maximum Ratings to include DLP9000XFLS absolute maximum ratings. ............................................. 11

Updated Recommended Operating Conditions to include DLP9000XFLS recommended operating conditions................. 12

Updated Electrical Characteristics to include DLP9000XFLS electrical characteristics....................................................... 14

Updated Electrical Characteristics to include DLP9000XFLS electrical characteristics....................................................... 15

Updated Timing Requirements to include DLP9000XFLS timing requirements................................................................... 16

Updated Typical Characteristics tables to have pixel data rates and patttern rates for both the DLP9000FLS and the

DLP9000XFLS...................................................................................................................................................................... 21

•

Updated Device Functional Modes section to include DLP9000X functional description. ................................................... 32

Updated Application and Implementations section to include typical application for the DLP9000XFLS............................ 37

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5 Description (continued)

Reliable function and operation of the DLP9000 family requires that each DMD be used in conjunction with its

specific digital controller. The DLP9000X must be driven by a single DLPC910 Controller and the DLP9000 must

be driven by two DLPC900 Controllers. These dedicated chipsets provide robust, high resolution, high speed

system solutions.

6 Pin Configuration and Functions

FLS Package Connector Terminals

355-Pin CLGA

Bottom View

4

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DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

Pin Functions

(1)

TYPE

(I/O/P)

DATA

INTERNAL

TRACE

(mils)

SIGNAL

DESCRIPTION

(2)

(3)

(4)

RATE

TERM

NAME

NO.

DATA BUS A

D_AN(0)

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

D_AP(0)

D_AP(1)

D_AP(2)

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

DATA BUS B

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

D_BN(5)

D_BN(6)

D_BN(7)

H10

G3

Input

LVDS

DDR

Differential Data, Negative

Differential Data, Positive

737

738

739

737

739

736

743

737

739

740

737

738

737

736

739

738

737

739

737

741

737

739

737

G9

F4

F10

E3

E9

D2

J5

C9

F14

B8

G15

B14

H16

D16

H8

G5

G11

F2

F8

E5

E11

D4

J3

C11

F16

B10

H14

B16

G17

D14

AD8

AE3

AF8

AF2

AG5

AH8

AG9

AH2

Input

LVDS

DDR

Differential Data, Negative

739

737

736

739

737

739

(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be

connected.

(2) DDR = Double Data Rate.

SDR = Single Data Rate.

Refer to the Timing Requirements regarding specifications and relationships.

(3) Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions regarding differential termination

specification.

(4) Dielectric Constant for the DMD Type A ceramic package is approximately 9.6.

For the package trace lengths shown:

Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns.

Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.

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TRACE

Pin Functions (continued)

(1)

TYPE

DATA

RATE

INTERNAL

TERM

SIGNAL

DESCRIPTION

(2)

(3)

(4)

(I/O/P)

(mils)

NAME

NO.

AL9

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

D_BP(8)

D_BP(9)

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

D_BP(15)

DATA BUS C

D_CN(0)

D_CN(1)

D_CN(2)

D_CN(3)

D_CN(4)

D_CN(5)

D_CN(6)

D_CN(7)

D_CN(8)

D_CN(9)

D_CN(10)

D_CN(11)

D_CN(12)

D_CN(13)

D_CN(14)

D_CN(15)

D_CP(0)

D_CP(1)

D_CP(2)

D_CP(3)

D_CP(4)

D_CP(5)

D_CP(6)

D_CP(7)

D_CP(8)

Input

LVDS

DDR

Differential Data, Negative

Differential Data, Positive

737

738

736

737

740

737

738

737

738

737

740

736

739

737

740

739

AJ11

AF14

AE11

AH16

AD14

AG17

AD16

AD10

AE5

AF10

AF4

AG3

AH10

AG11

AH4

AL11

AJ9

AF16

AE9

AH14

AE15

AG15

AE17

C15

E15

A17

F20

B20

G21

D22

E23

B26

F28

C27

J29

Input

LVDS

DDR

Differential Data, Negative

Differential Data, Positive

737

736

737

738

737

739

737

739

736

737

738

737

735

737

739

D26

H26

E29

G29

C17

E17

A15

F22

B22

H20

D20

E21

B28

6

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DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

TRACE

(mils)

SIGNAL

DESCRIPTION

(2)

(3)

(4)

NAME

NO.

F26

C29

J27

D_CP(9)

D_CP(10)

D_CP(11)

D_CP(12)

D_CP(13)

D_CP(14)

D_CP(15)

DATA BUS D

D_DN(0)

D_DN(1)

D_DN(2)

D_DN(3)

D_DN(4)

D_DN(5)

D_DN(6)

D_DN(7)

D_DN(8)

D_DN(9)

D_DN(10)

D_DN(11)

D_DN(12)

D_DN(13)

D_DN(14)

D_DN(15)

D_DP(0)

D_DP(1)

D_DP(2)

D_DP(3)

D_DP(4)

D_DP(5)

D_DP(6)

D_DP(7)

D_DP(8)

D_DP(9)

D_DP(10)

D_DP(11)

D_DP(12)

D_DP(13)

D_DP(14)

D_DP(15)

Input

LVDS

DDR

Differential Data, Positive

735

737

736

739

736

737

D28

H28

E27

G27

AJ15

AC27

AK16

AE29

AE21

AF20

AL15

AG29

AD22

AG21

AJ23

AJ29

AF28

AK22

AD28

AK28

AJ17

AC29

AK14

AE27

AD20

AF22

AL17

AG27

AE23

AG23

AJ21

AJ27

AF26

AK20

AD26

AK26

Input

LVDS

DDR

Differential Data, Negative

Differential Data, Positive

737

738

737

738

737

738

739

738

736

737

741

739

737

738

737

738

737

738

739

738

736

737

740

739

SERIAL CONTROL

SCTRL_AN

SCTRL_BN

SCTRL_CN

SCTRL_DN

SCTRL_AP

SCTRL_BP

SCTRL_CP

SCTRL_DP

D8

Input

LVDS

DDR

Differential Serial Control, Negative

Differential Serial Control, Positive

736

739

737

739

736

739

AK8

G23

AH28

D10

AK10

H22

AH26

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TRACE

Pin Functions (continued)

(1)

TYPE

DATA

RATE

INTERNAL

TERM

SIGNAL

DESCRIPTION

(2)

(3)

(4)

(I/O/P)

(mils)

NAME

NO.

CLOCKS

DCLK_AN

DCLK_BN

DCLK_CN

DCLK_DN

DCLK_AP

DCLK_BP

DCLK_CP

DCLK_DP

H2

AJ5

Input

LVDS

Differential Clock, Negative

Differential Clock, Positive

740

736

740

736

738

C23

AH22

H4

AJ3

C21

AH20

SERIAL COMMUNICATIONS PORT (SCP)

SCP_DO

SCP_DI

AC3

AD2

AE1

AD4

Output

Input

LVCMOS

SDR

Serial Communications Port Output

Pull-Down Serial Communications Port Data Input

Pull-Down Serial Communications Port Clock

SCP_CLK

SCP_ENZ

Pull-Down Active-low Serial Communications Port

Enable

MICROMIRROR RESET CONTROL

RESET_ADDR(0)

RESET_ADDR(1)

RESET_ADDR(2)

RESET_ADDR(3)

RESET_MODE(0)

RESET_MODE(1)

RESET_SEL(0)

H12

C5

Input

LVCMOS

Pull-Down Reset Driver Address Select

Pull-Down Reset Driver Mode Select

Pull-Down Reset Driver Level Select

B6

A19

J1

G1

AK4

AL13

H6

RESET_SEL(1)

RESET_STROBE

Pull-Down Reset Address, Mode, & Level latched on

rising-edge

ENABLES AND INTERRUPTS

PWRDNZ

B4

Input

LVCMOS

Active-low Device Reset

RESET_OEZ

AK24

Pull-Down Active-low output enable for DMD reset

driver circuits

RESETZ

AL19

Input

LVCMOS

Pull-Down Active-low sets Reset circuits in known

VOFFSET state

RESET_IRQZ

C3

Output

Active-low, output interrupt to ASIC

VOLTAGE REGULATOR MONITORING

PG_BIAS

J19

A13

AC19

J15

Input

LVCMOS

Pull-Up

Active-low fault from external VBIAS

regulator

PG_OFFSET

PG_RESET

EN_BIAS

Active-low fault from external VOFFSET

regulator

Input

Active-low fault from external VRESET

regulator

Output

Active-high enable for external VBIAS

regulator

EN_OFFSET

EN_RESET

H30

J17

Active-high enable for external VOFFSET

regulator

Active-high enable for external VRESET

regulator

LEAVE PIN UNCONNECTED

MBRST(0)

MBRST(1)

MBRST(2)

MBRST(3)

MBRST(4)

MBRST(5)

MBRST(6)

L5

M28

P4

Output

Analog

Pull-Down For proper DMD operation, do not connect

P30

L3

P28

P2

8

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DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

Pin Functions (continued)

(1)

TYPE

(I/O/P)

DATA

RATE

INTERNAL

TERM

TRACE

(mils)

SIGNAL

DESCRIPTION

(2)

(3)

(4)

NAME

NO.

T28

M4

MBRST(7)

MBRST(8)

MBRST(9)

MBRST(10)

MBRST(11)

MBRST(12)

MBRST(13)

MBRST(14)

MBRST(15)

MBRST(16)

MBRST(17)

MBRST(18)

MBRST(19)

MBRST(20)

MBRST(21)

MBRST(22)

MBRST(23)

MBRST(24)

MBRST(25)

MBRST(26)

MBRST(27)

MBRST(28)

MBRST(29)

MBRST(30)

MBRST(31)

Output

Analog

Pull-Down For proper DMD operation, do not connect

L29

T4

N29

N3

L27

R3

V28

V4

R29

Y4

AA27

W3

W27

AA3

W29

U5

U29

Y2

AA29

U3

Y30

AA5

R27

LEAVE PIN UNCONNECTED

RESERVED_PFE

RESERVED_TM

RESERVED_XI0

RESERVED_XI1

RESERVED_XI2

RESERVED_TP0

RESERVED_TP1

RESERVED_TP2

J11

Input

LVCMOS

Analog

Pull-Down For proper DMD operation, do not connect

For proper DMD operation, do not connect

AC7

AC25

AC23

J23

AC9

AC11

AC13

Analog

For proper DMD operation, do not connect

Analog

For proper DMD operation, do not connect

LEAVE PIN UNCONNECTED

RESERVED_BA

RESERVED_BB

RESERVED_BC

RESERVED_BD

RESERVED_TS

AC15

Output

LVCMOS

For proper DMD operation, do not connect

J13

AC21

J21

AC17

LEAVE PIN UNCONNECTED

NO CONNECT

J7

J9

For proper DMD operation, do not connect

J25

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Pin Functions

NAME

TYPE

(I/O/P)

SIGNAL

DESCRIPTION

(1)

NO.

A3, A9, A5, A11, A7, B2

L1, N1, R1

Supply voltage for positive Bias level of Micromirror reset

signal.

VBIAS

Power

Analog

Supply voltage for HVCMOS logic.

Supply voltage for stepped high voltage at Micromirror

address electrodes.

VOFFSET

VRESET

U1, W1

AC1, AA1

Supply voltage for Offset level of MBRST(31:0).

L31, N31, R31, U31, W31,

AA31

Supply voltage for negative Reset level of Micromirror reset

signal.

A21, A23, A25, A27, A29,

C1, C31, E31, G31, J31, K2,

AC31, AE31, AG1, AG31,

AJ31, AK2, AK30, AL3, AL5,

AL7, AL21, AL23, AL25,

AL27

Supply voltage for LVCMOS core logic.

Supply voltage for normal high level at Micromirror address

electrodes.

VCC

Power

Analog

H18, H24, M6, M26, P6, P26,

T6, T26, V6, V26, Y6, Y26,

AD6, AD12, AD18, AD24

VCCI

Supply voltage for LVDS receivers.

A1, B12, B18, B24, B30, C7,

C13, C19, C25, D6, D12,

D18, D24, D30, E1, E7, E13,

E19, E25, F6, F12, F18, F24,

F30, G7, G13, G19, G25, K4,

K6, K26, K28, K30, M2, M30,

N5, N27, R5, T2, T30, U27,

V2, V30, W5, Y28, AB2, AB4,

AB6, AB26, AB28, AB30,

AC5, AD30, AE7, AE13,

VSS

Power

Analog

Device Ground. Common return for all power.

AE19, AE25, AF6, AF12,

AF18, AF24, AF30, AG7,

AG13, AG19, AG25, AH6,

AH12, AH18, AH24, AH30,

AJ1, AJ7, AJ13, AJ19, AJ25,

AK6, AK12, AK18, AL29

(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be

connected.

10

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DLPS036B –SEPTEMBER 2014–REVISED OCTOBER 2016

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

SUPPLY VOLTAGES

(2)

VCC

Supply voltage for LVCMOS core logic

–0.5

–11

4

V

(2)

VCCI

Supply voltage for LVDS receivers

(2) (3)

VOFFSET

Supply voltage for HVCMOS and micromirror electrode

9

(2)

VBIAS

Supply voltage for micromirror electrode

17

0.5

0.3

8.75

(2)

VRESET

Supply voltage for micromirror electrode

(4)

| VCC – VCCI |

| VBIAS – VOFFSET |

INPUT VOLTAGES

Supply voltage delta (absolute value)

(5)

Supply voltage delta (absolute value)

(2)

Input voltage for all other LVCMOS input pins

–0.5

VCC + 0.3

VCCI + 0.3

700

V

(2) (6)

Input voltage for all other LVDS input pins

(7)

| V_ID

I_ID

|

Input differential voltage (absolute value)

mV

mA

(7)

Input differential current

7

CLOCKS

Clock frequency for LVDS interface, DCLK_A

Clock frequency for LVDS interface, DCLK_B

Clock frequency for LVDS interface, DCLK_C

Clock frequency for LVDS interface, DCLK_D

Clock frequency for LVDS interface, DCLK_A

Clock frequency for LVDS interface, DCLK_B

Clock frequency for LVDS interface, DCLK_C

Clock frequency for LVDS interface, DCLK_D

440

500

DLP9000

ƒ_clock

MHz

DLP9000X

ENVIRONMENTAL

(8) (9)

Array temperature: operational

Array temperature: non–operational

Window temperature: operational

0

90

70

90

T_ARRAY

ºC

(9)

-40

0

T_WINDOW

ºC

Window temperature: non–operational

-40

Absolute termperature delta between the window test points and the

ceramic test point TP1⁽¹⁰⁾

|T_DELTA

|

10

RH

Relative Humidity, operating and non–operating

95%

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.

(2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for

proper DMD operation. VSS must also be connected.

(3) VOFFSET supply transients must fall within specified voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply

Requirements for additional information.

(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential

temperature, or illumination power density may affect device reliability.

(9) The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1

(TP1) in Figure 15.

(10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15.

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7.2 Storage Conditions

applicable before the DMD is installed in the final product

MIN

MAX

80

UNIT

T_DMD

RH

DMD storage temperature

-40

°C

Relative Humidity, (non-condensing)

95%

7.3 ESD Ratings

VALUE

UNIT

(1)

V_(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

±2000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

(1) (2)

SUPPLY VOLTAGES

DLP9000

DLP9000X

DLP9000

DLP9000X

Supply voltage for LVCMOS core logic

Supply voltage for LVDS receivers

3.0

3.3

3.45

3.3

3.6

VCC

V

3.0

3.6

VCCI

Supply voltage for LVDS receivers

3.3

3.45

8.5

3.6

(3)

VOFFSET

VBIAS

Supply voltage for HVCMOS and micromirror electrodes

8.25

15.5

–9.5

8.75

16.5

–10.5

0.3

V

16

Supply voltage for micromirror electrodes

VRESET

–10

(4)

|VCCI–VCC| Supply voltage delta (absolute value)

|VBIAS–VO

(5)

Supply voltage delta (absolute value)

FFSET|

8.75

V

LVCMOS PINS

(6)

V_IH

High level Input voltage

Low level Input voltage

1.7

2.5

VCC + 0.3

V

(6)

V_IL

– 0.3

0.7

–20

15

I_OH

High level output current at V_OH= 2.4 V

Low level output current at V_OL= 0.4 V

mA

ns

I_OL

(7)

T_PWRDNZ

PWRDNZ pulse width

10

SCP INTERFACE

(8)

ƒ_clock

SCP clock frequency

500

800

700

kHz

ns

(9)

t_{SCP_SKEW}

t_{SCP_DELAY}

Time between valid SCPDI and rising edge of SCPCLK

–800

1

(9)

Time between valid SCPDO and rising edge of SCPCLK

Time between consecutive bytes

ns

t_{SCP_BYTE_INT}

µs

ERVAL

t_{SCP_NEG_ENZ}Time between falling edge of SCPENZ and the first rising edge of SCPCLK

t_{SCP_PW_ENZ}SCPENZ inactive pulse width (high level)

30

1

ns

µs

t_{SCP_OUT_EN}Time required for SCP output buffer to recover after SCPENZ (from tri-state)

1.5

ns

(10)

ƒ_clock

SCP circuit clock oscillator frequency

9.6

11.1

MHz

(1) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2) All voltages are referenced to common ground VSS.

(3) VOFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply

Requirements for additional information.

(6) Tester Conditions for V_IHand V_IL:

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)

Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)

(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the

SCPDO output pin.

(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9) Refer to Figure 1.

(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

LVDS INTERFACE

DLP9000

Clock frequency DCLK

400

480

600

ƒ_clock

|V_ID

MHz

(11)

DLP9000X

Clock frequency DCLK

400

100

(12)

|

Input differential voltage (absolute value)

400

mV

ns

(12)

V_CM

Common mode

1200

(12)

V_LVDS

t_{LVDS_RSTZ}

Z_IN

LVDS voltage

0

2000

10

Time required for LVDS receivers to recover from PWRDNZ

Internal differential termination resistance

95

90

105

110

Ω

Z_LINE

Line differential impedance (PWB/trace)

100

Ω

ENVIRONMENTAL ⁽¹³⁾For Illumination Source Between 420 nm and 700 nm

(14) (15)(16)

(17)

Array temperature, Long–term operational

Array temperature, Short–term operational

Array temperature, Long–term operational

Array temperature, Short–term operational

10

0

40 to 65

DLP9000

(14) (15)(18)

(14) (15)(16)

(14) (15)(18)

10

T_ARRAY

°C

(19)

DLP9000X

10

0

40

10

70

40

Window Temperature test points TP2 and TP3, Long-term

operational⁽¹⁶⁾

DLP9000

10

T_WINDOW

DLP9000X

Window Temperature test points TP2 and TP3, Long-term

operational⁽¹⁶⁾

Absolute Temperature delta between the window test points (TP2, TP3) and the

ceramic test point TP1⁽²⁰⁾

|T_DELTA

|

10

°C

Thermally

Limited

mW/cm²

ILL_VIS

RH

Illumination

(21)

Relative Humidity (non-condensing)

95%

ENVIRONMENTAL ⁽¹³⁾For Illumination Source Between 400 nm and 420 nm

(14) (15)(16)

Array temperature, Long–term operational

20

0

30

20

30

T_ARRAY

°C

(14) (15)(18)

Array temperature, Short–term operational

T_WINDOW

Window Temperature test points TP2 and TP3, Long-term operational⁽¹⁶⁾

°C

Absolute Temperature delta between the window test points (TP2, TP3) and the

ceramic test point TP1⁽²⁰⁾

|T_DELTA

|

10

W/cm²

ILL_VIS

RH

Illumination

10

Relative Humidity (non-condensing)

95%

ENVIRONMENTAL ⁽¹³⁾For Illumination Source <400 nm and >700 nm

(14) (15)(16)

(14) (15)(18)

(14) (15)(16)

(14) (15)(18)

(17)

Array temperature, Long–term operational

10

0

40 to 65

DLP9000

Array temperature, Short–term operational

T_ARRAY

10

°C

(19)

DLP9000X

Array temperature, Long–term operational

10

0

40

Array temperature, Short–term operational

10

(11) The DLP9000X, coupled with the DLPC910, is designed for operation at 2 specific DCLK frequencies only - 400 MHz or 480 MHz. 480

MHz operation is only allowed at the specific environmental operating conditions as shown in this table.

(12) Refer to Figure 2, Figure 3, and Figure 4.

(13) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application

parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage

and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that

application-specific effects be considered as early as possible in the design cycle.

(14) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in Figure 15 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation.

(15) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will

reduce device lifetime.

(16) Long-term is defined as the usable life of the device.

(17) Per Figure 16, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty

cycle.

(18) Array and Window temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up).

Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.

(19) For the DLP9000X, Figure 16 does not apply and the maximum temperature is as specified in table.

(20) Temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in Figure 15.

(21) Refer to Thermal Information and Micromirror Array Temperature Calculation.

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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

10

NOM

MAX

70

UNIT

Window Temperature test points TP2 and TP3, Long-term

DLP9000

operational⁽¹⁶⁾

T_WINDOW

°C

DLP9000X

Window Temperature test points TP2 and TP3, Long-term

operational⁽¹⁶⁾

10

40

Absolute Temperature delta between the window test points (TP2, TP3) and the

ceramic test point TP1⁽²⁰⁾

|T_DELTA

|

10

°C

mW/cm²

ILL_UV

ILL_IR

RH

Illumination, wavelength < 400 nm

Illumination, wavelength > 700 nm

Relative Humidity (non-condensing)

0.68

10

95%

7.5 Thermal Information

DLP9000

FLS (CLGA)

355 PINS

0.5

(1)

THERMAL METRIC

UNIT

R_θJA

Thermal resistance, active area to test point 1 (TP1) (max)

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate

heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the

Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area,

although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical

systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in

this area can significantly degrade the reliability of the device.

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC = 3 V, I_OH= –20 mA

MIN TYP

MAX UNIT

V_OH

High-level output voltage

Low level output voltage

2.4

V

V_OL

VCC = 3.6, I_OL= 15 mA

VCC = 3.6 V, V_I= VCC

VCC = 3.6 V, V_I= 0

VCC = 3.6 V

0.4

V

(2) (3)

I_IH

High–level input current

Low level input current

250

µA

IlL

–250

I_OZ

High–impedance output current

10

CURRENT

DLP9000 VCC = 3.6 V, DCLK=400 MHz

DLP9000X VCC = 3.6V, DCLK=480 MHz

DLP9000 VCCI = 3.6 V, DCLK=400 MHz

DLP9000X VCCI = 3.6, DCLK=480 MHz

VOFFSET = 8.75 V

1600

1850

985

1100

25

I_CC

(4)

Supply current

mA

I_CCI

I_OFFSET

I_BIAS

I_RESET

I_TOTAL

(5)

Supply current

mA

VBIAS = 16.5 V

14

VRESET = –10.5 V

11

Supply current

DLP9000 Total Sum

2634

3000

DLP9000X Total Sum

POWER

(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for

proper DMD operation. VSS must also be connected.

(2) Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.

(3) LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and

Functions to determine pull-up or pull-down configuration used.

(4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT

DLP9000 VCC = 3.6 V

5760

mW

P_CC

DLP9000X VCC = 3.6 V

DLP9000 VCCI = 3.6 V

DLP9000X VCCI = 3.6 V

VOFFSET = 8.75 V

6660

3546

mW

P_CCI

Supply power dissipation

3960

P_OFFSET

P_BIAS

219

231

mW

VBIAS = 16.5 V

P_RESET

VRESET = –10.5 V

115

DLP9000 Total Sum, DCLK = 400 MHz

DLP9000X Total Sum, DCLK = 480 MHz

9871

11185

(6)

P_TOTAL

Supply power dissipation

mW

CAPACITANCE

C_I

Input capacitance

Output capacitance

ƒ = 1 MHz

10

pF

C_O

Reset group capacitance

MBRST(31:0)

ƒ = 1 MHz; 2560 × 50 micromirrors

230

290

pF

(6) Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination

source. See the Micromirror Array Temperature Calculation.

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7.7 Timing Requirements

over Recommended Operating Conditions (unless otherwise noted)

(1)

MIN

NOM

MAX

UNIT

(2)

SCP INTERFACE

t_r

Rise time

20% to 80%

80% to 20%

200

ns

t_ƒ

Fall time

(2)

LVDS INTERFACE

t_r

Rise time

20% to 80%

80% to 20%

100

400

ps

t_ƒ

Fall time

(3)

LVDS CLOCKS

DCLK_A, 50% to 50%

DCLK_B, 50% to 50%

DCLK_C, 50% to 50%

DCLK_D, 50% to 50%

DCLK_A, 50% to 50%

DCLK_B, 50% to 50%

DCLK_C, 50% to 50%

DCLK_D, 50% to 50%

DCLK_A, 50% to 50%

DCLK_B, 50% to 50%

DCLK_C, 50% to 50%

DCLK_D, 50% to 50%

DCLK_A, 50% to 50%

DCLK_B, 50% to 50%

DCLK_C, 50% to 50%

DCLK_D, 50% to 50%

2.5

DLP9000

DLP9000X

DLP9000

DLP9000X

2.5

t_c

Cycle time

ns

2.083

1.19

1.25

1.19

1.25

1.19

1.25

Pulse

duration

t_w

ns

1.031

1.042

(3)

LVDS INTERFACE

D_A(15:0) before rising or falling edge of DCLK_A

D_B(15:0) before rising or falling edge of DCLK_B

D_C(15:0) before rising or falling edge of DCLK_C

D_D(15:0) before rising or falling edge of DCLK_D

SCTRL_A before rising or falling edge of DCLK_A

SCTRL_B before rising or falling edge of DCLK_B

SCTRL_C before rising or falling edge of DCLK_C

SCTRL_D before rising or falling edge of DCLK_D

0.2

0.5

0.4

0.5

0.4

t_su

Setup time

ns

t_su

D_A(15:0) after rising or falling edge of DCLK_A

D_B(15:0) after rising or falling edge of DCLK_B

D_C(15:0) after rising or falling edge of DCLK_C

D_D(15:0) after rising or falling edge of DCLK_D

D_A(15:0) after rising or falling edge of DCLK_A

D_B(15:0) after rising or falling edge of DCLK_B

D_C(15:0) after rising or falling edge of DCLK_C

D_D(15:0) after rising or falling edge of DCLK_D

SCTRL_A after rising or falling edge of DCLK_A

SCTRL_B after rising or falling edge of DCLK_B

SCTRL_C after rising or falling edge of DCLK_C

SCTRL_D after rising or falling edge of DCLK_D

SCTRL_A after rising or falling edge of DCLK_A

SCTRL_B after rising or falling edge of DCLK_B

SCTRL_C after rising or falling edge of DCLK_C

SCTRL_D after rising or falling edge of DCLK_D

DLP9000

DLP9000X

DLP9000

DLP9000X

t_h

Hold time

ns

t_h

Hold time

ns

(1) Refer to Pin Configuration and Functions for pin details.

(2) Refer to Figure 5.

(3) Refer to Figure 6.

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Timing Requirements (continued)

over Recommended Operating Conditions (unless otherwise noted) ⁽¹⁾

MIN

NOM

MAX

UNIT

(3)

LVDS INTERFACE

DLP9000 Channel A includes the following LVDS pairs:

DCLK_AP and DCLK_AN

SCTRL_AP and SCTRL_AN

D_AP(15:0) and D_AN(15:0)

–1.25

1.25

ns

DLP9000 Channel B includes the following LVDS pairs:

DCLK_BP and DCLK_BN

SCTRL_BP and SCTRL_BN

D_BP(15:0) and D_BN(15:0)

Channel B

relative to

Channel A

DLP9000X Channel A includes the following LVDS pairs:

DCLK_AP and DCLK_AN

SCTRL_AP and SCTRL_AN

D_AP(15:0) and D_AN(15:0)

-1.04

1.04

1.25

1.04

ns

DLP9000X Channel B includes the following LVDS pairs:

DCLK_BP and DCLK_BN

SCTRL_BP and SCTRL_BN

D_BP(15:0) and D_BN(15:0)

t_skew

Skew time

DLP9000 Channel C includes the following LVDS pairs:

DCLK_CP and DCLK_CN

SCTRL_CP and SCTRL_CN

D_CP(15:0) and D_CN(15:0)

–1.25

DLP9000 Channel D includes the following LVDS pairs:

DCLK_DP and DCLK_DN

SCTRL_DP and SCTRL_DN

Channel D

relative to

Channel C

D_DP(15:0) and D_DN(15:0)

DLP9000X Channel C includes the following LVDS pairs:

DCLK_CP and DCLK_CN

SCTRL_CP and SCTRL_CN

D_CP(15:0) and D_CN(15:0)

-1.04

DLP9000X Channel D includes the following LVDS pairs:

DCLK_DP and DCLK_DN

SCTRL_DP and SCTRL_DN

D_DP(15:0) and D_DN(15:0)

t

f

= 1 / t

c

clock

SCPCLK

50%

t_{SCP_SKEW}

SCPDI

50%

t_{SCP_DELAY}

SCPD0

50%

Not to scale.

Refer to SCP Interface section of the Recommended Operating Conditions table.

Figure 1. SCP Timing Parameters

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(V_IP+ V_IN) / 2

DCLK_P , SCTRL_P , D_P(0:?)

DCLK_N , SCTRL_N , D_N(0:?)

LVDS

Receiver

V_ID

V_IP

V_CM

V_IN

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Refer to Pin Configuration and Functions for list of LVDS pins.

Figure 2. LVDS Voltage Definitions (References)

V_{LVDS max}= V_{CM max}+ | 1/2 * V_{ID max}

|

V_CM

V_ID

V_{LVDS min}= V_{CM min}œ | 1/2 * V_{ID max}

|

Not to scale.

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Figure 3. LVDS Voltage Parameters

DCLK_P , SCTRL_P , D_P(0:?)

ESD

Internal

Termination

LVDS

Receiver

DCLK_N , SCTRL_N , D_N(0:?)

ESD

Refer to LVDS Interface section of the Recommended Operating Conditions table.

Refer to Pin Configuration and Functions for list of LVDS pins.

Figure 4. LVDS Equivalent Input Circuit

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LVDS Interface

SCP Interface

1.0 * VCC

1.0 * V

ID

V

CM

0.0 * VCC

0.0 * V

ID

t_r

t_f

t_r

t_f

Not to scale.

Refer to the Timing Requirements table

Refer to Pin Configuration and Functions for a list of LVDS pins and SCP pins..

Figure 5. Rise Time and Fall Time

Not to scale.

Refer to LVDS INTERFACE section in the Timing Requirements table.

Figure 6. Timing Requirement Parameter Definitions

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Not to scale.

Refer to LVDS INTERFACE section in the Timing Requirements table.

Figure 7. LVDS Interface Channel Skew Definition

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7.8 Capacitance at Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input capacitance

TEST CONDITIONS

ƒ = 1 MHz

MIN

MAX

10

UNIT

pF

C_I

C_O

C_IM

Output capacitance

ƒ = 1 MHz

10

pF

MBRST(31:0) input capacitance

f = 1 MHz. All inputs interconnected.

230

290

pF

7.9 Typical Characteristics

When the DLP9000 DMD is controlled by two DLPC900 controllers, these digital controllers offer four modes of

operation.

1. Video Mode

2. Video Pattern Mode

3. Pre-Stored Pattern Mode

4. Pattern On-The-Fly Mode

In video mode, the video source is displayed on the DMD at the rate of the incoming video source.

In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1.

When the DLP9000X DMD is controlled by the DLPC910 controller, the digital controller offers streaming 1-bit

binary patterns to the DMD at speeds greater than 61 Gigabits per second (Gbps). The patterns are streamed

from a customer designed applications processor into the DLPC910 input LVDS data interface. Table 2 shows

the pattern rates for the different DMD Reset Modes.

Table 1. DLPC900 with DLP9000 Pattern Rate versus Bit Depth

PRE-STORED or PATTERN ON-

BIT DEPTH

VIDEO PATTERN MODE (Hz)

THE-FLY MODE (Hz)

1

2

3

4

5

6

7

8

2880

1440

960

720

480

360

247

9523

3289

2638

1364

823

672

500

247

Table 2. DLPC910 with DLP9000X Pattern Rates versus Reset Mode

(3)

RESET MODE⁽¹⁾

MAX PIXEL DATA RATE (Gbps)⁽²⁾

MAX PATTERN RATE (Hz)

Global

Single

Dual

53.42

56.46

59.89

61.39

13043⁽⁴⁾

(5)

13783

(5)

14624

Quad

14989⁽⁵⁾

(1) Refer to the DLPC910 data sheet in Related Documentation for a description of the reset modes.

(2) Pixel data rates are based on continuous streaming.

(3) Increasing exposure periods may be necessary for a desired application but may decrease pattern rate.

(4) Global reset mode allows for continuous or pulsed illumination source.

(5) This reset mode typically requires pulsed illumination such as a laser or LED.

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7.10 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX UNIT

Thermal interface area (See Figure 8)

35

300

160

lbs

Maximum system mounting interface

load to be applied to the:

Electrical interface area

(1)

Datum A interface area

Thermal

Interface Area

Electrical

Interface Area

Other Area

Datum ‘A’ Areas

Figure 8. System Mounting Interface Loads

7.11 Micromirror Array Physical Characteristics

VALUE

UNIT

M

N

P

Number of active columns

Number of active rows

2560

1600

micromirrors

Micromirror (pixel) pitch

Micromirror active array width

Micromirror active array height

Micromirror active border

Micromirror total area

See Figure 9

7.56

µm

M × P

19.3536

12.096

14

mm

N × P

(1)

Pond of micromirror (POM)

P²x M x N (converted to cm)

micromirrors/ side

cm²

2.341

(1) Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum

A area (300 + 35 – Datum A).

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

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0

1

2

3

DMD Active Array

M x N Micromirrors

N x P

N œ 4

N œ 3

N œ 2

N œ 1

M x P

P

Border micromirrors omitted for clarity.

Details omitted for clarity.

Not to scale.

P

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 9. Micromirror Array Physical Characteristics

Figure 10. DMD Micromirror Active Area

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7.12 Micromirror Array Optical Characteristics

Refer to Optical Interface and System Image Quality for important information.

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

(1)

α

β

Micromirror tilt angle

DMD landed state

12

°

(1) (2) (3) (4) (5)

Micromirror tilt angle tolerance

–1

44

1

46

0

(5) (6)

Micromirror tilt direction

See Figure 11

45

Adjacent micromirrors

Non-adjacent micromirrors

Typical performance

(7)

Number of out-of-specification micromirrors

micromirrors

10

(8) (9)

Micromirror crossover time

2.5

μs

DMD efficiency within the wavelength range 400 nm to 420 nm

68%

(10)

DMD photopic efficiency within the wavelength range 420 nm

to 700 nm

66%

(10)

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in

colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State

direction. A binary value of 0 results in a micromirror landing in the OFF State direction.

(7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the

specified Micromirror Switching Time.

(8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.

(9) Performance as measured at the start of life.

(10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform

pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this

number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.

illumination

Not To Scale

0

1

2

3

On-State

Tilt Direction

Off-State

Tilt Direction

45°

N œ 4

N œ 3

N œ 2

N œ 1

Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.

Figure 11. Micromirror Landed Orientation and Tilt

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7.13 Optical and System Image Quality

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in a) through c)

below:

a. Numerical Aperture and Stray Light Control. The angle defined by the numerical aperture of the illumination

and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal

device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to

block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to

separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections

from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or

lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture

angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts

in the display’s border and/or active area could occur.

b. Pupil Match. TI’s optical and image quality specifications assume that the exit pupil of the illumination optics

is nominally centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils

can create objectionable artifacts in the display’s border and/or active area, which may require additional

system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

c. Illumination Overfill. Overfill light illuminating the area outside the active array can create artifacts from the

mechanical features that surround the active array and other surface anomalies that may be visible on the

screen. The illumination optical system should be designed to limit light flux incident anywhere outside the

active array more than 20 pixels from the edge of the active array on all sides. Depending on the particular

system’s optical architecture and assembly tolerances, this amount of overfill light on the outside of the active

array may still cause artifacts to still be visible.

NOTE

TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD

FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING

LIMITS DESCRIBED ABOVE.

7.14 Window Characteristics

(1)

PARAMETER

Window material designation

Window refractive index

Window aperture

TEST CONDITIONS

MIN

TYP

MAX UNIT

Corning 7056

at wavelength 589 nm

1.487

(2)

See

Illumination overfill

Refer to Illumination Overfill

At wavelength 405 nm. Applies to 0° and 24° AOI only.

95%

97%

Minimum within the wavelength range 420 nm to 680 nm.

Applies to all angles 0° to 30° AOI.

Window transmittance, single–pass

(3)

through both surfaces and glass

Average over the wavelength range 420 nm to 680 nm.

Applies to all angles 30° to 45° AOI.

97%

(1) Refer to Window Characteristics and Optics for more information.

(2) For details regarding the size and location of the window aperture, refer to the package mechanical characteristics listed in the

Mechanical ICD in the Mechanical, Packaging, and Orderable Information section.

(3) Refer to the TI application report DLPA031, Wavelength Transmittance Considerations for DMD Window.

7.15 Chipset Component Usage Specification

The DMD is a component of one or more DLP^®chipsets. Reliable function and operation of the DMD requires

that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology is the TI

technology and devices for operating or controlling a DMD.

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8 Parameter Measurement Information

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. Figure 12 shows an equivalent test load circuit for the

output under test. The load capacitance value stated is only for characterization and measurement of AC timing

signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

Timing reference loads are not intended as a precise representation of any particular system environment or

depiction of the actual load presented by a production test. System designers should use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation

section.

Device Pin

Tester Channel

Output Under Test

C_LOAD

Figure 12. Test Load Circuit

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9 Detailed Description

9.1 Overview

The DMD is a 0.9 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum

micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 9.

The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical

interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).

The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M

memory cell columns by N memory cell rows. Refer to the Functional Block Diagram.

The positive or negative deflection angle of the micromirrors can be individually controlled by changing the

address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).

Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes

underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror

Array Optical Characteristics. The micromirrors are electrically tied to the micromirror reset signals (MBRST) and

the micromirror array is divided into reset groups.

Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt

toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or

out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative

(–) tilt angle state corresponds to an 'off' pixel.

Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration

and Functions for more information on micromirror reset control.

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9.2 Functional Block Diagram

Not to Scale. Details Omitted for Clarity. See Accompanying Notes in this Section.

Channel A

Interface

Channel C

Interface

Control

Column Read & Write

Control

(0,0)

Word Lines

Voltages

Word Lines

Voltages

Row

Micromirror Array

Voltage

Generators

Voltage

Generators

(M-1, N-1)

Control

Column Read & Write

Control

Channel B

Interface

Channel D

Interface

For pin details on Channels A, B, C, and D, refer to Pin Configuration and Functions and LVDS Interface section of

Timing Requirements.

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9.3 Feature Description

The DMD consists of 4096000 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors)

organized in a two-dimensional orthogonal pixel array. Refer to Figure 9 and Figure 13.

Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular

positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to

Micromirror Array Optical Characteristics and Figure 14.

The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel

to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is

perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package,

as shown in Figure 13.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a

specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell

contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual micromirrors

changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory

cell data update.

Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror

switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the

corresponding micromirror switching to a – α position.

Updating the angular position of the micromirror array consists of two steps. First, update the contents of the

CMOS memory. Second, apply a micromirror reset (also referred as Mirror Clocking Pulse) to all or a portion of

the micromirror array (depending upon the configuration of the system). Micromirror reset pulses are generated

internally by the DMD, with application of the pulses being coordinated by the DLPC900 or the DLPC910 digital

controller.

For more information, refer to the TI application report DLPA008, DMD101: Introduction to Digital Micromirror

Device (DMD) Technology.

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Feature Description (continued)

Incident

Illumination

Package Pin

A1 Corner

Details Omitted For Clarity.

Not To Scale.

DMD

Micromirror

Array

Active Micromirror Array

(Border micromirrors eliminated for clarity)

0

Nœ1

Micromirror Pitch

P (um)

Micromirror Hinge-Axis Orientation

—On-State“

45°

Tilt Direction

—Off-State“

Tilt Direction

P (um)

Refer to Micromirror Array Physical Characteristics , Figure 9, and Figure 11.

Figure 13. Micromirror Array, Pitch, Hinge Axis Orientation

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Feature Description (continued)

Details Omitted For Clarity.

Not To Scale.

Package Pin

A1 Corner

DMD

Incident

Illumination

Two

—On-State“

Two

—Off-State“

Micromirrors Micromirrors

For Reference

Flat-State

( —parked“ )

Micromirror Position

a ± b

-a ± b

Silicon Substrate

—On-State“

Micromirror

—Off-State“

Micromirror

Micromirror States: On, Off, Flat

Figure 14. Micromirror States: On, Off, Flat

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9.4 Device Functional Modes

9.4.1 DLP9000

The DLP9000 DMD is controlled by two DLPC900 digital controllers. The digital controller operates in two

different modes. The first is video mode where the video source is displayed on the DMD. The second is Pattern

mode, where the patterns are downloaded over USB or pre-stored in flash memory, and then streamed to the

DMD. The resulting DMD pattern rate depends on which mode and bit-depth is selected. For more information,

refer to the DLPC900 data sheet listed under Related Documentation.

9.4.2 DLP9000X

The DLP9000X DMD is controlled by one DLPC910 digital controller. The digital controller offers high speed

streaming mode where 1-bit binary patterns are accepted at the LVDS interface input, and then streamed to the

DMD. To ensure reliable operation, the DLP9000X must always be used with the DLPC910. For more

information, refer to the DLPC910 data sheet listed under Related Documentation.

9.5 Window Characteristics and Optics

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

9.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

9.5.2 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light

path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt

angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.

9.5.3 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create

objectionable artifacts in the display’s border and/or active area, which may require additional system apertures

to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

9.5.4 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical

operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the

window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical

system should be designed to limit light flux incident anywhere on the window aperture from exceeding

approximately 10% of the average flux level in the active area. Depending on the particular system’s optical

architecture, overfill light may have to be further reduced below the suggested 10% level in order to be

acceptable.

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9.6 Micromirror Array Temperature Calculation

Figure 15. DMD Thermal Test Points

Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.

The relationship between micromirror array temperature and the reference ceramic temperature is provided by

the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

Q_ILLUMINATION= (C_L2W× SL)

)

(1)

(2)

(3)

Where:

T_ARRAY= Computed micromirror array temperature (°C)

T_CERAMIC= Measured ceramic temperature (°C), TP1 location in Figure 15

R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from micromirror array to outside ceramic (°C/W)

specified in Thermal Information

Q_ARRAY= Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W)

Q_ELECTRICAL= DMD electrical power dissipation (W), specified in Electrical Characteristics

C_L2W= Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified

below

SL = Measured ANSI screen lumens (lm)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. Absorbed optical power from the illumination source is variable and depends on the operating state

of the micromirrors and the intensity of the light source. Equations shown above produce a total projection

efficiency through the projection lens from DMD to the screen of 87%.

The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral

efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and

16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00274

W/lm.

Sample Calculation for typical projection application:

T_CERAMIC= 55°C, assumed system measurement; refer to Recommended Operating Conditions regarding

specific limits.

SL = 2000 lm

Q_ELECTRICAL= 9.87W for the DLP9000 (refer to the power specifications in Electrical Characteristics)

C_L2W= 0.00274 W/lm

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Micromirror Array Temperature Calculation (continued)

Q_ARRAY= 9.87 W + (0.00274 W/lm × 2000 lm) = 15.35 W

T_ARRAY= 55°C + (15.35 W × 0.5 ºC/W) = 62.68°C

9.7 Micromirror Landed-On/Landed-Off Duty Cycle

9.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On–state versus the amount of time the same

micromirror is landed in the Off–state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the

time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of

the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

9.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

Individual DMD mirror duty cycles vary by application as well as the mirror location on the DMD within any

specific application. DMD mirror useful life are maximized when every individual mirror within a DMD approaches

50/50 (or 1/1) duty cycle. Therefore, for the DLPC900 and DLP9000 chipset, it is recommended that DMD Idle

Mode be enabled as often as possible. Examples are whenever the system is idle, the illumination is disabled,

between sequential pattern exposures (if possible), or when the exposure pattern sequence is stopped for any

reason. This software mode provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors

are continuously flipped between the on and off states. Refer to the DLPC900 Programmer’s Guide DLPU018 for

a description of the DMD Idle Mode command. For the DLPC910 and DLP9000X chipset, it is recommended the

controlling applications processor provide a 50/50 pattern sequence to the DLPC910 for display on the

DLP9000X as often as possible, similar to the above examples stated for the DLPC900. The pattern provides a

50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on

and off states.

9.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in Figure 16. The importance of this curve is that:

•

All points along this curve represent the same usable life.

All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

•

All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a give long-term average Landed Duty Cycle.

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Micromirror Landed-On/Landed-Off Duty Cycle (continued)

80

70

60

50

40

30

0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55

50/50

100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 6040 55/45

Micromirror Landed Duty Cycle

Figure 16. Max Recommended DMD Temperature – Derating Curve

9.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the

pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 3.

Table 3. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

LANDED DUTY CYCLE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given

primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +

(Blue_Cycle_% × Blue_Scale_Value)

Where:

Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,

Green, and Blue are displayed (respectively) to achieve the desired white point.

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,

blue color intensities would be as shown in Table 4.

Table 4. Example Landed Duty Cycle for Full-Color

RED CYCLE PERCENTAGE

50%

GREEN CYCLE PERCENTAGE

20%

BLUE CYCLE PERCENTAGE

30%

LANDED DUTY CYCLE

RED SCALE VALUE

GREEN SCALE VALUE

BLUE SCALE VALUE

0%

100%

0%

0/100

50/50

20/80

30/70

6/94

100%

0%

100%

0%

12%

0%

35%

0%

7/93

0%

60%

0%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

0%

100%

0%

100%

0%

100%

12%

0%

35%

0%

60%

100%

12%

100%

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The DLP9000 DMD is controlled by two DLPC900 controllers. This chipset offers two modes of operation. The

first is video mode where the video source is displayed on the DMD. The second is Pattern mode, where the

patterns are pre-stored in flash memory and then streamed to the DMD. The allowed DMD pattern rate depends

on which mode and bit-depth is selected.

The DLP9000X DMD is controlled by the DLPC910 controller, where the DLPC910 is configured by the program

content in the DLPR910. This chipset offers streaming 1-bit binary patterns to the DMD at speeds greater than

61 Gigabits per second (Gbps). The patterns are streamed from an customer designed processor into the

DLPC910 LVDS input data interface.

Both the DLP9000 and the DLP9000X provide solutions for many varied applications including structured light,

3-D printing, video projection, and high speed lithography. The DMD is a spatial light modulator, which reflects

incoming light from an illumination source to one of two directions, with the primary direction being into a

projection or collection optic. Each application is derived primarily from the optical architecture of the system and

the format of the data being used.

10.2 Typical Applications

10.2.1 Typical Application using DLP9000

A typical embedded system application using two DLPC900 controllers and a DLP9000 DMD is shown in

Figure 17. In this configuration, the DLPC900 controller supports a 24-bit parallel RGB input, typical of LCD

interfaces, from an external source or processor. The 24-bit parallel data must be split between a left half and a

right half, each half between the two controllers. The external processor must format each half to consist of

1280x1600 plus any horizontal and vertical blanking at half the pixel clock rate. This system configuration

supports still and motion video as well as sequential pattern modes. For more information, refer to the DLPC900

digital controller data sheet listed under Related Documentation.

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Typical Applications (continued)

HEARTBEAT

FAULT_STATUS

LED

Status

Parallel

Flash

PM_ADDR[22:0],WE

DATA[15:0],OE,CS

Host

USB

I2C

USB_DN,DP

LEDs

LED EN[2:0]

I2C_SCL0, I2C_SDA0

LED PWM[2:0]

P1_A,P2_A[9:0]

P1_B,P2_B[9:0]

P1_C,P2_C[9:0]

PWM

FAN

DLPC900

Master

DMD_A,B[15:0]

DMD Control

DMD SSP

GUI

RAM

P1A_CLK, P1_DATEN

P1_VSYNC, P1_HSYNC

TRIG_OUT[1:0]

Camera

POWER RAILS

DLP9000FLS

VCC

TRIG_IN[1:0]

PWRGOOD

POSENSE Management

Power

Crystal

MOSC

TDO[1:0],TRST,TCK

RMS[1:0],RTCK

I2C_SCL1

I2C_SDA1

12V DC IN

JTAG

I2C

MOSC

P1_A,P2_A[9:0]

P1_B,P2_B[9:0]

P1_C,P2_C[9:0]

POWER RAILS

FPGA

PWRGOOD

POSENSE

DLPC900

Slave

DMD_A,B[15:0]

P1A_CLK, P1_DATEN

P1_VSYNC, P1_HSYNC

Digital Receiver

HDMI

DP

PM_ADDR[22:0],WE

DATA[15:0],OE,CS

Parallel

Flash

LED

HEARTBEAT

HDMI

DISPLAYPORT

Status FAULT_STATUS

Figure 17. DLP9000 Typical Application Schematic

10.2.1.1 Design Requirements

Detailed design requirements are located in the DLPC900 or the DLPC910 digital controller data sheets. Refer to

the data sheets listed under Related Documentation.

10.2.1.2 Detailed Design Procedure

Reference Design material exists for systems using either the DLP9000 or the DLP9000X DMD with their

respective Controllers. This reference material includes reference board schematics, PCB layouts, and Bills of

Materials. Layout guidelines for boards utilizing these controllers and DMDs can be found in the respective

DLPC900 or DLPC910 Controller data sheets. For more information, please refer to the individual controller data

sheets listed under Related Documentation.

10.2.2 Typical Application Using DLP9000X

Direct-write digital imaging is regularly used in high-end lithography printing. This mask-less technology offers a

continuous run of printing by changing the digitally created patterns without stopping the imaging head. Figure 18

shows a system where a DLPC910 digital controller is coupled with the DLP9000X DMD. This system offers an

ideal back-end imager that takes in digital images at 2560 x 1600 in resolution to achieve speeds of more than

61 Gbps. For more information, refer to the DLPC910 digital controller data sheet listed under Related

Documentation.

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Typical Applications (continued)

Illumination

Driver

Illumination

Sensor

LVDS Interface

DCLKIN(A,B,C,D),DVALID(A,B,C,D),DIN(A,B,C,D)[15:])

Row and Block Signals

USER

Interface

ROWMD(1:0),ROWAD(10:0),BLKMD(1:0),BLKAD(3:0),RST2BLKZ

Control Signals

DOUT(A,B,C,D)[15:0]

COMP_DATA,NS_FLIP,WDT_ENBLZ,PWR_FLOAT

DCLKOUT (A,B,C,D)

SCTRL(A,B,C,D)

APPS

FPGA

Connectivity

USB

Ethernet

Status Signals

RESET_ADDR(3:0)

RESET_MODE(1:0)

RST_ACTIVE,INIT_ACTIVE,ECP2_FINISHED

DLPC910

RESET_SEL(1:0)

RESET_STRB

RESET_OEZ

DLP9000XFLS

JTAG(3:0)

Volatile

And

DLPR910

PGM(4:0)

RESET_IRQZ

SCP BUS(3:0)

Non-volatile

Storage

CTRL_RSTZ

I2C

RESETZ

VLED0

VLED1

OSC

50 MHz

Power Management

Figure 18. DLP9000X Typical Application Schematic

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11 Power Supply Requirements

11.1 DMD Power Supply Requirements

The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET.

VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC900

or DLPC910 Controllers within their associated reference designs.

CAUTION

For reliable operation of the DMD, the following power supply sequencing

requirements must be followed. Failure to adhere to the prescribed power-up and

power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS,

and VRESET power supplies have to be coordinated during power-up and power-

down operations. VSS must also be connected. Failure to meet any of the below

requirements will result in a significant reduction in the DMD’s reliability and lifetime.

Refer to Figure 19.

11.2 DMD Power Supply Power-Up Procedure

•

During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

•

During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start

after VOFFSET.

•

During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

Power supply slew rates requirements during power-up are flexible, provided that the transient voltage levels

follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in

Figure 19.

•

During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at

operating voltages listed in Recommended Operating Conditions.

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11.3 DMD Mirror Park Sequence Requirements

11.3.1 DLP9000

For correct power down operation of the DLP9000 DMD, the following power down procedure must be executed.

Prior to an anticipated power removal, the controlling applications processor must command the DLPC900 to

enter Standby mode by using the Power Mode command and then wait for a minimum of 20 ms to allow the

DLPC900 to complete the power down procedure. This procedure will assure the mirrors are in a flat state.

Following this procedure, the power can be safely removed.

In the event of an unanticipated power loss, the power management system must detect the input power loss,

command the DLPC900 to enter Standby mode by using the Power Mode command, and then maintain all

operating power levels of the DLPC900 and the DLP9000 DMD for a minimum of 20 ms to allow the DLPC900 to

complete the power down procedure. Following this procedure, the power can be allowed to fall below safe

operating levels. Refer to the DLPC900 datasheet for more details on power down requirements.

In both anticipated power down and unanticipated power loss, the DLPC900 is commanded over the USB/I2C

interface, and then the DLPC900 loads the correct power down sequence to the DMD. Communicating over the

USB/I2C and loading the power down sequence accounts for most of the 20 ms. Compared to the DLPC910, the

controlling processor only needs to assert the PWR_FLOAT pin and wait for a minimum of 500 µs.

The controlling applications processor can resume normal operations by commanding the DLPC900 to enter

Normal mode. See Power Mode command in the DLPC900 Programmer’s Guide DLPU018 for a description of

this command.

11.3.2 DLP9000X

For correct power down operation of the DLP9000X DMD, the following power down procedure must be

executed.

Prior to an anticipated power removal, assert PWR_FLOAT to the DLPC910 for a minimum of 500 μs to allow the

DLPC910 to complete the power down procedure. This procedure will assure the DMD mirrors are in a flat state.

Following this procedure, the power can be safely removed.

In the event of an unanticipated power loss, the power management system must detect the input power loss,

assert PWR_FLOAT to the DLPC910, and maintain all operating power levels of the DLPC910 and the

DLP9000X DMD for a minimum of 500 μs to allow the DLPC910 to complete the power down procedure. Refer

to the DLPC910 datasheet for more details on power down requirements.

To restart after assertion of PWR_FLOAT without removing power, the DLPC910 must be reset by setting

CTRL_RSTZ low (logic 0) for 50 ms, and then back to high (logic 1), or power to the DLPC910 must be cycled.

11.4 DMD Power Supply Power-Down Procedure

•

During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are

discharged to within the specified limit of ground. Refer to Table 5.

•

During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in Recommended Operating Conditions. During power-down, it is not mandatory to stop

driving VBIAS prior to VOFFSET.

•

During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 19.

During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions.

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DMD Power Supply Power-Down Procedure (continued)

EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control

VBIAS, VOFFSET, and VRESET are disabled by DLP controller software

Note 3

Power Off

VCC / VCCI

Mirror Park Sequence

RESET_OEZ

Note 6

VSS

¸ ¸

VCC / VCCI

PWRDNZ

¸ ¸

VSS

VCC / VCCI

VCC

VCCI

¸ ¸

VSS

EN_BIAS

EN_OFFSET

EN_RESET

VSS

VCC / VCCI

¸ ¸

Note 3

VBIAS

¸ ¸

VBIAS

VBIAS < Specification

Note 1

∆V < Specification

Note 1

∆V < Specification

Note 4

VSS

VOFFSET

¸ ¸

VOFFSET < Specification

VOFFSET

Note 4

VSS

Note 5

Refer to specifications listed in Recommended Operating Conditions.

Waveforms are not to scale. Details are omitted for clarity.

VRESET < Specification

Note 4

VRESET

VRESET > Specification

VRESET

VCC

VRESET

¸ ¸

LVCMOS

Inputs

VSS

Note 2

LVDS

Inputs

¸ ¸

Figure 19. DMD Power Supply Sequencing Requirements

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DMD Power Supply Power-Down Procedure (continued)

1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in

Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power

VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.

2. During power-up, the LVDS signals are less than the input differential voltage (VID) maximum specified in

Recommended Operating Conditions. During power-down, LVDS signals are less than the high level input

voltage (VIH) maximum specified in Recommended Operating Conditions.

3. When system power is interrupted, the DLPC900 and the DLPC910 controllers initiate a hardware power-

down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park

sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park

sequence through software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET

are used to disable VBIAS, VOFFSET, and VRESET, respectively.

4. Refer to Table 5.

5. Figure not to scale. Details have been omitted for clarity. Refer to Recommended Operating Conditions.

6. Refer to DMD Mirror Park Sequence Requirements for details on powering down the DMD.

Table 5. DMD Power-Down Sequence Requirements

PARAMETER

MIN

MAX

4.0

UNIT

VBIAS

V

VOFFSET

VRESET

Supply voltage level during power–down sequence

4.0

–4.0

0.5

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12 Layout

12.1 Layout Guidelines

Each chipset provides a solution for many applications including structured light and video projection. This

section provides layout guidelines for the DMD.

12.1.1 General PCB Recommendations

The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to

IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches ±10%, using a dielectric material

with a low Loss-Tangent, for example: Hitachi 679gs or equivalent.

Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.

Refer to the digital controller data sheets listed under Related Documentation regarding DMD Interface

Considerations.

High-speed interface waveform quality and timing on the digital controllers (that is, the LVDS DMD interface) is

dependent on the following factors:

•

Total length of the interconnect system

Spacing between traces

Characteristic impedance

Etch losses

How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

•

Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI

degradation)

•

Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI

degradation)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as

simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.

Both the DLPC910 and the DLPC900 I/O timing parameters can be found in their respective data sheets.

Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI

degradation is not as easy to determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these

recommendations should be confirmed with PCB signal integrity analysis or lab measurements.

12.1.2 Power Planes

Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane

shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by

0.2".

Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid

PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital

ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes

should be connected together with a minimum distance between connections of 0.5". Extra vias are not required

if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and

signal vias should be inside the perimeter ring of ground vias.

Power and Ground pins of each component shall be connected to the power and ground planes with one via for

each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”).

Unused or spare device pins that are connected to power or ground may be connected together with a single via

to power or ground. Ground plane slots are NOT allowed.

Route VOFFSET, VBIAS, and VRESET as a wide trace >20 mils (wider if space allows) with 20 mils spacing.

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Layout Guidelines (continued)

12.1.3 LVDS Signals

The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation

such that constant differential impedance (as in section Board Stack and Impedance Requirements) is

maintained throughout the length. Avoid sharp turns and layer switching while keeping lengths to a minimum.

The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair.

12.1.4 Critical Signals

The critical signals on the board must be hand routed in the order specified below. In case of length matching

requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a

minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.

Table 6. Timing Critical Signals

GROUP

SIGNAL

CONSTRAINTS

ROUTING LAYERS

D_AP(0:15), D_AN(0:15), DCLK_AP,

DCLK_AN, SCTRL_AN, SCTRL_AP,

D_BP(0:15), D_BN(0:15), DCLK_BP,

DCLK_BN, SCTRL_BN, SCTRL_BP,

D_CP(0:15), D_CN(0:15), DCLK_CP,

DCLK_CN, SCTRL_CN, SCTRL_CP,

D_DP(0:15), D_DN(0:15), DCLK_DP,

DCLK_DN, SCTRL_DN, SCTRL_DP.

Internal signal layers. Avoid layer switching

when routing these signals.

1

Refer to Table 7 and Table 8

RESET_ADDR_(0:3),

RESET_MODE_(0:1),

RESET_OEZ,

Internal signal layers. Top and bottom as

required.

2

RESET_SEL_(0:1)

RESET_STROBE,

RESET_IRQZ.

SCP_CLK, SCP_DO,

SCP_DI, SCP_DMD_CSZ.

3

4

Any

Others

No matching/length requirement

12.1.5 Flex Connector Plating

Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of

electrolytic hard gold over a minimum of 150 micro-inches of electrolytic nickel.

12.1.6 Device Placement

Unless otherwise specified, all major components should be placed on top layer. Small components such as

ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high

frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly

around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the

case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are

side by side as much as possible and place the smaller value capacitor closer to the device.

12.1.7 Device Orientation

It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If

polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented

with the “+” terminal the same direction and likewise for the vertically oriented ones.

12.1.8 Fiducials

Fiducials for automatic component insertion should be placed on the board according to the following guidelines

or on recommendation from manufacturer:

•

Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB.

Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing

<0.05").

•

Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad).

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12.2 Layout Example

12.2.1 Board Stack and Impedance Requirements

Refer to Figure 20 regarding guidance on the parameters.

PCB design:

Configuration:

Asymmetric dual stripline

Etch thickness (T):

1.0-oz copper (1.2 mil)

0.5-oz copper (0.6 mil)

50 Ω (±10%)

Flex etch thickness (T):

Single-ended signal impedance:

Differential signal impedance:

100 Ω (±10%)

PCB stack-up:

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the I/O power plane or ground.

Dielectric material with a low Loss-Tangent,

for example: Hitachi 679gs or equivalent.

(Er): 3.8 (nominal)

5.0 mil (nominal)

34.2 mil (nominal)

Signal trace distance to reference plane 1

(H1):

Signal trace distance to reference plane 2

(H2):

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Layout Example (continued)

Figure 20. PCB Stack Geometries

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Layout Example (continued)

Table 7. General PCB Routing (Applies to All Corresponding PCB Signals)

PARAMETER

APPLICATION

SINGLE-ENDED SIGNALS

DIFFERENTIAL PAIRS

UNIT

4 .4

(0.1)

4 .3

(0.1)

mil

(mm)

Escape routing in ball field

7

4.25

(0.11)

mil

(mm)

Line width (W)

PCB etch data or control

PCB etch clocks

(0.18)

7

4.25

(0.11)

mil

(mm)

(0.18)

(1)

5.75

mil

PCB etch data or control

PCB etch clocks

N/A

–0.15

(mm)

Differential signal pair spacing (S)

(1)

5.75

mil

(mm)

–0.15

20

(0.51)

mil

(mm)

PCB etch data or control

PCB etch clocks

Minimum differential pair-to-pair

spacing (S)

20

(0.51)

mil

(mm)

4

(0.1)

4

(0.1)

mil

(mm)

Escape routing in ball field

PCB etch data or control

PCB etch clocks

10

(0.25)

20

(0.51)

mil

(mm)

Minimum line spacing to other

signals (S)

20

(0.51)

20

(0.51)

mil

(mm)

10

–0.25

mil

(mm)

Maximum differential pair P-to-N

length mismatch

Total data

N/A

10

–0.25

mil

(mm)

Total data

(1) Spacing may vary to maintain differential impedance requirements

Table 8. DMD Interface Specific Routing

SIGNAL GROUP LENGTH MATCHING

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

± 50

(± 1.3)

mil

(mm)

SCTRL_AN / SCTRL_AP

D_AP(15:0)/ D_AN(15:0)

DMD (LVDS)

DCKA_P/ DCKA_N

± 50

(± 1.3)

mil

(mm)

SCTRL_BN/ SCTRL_BP

D_BP(15:0)/ D_BN(15:0)

DMD (LVDS)

DCKB_P/ DCKB_N

DCK_CP/ DCK_CN

± 50

(± 1.3)

mil

(mm)

SCTRL_CN/ SCTRL_CP

D_CP(15:0)/ D_CN(15:0)

± 50

(± 1.3)

mil

(mm)

SCTRL_DN/ SCTRL_DP

D_DP(15:0)/ D_DN(15:0)

Number of layer changes:

•

Single-ended signals: Minimize

Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair

should not change layers.

(1)

Table 9. DMD Signal Routing Length

BUS

MIN

MAX

UNIT

DMD (LVDS)

50

375

mm

(1) Max signal routing length includes escape routing.

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Stubs: Stubs should be avoided.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω

internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements should be used:

•

Differential crosstalk: <5%

Differential impedance: 75 to 125 Ω

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed

in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference

for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should

be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers

shall have the predominant traces routed orthogonal to each other.

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Device Handling

All external signals on the DMD are protected from damage by electrostatic discharge, and are tested in

accordance with JESD22-A114-B electrostatic discharge (ESD) sensitivity testing human body model (HBM).

Table 10. DMD ESD Protection Limits

PACKAGE TERMINAL TYPE

VOLTAGE (MAXIMUM)

UNIT

V

Input

Output

2000

V

VCC

V

VCCI

V

VOFFSET

VBIAS

V

VRESET

All MBRST

V

All CMOS devices require proper Electrostatic Discharge (ESD) handling procedures. Refer to drawing 2504641

DMD Handling Specification, for precautions to protect the DMD from ESD and to protect the DMD’s glass and

electrical contacts. Refer to drawing 2504640 DMD Glass Cleaning Procedure, for correct and consistent

methods for cleaning the glass of the DMD, in such a way that the anti-reflective coatings on the glass surface

are not damaged.

13.1.2 Device Nomenclature

Figure 21 provides a legend for reading the complete device name for any DLP device.

Table 11. Package-Specific Information

PACKAGE TYPE

ALTERNATE NAME

FLS

LCCC

DLP9000 _ _ FLS

Package Type

Revision

Speed Grade

Blank = Standard Speed

X

= High Speed

Device Descriptor

Figure 21. Device Nomenclature

50

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13.1.3 Device Markings

The device marking will include both human-readable information and a 2-dimensional matrix code. The human-

readable information is described in Figure 22. The 2-dimensional matrix code is an alpha-numeric character

string that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first

character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial

Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias

voltage bin letter.

TI Internal Numbering

2 Dimensional Matrix Code

(DMD Part Number and

DMD Part Number

Serial Number)

YYYYYYY

DLP9000_ _ FLS

GHXXXXX LLLLLLM

LLLLLL

Part 2 of Serial Number

(7 characters)

Part 1 of Serial Number

(7 characters)

TI Internal Numbering

Figure 22. DMD Markings

13.2 Documentation Support

13.2.1 Related Documentation

The following documents contain additional information related to the use of the DLP9000 family of devices:

•

DLPC900 Digital Controller Data Sheet (DLPS037)

DLPC900 Software Programmer's Guide (DLPU018)

DLPC910 Digital Controller Data Sheet (DLPS064)

DLPR910 Configuration PROM Data Sheet (DLPS065)

13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

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13.4 Trademarks

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14.1 Thermal Characteristics

Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the

maximum temperature of any individual micromirror in the active array and the temperature gradient between

any two points on or within the package.

Refer to Absolute Maximum Ratings and Recommended Operating Conditions regarding applicable temperature

limits.

14.2 Package Thermal Resistance

The DMD is designed to conduct the absorbed and dissipated heat back to the series FLS package where it can

be removed by an appropriate thermal management system. The thermal management system must be capable

of maintaining the package within the specified operational temperatures at the thermal test point locations (refer

to Figure 15 or Micromirror Array Temperature Calculation). The total heat load on the DMD is typically driven by

the incident light absorbed by the active area; although other contributions can include light energy absorbed by

the window aperture, electrical power dissipation of the array, and parasitic heating. For the thermal resistance,

refer to Thermal Information.

14.3 Case Temperature

The temperature of the DMD case can be measured directly. For consistency, a thermal test point location is

defined as shown in Figure 15 and Micromirror Array Temperature Calculation.

52

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLP9000XBFLS
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.90 高速 WQXGA A 型 DMD \| FLS \| 355 \| 0 to 70 商用集成电路
文件：	总60页 (文件大小：1070K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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