DLPA2005ERSLR [TI]
DLP® PMIC/LED driver for DLP2010 and DLP2010NIR (0.2 WVGA) DMDs | RSL | 48 | -10 to 85;
| 型号： | DLPA2005ERSLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® PMIC/LED driver for DLP2010 and DLP2010NIR (0.2 WVGA) DMDs | RSL | 48 | -10 to 85 驱动 集成电源管理电路 接口集成电路 |
| 文件： | 总56页 (文件大小：1910K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
DLPA2005 电源管理和 LED/灯驱动器 IC
1
1 特性
•
高效红-绿-蓝三色 (RGB) 发光二极管 (LED)/灯驱动
–
–
–
光传感器（用于白点修正）
内部基准电压
器，在小型芯片级封装中集成了降压/升压 DC-DC
转换器、数字微镜器件 (DMD) 电源、数字电源外
设 (DPP) 内核电源、1.8V 负载开关以及测量系统
外部（热敏电阻）温度传感器
•
•
监视和保护电路
•
三个用于通道选择的低阻抗（27°C 时典型值为
30mΩ）金属氧化物半导体场效应晶体管
(MOSFET) 开关
–
–
–
–
–
热模警告和热关断
低电池电压警告
可编程的电池欠压闭锁 (UVLO)
负载开关 UVLO
•
•
每个通道具有独立的 10 位电流控制
针对 DLPA2005 嵌入式应用的最大 LED 电流为
2.4A
过流和欠压保护
•
DMD 调节器
DLPA2005 QFN 封装
–
–
–
–
–
仅需一个电感器
–
–
48 引脚 0.4mm 间距
VOFS：10V
芯片尺寸：6.0mm × 6.0mm ± 0.15mm
VBIAS：18V
2 应用
VRST：–14V
DLP® Pico™投影仪
DLP®移动传感
当禁用时对接地 (GND) 被动放电
•
DPP 1.1V 内核电源
–
具有集成开关场效应晶体管 (FET) 的同步降压
转换器
3 说明
DLPA2005 是一款专用于 DLP2010、DLP2010NIR 和
DLP3010 数字微镜器件 (DMD) 的电源管理多通道 IC
(PMIC)/RGB LED/灯驱动器，与 DLPC3430、
DLPC3433、DLPC3435、DLCP3438 或 DLPC150 数
字控制器搭配使用。为确保这些芯片组可靠运行，必须
与 DLPA2000 或 DLPA2005 搭配使用。
–
支持高达 600mA 的输出电流
•
•
VLED 降压/升压转换器
轻负载电流状态下的省电模式
低阻抗负载开关
–
–
–
–
VIN 范围为 1.8V 至 3.6V
支持高达 200mA 的电流
器件信息(1)
当禁用时对接地 (GND) 被动放电
器件型号
DLPA2005
封装
封装尺寸（标称值）
•
•
•
DMD 复位信号生成和电源排序
33MHz 串行外设接口 (SPI)
用于测量模拟信号的多路复用器
6.00mm × 6.00mm
± 0.150mm
VQFN (48)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
电池电压
LED 电压，LED 电流
DC_IN
Charger
BAT
...
2.3V-5.5V
Projector Module Electronics
DC Supplies
1.8V
VSPI
Other
Supplies
1.8V
1.1V
1.8V
1.1V
Reg
On/Off
L3
SYSPWR
1.8V
VDD
HDMI
VGA
HDMI
Receiver
PROJ_ON
PROJ_ON
VLED
Current
Sense
L1
L2
Triple
ADC
GPIO_8 (Normal Park)
SPI_0
Keystone
Sensor
DLPA2005
FLASH
Cal data
(optional)
4
Front-End
Chip
RED
GREEN
BLUE
EEPROM
SPI_1
4
FLASH,
SDRAM
RESETZ
INTZ
I2C_1
- OSD
- AutoLock
- Scaler
PARKZ
HOST_IRQ
BIAS, RST, OFS
3
LED_SEL(2)
CMP_PWM
Illumination
Optics
DLPC3430/
DLPC3435
WPC
LABB
- uController
Keypad
Parallel I/F
28
CMP_OUT
eDRAM
DLP2010
DMD)
SD Card
Reader,
etc.
(optional)
Thermistor
I2C
(WVGA
Sub-LVDS DATA
CTRL
1.8V
1.1V
VIO
VCC_INTF
VCC_FLSH
VCORE
Spare R/W
GPIO
18
TVP5151
BT.656
CVBS
Video
Decoder
Included in DLP® Chip Set
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: DLPS047
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 25
7.5 Register Maps......................................................... 27
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Projector Application .................................. 38
8.3 Typical Mobile Sensing Application ....................... 40
Power Supply Recommendations...................... 43
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Data Transmission Timing Requirements............... 10
6.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 44
10.3 Thermal Considerations........................................ 45
11 器件和文档支持 ..................................................... 46
11.1 器件支持................................................................ 46
11.2 商标....................................................................... 46
11.3 静电放电警告......................................................... 46
11.4 Glossary................................................................ 46
12 机械、封装和可订购信息....................................... 46
7
4 修订历史记录
Changes from Revision A (September 2014) to Revision B
Page
•
•
•
•
已更新标题.............................................................................................................................................................................. 1
已添加 移动传感应用 .............................................................................................................................................................. 1
Updated Detailed Description .............................................................................................................................................. 12
Added new Typical Mobile Sensing application in Application Information ......................................................................... 38
Changes from Original (August 2014) to Revision A
Page
•
•
已更新特性, 应用, 和 说明 ...................................................................................................................................................... 1
已更改 器件状态“产品预览”至“量产数据”并发布了完整文档。................................................................................................ 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
5 Pin Configuration and Functions
DLPA2005 VQFN Package
(BOTTOM VIEW)
Package Marking DLPA2005
(TOP VIEW)
PGNDR
SWN
VINC
12
11
10
9
25
26
27
28
29
30
31
32
33
34
35
36
PWM_IN
PROJ_ON
CMP_OUT
VCORE
SENS2
VINR
TI
= TI LETTERS
SPI_DOUT
SPI_CSZ
SPI_CLK
INTZ
YM = YEAR / MONTH DATE CODE
LLLL = ASSY LOT CODE
PAD2005
A4
8
S
= ASSEMBLY SITE CODE
PER QSS 005-120
7
LED_SEL0
VSPI
6
TI YMS$$
LLLL G4
$$
= WAFER FAB CODE
(1 or 2 CHARACTERS)
=pin 1 Marking
AGND1
RESETZ
SPI_DIN
VINL
5
SENS1
4
LED_SEL1
V6V
3
2
VINL
RLIM_K
1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
1
2
VINL
I
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
SPI_DIN
RESETZ
AGND1
INTZ
3
I
SPI data input
4
O
Reset output to the DLP system (active low). Pin is held low to reset DLP system.
Analog ground. Connect to ground plane.
5
GND
6
O
Interrupt output signal (open drain). Connect to pullup resistor or short to ground.
Clock input for SPI interface
SPI_CLK
SPI_CSZ
7
I
8
I
SPI chip select (active low)
SPI_DOUT
VINR
9
O
SPI data output
10
11
12
13
14
15
I
I
Power supply input for DMD switch mode power supply (SMPS). Connect to system power.
Connection for the DMD SMPS-inductor (high-side switch).
Power ground for DMD SMPS. Connect to ground plane.
Connection for the DMD SMPS-inductor (low-side switch).
Connection to VRST for fast discharge function
VBIAS output rail. Connect to ceramic capacitor.
SWN
PGNDR
SWP
GND
O
CNTR_VRST
VBIAS
O
O
Previously reference pin for the VRST regulator. On A4 design this reference is internal to
DLPA2005 chip.
No Connect
16
I
VOFS
17
18
19
20
21
22
23
24
25
26
27
O
VOFS output rail. Connect to ceramic capacitor.
VINA
POWER Power supply input for sensitive analog circuitry
V2V5
O
Internal supply filter pin for digital logic; typical 2.5 V
Ground connection to be connected to ground plane.
Load switch
GND
GND
LS_OUT
LS_IN
PGNDC
SWC
O
I
Load switch
GND
Power ground for VCORE BUCK
I/0
Connection for 1.1-V BUCK inductor
VINC
I
I
I
Power supply input for VCORE BUCK power stage. Connect to system power.
Reference voltage input for analog comparator.
Input signal to enable or disable the IC and DLP projector.
PWM_IN
PROJ_ON
Copyright © 2014–2015, Texas Instruments Incorporated
3
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
CMP_OUT
VCORE
SENS2
NUMBER
28
29
30
31
32
33
34
35
O
I
Analog-comparator output.
VCORE BUCK converter feedback pin.
I
Input signal from temperature sensor.
LED_SEL0
VSPI
I
Digital input to the RGB Strobe Decoder
I
Power supply input for SPI interface. Connect to system I/O voltage.
Input signal from light sensor.
SENS1
I
LED_SEL1
V6V
I
Digital input to the RGB Strobe Decoder
O
Internal supply filter pin for gate driver circuitry. Typical 6.25 V
Kelvin sense connection to top side of LED current sense resistor.
RLIM_K
36
I
For best accuracy, route this trace directly to the top of the current sense resistor and
separate it from the normal trace from the current sense resistor to the RLIM pins.
SW6
SW5
SW4
37
38
39
O
O
O
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Connection to LED ‘current sense’ resistor.
Bottom side of sense resistor is connected to GND.
RLIM
40
O
VLED
L2
41 / 42
43 / 44
45 / 46
47 / 48
O
I
VLED BUCK-BOOST converter output pin.
Connection for VLED BUCK-BOOST inductor.
Power ground for VLED BUCK-BOOST. Connect to ground plane.
Connection for VLED BUCK-BOOST inductor.
PGNDL
L1
GND
O
4
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.3
–0.3
–18
MAX
7
UNIT
V
Input voltage at VINL, VINA, VINR, VINC
Ground pins to system ground
Voltage at SWN
0.3
7
V
V
Voltage at SWP, VBIAS
–0.3
–0.3
–0.3
–0.3
20
12
7
V
Voltage at VOFS
V
Voltage at V6V, VLED, L1, L2, SWC, SW4, SW5, SW6, INTZ, PROJ_ON
Voltage at all pins, unless noted otherwise
Source current RESETZ, CMP_OUT
Source current SPI_DOUT
V
3.6
1
V
mA
mA
mA
mA
5.5
1
Sink current RESETZ, CMP_OUT
Sink current SPI_DOUT, INTZ
Peak output current
5.5
Internally limited
Internally limited by thermal
shutdown
Continuous total power dissipation
TJ
Tstg
Operating junction temperature
Storage temperature
–30
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN
2.7
NOM
3.6
MAX UNIT
Full functional and parametric performance
6
6
V
Input voltage at VINL, VINA,
VINR, VINC,
Extended operating range, limited parametric performance
2.3
3.6
Voltage at VSPI
1.65
–10
–10
1.8
3.6
85
V
Operational ambient temperature
Operational junction temperature
°C
°C
120
6.4 Thermal Information
DLPA2005
THERMAL METRIC(1)
UNIT
°C/W
RSL (48 PINS)
RθJA
Junction-to-ambient thermal resistance(2)
27.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm × 114.3 mm, and
2-oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
Copyright © 2014–2015, Texas Instruments Incorporated
5
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (see
(1)(2)(3)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
SUPPLIES
INPUT VOLTAGE
Input voltage range
Extended input voltage range(1)
Low-battery warning threshold
Hysteresis
2.7
2.3
3.6
3.6
3
6
V
6
VIN
VINA, VINR, VINL, VINC
VINA falling
V
VLOW_BAT
VINA rising
100
mV
Undervoltage lockout threshold
Hysteresis
VINA falling (through 5-bit trim function)
VINA rising
2.3
2.5
4.5
V
mV
V
Vhys(UVLO)
100
VSTARTUP
Startup voltage
VBIAS, VOFS, VRST; loaded with 2 mA
INPUT CURRENT
IQ
ACTIVE mode
STANDBY mode
IDLE mode
Motor current excluded
15
900
10
mA
µA
µA
ISTD
IIDLE
INTERNAL SUPPLIES
VV6V
Internal supply, analog
6.25
100
2.5
V
nF
V
CLDO_V6V
VV2V5
Filter capacitor for V6V LDO
Internal supply, logic
CLDO_V2V5
Filter capacitor for V2V5 LDO
2.2
µF
DMD REGULATOR
Switch E (from VINR to SWN)
Switch F (from SWP to PGNDR)
1000
320
RDS(ON) MOSFET ON-resistance
mΩ
Switch G(2) (from SWP to VBIAS[2])
VINR = 5 V, VSWP = 2 V, IF = 100 mA
1.3
1.3
VFW
Forward voltage drop
V
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA
tDIS
tPG
ILIMIT
L
Rail discharge time
Power-good timeout
Switch current limit
Inductor value
VIN = 2.9 V; COUT = 110 nF
Not tested in production
40
µs
ms
mA
µH
6
312
10
VOFS REGULATOR
Output voltage
10
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
2%
VOFS
VIN = 3.6 V, IOUT = 0 to 2 mA
–19
35
V/A
VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2
mA
DC line regulation
mV/V
VRIPPLE
IOUT
Output ripple
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF(4)
375
mVpp
mA
Output current
0
3
VOFS rising
86%
66%
100
Power-good threshold
(fraction of nominal output voltage)
PG
VOFS falling
RDIS
Output discharge resistor
Active when rail is disabled
Ω
Recommended value (output capacitors for
VOFS / VBIAS must be equal)
110
100
220
nF
nF
COUT
Output capacitor
tDISCHARGE < 40 µs at 2.9 V
110
(1) Fully functional but limited parametric performance
(2) Including rectifying diode
(3) Typicals are at 25 C.
(4) To reduce ripple the COUT can be increased. VRIPPLE is inversely proportional to COUT
.
6
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)(3)
)
PARAMETER
VBIAS REGULATOR
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output voltage
18
V
DC output voltage accuracy
DC Load regulation
IOUT = 2 mA
–2%
2%
VBIAS
VIN = 3.6 V, IOUT = 0 to 2 mA
–14
18
V/A
VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2
mA
DC Line regulation
mV/V
mVpp
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF
VRIPPLE
IOUT
Output ripple
375
(4)
(see
)
Output current
0
4
mA
VBIAS rising
86%
66%
100
Power-good threshold
(fraction of nominal output voltage)
PG
VBIAS falling
RDIS
Output discharge resistor
Active when rail is disabled
Ω
Recommended value (output capacitors for
VOFS / VBIAS must be equal)
110
100
220
COUT
Output capacitor
nF
tDISCHARGE < 40 µs at 2.9 V
110
3%
VRST REGULATOR
Output voltage
–14
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–3%
VRST
VIN = 3.6 V, IOUT = 0 to 2 mA
13
V/A
VINA, VINL, VINR, VINC 2.7 to 6 V, IOUT = 2
mA
DC line regulation
Output ripple
–21
mV/V
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF
VRIPPLE
375
500
mVpp
(4)
(see
)
VREF_VRST
IOUT
Reference voltage
Output current
mV
mA
0
4
VRST rising
90%
90%
±150
220
Power-good threshold (fraction of
nominal output voltage)
PG
VRST falling
RDIS
Output discharge resistor
Output capacitor
Active when rail is disabled
Ω
110
100
COUT
nF
tDISCHARGE < 70 µs at VBAT ≥ 2.7 V
110
LED DRIVER
VLED BUCK-BOOST
Output voltage range
1.2
5.5
3.5
5.4
7
VLED
V
Default output voltage
Output overvoltage protection
Fault detection threshold
Switch current limit
SW4, SW5, SW6 in OPEN position
Clamps buck-boost output
3.5
VOVP
V
V
A
VLED_OVP
ISW
Triggers VLED_OVP interrupt
5.4
4.0
4.5
Switch A (from VINL to L1)
Switch B (from L1 to PGNDL)
Switch C (from L2 to PGNDL)
Switch D (from L2 to VLED)
50
50
RDS(ON)
MOSFET ON-resistance
mΩ
50
50
fSW
Switching frequency
Output capacitance
2.25
2 × 22
MHz
µF
COUT
RGB STROBE CONTROLLER SWITCHES
RDS(ON)
ILEAK
Drain-source ON-resistance
OFF-state leakage current
SW4, SW5, SW6
VDS = 5 V
30
75
1
mΩ
µA
Copyright © 2014–2015, Texas Instruments Incorporated
7
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)(3)
)
PARAMETER
LED CURRENT CONTROL
TEST CONDITIONS
MIN
TYP
Vƒ
LED forward voltage
4.55
V
VIN ≥4.50 V, VLED ≤4.8 V; (closed loop
operation)
Covers USB power and 5 V AC adapter
Current at max. code 0x3CBh for
SWx_IDAC[9:0]
2200
2400
2600
RLIM =39mΩ, 0.1%, TA ≤45°C (see register
settings)
LED Currents
mA
VIN ≥ 2.7 V, VLED ≤4.8 V, (closed loop
operation)
Covers single cell Li-ion battery with high
current loading
Current at max. code 0x20Eh for
SWx_IDAC[9:0]
1300
ILED
RLIM = 39 mΩ, 0.1%, TA=25 C (see register
settings)
DC current accuracy, SW4, 5, 6
Transient LED current limit range
RLIM = 39 mΩ
±100
333
mA
mA
ILIM[3
:0] =
0000
at RLIM = 39 mΩ
ILIM[3
:0] =
3846
1111
ILED from 5% to 95%, ILED = 300 mA,
Transient current limit disabled
Not tested in production
trise
Current rise time
50
µs
1.1-V REGULATOR
VCORE (BUCK)
VIN
Input voltage
2.3
6
V
V
Nominal fixed output voltage
1.1
VOUT
0 mA ≤ IOUT ≤ 600 mA at VIN > 2.5 V
VOUT = 1.1 V
DC output voltage accuracy
–1.5%
1.5%
d
Maximum duty cycle
100%
380
Low-side MOSFET on-resistance
High-side MOSFET on-resistance
Output current
185
240
300
1
mΩ
mΩ
mA
A
RDS(ON)
VIN = 3.6 V, TJ = 27ºC
VIN > 2.3 V
480
IOUT
600
ILIMIT
Switch current limit
Time to ramp from 10% to 90% of VOUT, VIN
= 3.6 V
tSS
Soft-start time
250
µs
COUT
Output capacitance
Nominal Inductance
10
µF
µH
L
2.2
LOAD SWITCH
VIN
Input voltage range
LS_IN
1.8
3.6
385
12
V
RDS(ON)
P-channel MOSFET on-resistance
Output capacitor
VIN = 1.8 V, over full temperature range
340
10
mΩ
µF
Ceramic
Ceramic
4.7
5
COUT
ESR of output capacitor
20
500
mΩ
MEASUREMENT SYSTEM (AFE)
AFE_GAIN[1:0] = 01
AFE_GAIN[1:0] = 10
AFE_GAIN[1:0] = 11
1.0
9.5
18
G
Amplifier gain (PGA)
V/V
8
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)(3)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PGA, AFE_CAL_DIS = 1
Not tested in production
–1
1
mV
1.5
VOFS
Input referred offset voltage
Comparator
Not tested in production
–1.5
To 1% of final value (not tested in
production)
15
µs
52
tsettle
Settling time
To 0.1% of final value (not tested in
production)
ƒsample
Sampling rate
Not tested in production
19
kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
IO = 0.5-mA sink current
(RESETZ, CMP_OUT)
0
0
0.3
VOL
Output low-level
V
IO = 5-mA sink current
(SPI_DOUT, INTZ)
0.3 ×
VSPI
IO = 0.5-mA source current
(RESETZ, CMP_OUT)
1.3
2.5
VOH
Output high-level
Input low-level
V
IO = 5-mA source current
(SPI_DOUT)
0.7 ×
VSPI
VSPI
0.4
PROJ_ON, LED_SEL0, LED_SEL1
SPI_CSZ, SPI_CLK, SPI_DIN
PROJ_ON, LED_SEL0, LED_SEL1
SPI_CSZ, SPI_CLK, SPI_DIN
0
VIL
V
V
0.3 ×
VSPI
0
1.2
VIH
Input high-level
Input bias current
Deglitch time
0.7 ×
VSPI
VSPI
0.5
IBIAS
VIO = 3.3 V, any input pin
µA
ms
PROJ_ON, (not tested in production)
1
tDEGLITCH
LED_SEL0, LED_SEL1 pins (not tested in
production)
300
ns
INTERNAL OSCILLATOR
Oscillator frequency
Frequency accuracy
THERMAL SHUTDOWN
9
MHz
ƒOSC
TA = –30 to 85°C
–10%
10%
Thermal warning (HOT threshold)
120
10
TWARN
°C
°C
Hysteresis
Thermal shutdown (TSD threshold)
Hysteresis
150
15
TSHTDWN
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6.6 Data Transmission Timing Requirements
VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted)
MIN
0
TYP
MAX
UNIT
MHz
ns
ƒCLK
tCLKL
tCLKH
tt
Serial clock frequency
36
Pulse width low, SPI_CLK, 50% level
Pulse width high, SPI_CLK, 50% level
Transition time, 20% to 80% level, all signals
SPI_CSZ falling to SPI_CLK rising, 50% level
SPI_CLK falling to SPI_CSZ rising, 50% level
SPI_DIN data setup time, 50% level
SPI_DIN data hold time, 50% level
SPI_DOUT data setup time(1)), 50% level
SPI_DOUT data hold time(1), 50% level
SPI_CLK falling to SPI_DOUT data valid, 50% level
SPI_CSZ rising to SPI_DOUT HiZ
10
10
0.2
8
ns
4
1
ns
tCSCR
tCFCS
tCDS
tCDH
tiS
ns
ns
7
6
ns
ns
10
0
ns
tiH
ns
tCFDO
tCSZ
13
6
ns
ns
(1) The DLPC3430/DLPC3435 processors send and receive data on the falling edge of the clock.
SPI_CSZ
(SS)
tCSCR
tCLKL
tCLKH
tCFCS
SPI_CLK
(SCLK)
tCDS
tCDH
SPI_DIN
(MOSI)
tCFDO
tiH
tCSZ
tiS
SPI_DOUT
(MISO)
HiZ
HiZ
Figure 1. SPI Timing Diagram
10
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6.7 Typical Characteristics
The maximum output current of the buck-boost is a function of input voltage (VIN), and output voltage (VLED).
The relationship between VIN, VLED, and MAX ILED is shown in Figure 2. Please note that VLED is the output
of the buck-boost regulator, which includes the voltage drop across the sense resistor RLIM (39 mOhms typical),
internal strobe control switch (75 mΩ max), and the forward voltage of the LED. For example, to drive 2.4 A of
current through a LED with Vƒ = 4.8 V using the DLPA2005, the minimum input voltage needs to be 4.5 V.
2.3 V < VLED < 4.8 V
Figure 2. Maximum LED Output Current as a Function of
Input Voltage (VIN) and Buck-Boost Output Voltage (VLED)
NOTE
Measured on a typical unit. VLED is the output of the buck-boost regulator and includes
the voltage drop across the sense resistor, internal strobe control switch, and the forward
voltage of the LED.
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7 Detailed Description
7.1 Overview
The DLPA2005 is a power management and LED driver IC optimized for DLP video and data display systems.
DLPA2005 is part of the chipset comprising of either DLP2010 (.2WVGA) DMD and DLPC3430/DLPC3435
controller, the DLP2010NIR (.2WVGA-NIR) DMD and DLPC150 controller, or the DLP3010 (.3 720p) DMD and
DLPC3433/DLPC3438 controller. The DLPA2005 contains a complete LED driver including high efficiency power
convertors. The DLPA2005 can supply up to 2.4 A per LED. Integrated high-current switches are included for
sequentially selecting R, G, and B LEDs. The DLPA2005 also contains three regulated DC supplies for the DMD
reset circuitry: VBIAS, VRST and VOFS, as well as a regulated DC supply of 1.1 V and a load switch for the 1.8
V to support the controllers. The DLPA2005 has a SPI used for setting the configuration. Using SPI, currents can
be set independently for each LED with 10-bit resolution. Other features included are the generation of the
system reset, power sequencing, input signals for sequentially selecting the active LED, IC self-protections, and
an analog MUX for routing analog information to an external ADC.
7.2 Functional Block Diagram
VINA
V2V5
V6V
REFERENCE
SYSTEM
VREF
VLED
From system power
LDO_V2V5
LDO_V6V
2.2µ
1µ
UVLO
VREF
VLED_OVP
100n
LOW_BAT
VREF
VINL
L1
From system power
GND
A
B
C
D
SET_LOW_BAT_USB
1µ
PGNDL
L2
VLED
BUCK-BOOST
AFE_GAIN [1:0]
AFE_SEL[3:0]
2.2µ
VINA/3
VLED/3
SW4
AFE
PWM_IN
From host
To host
SW5
CMP_OUT
SW6
RLIM_K
VREF
VLED
MUX
22µ
22µ
SW4
SW5
SW6
SENS1
SENS2
From light sensor
RGB
From temperature sensor
STROBE
DECODER
RLIM
VINR
RLIM
From system power
VRST
RLIM_K
E
10µ
SWN
SWP
220n
VINC
SWC
10µ
From system power
H
CNTR_VRST
G
2.2uH
Vout DCDC1 (0.9-1.2V @ 450mA)
F
DMD
RESET
REGULATORS
VCORE
BUCK
220n
220n
PGNDR
VBIAS
VOFS
10µF
GND
VBIAS
VOFS
VCORE
LS_IN
from any 1.8V-3.3V supply
to system load
LS_OUT
Load Switch
10mF
V2V5
PROJ_ON
LED_SEL0
LED_SEL1
RESETZ
From host
From host
From host
To system
0.1u
DIGITAL
CORE
VSPI
SPI_CSZ
SPI_CLK
SPI_DIN
VIO (depends on DPP requirements)
5k
From host
From host
INTZ
GND
To DPP (optional)
From host
From host
SPI
SPI_DOUT
To host
A. Pin names refer to DLPA2005 pinout
B. Pins connected to ‘system power’ can be locally decoupled with the capacity as indicated in the block diagram. At
least adequate decoupling capacity (50 μF or more) should be connected at the location the supply is entering the
board.
12
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7.3 Feature Description
7.3.1 DMD Regulators
DLPA2005 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and
VRST. After pulling the PROJ_ON pin high, the DMD is first initialized followed by a power-up of the VOFS line
after a small delay of less than 10 ms followed by VBIAS and VRST with an additional delay of 145 ms. The LED
driver and STROBE DECODER circuit can only be enabled after all three rails are enabled. There are two
power-down sequences, the normal power-down timing initiated after pulling the PROJ_ON pin low, and a fast
power-down mode where if any one of the rails encounters a fault such as an output short, all three rails are
discharged simultaneously. The detailed power-up and power-down diagrams are shown in Figure 3 and
Figure 4.
5 ms (min)
System Power
(VINx)
10 ms
25 ms
PROJ_ON
DMD_EN
in register 0x01h
V2V5
Stop Regulating
VBIAS
VBIAS
Pad DMD_EN
by DPP through
VOFS
SPI write
VRST
Stop Regulating
VRST
10 ms
DMD
initialization
by DPP
≤ 10 ms
145 ms
≥10 ms
VCORE
LS_OUT (1.8 V)
VLED
INTZ
Startup DPP
RESETZ
ACTIVE1
OFF
STANDBY
ACTIVE2
OFF
STATE
Figure 3. Power Sequence Normal Shutdown Mode
NOTE
All values are typical (unless otherwise noted).
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Feature Description (continued)
Fault Condition
5 ms (min)
System Power
(VINx)
PROJ_ON
DMD_EN
in register 0x01h
V2V5
Stop Regulating
VBIAS
VBIAS Delay
VBIAS
Pad DMD_EN
by DPP through
VOFS
VOFS
Delay
SPI write
VRST
VRST Delay
10 ms
DMD
initialization
by DPP
≤ 10 ms
145 ms
Stop Regulating
VRST
≥ 10 ms
VCORE
LS_OUT (1.8V)
VLED
INTZ
Startup DPP
RESETZ
RESETZ Delay
ACTIVE1
OFF
STANDBY
ACTIVE2
STANDBY
STATE
(1) If the FAULT condition happens and its associated interrupt is masked in the Interrupt Mask Register (0Dh), the INTZ
does not go low, but all other timing shown in the diagram is unaffected.
Figure 4. Power Sequence Fault Shutdown Mode
NOTE
All values are typical (unless otherwise noted).
7.3.2 RGB Strobe Decoder
DLPA2005 contains RGB color-sequential circuitry that is composed of three NMOS switches, the LED driver,
the strobe decoder, and the LED current control. The NMOS switches are connected to the terminals of the
external LED package and turn the currents through the LEDs on and off. Package connections are shown in
Figure 5 and Figure 9 and corresponding switch map in Table 1.
The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then
back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based
on the color selected, and a 10-bit current control DAC for this color is selected that provides a control current to
the RGB LEDs feedback control network.
14
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Feature Description (continued)
VLED
SW4
SW5
SW6
R
G
B
SW4
SW5
SW6
RLIM
RLIM_K
RLIM
RBOT_K
Figure 5. Switch Connection for a Common-Anode LED Assembly
Table 1. Switch Positions for Common Anode RGB LEDs (MAP = 0)
Common Anode
LED_SEL[1:0]
0x00h
SW6
Open
Open
Open
Closed
SW5
Open
Open
Closed
Open
SW4
Open
Closed
Open
Open
IDAC Input
N/A
0x01h
SW4_IDAC[9:0]
SW5_IDAC[9:0]
SW6_IDAC[9:0]
0x02h
0x03h
The switching of the three NMOS switches is controlled such that switches are returned to the open position first
before the closed connections are made (break before make). The dead time between opening and closing
switches is controlled through the BBM register. Switches that already are in the closed position (and are to
remain in the closed state according to the SWCNTRL register) are not opened during the BBM delay time.
BBM dead time
SW6
SW4
SW5
SW6
SW4
TIME
Figure 6. BBM Timing (See Register 0Bh in Table 20)
7.3.3 LED Current Control
DLPA2005 provides time-sequential circuitry to drive three LEDs with independent current control. A system
based on a common anode LED configuration is shown in Figure 9 and consists of a buck-boost converter,
which provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, an RLIM
resistor used to sense the LED current, and a current DAC to control the LED current. The voltage measured at
the pin V(RLIM_K) is used by the regulator loop.
The STROBE DECODER controls the switch positions as described in the previous section (RGB Strobe
Decoder ). With all switches in the open position, the buck-boost output assumes an output voltage of 3.5 V.
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For a common-anode RGB LED configuration, the buck-boost output voltage (VLED) assumes a value such that
the voltage drop across the sense resistor equals
SPACE
(SW4_IDAC[9:0]Ivalue + ILED) × RLIM
(1)
SPACE
when SW4 is closed. The exact value of VLED depends on the current setting and the voltage drop across the
LED but is limited to 5.4 V. When the STROBE decoder switches from SW4 to SW5, the buck-boost assumes a
new output voltage such that the sense voltage equals:
SPACE
(SW5_IDAC[9:0]Ivalue + ILED) × RLIM
(2)
SPACE
and finally when SW6 is selected.
SPACE
(SW6_IDAC[9:0]Ivalue + ILED) × RLIM
(3)
SPACE
7.3.4 Maximum Led Currents and Efficiency Considerations
The DLPA2005 comprises a buck-boost power converter to supply the appropriate VLED to the LEDs. The
maximum obtainable LED current for a given LED forward voltage are limited by three items:
•
•
•
•
The inherent maximum LED current of the PAD2005, i.e. for DAC setting 03FFh.
The maximum input current of about 4 A.
The converter efficiency.
Junction and ambient temperature
In the Figure 2 graph the LED current versus DAC setting is given for several supply voltages (VIN). The load
was configured for each supply case such that at the maximum attainable current VOUT max=4.8 V.
For the higher supply voltages VIN>4.5 V the DAC current increases linearly up to the max setting of 3FFh. At
that setting the ILED is about 2.5 A. For VIN=2.3 V and VIN=2.7 V the LED current is typically limited to 0.9 A
and 1.3 A, respectively. Main reason of this limitation is the maximum input current in combination with the
limited converter efficiency. This can be understood by looking at the equation describing the power conversion:
SPACE
VOUT ∂ IOUT
=heff ∂VIN ∂ IIN
This equation states that the output power of the converter is equal to the input power times the converter
efficiency. As indicated above, the input current IIN of the power converter is maximized to about 4A. The neff is
the efficiency of the power converter, as described further down this section. For the lower input voltage the
power converter runs as a boost converter.
(VOUT=4.8 V). Assuming 100% efficiency, VIN=2.3 V, VOUT=4.8 V and IINmax=4 A, the maximum attainable
ILED is:
heff ∂VIN ∂IIN
1∂2.3V ∂4A
4.8V
ILED
=
=
=1.9A
VOUT
For the power converter approaching the maximum input current, the efficiency can roll down significantly. As a
result the maximum LED current for VIN=2.3 V and VOUT=4.8 V is about 0.9 A.
The efficiency of the power converter depends on the input supply voltage and the output loading, i.e. output
voltage and output current. In the below graph efficiency curves as a function of the LED current are given for
several input supply voltages. Again for each of these supply cases the load was controlled such that at
maximum output current the output voltage was about 4.8 V.
16
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DLPA2005
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Figure 7. Measured Typical Power converter efficiency as a function of ILED for several supply voltages
(VOUTmax=4.8V for each supply)
Note that in the measurement the output of the buck-boost regulator includes the voltage drop across the sense
resistor RLIM, the voltage drop across the internal strobe control switch, and the forward voltage of the LED.
For higher input voltages the power converter runs at an efficiency of 85% or better. For the lower supply
voltages because of the boost action, the efficiency quickly rolls down. Refer to section Thermal Considerations
for information related to these efficiencies.
7.3.5 Calculating Inductor Peak Current
To properly configure the DLPA2005 device, a 2.2-μH inductor must be connected between pin L1 and pin L2.
The peak current for the inductor in steady state operation can be calculated.
Equation 4 shows how to calculate the peak current I1 in step down mode operation, and Equation 5 shows how
to calculate the peak current I2 in boost mode operation. VIN1 is the maximum input voltage, VIN2 is the minimum
input voltage, ƒ is the switching frequency (2.25 MHz), and L the inductor value (2.2 μH).
VOUT
VIN1 - VOUT
IOUT
0.8
(
)
I1 =
+
2ì VIN1 ì f ìL
(4)
V
V
- V
VOUT ìIOUT
(
)
IN2
OUT IN2
I2 =
+
0.8ì V
2ì VOUT ì f ìL
IN2
(5)
The critical current value for selecting the right inductor is the higher value of I1 and I2. Also consider that load
transients and error conditions may cause higher inductor currents. This needs to be accounted for when
selecting an appropriate inductor. Internally the switching current is limited to a maximum of 4 A.
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7.3.6 LED Current Accuracy
The LED drive current is controlled by a current DAC (Digital to Analog Converter) and can be set independently
for switch SW4, SW5 and SW6. For the DLPA2005, the DAC is trimmed at a current of 2528 mA at code:
0x3FFh, and the step size is 2.47 mA. First order gain-error of the DAC can be neglected, but an offset current
error must be taken into account. This offset error differs depending on the used RLIM, and is ±100 mA for the
DLPA2005 using a current sense resistor of 39 mΩ.
The max current of the DLPA2005 (SWx_IDAC[9:0] = 0x3FFh) is regulated to 2528 mA. At the lowest setting
(SWx_IDAC[9:0] = 0x029h) the current is regulated to 101 mA (DLPA2005). For this current setting (0x028h), the
absolute current error results into a large relative error, however this is not a typical operating point.
For best accuracy of the LED current, take the below two considerations into account:
•
The LED current setting does not only depend on the accuracy of the RLIM resistor but also strongly depends
on the added resistance of pcb traces in the ground route of RLIM and the soldering quality. Due to the low
value of the current sense resistor RLIM, any extra introduced resistance of e.g. several milliohms will result
in a noticeable different LED current.
•
Voltage sensing across RLIM is internally referred to the analog ground, i.e. pin 5 AGND1 and pin 20 GND.
To prevent any voltage drop between the ground connection of RLIM and the AGND of the PAD2005, make a
star connection of the RLIM ground near pin 5. Take care to make it a low ohmic route that can handle the
high LED current. Subsequently, make the ground connection for pin 5 to the system ground low ohmic as
well.
Taking the above measures relative to RLIM, the ILED current should align with the calculated value according
to:
•
•
Decimal_Code# = (set_current - min_current)/ step_current.
If needed translate the Decimal_Code# to HEX code before entering in the control software.
7.3.7 Transient Current Limiting
Typically the forward voltages of the green and blue diodes are close to each other (about 3 to 4 V). However,
the forward voltage of the red diode is significantly lower (1.8 to 2.5 V). This can lead to a current spike in the red
diode when the strobe controller switches from green or blue to red because VLED is initially at a higher voltage
than required to drive the RED diode. DLPA2005 provides transient current limiting for each switch to limit the
current in the LEDs during the transition. The transient current limit value is controlled through the ILIM[3:0] bits
in the IREG register. The same register also contains three bits to select which switch employs the transient
current limiting feature. In a typical application, the transient current limit will only apply to the RED diode, and
the ILIM[3:0] value will typically be set approximately 10% higher than the DC regulation current. The effect that
the transient current limit has on the LED current is shown in Figure 8.
18
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
1500
1200
900
600
300
0
1500
1200
900
600
300
0
Current overshoot due to
initially too high buck-boost
output voltage
Transient current
limit active
TIME
LED current with transient current limit.
Red LED current without transient current limit. The
current overshoots because the buck-boost voltage
starts at the (higher) level of the green or blue LED.
Figure 8. RED LED Current With and Without Transient Current Limit
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VLED
VLED
SW4
FB
BUCK-BOOST
SW4LIM_EN
I-LED
I-LED
I-LED
0
ILIM [3:0]
VDAC
E/A
1
SW5LIM_EN
SW5
0
E/A
1
SW6LIM_EN
SW6
RLIM
0
LED_SEL [1:0]
STROBE
MAP
DECODER
E/A
1
SW4_IDAQ [9:0]
RLIM_K
SW5_IDAQ [9:0]
SW6_IDAQ [9:0]
IDAC
I-DAC
200
RLIM
Figure 9. LED Driver Block Diagram
7.3.8 1.1-V Regulator (Buck Converter)
The buck converter creates a voltage of 1.1 V, and due to its switching nature, an output ripple with a frequency
of approximately 2.25 MHz occurs on its output. This ripple is strongly dependent on the decoupling capacitor at
the output in combination with the inductor. The magnitude of the ripple can be calculated with Equation 6.
VCORE
1 -
≈
∆
«
’
÷
◊
V
1
INC
DVCORE = VCORE
ì
ì
+ ESR
L ì f
8 ì COUT ì f
(6)
The best way to minimize this ripple is to select a capacitor with a very-low ESR.
20
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
7.3.9 Measurement System
The measurement system is composed of a 10:1 analog multiplexer (MUX), a programmable-gain amplifier, and
a comparator. It works together with the DPP processor to provide:
•
White-point correction (WPC) by independently adjusting the RGB LED currents after measuring the
brightness of each color with an external light sensor
•
A measurement of the:
–
–
–
–
Battery voltage
LED forward voltage
Exact LED current
Temperature as derived by measuring the voltage across an external thermistor
Figure 10 shows a block diagram of the measurement system.
AFE_GAIN [1:0]
AFE_SEL[3:0]
From host
VINA/3
VLED/3
SW4
AFE
PWM_IN
SW5
CMP_OUT
MUX
To host
From light sensor
SENS1
SENS2
From temperature sensor
Figure 10. Block Diagram of the Measurement System
Table 2. Recommended Configuration of the AFE for Different Input Selections
RECOMMENDED GAIN SETTING
AFE-GAIN[1:0]
RECOMMENDED SETTING OF
AFE_CAL_DIS BIT
AFE_SEL[3:0]
SELECTED INPUT
0x00h
0x01h
0x02h
0x03h
SENS2
VLED
0x01h (1x)
0x01h (1x)
0x01h (1x)
0x01h (1x)
Setting has no effect on measurement
Setting has no effect on measurement
Setting has no effect on measurement
Setting has no effect on measurement
VINA
SENS1
Set to 1 if sense voltage is >100 mV.
Otherwise set to 0 (default)
0x04h
0x05h
0x06h
0x07h
RLIM_K
SW4
0x03h (18x)
0x02h (9.5x)
0x02h (9.5x)
0x02h (9.5x)
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default)
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default)
SW5
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default)
SW6
0x08h
0x09h
No connect
VREF
N/A
N/A
0x01h (1x)
Setting has no effect on measurement
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7.3.10 Protection Circuits
DLPA2005 has several protection circuits to protect the IC and system from damage due to excessive power
consumption, die temperature, or over-voltages. These circuits are described in the following sections.
7.3.10.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
DLPA2005 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds
the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are
disabled and the TSD bit in the INT register is set. After the temperature drops below its threshold, the system
recovers and waits for the DPP to resend the DMD_EN bit.
Thermal Shutdown
Threshold
Hysteresis
Thermal warning
Threshold
Hysteresis
Temperature
HOT
(Internal Signal)
TSD
(Internal Signal)
Available Time for Controlled
Shutdown of System
Figure 11. Definition of the Thermal Shutdown and Hot-Die Temperature Warning
7.3.10.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued, but
normal operation continues. After the battery drops below the undervoltage threshold which has a default
hardcoded value of 2.3 V (this UVLO voltage can be changed through register 09 h from 2.3 to 4.5 V), the UVLO
interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters
STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to >2.4 V. To re-enable
the rails, the PROJ_ON pin must be toggled. The undervoltage threshold is programmable from 2.3 to 4.5 V in
31 steps.
The UVLO shutdown process will protect the DMD by allowing time for the mirrors to park, then doing a fast
discharge of VOFS, VRST, and VBIAS. This protection occurs even in the case of sudden battery removal from
the projector, as long as the bulk capacitance on the battery voltage (VINx) keeps this voltage above 2.3 V for as
long as needed for VOFS, VRST, and VBIAS to discharge to the required safe levels as shown in the DMD data
sheet. VOFS, VRST, and VBIAS discharge times depend on the load capacitance on each regulator. When for
instance every supply is decoupled using a capacitor of 0.5 µF, VINx should stay above 2.3 V for at least 100 µs
after the battery is suddenly removed. During this time, the mirrors can be placed in a safe position and VOFS,
VRST, and VBIAS can be discharged.
NOTE
Capacitive loads should be such that LS_OUT stays above 1.65 V until VOFS, VRST, and
VBIAS have discharged to their required safe levels.
22
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
VINA
Hysteresis
BAT_LOW Threshold
Hysteresis
UVLO Threshold
ACTIVE
BAT LOW
(Internal Signal)
INACTIVE
ACTIVE
200-µs
deglitch
UVLO
INACTIVE
(Internal Signal)
Programmable Deglitch Time1
(1) This time is programmable from 0 to 100 µs
Figure 12. UVLO is Asserted When the Input Supply Drops Below the UVLO Threshold
7.3.10.3 DMD Regulator Fault (DMD_FLT)
The DMD regulator is continuously monitored to check if the output rails are in regulation and if the inductor
current increases as expected during a switching cycle. If either one of the output rails drops out of regulation (for
example, due to a shorted output) or the inductor current does not increase as expected during a switching cycle
(due to a disconnected inductor), the DMD_FLT interrupt bit is set in the INT register, the DMD_EN bit is reset,
and the DMD regulator is shut down. Resetting the DMD_EN bit also causes the LED driver to power down. To
restart the system, the PROJ_ON pin must be toggled. In case the interrupt is masked, it is sufficient to set the
DMD_EN bit to restart the system.
7.3.10.4 V6V Power-Good (V6V_PGF) Fault
The LED driver regulation loop requires the V6V rail for proper operation. The rail is continuously monitored and
should the output drop below the power-good threshold, the V6V_PGF bit is set. The VLED buck-boost is then
disabled and attempts to restart automatically.
7.3.10.5 VLED Overvoltage (VLED_OVP) Fault
If the buck-boost output voltage rises above 5.4 V, the VLED_OVP interrupt is set but the buck-boost regulator is
not turned off. A typical condition to cause this fault is an open LED.
7.3.10.6 VLED Power Save Mode
In normal PWM operation, the efficiency of the VLED buck-boost converter dramatically reduces for LED currents
below 100 mA. In this case, the power save mode allows high converting efficiency at low output currents by
skipping pulses in the switcher’s gate driver control.
7.3.10.7 V1V8 PG Failure
If for any reason the voltage on the LS_OUT drops below approximately 1.3 V, then VOFS, VBIAS, and VRST
immediately go into fast shut down. Holding off power down to do mirror parking is not included since 1.3 V is too
low to wait for this. Reactivating can only be done by toggling the PROJ_ON off and on again.
7.3.10.8 Interrupt Pin (INTZ)
Use the interrupt pin to signal events and fault conditions to the host processor. Whenever a fault or event occurs
in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low. The
INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the host.
However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again after a
maximum of 32 µs.
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Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shutdown,
and UVLO. For all interrupt conditions see the interrupt register on Table 22.
The MASK register is used to mask events from generating interrupts, that is, from pulling the INTZ pin low. The
MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When
an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register.
However, it does not pull the INTZ pin low.
7.3.10.9 SPI
DLPA2005 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Support
includes register and data buffer write and read operations. The SPI_CSZ input serves as the active low chip
select for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data
buffers. When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is
forced to a high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT
output serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and
output data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the
SPI_DOUT output on the falling edge of SPI_CLK. Figure 13 illustrates the SPI port protocol. Byte 0 is referred to
as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a
write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the
register address targeted by the write or read operation. The SPI port supports write and read operations for
multiple sequential register addresses through the implementation of an auto-increment mode. As shown in
Figure 13, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes.
The register address is automatically incremented after each data byte transferred, starting with the address
specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.
Set SPI_CSZ = 1 here to write/read one register location
Hold SPI_CSZ = 0 to enable auto-increment mode
SPI_CSZ
SPI_DIN
Header
Register Data (write)
Byte0
Byte1
Byte2
Byte3
ByteN
Register Data (read)
Data for A[6:0]
Data for A[6:0] + 1
SPI_DOUT
SPI_CLK
Data for A[6:0] + (N – 2)
Byte 0
Byte 1
W/nR
W/nR
SPI_DIN
A6 A5 A4 A3 A2 A1 A0 N7 N6 N5 N4 N3 N2 N1 N0
Set high for write, low for read
Register Address
SPI_CLK
Figure 13. SPI Protocol
7.3.11 Password Protected Registers
Register addresses 0x11h through 0x27h can be read-accessed the same way as any other register, but are
protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a
protected register, follow these steps:
1. Write data 0xBAh to register address 0x10h.
2. Write data 0xBEh to register address 0x10h.
Both writes must be consecutive, that is, there must be no other read or write operation in between sending the
two bytes. After the password has been successfully written, registers 0x11h through 0x27h are unlocked and
can be write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is
written to the PASSWORD register or the part is power cycled.
To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the
registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.
24
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DLPA2005
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
7.4 Device Functional Modes
MODES OF OPERATION
OFF
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to
their default values and the IC does not respond to SPI commands. RESETZ pin is pulled low. The
IC will enter OFF mode whenever the PROJ_ON pin is low.
STANDBY The DMD regulators and LED power (VLED) are turned off, but the IC does respond to the SPI
interface. The device enters STANDBY mode whenever PROJ_ON is set high or DMD_EN7 bit is
set to 0 using the SPI interface after PROJ_ON is already high. The device also enters STANDBY
mode when a fault condition is detected8. (see the section about Protection Circuits on pages 28 &
30)
ACTIVE1
The DMD supplies are enabled but LED power (VLED) is disabled. PROJ_ON pin must be high,
DMD_EN bit must be set to 1, and VLED_EN9 bit is set to 0.
ACTIVE2
DMD supplies and LED power are enabled. PROJ_ON pin must be high and DMD_EN and
VLED_EN bits must both be set to 1.
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Device Functional Modes (continued)
POWERDOWN
Valid power source connected
VRST = OFF
VBIAS = OFF
VOFS = OFF
VLED = OFF
PROJ_ON = low
OFF
SPI interface disabled
PWR_EN = low
RESETZ = low
All registers set to default values
PROJ_ON = low
PROJ_ON = high
VRST = OFF
VBIAS = OFF
VOFS = OFF
DMD_EN = 0
||
VLED = OFF
FAULT = 1
STANDBY
SPI interface enabled
PWR_EN = high
RESETZ = high (but is low if entered
state due to UVLO detection)
DMD_EN = 1
FAULT = 0
&
VRST = ON
VBIAS = ON
VOFS = ON
ACTIVE 1
VLED = OFF
SPI interface enabled
PWR_EN = high
RESETZ = high
VLED_EN = 1
VLED_EN = 0
VRST = ON
VBIAS = ON
VOFS = ON
VLED = ON
ACTIVE 2
SPI interface enabled
PWR_EN = high
RESETZ = high
A. || = OR , & = AND
B. FAULT = Undervoltage on any supply (except LS_OUT), thermal shutdown, or UVLO detection
C. UVLO detection, per the diagram, causes the DLPA2005 to go into the standby state. This is not the lowest power
state. If lower power is desired, PROJ_ON should be set low.
D. DMD_EN register bit can be reset or set by SPI writes. DMD_EN defaults to 0 when PROJ_ON goes from low to high
and then the DPP ASIC software automatically sets it to 1. Also, FAULT = 1 causes the DMD_EN register bit to be
reset.
E. PWR_EN is a signal internal to the DLPA2005. This signal turns on the VCORE regulator and the load switch that
drives pin LS_OUT
Figure 14. State Diagram
26
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DLPA2005
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 3. Device State as a Function of Control-Pin
Status
PROJ_ON PIN
STATE
LOW
OFF
STANDBY
ACTIVE1
ACTIVE2
HIGH
(Device state depends on
DMD_EN and VLED_EN bits
and whether there are any
fault conditions.)
Table 4. Modes of Operation
MODE
DESCRIPTION
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values, and
the IC does not respond to SPI commands. RESETZ pin is pulled low. The IC will enter OFF mode whenever the PROJ_ON
pin is low.
OFF
The DMD regulators and LED power (VLED) are turned off, but the IC does respond to the SPI. The device enters STANDBY
mode whenever PROJ_ON is set high or DMD_EN(1) bit is set to 0 using the SPI interface after PROJ_ON is already high.
The device also enters STANDBY mode when a fault condition is detected(2). (See Protection Circuits .)
STANDBY
The DMD supplies are enabled but LED power (VLED) is disabled. PROJ_ON pin must be high, DMD_EN bit must be set to
1, and VLED_EN(3) bit is set to 0.
ACTIVE1
ACTIVE2
DMD supplies and LED power are enabled. PROJ_ON pin must be high and DMD_EN and VLED_EN bits must both be set
to 1.
(1) Settings can be done through Reg01h [9] and Reg2E [119]
(2) Power-good faults, over-voltage, overtemperature shutdown, and undervoltage lockout
(3) Settings can be done through Reg47h [60], bit is named VLED_EN_SET
7.5 Register Maps
Table 5. Register Description
REGISTE ADDRESS
DEFAULT
NAME
TABLE
DESCRIPTION
R
(Hex)
USER CONFIGURATION DEFINITIONS
R
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
CHIP ID
CHIPENABLE
IREG
Table 6
Table 7
Table 8
Table 9
Chip Revision Register; DLPA2005
Enable Register
C4
0F
30
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Transient-current limit settings
Regulation current MSB, SW4
Regulation current LSB, SW4
Regulation current MSB, SW5
Regulation current LSB, SW5
Regulation current MSB, SW6
Regulation current LSB, SW6
Switch ON/OFF control (direct mode)
AFE (MUX) control
SW4MSB
SW4LSB
SW5MSB
SW5LSB
SW6MSB
SW6LSB
SWCNTRL
AFE
Table 10, Table 11
Table 12
0
0
Table 13, Table 14
Table 15
0
0
Table 16, Table 17
Table 18
0
0
Table 19
0
BBM
Table 20, Table 21
Table 22, Table 23
Table 24, Table 25
Table 26, Table 27
Break Before Make timing
0
INT
Interrupt register
0
R/W
R/W
INT MASK
TIMING
Interrupt Mask register
DFh
7
Timing register VOFS, VBIAS, VRST, and RESETZ
USER PROTECTED DEFINITION
R/W
R/W
0x10
0x11
PASSWORD
SYSTEM
Table 28
Table 29
Password register
0
0
System Configuration register
USER EEPROM SCRATCH PAD DEFINITION
R/W 0x20 BYTE0 Table 31
User EEPROM, Byte0
0
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DEFAULT
Register Maps (continued)
Table 5. Register Description (continued)
REGISTE ADDRESS
NAME
BYTE1
TABLE
DESCRIPTION
R
(Hex)
0x21
0x22
0x23
0x24
0x25
0x26
0x27
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 32
User EEPROM, Byte1
0
0
0
0
0
0
0
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
User EEPROM, Byte2
User EEPROM, Byte3
User EEPROM, Byte4
User EEPROM, Byte5
User EEPROM, Byte6
User EEPROM, Byte7
Table 6. Chip Revision Register
REGISTER = 00h
DATA BIT
FIELD NAME
READ/WRITE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CHIP ID [7:0]
R
1
R
1
R
0
R
R
R
1
R
0
R
0
RESET VALUE
DLPA2005
0
0
C4
FIELD NAME
BIT
BIT DEFINITION
7:4
3:0
CHIPID<3:0>
REVID<3:0>
CHIP ID
[7:0]
Table 7. Enable Register
REGISTER = 01h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CHIPENABLE [15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
0F
BIT
BIT DEFINITION
15:12
11
USER_GPO<3:0>
VLED_POWER_SAVE_MODE_DIS
Power save mode is used to improve efficiency at light load.
FAST_SHUTDOWN_EN
Applicable only during a fault condition.
Shutdown timing is defined by register 0Eh. (see Figure 5)
CHIPENABLE
[15:8]
10
9
8
DMD_EN
VLED_EN
28
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DLPA2005
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 8. Transient-Current Limit Settings
REGISTER = 02h
DATA BIT
Field Name
Read/Write
Reset Value
FIELD NAME
Not used
D7
D6
D5
D4
D3
D2
D1
D0
HEX
IREG [23:16]
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
30
BIT
BIT DEFINITION
23
TBD
IREG_ILIM<3:0>
0000
Rlim = 39 mΩ
333 mA
385 mA
442 mA
494 mA
564 mA
705 mA
846 mA
1128 mA
1410 mA
1692 mA
1974 mA
2256 mA
2538 mA
2974 mA
3410 mA
3846 mA
0001
0010
0011
0100
0101
0110
IREG [3:0]
22:19
0111
1000
1001
1010
1011
[23:16]
1100
1101
1110
1111
SW6LIM_EN
Transient current-limit enable for SW6
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
SW6LIM_EN
SW5LIM_EN
SW4LIM_EN
18
17
16
SW5LIM_EN
Transient current-limit enable for SW5
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
SW4LIM_EN
Transient current-limit enable for SW4
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
Table 9. Regulation Current MSB, SW4(1)
REGISTER = 03h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW4MSB [31:24]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
Bit
BIT DEFINITION
31:26
25:24
TBD
SW4_IDAC<9:8>
SW4MSB
[31:24]
(1) The DLPA2005 can use up to code 0x3ffh for SW4_IDAC[9:0].
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Table 10. Regulation Current LSB, SW4
REGISTER = 04h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
SW4LSB
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW4LSB [39:32]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
Bit
BIT DEFINITION
[39:32]
39:32
SW4_IDAC<7:0>
Table 11. Regulation Current LSB, SW4 Bit Definitions
(1) (2)
DLPA2005
LED
CURRENT
LED
CURRENT
LED
CURRENT
SW4_IDAC[9:0]
SW4_IDAC[9:0]
SW4_IDAC[9:0]
SW4_IDAC[9:0]
LED CURRENT
0x000h
0x029h
0x02Ah
...
0 mA
0x100h
0x101h
0x102h
...
633 mA
635 mA
638 mA
...
0x200h
0x201h
0x202h
...
1265 mA
1268 mA
1270 mA
...
0x300h
0x301h
0x302h
...
1898 mA
1900 mA
1903 mA
...
101 mA
104 mA
...
0x0FEh
0x0FFh
628 mA
630 mA
0x1FEh
0x1FFh
1260 mA
1263 mA
0x2FEh
0x2FFh
1893 mA
1895 mA
0x3FEh
0x3FFh
2526 mA
2528 mA
(1) Values shown are for a typical DLPA2005 unit at T = 25°C. Typical step size is 2.47 mA for RLIM = 39 mΩ
(2) The DLPA2005 can use up to code 0x3FFh for SW4_IDAC[9:0].
Table 12. Regulation Current MSB, SW5(1)
REGISTER = 05h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW5MSB [47:40]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
Bit
BIT DEFINITION
47:42
41:40
TBD
SW5_IDAC<9:8>
SW5MSB
[47:40]
(1) The DLPA2005 can use up to code 0x3FFh for SW5_IDAC[9:0].
Table 13. Regulation Current LSB, SW5
REGISTER = 06h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
SW5LSB
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW5LSB [55:48]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[55:48]
55:48
SW5_IDAC<7:0>
30
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 14. Regulation Current LSB, SW5 Bit Definitions
(1) (2)
DLPA2005
LED
CURRENT
LED
CURRENT
LED
CURRENT
SW5_IDAC[9:0]
SW5_IDAC[9:0]
SW5_IDAC[9:0]
SW5_IDAC[9:0]
LED CURRENT
0x000h
0x029Ch
0x02Ah
...
0 mA
0x100h
0x101h
0x102h
...
633 mA
635 mA
638 mA
...
0x200h
0x201h
0x202h
...
1265 mA
1268 mA
1270 mA
...
0x300h
0x301h
0x302h
...
1898 mA
1900 mA
1903 mA
...
101 mA
104 mA
...
0x0FEh
0x0FFh
628 mA
630 mA
0x1FEh
0x1FFh
1260 mA
1263 mA
0x2FEh
0x2FFh
1893 mA
1895 mA
0x3FEh
0x3FFh
2526 mA
2528 mA
(1) Values shown are for a typical DLPA2005 unit at T = 25°C. Typical step size is 2.47 mA for RLIM = 39 mΩ
(2) The DLPA2005 can use up to code 0x3FFh for SW5_IDAC[9:0].
Table 15. Regulation Current MSB, SW6(1)
REGISTER = 07h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW6MSB [63:56]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
63:58
57:56
TBD
SW6_IDAC<9:8>
SW6MSB
[63:56]
(1) The DLPA2005 can use up to code 0x3FFh for SW6_IDAC[9:0].
Table 16. Regulation Current LSB, SW6
REGISTER = 08h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
SW6LSB
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SW6LSB [71:64]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[71:64]
71:64
SW6_IDAC<7:0>
Table 17. Regulation Current LSB, SW6 Bit Definitions
(1) (2)
DLPA2005
LED
CURRENT
LED
CURRENT
LED
CURRENT
SW6_IDAC[9:0]
SW6_IDAC[9:0]
SW6_IDAC[9:0]
SW6_IDAC[9:0]
LED CURRENT
0x000h
0x029h
0x02Ah
...
0 mA
0x100h
0x101h
0x102h
...
633 mA
635 mA
638 mA
...
0x200h
0x201h
0x202h
...
1265 mA
1268 mA
1270 mA
...
0x300h
0x301h
0x302h
...
1898 mA
1900 mA
1903 mA
...
101 mA
104 mA
...
0x0FEh
0x0FFh
628 mA
630 mA
0x1 FEh
0x1 FFh
1260 mA
1263 mA
0x2FEh
0x2FFh
1893 mA
1895 mA
0x3FEh
0x3FFh
2526 mA
2528 mA
(1) Values shown are for a typical DLPA2005 unit at T = 25°C. Typical step size is 2.47 mA for RLIM = 39 mΩ
(2) The DLPA2005 can use up to code 0x3FFh for SW6_IDAC[9:0].
Copyright © 2014–2015, Texas Instruments Incorporated
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DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Table 18. Switch On/Off Control (Direct Mode)
REGISTER = 09h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SWCNTRL [79:72]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
79
78
SW6 (controls switch 6 if direct mode (see reg 11h) is enabled)
SW5 (controls switch 5 if direct mode (see reg 11h) is enabled)
SW4 (controls switch 4 if direct mode (see reg 11h) is enabled)
UVLO_TRIM<4:0>
SWCNTRL
[79:72]
77
76:72
00000
00001
.....
11110
11111
2.3 V (minimum value – default value)
2.37 V
Step approximately 70 mV
4.43 V
4.5 V (maximum value)
Table 19. AFE (MUX) Control
REGISTER = 0Ah
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
AFE [87:80]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
87
86
AFE_EN
AFE_CAL_DIS
AFE_GAIN<1:0>
AFE_SEL<3:0>
AFE
[87:80]
85:84
83:80
Table 20. Break Before Make (BBM) Timing
REGISTER = 0Bh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BBM [95:88]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
Table 21. Break Before Make (BBM) Timing Bit Definitions(1)
FIELD NAME
BIT
BIT DEFINITION
BBM_DELAY<7:0>
0x00 – 0 ns
0x01 – 333 ns
0x02 – 444 ns
...
0x40 – 7326 ns
0x41 – 7437 ns
0x42 – 7548 ns
...
0x80 – 14430 ns
0x81 – 14541 ns
0x82 – 14652 ns
...
0xC0 – 21534 ns
0xC1 – 21645 ns
0xC2 – 21756 ns
...
BBM
[95:88]
95:88
0x3E – 7104 ns
0x3F – 7215 ns
0x7E – 14208 ns
0x7F – 14319 ns
0xBE – 21312 ns
0xBF – 21423 ns
0xFE – 28416 ns
0xFF – 28527 ns
(1) It takes 333 to 444 ns to turn off the switches from the time a change occurs on LED_SEL[1:0].
Table 22. Interrupt Register
REGISTER = 0Ch
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INT [103:96]
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
00
32
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
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FIELD NAME
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 23. Interrupt Register Bit Definitions
BIT
BIT DEFINITION
VLED_OVP
VLED buck_boost overvoltage fault interrupt (normal operation resumes)
0 – No fault
1 – Buck_boost output is above OVP threshold
103
102
101
IREG_PG_FAULT
V6V power-good fault interrupt (normal operation resumes)
0 – No fault
1 – V6V is not in regulation
PROJ_ON_INT
Proj_On interrupt (part enters OFF mode)
0 – Pin is pulled high, normal mode
1 – Pin is pulled low, alerts the DPP that the DMD regulator is about to shut down.
DMD_FAULT
DMD regulator fault (part enters STANDBY mode and DMD_EN bit is cleared)
0 – No fault
100
1 – The inductor current is not increasing at the correct rate, likely to be caused by an
open inductor.
Or, one of the regulator outputs has dropped below the power-good threshold, likely to
be caused by a short
INT
[103:96]
UVLO
UVLO interrupt (sensed at VINA pin), DMD bit is cleared.
0 – Battery voltage is above the UVLO threshold
1 – Battery voltage has dropped below the UVLO threshold
99
98
BAT_LOW_WARN
Low battery warning interrupt (sensed at VINA pin, normal operation resumes)
0 – Battery voltage is above the low-battery threshold
1 – Battery voltage has dropped below the low-battery threshold
TS_WARN
Thermal warning interrupt (normal operation resumes)
0 – Die temperature is in normal operating range
1 – Die temperature is above the HOT threshold
Or, part has not cooled down enough to recover from HOT.
97
96
TS_WARN
Thermal Warning Interrupt (normal operation resumes)
0 – Die temperature is in normal operating range
1 – Die temperature is above the HOT threshold
Or, part has not cooled down enough to recover from HOT.
Table 24. Interrupt Mask Register
REGISTER = 0Dh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INT MASK [111:104]
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DF
Copyright © 2014–2015, Texas Instruments Incorporated
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DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Table 25. Interrupt Mask Register Bit Definitions
FIELD NAME
BIT
BIT DEFINITION
VLED BUCK_BOOST
Overvoltage fault interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
111
IREG_PG_FAULT_MASK
0 – Interrupt is not masked
1 – Interrupt is masked
110
109
108
107
106
105
104
PROJ_ON interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
DMD_REGULATOR fault mask
0 – Interrupt is not masked
1 – Interrupt is masked
INT MASK
[111:104]
UVLO_MASK
0 – Interrupt is not masked
1 – Interrupt is masked
Low Battery Warning Mask (sensed at VINA pin)
0 – Interrupt is not masked
1 – Interrupt is masked
Thermal Shutdown Interrupt Mask
0 – Interrupt is not masked
1 – Interrupt is masked
Thermal Warning Interrupt Mask
0 – Interrupt is not masked
1 – Interrupt is masked
Table 26. Timing Register VOFS, VBIAS, VRST, and RESETZ
REGISTER = 0Eh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
TIMING [119:112]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
07
34
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
FIELD NAME
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 27. Timing Register VOFS, VBIAS, VRST, and RESETZ Bit Definitions
BIT
BIT DEFINITION
119:116
115:112
VOFS/RESETZ_DELAY<3:0> (for values see min and max delay)
VBIAS/VRST_DELAY<3:0> (for values see min and max delay)
Min Delay (μs)
4.0
Max Delay (μs)
4.4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8.0
8.9
16.0
17.8
32.0
35.5
64.0
71.1
128.0
256.0
512.0
6.2
142.2
284.4
569.0
7.1
TIMING
[119:112]
12.4
14.2
24.9
28.4
49.8
56.9
99.5
113.8
227.6
455.2
1138.0
199.1
398.3
1024.2
Table 28. Password Register
REGISTER = 10h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PASSWORD [135:128]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
USER PASSWORD (0xBAh + 0xBEh) Disable (0x00h)
Once set, register 11h can be written.
PASSWORD
[135:128]
135:128
Table 29. System Configuration Register
REGISTER = 11h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SYSTEM [143:136]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
Table 30. System Configuration Register Bit Definitions
FIELD NAME
BIT
BIT DEFINITION
143:139
138
TBD
EEPROM_PROGRAM
Program scratch pad values to EEPROM
SYSTEM
[143:136]
DIRECT_MODE
137
136
Allows direct control of switches through SW CONTROL REGISTER
TBD
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35
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Table 31. User EEPROM, BYTE0
REGISTER = 20h
D4 D3
BYTE0 [7:0]
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE0
D7
D6
D5
D2
D1
D0
HEX
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
[7:0]
BIT DEFINITION
7:0
USER BYTE 0
Table 32. User EEPROM, BYTE1
REGISTER = 21h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE1
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE1 [15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
[15:8]
BIT DEFINITION
15:8
USER BYTE 1
Table 33. User EEPROM, BYTE2
REGISTER = 22h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE2
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE2 [23:16]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[23:16]
23:16
31:24
39:32
USER BYTE 2
Table 34. User EEPROM, BYTE3
REGISTER = 23h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE3
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE3 [31:24]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[31:24]
USER BYTE 3
Table 35. User EEPROM, BYTE4
REGISTER = 24h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE4
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE4 [39:32]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[39:32]
USER BYTE 4
36
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DLPA2005
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ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Table 36. User EEPROM, BYTE5
REGISTER = 25h
D4 D3
BYTE5 [47:40]
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE5
D7
D6
D5
D2
D1
D0
HEX
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[47:40]
47:40
55:48
63:56
USER BYTE 5
Table 37. User EEPROM, BYTE6
REGISTER = 26h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE6
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE6 [55:48]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
00
BIT
BIT DEFINITION
[55:48]
USER BYTE 6
Table 38. User EEPROM, BYTE7
REGISTER = 27h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
FIELD NAME
BYTE7
D7
D6
D5
D4
D3
D2
D1
D0
HEX
BYTE7 [63:56]
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
00
BIT
BIT DEFINITION
[63:56]
USER BYTE 7
Copyright © 2014–2015, Texas Instruments Incorporated
37
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A DLPC343x controller can be used with a DLP2010 (.2 WVGA) DMD or DLP3010 (.3 720p) DMD to provide a
compact, reliable, high-efficiency display solution for many different video display applications. The DMDs are
spatial light modulators which reflect incoming light from an illumination source to one of two directions with the
primary direction being into collection optics within a projection lens. The projection lens sends the light to the
destination needed for the application. Each application is derived primarily from the optical architecture of the
system and the format of the pixel data being input into the DLPC343x.
In display applications using the DLP2010 DMD or DLP3010 DMD, the DLPA2005 provides all needed analog
functions including the analog power supplies and the RGB LED driver to provide a robust and efficient display
solution. Display applications of interest include pico-projectors embedded in display devices like smart phones,
tablets, cameras, and camcorders. Other applications include wearable (near-eye) displays, battery-powered
mobile accessory, interactive display, low latency gaming displays, and digital signage.
Alternately, a DLPC150 controller can be used with a DLP2010 or DLP2010NIR DMD. Applications of interest
when using the DLPC150 controller include machine vision systems, spectrometers, skin analysis, medical
systems, material identification, chemical sensing, infrared projection, and compressive sensing. In a
spectroscopy application the DLPC150 controller and DLP2010NIR DMD are often combined with a single
element detector to replace expensive InGaAs array-based detector designs. In this application the DMD acts as
a wavelength selector reflecting specific wavelengths of light into the single point detector.
8.2 Typical Projector Application
A common application when using DLPA2005 with DLP2010 DMD and DLPC3430/DLPC3435 controller is for
creating an accessory projector for a smart phone, tablet or any other portable smart device. The
DLPC3430/DLPC3435 in an accessory projector typically receives images from a smart device over either HDMI
as shown below (WI-FI can also be used to transmit data). DLPA2005 provides power supply sequencing and
controls the RGB LED currents as required by the application.
38
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Typical Projector Application (continued)
DC_IN
Charger
BAT
...
2.3V-5.5V
Projector Module Electronics
DC Supplies
1.8V
VSPI
1.8V
Other
Supplies
1.1V
1.8V
1.1V
Reg
L3
SYSPWR
1.8V
PROJ_ON
PROJ_ON
MSP430
VLED
Current
Sense
L1
L2
GPIO_8 (Normal Park)
SPI_0
DLPA2005
FLASH
Cal data
4
(optional)
RED
GREEN
BLUE
EEPROM
SPI_1
4
RESETZ
INTZ
I2C_1
HDMI
PARKZ
I2C
BIAS, RST, OFS
3
HDMI
Receiver
LED_SEL(2)
CMP_PWM
Illumination
Optics
28
DLPC3430/
DLPC3435
WPC
LABB
Parallel I/F
CMP_OUT
eDRAM
DLP2010
DMD)
Thermistor
(WVGA
Sub-LVDS DATA
CTRL
1.8V
1.1V
VIO
VCC_INTF
VCC_FLSH
VCORE
Spare R/W
GPIO
18
Figure 15. Typical Setup Using DLPA2005
8.2.1 Design Requirements
A pico-projector is created by using a DLP chip set comprised of DLP2010 (.2 WVGA) DMD, DLPC3430 or
DLPC3435 controller and DLPA2005 PMIC/LED driver. The DLPC3430 or DLPC3435 does the digital image
processing, the DLPA2005 provides the needed analog functions for the projector, and DMD is the display
device for producing the projected image. In addition to the three DLP chips in the chip set, other chips may be
needed. At a minimum a flash part is needed to store the software and firmware to control the DLPC3430 or
DLPC3435. The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These
are often contained in three separate packages, but sometimes more than one color of LED die may be in the
same package to reduce the overall size of the pico-projector. For connecting the DLPC3430 or DLPC3435 to
the front end for receiving images parallel interface is used. While using parallel interface, I2C should be
connected to the front end for sending commands to the DLPC3430 or DLPC3435. The only power supplies
needed external to the projector are the battery (SYSPWR) and a regulated 1.8 V supply. The entire pico-
projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is high, the
projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and draws
just microamps of current on SYSPWR. When PROJ_ON is set low, the 1.8 V supply can continue to be left at
1.8 V and used by other non-projector sections of the product. If PROJ_ON is low, the DLPA2005 will not draw
current on the 1.8 V supply.
8.2.2 Detailed Design Procedure
For connecting together the DLP2010, DLPC3430 or DLPC3435 and DLPA2005, see the reference design
schematic. When a circuit board layout is created from this schematic a very small circuit board is possible. An
example small board layout is included in the reference design data base. Layout guidelines should be followed
to achieve a reliable projector. The optical engine that has the LED packages and the DMD mounted to it is
typically supplied by an optical OEM who specializes in designing optics for DLP projectors.
Copyright © 2014–2015, Texas Instruments Incorporated
39
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Projector Application (continued)
8.2.3 Application Curves
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents. It’s assumed that the same current amplitude is applied to the red,
green, and blue LEDs.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
500
1000
1500
2000
2500
3000
Current (mA)
D001
Figure 16. Luminance vs Current
8.3 Typical Mobile Sensing Application
A typical embedded system application using the DLPC150 controller and the DLPC2010NIR is shown in
Figure 17. In this configuration, the DLPC150 controller supports a 24-bit parallel RGB input, typical of LCD
interfaces, from an external source or processor. The DLPC150 controller processes the digital input image and
converts the data into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific
micromirrors to the "on" position, directing light to the detector, while unwanted micromirrors are set to "off"
position, directing light away from the detector. The microprocessor sends binary images to the DLP2010NIR to
steer specific wavelengths of light into the detector. The microprocessor uses an analog-to-digital converter to
sample the signal received by the detector into a digital value. By sequentially selecting different wavelengths of
light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light.
40
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
Typical Mobile Sensing Application (continued)
0/F5:
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Figure 17. Typical Application Diagram
8.3.1 Design Requirements
All applications using the DLP 0.2-inch WVGA chipset require the:
•
•
•
DLPC150 controller, and
DLPA2005 PMIC, and
DLP2010 or DLP2010NIR DMD
components for operation. The system also requires an external parallel flash memory device loaded with the
DLPC150 configuration and support firmware. DLPC150 does the digital image processing and formats the
data for the DMD. DLPA2005 PMIC provides the needed analog functions for the DLPC150 and DLP2010 or
DLP2010NIR. The chipset has several system interfaces and requires some support circuitry. The following
interfaces and support circuitry are required:
•
DLPC150 system interfaces:
–
–
–
–
Control interface
Trigger interface
Input data interface
Illumination interface
•
•
DLPC150 support circuitry and interfaces:
–
–
–
Reference clock
PLL
Program memory flash interface
DMD interfaces:
–
–
–
DLPC150 to DMD digital data
DLPC150 to DMD control interface
DLPC150 to DMD micromirror reset control interface
Copyright © 2014–2015, Texas Instruments Incorporated
41
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Mobile Sensing Application (continued)
8.3.2 Detailed Design Procedure
8.3.2.1 Dlpc150 System Interfaces
The 0.2-inch WVGA chipset supports a16-bit or 24-bit parallel RGB interface for image data transfers from
another device. There are two primary output interfaces: illumination driver control interface and sync outputs.
8.3.2.1.1 Control Interface
The 0.2-inch WVGA chipset supports I2C commands through the control interface. The control interface allows
another master processor to send commands to the DLPC150 controller to query system status or perform
realtime operations such as LED driver current settings.
8.3.3 Application Curve
In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light
spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150 controls
individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The
microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital
value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the
microprocessor can then plot a spectral response to the light. This systems allows the measurement of the
collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption
spectrum shown in Figure 18.
Figure 18. Sample Dlpc150 Based Spectrometer Output
42
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
9 Power Supply Recommendations
The DLPA2005 is designed to operate from a 2.3 to 6 V input voltage supply or battery. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current
limitations, additional bulk capacitance may be required. In the case ringing that is caused by the interaction with
the ceramic input capacitors, an electrolytic or tantalum type capacitor may be needed for damping.
The amount of bulk capacitance required should be evaluated such that the input voltage can remain in spec
long enough for a proper fast shutdown to occur for the vofs, vrst, and vbias supplies. The shutdown begins
when the input voltage drops below the programmable UVLO threshold such as when the external power supply
or battery supply is suddenly removed from the system.
Copyright © 2014–2015, Texas Instruments Incorporated
43
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
As for all chips with switching power supplies, the layout is an important step in the design, especially in the case
of high peak currents and high switching frequencies. If the layout is not carefully done, the regulators could
show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths
and for the power ground tracks. Input capacitors, output capacitors, and inductors should be placed as close as
possible to the IC.
Figure 19 shows an example layout that has critical parts placed as close as possible to the pins they are
connected to. Here are recommendations for the following components:
R1
is RLIM and is connected via a wide trace (low resistance) to the system ground. The analog ground
at pin 5 should be star connected to the point where RLIM is connected to the system ground. Aim on
a wide and low-ohmic trace as well, although this one is less critical (tens of mA).
L1
is the big inductor for the VLED that is connected via two wide traces to the pins
C4
are the decoupling capacitors for the VLED and they are as close as possible placed to the part and
directly connected to ground.
L3/C20 are components used for the VCORE BUCK. L3 is placed close to the pin and connected with a wide
trace to the part. C20 is placed directly beside the inductor and connected to the PGND pin
L2
This inductor is part of the DMD reset regulators and is also placed as close as possible to the
DLPA2005 using wide PCB traces.
10.2 Layout Example
Figure 19. Example Layout of DLPA2005
44
Copyright © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
10.3 Thermal Considerations
An important consequence of the efficiency numbers shown in Figure 7 is that it enables to perform DLPA2005
thermal calculations. Since the efficiency is not 100%, power is dissipated in the DLPA2005 chip. Due to that
dissipation die temperature will rise. For reliability reasons it is good to aim for as low as possible die
temperatures. Using a heat sink and airflow are efficient means to keep die temperature reasonably low. In cases
that airflow and / or a heat sink are / is not feasible, the system designer should specifically pay attention to the
thermal design. The die temperature for regular operation should remain below 120°C.
In the following an example is given of such a thermal calculation. The calculation starts with summarizing all
blocks in the DLPA2005 that dissipate. Clearly, the buck-boost converter supplying the LED power is the main
source of dissipation. For illustrating purposes here we assume this buck-boost converter to be the only block
that dissipates significantly. For the example assume: VOUT=4.8 V (for all three LEDs), IOUT=2.4 A and VIN=5
V. From Figure 7 it can be derived that the related efficiency equals about neff=88%.
The power dissipated by the DLPA2005 is then given by:
SPACE
≈
’
÷
◊
100%
100%
88%
≈
’
◊
P
= P - P = P
-1 = 4.8V ∂2.4A∂
-1 =1.6W
∆
∆
÷
DISS
IN
OUT
OUT
∆
«
÷
heff
«
SPACE
The rise of die temperature due to this power dissipation can be calculated using the thermal resistance from
junction to ambient, M JA=27.9°C/W. This calculation yields:
TJUNSCTPIOANC=ETAMBIENT + P
∂qJA = 25°C +1.6W ∂27.9°C /W = 69.6°C
DISS
SPACE
It is also possible to calculate the maximum allowable ambient temperature to prevent surpassing the maximum
die temperature. Assume again the dissipation of PDISS=1.6W. The maximum ambient temperature that is
allowed is then given by:
SPACE
TAMBIENT-max =TJUNCTION-max - P
∂qJA =120°C -1.6W ∂27.9°C /W = 75.4°C
DISS
SPACE
It is again stressed here that for proper calculations the total power dissipation of the PAD2005 should be taken
into account. On top of that, if components that are close to the PAD2005 also dissipate a significant amount of
power, the (local) ambient temperature can be higher than the ambient temperature of the system.
If calculations show that the die temperature will surpass the maximum specified value, two basic options exist:
•
•
Adding a heat sink with or without airflow. This will reduce 0JA yielding lower die temperature.
Lowering the dissipation in the PAD2005 implying lowering the maximum allowable LED current.
版权 © 2014–2015, Texas Instruments Incorporated
45
DLPA2005
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
Package Marking DLPA2005
(TOP VIEW)
TI
= TI LETTERS
YM = YEAR / MONTH DATE CODE
LLLL = ASSY LOT CODE
PAD2005
A4
S
= ASSEMBLY SITE CODE
PER QSS 005-120
TI YMS$$
LLLL G4
$$
= WAFER FAB CODE
(1 or 2 CHARACTERS)
=pin 1 Marking
图 20. 封装标记 DLPA2005（顶视图）
11.2 商标
Pico is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
盖带
盖带不覆盖导孔并且不会从载带移出。
抗静电放电 (ESD) 载带和盖带使用的塑料材料均为抗静电型。
器件插入方向 定位器件时，符号朝上，引脚朝下。
46
版权 © 2014–2015, Texas Instruments Incorporated
DLPA2005
www.ti.com.cn
ZHCSD09B –SEPTEMBER 2014–REVISED OCTOBER 2015
包装方法
用胶带将导引带末端固定，然后用防潮袋来包装卷带并热封固定。方形扁平无引脚 (QFN) 器件的包装
中含有干燥剂和湿度指示剂。
带盒
每个防潮袋均包装到带盒内。
带结构
载带由塑料制成，其结构如上文的电路原理图所示。器件置于载带的压纹区域，并由塑料制成的盖带
覆盖。
带盒材料
瓦楞纸板
版权 © 2014–2015, Texas Instruments Incorporated
47
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPA2005ERSLR
DLPA2005ERSLT
ACTIVE
VQFN
VQFN
RSL
48
48
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-10 to 85
-10 to 85
PAD2005
A4
Samples
Samples
ACTIVE
RSL
NIPDAU
PAD2005
A4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DLPA2005ERSLR
DLPA2005ERSLT
VQFN
VQFN
RSL
RSL
48
48
3000
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DLPA2005ERSLR
DLPA2005ERSLT
VQFN
VQFN
RSL
RSL
48
48
3000
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
DLPA2005ERSLT
DLP® PMIC/LED driver for DLP2010 and DLP2010NIR (0.2 WVGA) DMDs | RSL | 48 | -10 to 85
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