DLPA200PFP [TI]
DMD Micromirror Driver;
| 型号： | DLPA200PFP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DMD Micromirror Driver |
| 文件： | 总20页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLPA200
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DLPS015A –APRIL 2010–REVISED JUNE 2010
®
DLP DLPA200 DMD Micromirror Driver
Check for Samples: DLPA200
1
FEATURES
ETQFP PACKAGE
(TOP VIEW)
2
•
Designed for use as a part of a DLP Chipset
•
Generates the Micromirror Clocking Pulses
required by the DLP Digital Micromirror Device
(DMD)
•
Generates specialized voltage levels required
for micromirror clocking pulse generation
•
•
Operates from a single 12-V power supply
GND
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
2
RESETZ
SCPENZ
SCPDI
SCPCK
GND
MODE1
MODE0
SEL1
3
Provides a VBIAS voltage level, used by the
DMD to control the array border mirrors
4
5
SEL0
OEZ
GND
6
7
NC
G
•
•
•
Provides a VOFFSET voltage level, used by the
DMD as DMDVCC2
VBIAS_SWL
VBIAS
VBIAS_LHI
P12V
8
9
NC
NC
P12V
VOFFSET
P12V
10
11
12
13
14
15
16
17
18
19
20
All logic inputs are LVTTL and CMOS
compatible
VRESET_SWL
VRESET
GND
V5REG
GND
DEV_ID1
STROBE
A3
A2
Packaged in an Pb-free Thermally Enhanced
Surface-Mount Package: 80-pin, 0.5 mm-pitch,
enlarged terminal pitch, thin profile quad flat
pack (eTQFP)
DEV_ID0
IRQZ
A1
A0
SCPDO
GND
GND
DESCRIPTION
The DLPA200 is designed to be used as a part of a complete DLP chipset. A DLP chipset typically consists of a
DMD, a DMD Controller, DMD Controller Firmware, and the DMD Micromirror Driver.
Within a chipset, the DLPR200 is responsible for generating micromirror clocking pulses. These clocking pulses
(also referred to as micromirror reset pulses) are what cause the DMD micromirrors to switch from one binary
landed state to another (as dictated by the binary contents of the DMD CMOS memory array).
A DMD Controller is responsible for writing data to the DMD CMOS memory array, and then commanding the
DLPR200 to generate the required micromirror clocking pulses.
The DLPA200 consists of three functional blocks: A High-Voltage Power Supply function, a DMD Micromirror
Clock Generation function, and a Serial Communication function.
The High-Voltage Power Supply function generates three specialized voltage levels: VBIAS (19 to 28 V), VRESET
(–19 to –28 V), and VOFFSET (4.5 to 10 V).
The Micromirror Clock Generation function uses the three voltages generated by the High-Voltage Power Supply
function to create the sixteen micromirror clock pluses (output the OUTx pins of the DLPA200).
The Serial Communication function allows the chipset Controller to: control the generation of VBIAS, VRESET, and
VOFFSET; control the generation of the micromirror clock pulses; status the general operation of the DLPA200.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DLP is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
DLPA200
DLPS015A –APRIL 2010–REVISED JUNE 2010
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Functional Block Diagram
MODE[1:0]
SEL[1:0]
A[3:0]
2
4
Select, Latch,
Output Logic
and
High-Voltage
Output
FET Switches
2
OUT(00–15)
16
STROBE
OEZ
P12V
Internal 5 V
and Ref. Supplies
V5REG
VBIAS_RAIL
VBIAS
VBIAS_LHI
V
BIAS
Boost Converter
VBIAS_SWL
(SUBSTRATE)
VRESET_RAIL
VRESET
V
RESET
VRESET_SWL
Buck-Boost Converter
VOFFSET_RAIL
VOFFSET
V
OFFSET
Regulator
SCPENZ
SCPCK
SCPDI
Power-Up Initialization
Fault Logic
Serial Bus
Interface
IRQZ
SCPDO
DEV_ID[1:0]
2
GND
RESETZ
2
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DLPS015A –APRIL 2010–REVISED JUNE 2010
Device Marking
The device marking consists of the fields shown in Figure 1.
Figure 1. Device Marking (Device Top View)
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
(INPUT
DEFAULT)
DESCRIPTION
16 micromirror clocking waveform outputs (enabled by OE = 0).
NO.
OUT00
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUT08
OUT09
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
A0
22
24
27
29
32
34
37
39
62
64
67
69
72
74
77
79
19
18
17
16
3
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input (pull down) Output Address. Used to select which OUTxx pin is active at a given time.
A1
Input (pull down)
A2
Input (pull down)
A3
Input (pull down)
MODE0
MODE1
SEL0
Input (pull down) Mode Select. Used to determine the operating mode of the DLPA200.
Input (pull down)
2
5
Input (pull down) Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx
pin.
SEL1
4
Input (pull down)
STROBE
15
Input (pull down) A rising edge on STROBE latches in the control signals after a tri-state delay.
Asynchronous input controls whether the 16 OUTxx pins are active or are in a in
OE
6
Input (pull up)
high-impedance state.
OE = 0 : Enabled. OE = 1 : High Z.
RESET
SCPEN
59
58
Input (pull up)
Input (pull up)
Resets the DLPA200 internal logic. Active low. Asynchronous.
Enables serial bus data transfers. Active low.
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
(INPUT
DEFAULT)
DESCRIPTION
NAME
NO.
SCPDI
57
56
Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK.
Input (pull down) Serial bus clock. Provided by chipset Controller.
SCPCK
Serial bus data output (open drain). Clocked out on the rising edge of SCPCK.
A 1kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended.
SCPDO
IRQ
42
43
Output
Output
Interrupt request output to the chipset Controller. Active low.
A 1 kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended.
DEV_ID1
DEV_ID0
VBIAS
45
44
9
Input (pull up)
Input (pull up)
Power
Serial bus device address:
00 = all; 01 = device 1; 10 = device 2; 11 = device 3.
One of three specialized voltages which are generated by the DLPA200.
Current limiter output for VBIAS supply. (also the VBIAS switching inductor input)
Connection point for VBIAS supply switching inductor.
VBIAS_LHI
VBIAS_SWL
10
8
Power
Power
21, 30, 31,
40, 61, 70,
71, 80
The internally-used VBIAS supply rail. Internally isolated from VBIAS.
VBIAS_RAIL
Power (substrate)
One of three specialized voltages which are generated by the DLPA200. The
package thermal pad is tied to this voltage level.
VRESET
13
12
Power
Power
VRESET_SWL
Connection point for VRESET supply switching inductor..
25, 26, 35,36,
65, 66, 75,
76
The internally-used VRESET supply rail. Internally isolated from VRESET.(1)
VRESET_RAIL(1)
VOFFSET
Power
Power
Power
49
One of three specialized voltages which are generated by the DLPA200.
The internally-used VOFFSET supply rail. Internally isolated from VOFFSET.
23, 28, 33,
38, 63, 68,
73, 78
VOFFSET_RAIL
1, 7, 14, 20,
41, 46, 53,
55, 60
Common ground
GND
Power
V5REG
P12V
NC
47
Power
Power
The 5-volt logic supply output.
The main power input to the DLPA200.
No connect
11, 48, 50
51, 52, 54
No Connect
(1) Exposed thermal pad is internally connected to VRESET_RAIL.
4
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DLPS015A –APRIL 2010–REVISED JUNE 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under " Absolute Maximum
Ratings” may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional
performance of the device at these or any other conditions beyond those indicated under “ Recommended Operating
Conditions” is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability.
CONDITIONS
MIN
TYP
MAX
14
UNIT
V
P12V
Load supply voltage
VRESET_SWL
VRESET_S
VBIAS_R
VOFFSET_R
VIN
Measured with respect to VRESET_RAIL
Measured with respect to VRESET_RAIL
Measured with respect to VRESET_RAIL
–1
V
VBIAS_RAIL
60
V
VOFFSET_RAIL
Logic inputs
40.5
7
V
–0.3
V
VOUT
Open drain logic outputs
7
V
TJ
Maximum junction
temperature
125
75
°C
°C
°C
TA
Operating temperature
range
0
TSTORE
Rc-j
Storage temperature
range
–55
150
Thermal resistance
VBIAS = 26 V, VRESET = -26 V, VOFFSET = 10 V,
Output load = 390 pF and 39R on each output,
Phase by one with global mode,
Channel repetition frequency = 50 kHz,
Additional external loads: IBIAS = 5 mA, IOFFSET = 30
mA, I5REG = 30 mA
3
°C/W
ESD
Human Body Model
Charge Device Model
2
kV
V
800
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RECOMMENDED OPERATING CONDITIONS
at TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No
level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Control Logic
VIL
VIH
IIH
Low-level logic input voltage
High-level logic input voltage
High-level logic input current
0.8
V
V
1.97
VIN = 5 V, input with pulldown. See terminal
functions table.
40
50
µA
µA
µA
µA
IIL
IIH
IIL
Low-level logic input current
VIN = 0 V, input with pullup. See terminal functions
table.
–50
–1
–40
High-level logic input leakage
current
VIN = 0 V, input with pulldown
1
1
Low-level logic input leakage
current
VIN = 5 V, input with pullup
–1
VOL
Open drain logic outputs
I = 4 mA
0.4
1
V
IOL
Logic output leakage current
V = 3.3 V
µA
Power
IP12V1
P12V supply current(1)
Global shadow at 50 kHz, OUT load = 39 Ω and 390
pF, V5REG = 30 mA, VBIAS = 26 V at 5 mA, VOFFSET
= 10V at 30 mA, VRESET = –26 V
200
mA
mA
IP12V2
Outputs disabled and no external loads, VBIAS = 19
V, VOFFSET = 4.5 V, VRESET = –19 V
22
TJTSDR Thermal shutdown temperature With device temperature rising
Hysteresis
145
5
160
10
175
15
°C
°C
Delta between thermal
shutdown and thermal warning
5
10
15
°C
TJTWR
Thermal warning temperature
With device temperature rising
Hysteresis
125
5
140
10
155
15
°C
°C
(1) During power up the inrush power supply current can be as high as 1 A for a momentary period of time.
ELECTRICAL CHARACTERISTICS
5-V Linear Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
TEST CONDITIONS
MIN
4.75
4
TYP
MAX
5.25
20
UNIT
V
V5REG
IIL
Output voltage
Average voltage, I_out = 4 mA to 50 mA
5
Output current: internal logic
mA
IIE
Output current: external
circuitry
0
30
mA
mA
ICL5
Current limit
80
VUV5
Undervoltage threshold
I_out = 50 mA
V5REG voltage increasing, P12V
= 5.4 V
4.1
3.9
V
V5REG voltage falling, P12V =
5.2 V
VRIP
VOS5
tss
Output ripple voltage(1)
Voltage overshoot at start up
Power up
200 mVpk-pk
2
1
%V5REG
ms
Measured between 10 to 90% of V5REG
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
6
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ELECTRICAL CHARACTERISTICS
Bias Voltage Boost Converter
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IRL
IQL
Output current: reset outputs
Load = 400pF, 39 Ω, repetition frequency = 50
kHz
0
18
mA
Output current: quiescent /
drivers
Load = 400 pF, 39 Ω, repetition frequency = 50
kHz
3
5
mA
IDL
Output current: DMD load
Current limit flag
0
30
mA
mA
mA
ICLFB
ICLB
VUVB
VUVLHI
Corresponding current on output at P12V = 10.8 V
Measured on input
Current limit
330
50
376
8
460
VBIAS undervoltage threshold
Bias voltage falling
92 %VBIAS
VBIAS_LHI undervoltage
threshold
VBIAS_LHI voltage increasing
V
VBIAS_LHI voltage falling
TJ = 25°C
6.5
2
V
Ω
RDS
VRIP
FSW
VOSB
tss
Boost switch Rdson
Output ripple voltage(1)
Switching frequency
Voltage overshoot at start up
Power up
200 mVpk-pk
1.35
400
1.5
1.65
2
MHz
%VBIAS
Cout = 3.3 µF, Measured between 10 to 90% of
target VBIAS
1
ms
tdis
Discharge current sink
mA
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
ELECTRICAL CHARACTERISTICS
Reset Voltage Buck-Boost Converter
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IRL
Output current: reset outputs
Load = 400 pF, 39 Ω, repetition frequency = 50
kHz
0
18
mA
IQL
Output current: quiescent / drivers
Current limit flag
Load = 400 pF, 39 Ω , repetition frequency = 50
kHz
3
mA
ICLFR
Corresponding current on output at P12V = 10.8
V
25
mA
mA
ICLR
VUVR
RDS
VRIP
FSW
VOSR
tss
Current limit
Measured on input
Reset voltage falling
TJ = 25°C
400
50
800
Undervoltage threshold
Buck-boost switch Rdson
Output ripple voltage(1)
Switching frequency
Voltage overshoot at start up
Power up
92 %VRESET
Ω
8
200 mVpk-pk
1.35
1.5
1.65
2
MHz
%VRESET
Cout = 3.3 µF, Measured between 10 to 90% of
target VRESET
1
ms
tdis
Discharge current sink
400
mA
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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ELECTRICAL CHARACTERISTICS
VOFFSET/DMDVCC2 Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAAMETER
TEST CONDITIONS
MIN
TYP
MAX
12.2
3
UNIT
IRL
IQL
Output current: reset outputs
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
0
mA
Output current: quiescent /
drivers
mA
IDL
Output current: DMDVCC2
0
100
50
30
mA
mA
ICLO Current limit
VUVO Undervoltage threshold
VRIP Output ripple voltage(1)
VOSO Voltage overshoot at start-up
VOFFSET voltage falling
92 %VOFFSET
100
mVpk-pk
2
1
%VOFFSET
tss
Power up
Cout = 4.7 µF, Measured between 10 to 90% of target
VOFFSET
ms
tdis
Discharge time constant
100
ms
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Serial Communication Port Interface
A(1)
B(1)
C(1)
D(1)
Setup SCPEN Low To SCPCK
Byte To Byte Delay
Reference to rising edge of SCPCK
Nominally 1 SCPCK cycle, rising edge to rising edge
Last byte to slave disable
360
1.9
360
0
ns
µs
Setup SCPDI To SCPEN High
SCPCK Frequency(2)
SCPCK Period
ns
526 kHz
1.9
300
300
300
2
µs
ns
ns
ns
ns
E(1)
F(1)
G(1)
H(1)
SCPCK High Or Low Time
SCPDI Set-Up Time
Reference to falling edge of SCPCK
Reference from falling edge of SCPCK
Reference from rising edge of SCPCK
SCPDI Hold Time
SCPDO Propagation Delay
300
SCPEN, SCPCK, SCPDI, RESET
Filter (Pulse Reject)
150
ns
Output Micromirror Clocking Pulses
Phased reset repetition frequency
FPREP
50 kHz
50 kHz
each output pin (non-overlapping)
Global reset repetition frequency all
FGREP
output pins
IRLK
IBLK
IOLK
VRESET output leakage current
VBIAS output leakage current
VOFFSET output leakage current
OE = 1, VRESET_RAIL = -28.5V
OE = 1, VBIAS_RAIL = 28.5V
OE = 1, VOFFSET_RAIL = 10.25V
-1
1
-10
10
10
µA
µA
µA
1
Output Micromirror Clocking Pulse Controls
tSPW
tSP
STROBE Pulsewidth
STROBE Period
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHZ
tOEN
tSUS
tHOS
tPBR
tPRO
tPOB
Output Time To High Z
Output Enable Time From High Z
Set-Up Time
OE Pin = High
100
100
OE Pin = Low
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
From STROBE to VBIAS/VRESET edge 50% point.
From STROBE to VRESET/VOFFSET edge 50% point.
From STROBE to VOFFSET/VBIAS edge 50% point.
8
8
Hold time
80
80
80
200
200
200
Propagation time
Maximum difference between the slowest and fastest
propagation times for any given reset output.
tDEL
Edge-to-edge propagation delta
40
20
ns
ns
Output channel-to-channel
propagation delta
Maximum difference between the slowest and fastest
propagation times for any two outputs for any given edge.
tCHCH
(1) See Figure 2
(2) There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.
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SCPENZ
D
C
A
E
E
B
Clock 1
Byte 1
Clock 2
Byte 1
Clock 3
Byte 1
Clock 8
Byte 1
Clock 1
Byte 2
Clock 8
Last byte
SCPCK
F
G
G
G
F
F
SCPDI
X
X
X
X
X
X
H
H
H
SCPDO
X = Don’t care
Figure 2. Serial Interface Timing
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DLPS015A –APRIL 2010–REVISED JUNE 2010
PRINCIPLES OF OPERATION
5-V Linear Regulator
The 5-V linear regulator supplies the 5 V requirement of the DLPA200 internal logic.
Figure 3 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal
DLPA200 modules. See Component Selection Guidelines for recommended component values.
5 V Linear
Regulator
P12V
V5REG
GND
Figure 3. 5-Volt Linear Regulator Block Diagram
Bias Voltage Boost Converter
The bias voltage converter is a switching supply that operates at 1.5 MHz. The bias switching device switches
180° out-of-phase with the reset switching device.
The converter supplies the internal bias voltage for the high voltage FET switches and the external VBIAS for the
DMD border mirrors. The VBIAS voltage level can be different for different generations of DMDs. The VBIAS voltage
level is configured by the DLP Controller chip over a serial communication interface. Four control bits select the
voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and
unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.
Figure 4 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal
DLPA200 modules. See Component Selection Guidelines for recommended component values.
Inductor
VBIAS_LHI
VBIAS_SWL
P12V
VBIAS
V5REG
BGAP REF
OSC
Bias Boost
Converter and
Current Limit
BIAS
STATUS
Serial Interface
and Control
2
4
BIAS
CONTROL
ENABLE
GND
Figure 4. Bias Voltage Boost Converter Block Diagram
Reset Voltage Buck-Boost Converter
The reset voltage buck-boost converter is a switching supply that operates at 1.5 MHz. The reset switching
device switches 180° out-of-phase with the bias switching device.
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The converter supplies the internal reset voltage levels for the high voltage FET switches. The VRESET voltage
level can be different for different generations of DMDs. The VRESET voltage level is configured by the DLP
Controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is
the on/off control. The module provides two status bits to indicate latched and unlatched status bits for
under-voltage (VUV) and current-limit (CL) conditions.
Figure 5 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal
DLPA200 modules. See Component Selection Guidelines for recommended component values.
P12V
SWL
VRESET
V5REG
BGAP REF
OSC
VRESET_SWL
Reset Buck-Boost
Converter and
Current Limit
Serial Interface
and Control
RESET
STATUS
2
4
RESET
CONTROL
Inductor
ENABLE
GND
Figure 5. Reset Voltage Buck-Boost Converter Block Diagram
VOFFSET/DMDVCC2 Regulator
The VOFFSET/DMDVCC2 regulator supplies the internal VOFFSET voltage for the high voltage FET switches and the
external DMDVCC2 for the DMD. The VOFFSET voltage level can be different for different generations of DMDs.
The VOFFSET voltage level is configured by the DLP Controller chip over a serial communication interface.Four
control bits select the voltage level while a fifth bit is the on/off control. The module provides 2 status bits to
indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.
Figure 6 shows the block diagram of this module. The input de-coupling capacitors are shared with other
DLPA200 modules. See Component Selection Guidelines for recommended component values.
P12V
VOFFSET
DMDVCC2
V5REG
BGAP REF
V
Linear
OFFSET
Serial Interface
and Control
Regulator and
Current Limit
OFFSET
STATUS
2
4
OFFSET
CONTROL
ENABLE
GND
Figure 6. Offset Voltage Boost Convertor Block Diagram
Driver Output Logic Block
The clocking waveform present on each OUTxx pin is managed by the DLP Controller chip, as shown in
Figure 7.
12
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DLPS015A –APRIL 2010–REVISED JUNE 2010
OEZ
UU[1:0]
D
D
D
D
Q
Q
SEL[1:0]
A[3:0]
V
RESET
V
OFFSET
V
BIAS
Q
Q
Shadow
Enable
MODE[1:0]
OUTPUT
CONTROL
DECODE
LOGIC
VOLTAGE
SELECT
OUTPUT
BBM &
DRIVERS
X16
Enable
CONTROL
LATCHES
X16
Reset
Output
D
D
GLOBAL SHADOW
Q
Q
Global or
Adjacent
ADJACENT SHADOW
STROBE
RESETZ
Figure 7. Driver Output Logic Block
PWB LAYOUT AND ROUTING GUIDELINES
WARNING
Board layout and routing guidelines must be followed explicitly and all external
components used must be in the range of values and of the quality
recommended for proper operation of the DLPA200. Important: Thermal pad(s)
must be tied to VRESET_RAIL, do not connect to ground.
WARNING
Thermal pad(s) must be tied to VRESET_RAIL, do not connect to ground.
General Guidelines
Suitable Kelvin connections should be provided for the switching regulator feedback pins: VBIAS (pin 9) and
VRESET (pin 13).
The etch traces that connect the switching devices: VBIAS_SWL (pin 8) and VRESET_SWL (pin 12) should be
as short and wide as possible to minimize leakage inductances. The etch traces that connect the switching
converter components (inductors, flywheel diodes and filtering capacitors) should also be as short and wide as
possible. The electrical loops that these components form should be as small and compact as possible, with the
ground referenced components forming a star connection.
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Due to the fast switching transitions appearing on the sixteen reset OUTx pins, it is recommended to keep these
traces as short as possible. Also, to minimize potential cross-talk between outputs, it is advisable to maintain as
much clearance between each of the output traces.
Grounding Guidelines
The PWB should have an internal ground plane that extends under the DLPA200. All 9 ground pins (1, 7, 14, 20,
41, 46, 53, 55, and 60) must be connected to the ground plane using the shortest possible runs and vias. All filter
and bypass capacitors must be placed near the pin being filtered or bypassed for the shortest possible runs to
the part and to the ground plane.
Thermal Guidelines
The DLPA200 package should be thermally bonded or soldered to an external thermal pad on the PWB surface.
The recommended dimensions of the thermal pad are 10 x 10 mm centered under the part. The metal bottom of
the package is tied internally to the substrate at the VRESET_RAIL voltage level. Therefore, the thermal pad on
the board must be isolated from any other extraneous circuit or ground and no circuit vias are allowed inside the
pad area. Thermal pads are required on both sides of the PWB and should be connected together through an
array of 5 x 5 thermal vias, 0.5 mm in diameter. Thermal pads and the thermal vias are connected to
VRESET_RAIL and isolated from ground, or any other circuit. An internal P12V or VBB plane should be
located directly underneath the top layer and have an isolated area under the DLPA200. This isolated area must
be a minimum of 20 cm2 and connect to the thermal pad of the DLPA200 through the thermal vias. The potential
of the isolated area will also be at VRESET_RAIL. The internal ground plane should extend under the DLPA200
to help carry the heat away.
Careful consideration should be taken with respect to DLPA200 placement in the vicinity of local PWB hotspots.
Heat generated from adjacent components may impact the DLPA200 thermal characteristics.
Power Supply Rail Guidelines
Table 1 through Table 5 provides discrete component selection guidelines.
The P12V filter and bypass capacitors should be distributed and connected to pin 11 and pins 48 & 50. These
capacitors should be placed as near to their respective pins as possible and if necessary, should be placed on
the bottom layer.
The V5REG filter and bypass capacitors must be placed near and connected to pin 47.
The VBIAS_RAIL etch runs should be routed in the following order: pin 40, pin 31, pin 30, pin 21, pin 80, pin 71,
pin 70, and pin 61. The etch runs should be short and direct as they must carry 35 ns current spikes of up to
0.64 amps peak. Bypass capacitors should be located near and connected to pins 30 and 71 to provide
bypassing on both sides.
The VBIAS_LHI filter and bypass capacitors must be placed near and connected to pin 10.
The VBIAS filter and bypass capacitors must be placed near and connected to pin 9. VBIAS pin 9 must also be
connected (optionally with a 0-ohm resistor) to VBIAS_RAIL at or between pins 21 and 80.
The VRESET_RAIL etch runs should be routed in the following order: pin 36, pin 35, pin 26, pin 25, pin 76, pin
75, pin 66, and pin 65. The etch runs should be short and direct as they must carry 35 ns current spikes of up to
0.64 amps peak. Bypass capacitors should be placed near and connected to pins 35 and 66 to provide
bypassing on both sides.
The VRESET filter and bypass capacitors must be located near and connected to pin 13. VRESET pin 13 must
also be connected (optionally with a 0-ohm resistor) to VRESET_RAIL at or between pins 25 and 76.
The VOFFSET_RAIL etch runs should be routed in the following order: pin 23, pin 28, pin 33, pin 38, pin 63, pin
68, pin 73, and pin 78. The etch runs should be short and direct as they must carry 35 ns current spikes of up to
0.64 amps peak. Bypass capacitors should be placed near and connected to pins 28 and 73 to provide
bypassing on both sides.
The VOFFSET filter and bypass capacitors must be placed near and connected to pin 49. VOFFSET pin 49 must
also be connected (optionally with a 0-ohm resistor) to VOFFSET_RAIL at or between pins 38 and 63.
14
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WARNING
Aluminum electrolytic capacitors may not be suitable for the DLPA200
application. At the switching frequencies used in the DLPA200 (up to 1.5MHz),
aluminum electrolytic capacitors drop significantly in capacitance and increase
in ESR resulting in voltage spikes on the power supply rails, which could cause
the device to shut down or perform in an unreliable manner.
COMPONENT SELECTION GUIDELINES
Table 1. 5-V Regulator
TYPE OR PART
COMPONENT
VALUE
CONNECTION 1
CONNECTION 2
Neg: Ground
Ground
NUMBER
10 to 33 µF, 20 VDC,
Pos: P12V, pin 11
(locate near pin 11)
P12V filter capacitor
P12V bypass capacitor
V5REG filter capacitor
V5REG bypass capacitor
Tantalum or ceramic
1Ω max ESR
0.1 µF, 50 VDC,
0.1Ω max ESR
0.1(1) to 1.0 µF, 10 VDC,
P12V, pin 11
(locate near pin 11)
Ceramic
Tantalum or ceramic
Ceramic
Pos: V5REG, pin 47
(locate near pin 47)
Neg: Ground
Ground
2.5Ω max ESR
0.1 µF(1), 16 VDC,
0.1Ω max ESR
V5REG, pin 47
(locate near pin 47)
(1) To ensure stability of the linear regulator, the capacitance should not be less than 0.1 µF.
Table 2. Bias Voltage Boost Converter
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
10 µF, 20 VDC,
1Ω max ESR
Pos: VBIAS_LHI, pin 10
(locate near pin 10)
LHI filter capacitor
Tantalum or ceramic
Ceramic
Neg: Ground
Ground
0.1 µF, 50 VDC,
0.1Ω max ESR
VBIAS_LHI, pin 10
(locate near pin 10)
LHI bypass capacitor
1 to 10 µF, 35 VDC,
1Ω max ESR;
(3.3 µF nominal value)
Pos: VBIAS, pin 9
(locate near pin 9)
VBIAS filter capacitor
Tantalum or ceramic
Neg: Ground
0.1 µF, 50 VDC,
0.1Ω max ESR
VBIAS, pin 9
(locate near pin 9)
VBIAS bypass capacitor
Ceramic
Ceramic
Ground
Ground
VBIAS_RAIL bypass
capacitors (2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
VBIAS_RAIL, pins 30 and 71
(locate near pins 30 and 71)
0-ohm normally
VBIAS_RAIL,
pins 21 or 80
Resistor jumper (optional)
Inductor
VBIAS, pin 9
(1Ω for testing(1)
)
22 µH, 0.5 amp,
160 mΩ ESR
Coil Craft DT1608C-223
(or equivalent)
VBIAS_LHI, pin 10
VBIAS_SWL, pin 8
Motorola MBR0540T1 or
STMicroelectronics
STPS0540Z, STPS0560Z
(or equivalent)
Anode:
VBIAS_SWL, pin 8
Cathode:
VBIAS, pin 9
Schottky diode
0.5A, 40V (minimum)
(1) Allows for VBIAS current measurement.
Table 3. Reset Voltage Boost Converter
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
1 to 10 µF, 35 VDC,
1Ω max ESR;
(3.3 µF nominal value)
Neg: VRESET, pin 13
(locate near pin 13)
VRESET filter capacitor
Tantalum or ceramic
Ceramic
Pos: Ground
Ground
0.1 µF, 50 VDC,
0.1Ω max ESR
VRESET, pin 13
(locate near pin 13)
VRESET bypass capacitor
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Table 3. Reset Voltage Boost Converter (continued)
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
VRESET_RAIL,
pins 35 and 66
(locate near pins 35 and 66)
VRESET_RAIL bypass
capacitors (2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
Ground
0-ohm normally
VRESET_RAIL,
pins 25 or 76
Resistor jumper (optional)
Inductor
VRESET, pin 13
(1Ω for testing(1)
)
22 µH, 0.5A,
160 mΩ
Coil Craft DT1608C-223
(or equivalent)
VRESET_SWL, pin 12
Ground
STMicroelectronics
STPS0560Z or
International Rectifier
10MQ060N (or equivalent)
Cathode:
VRESET_SWL, pin 12
Anode:
VRESET, pin 13
Schottky diode
0.5 A (minimum), 60 V
(1) Allows for VRESET current measurement.
Table 4. Offset Voltage Regulator
COMPONENT
VALUE
TYPE OR PART
NUMBER
CONNECTION 1
CONNECTION 2
Pos: VOFFSET, pin 49
(1st near pin 49)
Pos: DMDVCC2 pins
(locate 2nd at DMD)
VOFFSET/VCC2
filter capacitors
(2 required)
1.0(1) to 4.7(2) µF, 35
VDC,
Neg: Ground at DLPA200
Neg: Ground at DMD
Tantalum or ceramic
Ceramic
1Ω max ESR
VOFFSET, pin 49
(locate 1 near pin 49)
DMD DMDVCC2 pins
(locate 4 near DMD pins)
VOFFSET/VCC2
bypass capacitors
(5 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Ground at DLPA200
Ground at DMD
VOFFSET_RAIL,
pins 28 and 73
(locate near pins 28 and
73)
VOFFSET_RAIL
bypass capacitor
(2 required)
0.1 µF, 50 VDC,
0.1Ω max ESR
Ceramic
Ground
Resistor jumper
(optional)
0-ohm normal
VOFFSET_RAIL,
pins 38 or 63
VOFFSET, pin 49
VOFFSET, pin 49
(1Ω for testing(3)
)
Resistor jumper
(optional)
0-ohm normal
DMDVCC2 pins
(1Ω for testing(4)
)
(1) To ensure stability of the linear regulator, the absolute minimum output capacitance should not be less than 1.0 µF.
(2) Recommended value is 3.3 µF each. Different values are acceptable, provided that the sum of the two is 6.8 µF maximum.
(3) Allows for VOFFSET current measurement
(4) Allows for DMDVCC2 current measurement
Table 5. Pullup Resistors
COMPONENT
VALUE
TYPE OR PART NUMBER
CONNECTION 1
CONNECTION 2
Chipset controller
3.3-V VDD
Resistor
1 kΩ
SCPDO, pin 42
Chipset Controller
3.3-V VDD
Resistor
1 kΩ
1 kΩ
IRQ, pin 43
OE, pin 6
Chipset Controller
3.3-V VDD
Resistor (optional)
16
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DLPS015A –APRIL 2010–REVISED JUNE 2010
Revision History
REVISION
DATE
SECTION(S)
All
COMMENT
Initial release
*
March 2010
June 2010
A
Device Marking
Modified Device marking to show TI internal part number
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Purchase Samples
Purchase Samples
DLPA200PFC
DLPA200PFCT
ACTIVE
ACTIVE
TQFP
TQFP
PFC
PFC
80
80
1
Pb-Free (RoHS)
Pb-Free (RoHS)
Call TI
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
10
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996
PFC (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,50
60
0,08
41
40
61
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
0,25
14,20
SQ
0,05 MIN
0°–7°
13,80
0,75
0,45
1,05
0,95
Seating Plane
0,08
1,20 MAX
4073177/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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