DLPA300 [TI]
DLP® driver for DLP780NE (0.78 1080p), DLP780TE (0.78 4K UHD), DLP800RE (0.80 WUXGA) DM;
| 型号： | DLPA300 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® driver for DLP780NE (0.78 1080p), DLP780TE (0.78 4K UHD), DLP800RE (0.80 WUXGA) DM |
| 文件： | 总28页 (文件大小：1261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLPA300
ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
DLPA300 适用于DLP 数字微镜器件的驱动器
1 特性
3 说明
• 专为DLP® 9μm 像素数字微镜器件(DMD) 而设计
DLPA300 器件是一款适用于DLP 9μm 像素、高效数
字微镜器件(DMD)（包括DLP780NE、DLP780TE、
DLP800RE、DLP781NE、DLP781TE、DLP801RE
和DLP801XE DMD）的微镜驱动器。在这些DMD 芯
片组中，DLPA300 微镜驱动器会生成VOFFSET 和
– DLP780NE
– DLP780TE
– DLP800RE
– DLP781NE
V
BIAS 电压。它还可以切换VOFFSET、VBIAS 和外部生
– DLP781TE
成的VRESET，从而生成DLP DMD 的微镜时钟脉冲。
– DLP801RE
TI DLPC4420 或DLPC4430 显示控制器管理此波形的
时序。
– DLP801XE
• 生成9μm 像素DMD 所需的微镜时钟脉冲
• 生成微镜时钟脉冲所需的特定电压电平
器件信息
器件型号(1)
封装
封装尺寸
2 应用
DLPA300
HTQFP (80)
14.00mm × 14.00mm
• 企业投影仪
• 智能投影仪
• 激光电视
(1) 如需了解所有可用封装，请参阅此数据表末尾的可订购产品附
录。
• 数字标牌
• 大型场馆投影仪
• ProAV 投影仪
SCP
MODE
SELECT
(2)
(2)
(4)
A[0:3]
STROBE
OE
MBRST
(15)
DLPA300
Micromirror
Driver
RESET
DLPC4430
Display Controller
DLP780NE
DMD
IRQ
DEV_ID
(2)
GND
VRESET_RAIL
-16.5 V
VREG
12 V
DMD POWER En
10 V
VREG
VREG
1.8 V
3.3 V
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS227
DLPA300
www.ti.com.cn
ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
Table of Contents
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................22
9.1 Power Supply Rail Guidelines...................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Thermal Considerations..........................................23
11 Device and Documentation Support..........................24
11.1 第三方产品免责声明................................................24
11.2 Device Support........................................................24
11.3 Documentation Support.......................................... 24
11.4 接收文档更新通知................................................... 24
11.5 支持资源..................................................................24
11.6 Trademarks............................................................. 25
11.7 静电放电警告...........................................................25
11.8 术语表..................................................................... 25
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics Control Logic...................... 7
6.6 5-V Linear Regulator...................................................8
6.7 Bias Voltage Boost Converter.....................................8
6.8 Reset Voltage Buck-Boost Converter......................... 9
6.9 VOFFSET Regulator...................................................... 9
6.10 Switching Characteristics........................................10
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2021) to Revision A (June 2023)
Page
• 针对全新 DMD 更新了 特性 ...............................................................................................................................1
• 更新了 应用 ....................................................................................................................................................... 1
• 针对全新 DMD 更新了 说明 ...............................................................................................................................1
• Added minimum value to VIN in Absolute Maximum Ratings .............................................................................6
• Updated FSW in Bias Voltage Boost Converter ..................................................................................................8
• Deleted Discharge time constant in VOFFSET Regulator .................................................................................... 9
• Added Discharge current sink in VOFFSET Regulator ......................................................................................... 9
• Updated Overview ........................................................................................................................................... 12
• Updated drawing for proper logic polarity in Functional Block Diagram .......................................................... 13
• Updated switching frequency in Bias Voltage Boost Converter .......................................................................14
• Updated Bias Voltage Boost Converter for new DMDs.................................................................................... 14
• Updated VOFFSET Regulator for new DMDs......................................................................................................15
• Updated Application Information ......................................................................................................................17
• Updated Typical Application ............................................................................................................................ 17
• Updated Design Requirements ........................................................................................................................18
• Corrected minor typos in Detailed Design Procedure ......................................................................................19
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS227
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
5 Pin Configuration and Functions
GND
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
RESET
SCPEN
SCPDI
SCPCK
GND
MODE1
MODE0
SEL1
SEL0
OE
GND
NC
GND
_
VBIAS SWL
VBIAS
_
VBIAS LHI
P12V
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
P12V
VOFFSET
P12V
V5REG
GND
_
VRESET SWL
VRESET
GND
STROBE
A3
_
DEV ID1
A2
A1
A0
GND
_
DEV ID0
IRQ
SCPDO
GND
图5-1. PFP Package 80-Pin HTQFP Top View
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Product Folder Links: DLPA300
English Data Sheet: DLPS227
DLPA300
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
表5-1. Package Pinout
PIN
I/O
(INPUT
DEFAULT)
DESCRIPTION
NAME
OUT00
NO.
22
24
27
29
32
34
37
39
62
64
67
69
72
74
77
79
19
18
17
16
3
Output
Output
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUT08
OUT09
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
A0
Output
Output
Output
Output
Output
Output
16 micromirror clocking waveform outputs (enabled by OE = 0)
Output
Output
Output
Output
Output
Output
Output
Output
Input (pulldown)
Input (pulldown)
Input (pulldown)
Input (pulldown)
Input (pulldown)
Input (pulldown)
Input (pulldown)
Input (pulldown)
A1
Output Address. Used to select which OUTxx pin is active at a given time
Mode Select. Used to determine the operating mode of the DLPA300
A2
A3
MODE0
MODE1
SEL0
2
5
Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx
pin
SEL1
4
STROBE
15
Input (pulldown) A rising edge on STROBE latches in the control signals after a tristate delay
Asynchronous input controls whether the 16 OUTxx pins are active or are in a in
OE
6
Input (pullup)
high-impedance state.
OE = 0 : Enabled. OE = 1 : High Z
RESET
SCPEN
SCPDI
SCPCK
59
58
57
56
Input (pullup)
Input (pullup)
Resets the DLPA300 internal logic. Active low. Asynchronous
Enables serial bus data transfers. Active low
Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK
Input (pull down) Serial bus clock. Provided by chipset controller
Serial bus data output (open drain). Clocked out on the rising edge of SCPCK.
Output
SCPDO
42
A 1-kΩpullup resistor to the chip-set controller VDD supply is recommended.
Interrupt request output to the chipset Controller. Active low.
Output
IRQ
43
45
44
A 1-kΩpullup resistor to the chip-set controller VDD supply is recommended.
DEV_ID1
DEV_ID0
Input (pullup)
Input (pullup)
Serial bus device address:
00 = all; 01 = device 1; 10 = device 2; 11 = device 3
VBIAS
9
10
8
Output
Input
One of three specialized voltages the DLPA300 generates
VBIAS_LHI
VBIAS_SWL
Current limiter output for VBIAS supply (also the VBIAS switching inductor input)
Connection point for VBIAS supply switching inductor
Input
21, 30, 31,
40, 61, 70,
71, 80
VBIAS_RAIL
VRESET
Input
The internally used VBIAS supply rail. Internally isolated from VBIAS
This pin is unused by the DLPA300.
13
No Connect
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English Data Sheet: DLPS227
DLPA300
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
表5-1. Package Pinout (continued)
PIN
I/O
(INPUT
DEFAULT)
DESCRIPTION
NAME
NO.
VRESET_SWL
12
No Connect
This pin is unused by the DLPA300.
The internally-used VRESET supply rail. Internally isolated from VRESET. The
external VRESET supply is connected to this pin. The package thermal pad is tied to
this voltage level.(1)
25, 26, 35,36,
65, 66, 75, 76
VRESET_RAIL(1)
VOFFSET
Input
49
Output
Input
One of three specialized voltages the DLPA300 generates
23, 28, 33,
38, 63, 68,
73, 78
VOFFSET_RAIL
The internally-used VOFFSET supply rail. Internally isolated from VOFFSET
1, 7, 14, 20,
41, 46, 53,
55, 60
GND
GND
Common ground
V5REG
P12V
NC
47
Output
Input
The 5-V logic supply output
The main power input to the DLPA300
No connect
11, 48, 50
51, 52, 54
No Connect
(1) Exposed thermal pad is internally connected to VRESET_RAIL.
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Product Folder Links: DLPA300
English Data Sheet: DLPS227
DLPA300
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
ELECTRICAL
P12V
Load supply voltage
14
V
V
Reset supply switching inductor connection
point
(VRESET_SWL-
VRESET_RAIL )
VRESET_SWL
–1
(VBIAS_RAIL-
VRESET_RAIL)
VBIAS_RAIL
Internally-used VBIAS supply rail
60
V
V
(VOFFSET_RAIL-
VRESET_RAIL)
VOFFSET_RAIL Internally-used VOFFSET supply rail
40.5
VIN
Logic inputs
7
7
V
V
–0.3
VOUT
Open drain logic outputs
ENVIRONMENTAL
TJ(max)
TA
Maximum junction temperature
Operating temperature
Storage temperature
125
75
°C
°C
°C
0
Tstg
150
–55
(1) Stresses beyond those listed under 节6.1 may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under 节6.3 is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
800
UNIT
Human body model (HBM)(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM)(2)
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
at TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)(2)
POWER
MIN
NOM
MAX
UNIT
Global shadow at 50 kHz, OUT load = 39 Ωand 410
IP12V1
200
mA
pF, V5REG = 30 mA, VBIAS = 21 V at 5 mA, VOFFSET
10V at 30 mA
=
P12V supply current(1)
Outputs disabled and no external loads, VBIAS = 21 V,
VOFFSET = 4.5 V
IP12V2
22
mA
With device temperature rising
Hysteresis
145
5
160
10
175
15
°C
°C
TJTSDR Thermal shutdown temperature
Delta between thermal
shutdown and thermal warning
5
10
15
°C
With device temperature rising
Hysteresis
125
5
140
10
155
15
°C
°C
TJTWR
Thermal warning temperature
(1) During power up the inrush power supply current can be as high as 1 A for a momentary period of time.
(2) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: DLPS227
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6.4 Thermal Information
DLPA300
THERMAL METRIC(1)
PFP (HTQFP)
UNIT
80 PINS
Rc-j
Thermal resistance
3
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics Control Logic
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIL
VIH
Low-level logic input voltage
High-level logic input voltage
0.8
1.97
V
VIN = 5 V, input with pulldown. See terminal functions
table.
IIH
IIL
IIH
IIL
High-level logic input current
Low-level logic input current
40
50
µA
µA
µA
µA
VIN = 0 V, input with pullup. See terminal functions
table.
–50
–1
–40
High-level logic input leakage
current
VIN = 0 V, input with pulldown
VIN = 5 V, input with pullup
1
1
Low-level logic input leakage
current
–1
VOL
IOL
Open drain logic outputs
I = 4 mA
0.4
1
V
Logic output leakage current
V = 3.3 V
µA
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English Data Sheet: DLPS227
DLPA300
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
6.6 5-V Linear Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.75
4
TYP
MAX
UNIT
V
V5REG
IIL
Output voltage
Average voltage, IOUT = 4 mA to 50 mA
5
5.25
20
Output current: internal logic
mA
Output current: external
circuitry
IIE
0
30
mA
mA
ICL5
Current limit
80
V5REG voltage increasing, P12V
= 5.4 V
4.1
3.9
VUV5
Undervoltage threshold
IOUT = 50 mA
V
V5REG voltage falling, P12V =
5.2 V
VRIP
VOS5
tss
Output ripple voltage(1)
Voltage overshoot at start up
Power up
200 mVpk-pk
2
1
%V5REG
ms
Measured between 10 to 90% of V5REG
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
6.7 Bias Voltage Boost Converter
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Load = 400pF, 39 Ω,
repetition frequency = 50 kHz
IRL
IQL
Output current: reset outputs
0
18
mA
mA
Output current: quiescent /
drivers
Load = 400 pF, 39 Ω,
repetition frequency = 50 kHz
3
5
IDL
Output current: DMD load
Current limit flag
0
30
mA
mA
mA
V
ICLFB
ICLB
Corresponding current on output at P12V = 10.8 V
Measured on input
Current limit
330
20.5
50
376
21
460
VBIAS
VUVB
Output voltage
21.5
VBIAS undervoltage threshold
Bias voltage falling
92 %VBIAS
VBIAS_LHI voltage increasing
VBIAS_LHI voltage falling
TJ = 25°C
8
6.5
2
V
V
VBIAS_LHI undervoltage
threshold
VUVLHI
RDS
VRIP
FSW
VOSB
Boost switch RDS(on)
Ω
Output ripple voltage(1)
200 mVpk-pk
Switching frequency
1.1
1.3
1.5
2
MHz
Voltage overshoot at start up
%VBIAS
COUT = 3.3 µF, Measured between 10 to 90% of
target VBIAS
tss
Power up
1
ms
tdis
Discharge current sink
400
mA
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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English Data Sheet: DLPS227
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6.8 Reset Voltage Buck-Boost Converter
This is feature is not used in the DLPA300.
6.9 VOFFSET Regulator
TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output current: reset
outputs
IRL
IQL
0
12.2
mA
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
Load = 400 pF, 39 Ω, repetition frequency = 50 kHz
Output current: quiescent /
drivers
3
mA
IDL
Output current
Current limit
0
100
9.75
50
30
mA
mA
V
ICLO
VOFFSET Output Voltage
10
10.25
VUVO
VRIP
Undervoltage threshold
VOFFSET voltage falling
92 %VOFFSET
Output ripple voltage(1)
100
mVpk-pk
Voltage overshoot at start-
up
VOSO
2 %VOFFSET
COUT = 4.7 µF, Measured between 10 to 90% of target
VOFFSET
tss
Power up
1
ms
Idis
Discharge current sink
400
mA
(1) Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice.
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English Data Sheet: DLPS227
DLPA300
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ZHCSOK9A –OCTOBER 2021 –REVISED JUNE 2023
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SERIAL COMMUNICATION PORT INTERFACE
A(1)
B(1)
C(1)
D(1)
Setup SCPEN low to SCPCK
Byte to byte delay
Reference to rising edge of SCPCK
360
1.9
360
0
ns
µs
Nominally 1 SCPCK cycle, rising edge to rising edge
Last byte to secondary disable
Setup SCPDI to SCPEN high
SCPCK frequency(2)
SCPCK period
ns
526 kHz
1.9
300
300
300
2
µs
ns
ns
ns
ns
E(1)
F(1)
G(1)
H(1)
SCPCK high or low time
SCPDI set-up time
Reference to falling edge of SCPCK
Reference from falling edge of SCPCK
Reference from rising edge of SCPCK
SCPDI hold time
SCPDO propagation delay
300
SCPEN, SCPCK, SCPDI, RESET
filter (pulse reject)
150
ns
OUTPUT MICROMIRROR CLOCKING PULSES
Phased reset repetition frequency
FPREP
50 kHz
50 kHz
each output pin (non-overlapping)
Global reset repetition frequency all
FGREP
output pins
IRLK
IBLK
IOLK
VRESET output leakage current
VBIAS output leakage current
VOFFSET output leakage current
OE = 1, VRESET_RAIL = -28.5V
OE = 1, VBIAS_RAIL = 28.5V
OE = 1, VOFFSET_RAIL = 10.25V
-1
1
-10
10
10
µA
µA
µA
1
OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS
tSPW
tSP
STROBE pulse width
STROBE period
10
20
ns
ns
ns
tOHZ
Output time to high impedance
OE Pin = High
OE Pin = Low
100
100
Output enable time from high
impedance
tOEN
ns
tSUS
tHOS
tPBR
tPRO
tPOB
Set-up time
Hold time
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge
From STROBE to VBIAS/VRESET edge 50% point.
From STROBE to VRESET/VOFFSET edge 50% point.
From STROBE to VOFFSET/VBIAS edge 50% point.
8
8
ns
ns
ns
ns
ns
80
80
80
200
200
200
Propagation time
Maximum difference between the slowest and fastest
propagation times for any given reset output.
tDEL
Edge-to-edge propagation delta
40
20
ns
ns
Output channel-to-channel
propagation delta
Maximum difference between the slowest and fastest
propagation times for any two outputs for any given edge.
tCHCH
(1) See 图6-1
(2) There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.
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English Data Sheet: DLPS227
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SCPEN
D
C
A
E
E
B
Clock 1
Byte 1
Clock 2
Byte 1
Clock 3
Byte 1
Clock 8
Byte 1
Clock 1
Byte 2
Clock 8
Last byte
SCPCK
F
G
G
G
F
F
SCPDI
X
X
X
X
X
X
H
H
H
SCPDO
X = Don’t care
图6-1. Serial Interface Timing
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English Data Sheet: DLPS227
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7 Detailed Description
7.1 Overview
The DLPA300 is a micromirror driver for the 9-μm pixel family of DMDs. These include the DLP780NE,
DLP800RE. DLP780TE, DLP781NE, DLP781TE, DLP801RE and DLP801XE DMDs. The DLPA300 micromirror
driver generates VOFFSET and VBIAS voltages required by the DMD. VRESET for the DMDs is generated by an
external voltage regulator. Under the control of the DLPC4430 (or DLPC4420) display controller, the DLPA300
micromirror driver switches these three voltage supplies to control the micromirror reset waveform via the
MBRST pins on the DMD.
Reliable function and operation of the DLPA300 micromirror driver require that it is used as part of the family of
9-μm pixel DMD chipsets. For LED and RGB direct laser illumination, the DLPA100 can be replaced by discrete
power supply ICs and a power supply sequencer.
The DLPA300 consists of three functional blocks: a high-voltage power supply function, a DMD micromirror clock
generation function, and a serial communication (SCP) function.
The high-voltage power supply function generates two specialized voltage levels: VBIAS (21-V) and VOFFSET (10-
V). The exact values are controlled by the DLPC4430 or DLPC4420 display controller. VRESET is generated by
external voltage regulator.
The micromirror clock generation function uses the two voltages generated by the high-voltage power supply
function and the one generated by the external voltage regulator to create the fifteen micromirror clock pluses
(output the OUT[0:14] pins of the DLPA300). OUT15 is unused.
The serial communication function allows the display controller to control the generation of VBIAS, VRESET, and
VOFFSET; control the generation of the micromirror clock pulses; and control the general operation of the
DLPA300 micromirror driver.
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7.2 Functional Block Diagram
MODE[1:0]
SEL[1:0]
A[3:0]
/2
/2
/4
Select, Latch,
Output Logic and
High-Voltage
Output FET
OUT(00-15)
/16
STROBE
OE
Switches
5-V and
Reference
P12V
V5REG
VBIAS_RAIL
VBIAS
VBIAS_LHI
V
BIAS Boost
VBIAS_SWL
VRESET_RAIL
(substrate)
VRESET
Buck-Boost
VRESET_SWL
VRESET
VOFFSET_RAIL
VOFFSET
VOFFSET
Regulator
SCPEN
SCPCK
Power-Up
Serial Bus Ini aliza on
Interface
Fault Logic
IRQ
SCPDI
SCPDO
DEV_ID[1:0]
/2
GND
RESET
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7.3 Feature Description
7.3.1 5-V Linear Regulator
The 5-V linear regulator supplies the 5-V needed for the internal logic of the DLPA300 micromirror driver. It can
also provide 5-V, up to 30 mA, for external peripherals.
图 7-1 shows the block diagram of this module. The input decoupling capacitors are shared with other internal
DLPA300 modules. See 节8.2.2.1 for recommended component values.
5 V Linear
Regulator
P12V
V5REG
GND
图7-1. 5-Volt Linear Regulator Block Diagram
7.3.2 Bias Voltage Boost Converter
The bias voltage converter is a switching supply that operates at 1.3 MHz. The converter supplies the internal
bias voltage for the high voltage FET switches. The VBIAS voltage level for the 9-μm pixel family of DMDs is
21V. The VBIAS voltage level is configured by the DLP display controller chip over the serial communication port
(SCP). Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two
status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions.
图 7-2 shows the block diagram of this module. The input decoupling capacitors are shared with other internal
DLPA300 modules. See 节8.2.2.1 for recommended component values.
Inductor
VBIAS_LHI
VBIAS_SWL
P12V
VBIAS
V5REG
BGAP REF
OSC
Bias Boost
Converter and
Current Limit
BIAS
STATUS
Serial Interface
and Control
2
4
BIAS
CONTROL
ENABLE
GND
图7-2. Bias Voltage Boost Converter Block Diagram
7.3.3 Reset Voltage Buck-Boost Converter
The internal reset voltage buck-boost converter in the DLPA300 is unused. An external voltage regulator is used
to generate the –16.5-V for VRESET. The output of this regulator is connected to the VRESET_RAIL pin on the
DLPA300 micromirror driver.
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The external voltage regulator provide reset voltage level for the high voltage FET switches. The internal reset
voltage buck-boost converter is disabled by the DLP display controller over the serial communication port.
7.3.4 VOFFSET Regulator
The VOFFSET regulator supplies the internal VOFFSET voltage for the high voltage FET switches. The VOFFSET
voltage level for the 9-μm pixel family of DMDs is 10-V during normal operation and 4.5-V during power down.
The VOFFSET voltage level is configured by the DLP controller chip over the serial communication port. Four
control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to
indicate latched and unlatched status bits for undervoltage (VUV) and current-limit (CL) conditions.
图 7-3 shows the block diagram of this module. The input decoupling capacitors are shared with other DLPA300
modules. See 节8.2.2.1 for recommended component values.
P12V
VOFFSET
DMDVCC2
V5REG
BGAP REF
V
Linear
OFFSET
Serial Interface
and Control
Regulator and
Current Limit
OFFSET
STATUS
2
4
OFFSET
CONTROL
ENABLE
GND
图7-3. Offset Voltage Boost Convertor Block Diagram
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7.3.5 Serial Communications Port (SCP)
The SCP is a full duplex, synchronous, character-oriented (byte) port that allows exchange of data between the
DLPC4430 or DLPC4420 display controller, and the DLPA300 micromirror driver (and other DLP devices). The
display controller is the primary on the SCP bus. The DLPA300 micromirror driver is the secondary on the SCP
bus.
表7-1. Serial Communications Port Signal Definitions
SIGNAL
I/O
FROM/TO
TYPE
DESCRIPTION
SCP bus primary to
secondary
SCP bus serial transfer clock. The host processor
(primary) generates this clock.
SCPCK
I
LVTTL compatible
SCP bus access enable (low true). When high,
secondary resets to the idle state, and SCPDO output
is tristated. Pulling SCPEN low initiates a read or write
access. SCPEN must remain low for an entire read/
write access, and must be pulled high after the last
data cycle. To abort a read or write cycle, pull SCPEN
high at any point.
SCP bus primary to
secondary
SCPEN
I
LVTTL compatible
SCP bus primary to
secondary
SCP bus serial data input. Data bits are valid and
must be clocked in on the falling edge of SCPCK.
SCPDI
I
LVTTL compatible
SCP bus serial data output. Data bits must clocked
out on the rising edge of SCPCK. A 1-kΩpullup
resistor to the 3.3-V display controller supply is
required.
SCP bus secondary to
primary
SCPDO
O
LVTTL, open drain w/tristate
Not part of the SCP bus definition. Asynchronous
interrupt signal from secondary to request service
from the primary. A 1-kΩpullup resistor to the 3.3-V
display controller supply is required.
SCP bus secondary to
primary
IRQ
O
LVTTL, open drain
7.4 Device Functional Modes
At power up, the DLPC4430 or DLPC4420 display controller configures the DLPA300 over the SCP bus. There
are two device functional modes. When OE is high, OUT[0:14] are tristated. When OE is low, the OUT[0:14] are
active under the control of the display controller.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLP display
controller. Typical applications using the DLP780NE, DLP800RE and DLP780TE chipsets include laserTVs,
smart projectors, enterprise projectors and digital signage. The DLP781NE, DLP781TE, DLP801RE and
DLP801XE are used in higher brightness applications such as ProAV and large venue projectors.
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller through the
DLPA300. Refer to Power Supply Recommendations section in the DLP780NE, DLP780TE, DLP800RE,
DLP781NE, DLP781TE, DLP801RE and DLP801XE datasheets for power-up and power-down specifications. To
ensure reliable operation, the DLP780NE, DLP800RE, DLP781NE and DLP801RE DMDs must always be used
with DLPC4430 display controller, a DLPA100 power management and motor driver and a DLPA300 micromirror
driver. The DLP780TE, DLP781Te and DLP801XE DMDs must always be use with the DLPC4420 display
controller, the DLPA100 power management and motor driver and a DLPA300 micromirror driver. For LED and
RGB direct laser illumination, the DLPA100 power management and motor driver can be replaced with discrete
power supplies that are sequenced to meet the display controller power supply sequencing.
8.2 Typical Application
The DLPA300 micromirror driver controls the switching of the bias, offset and reset voltage levels on the MBRST
pins to assure correct DMD operation. It is a controlled by a DLP display controller which synchronizes the
display data sent to the DMD with the correct sequencing of the bias, offset and reset voltage levels by the
DLPA300 micromirror driver. The typical application shown in 图 8-1 is a Full-HD display using the DLP780NE
chipset. The application is the same for the DLP800RE, DLP781NE or DLP801RE/DLPC4430 chipsets and the
DLP780TE, DLP781TE or DLP801XE/dual-DLPC4420 chipsets. The DLPA300 micromirror driver creates VBIAS
and VOFFSET with internal voltage regulators. VRESET is created by an external regulator. These voltages are
switched by the DLPA300 micromirror driver on the OUT[0:14] pins which are connected to the MBRST pins on
the DMD.
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2-Port 2xLVDS (68)
DMD Control (4)
RESET
3.3-V to 1.8-V
level shifters
SCPEN_DMD
SCP (3)
SCPEN-DMD
SCP (3)
2.2k
3.3V
SCPEN
RESET
DLPC4430
Display Controller
MODE (2)
SELECT (2)
A[0:3] (4)
STROBE
2.2k
2.2k
DEV_ID (2)
MBRST (15)
3.3V
3.3V
GND
OE
IRQ
VOFFSET_RAIL
0.1 F (3x)
4.7
F
11V
DLPA300
Micromirror Driver
GND
GND
GND
VOFFSET
VBIAS_RAIL
VBIAS
DLP780NE
DMD
12V
VBIAS_SWL
VBIAS_LHI
GND
22 ꢀH
P12V
12V
5V
1
F (2x)
0.1 F
10
F
0.1 F (2x)
1
F
0.1 F
BSS84-7-F
2N7002
GND
GND
GND
GND
GND
GND
GND
V5REG
1
F
0.1 F
VRESET_RAIL
PAD
2.2 ꢀF
0.01 ꢀF
10 F (6x)
4.7
F
GND
GND
VCC
EN
SS/TRK
FB
3.3V
4.7 ꢀF
180 pF
GND
AGND
PGND
PAD
BIAS
EN
VIN
F
VOUT
VDD/VDDI
LM43601
10
F
47ꢀH
10
SW
P12V
12V
LP38513S-1.8
CBOOT
GND
0.47
F
ERROR
GND
GND_TAB
GND
GND
3.3V
GND
33
VOFFSET
2N7002
EN
VIN
VOUT
FB
VCC2
12V
SN74AUP1G07DCKR
GND
10
F
10
F
TPS73801
GND
GND_TAB
GND
GND
GND
GND
GND
GND
3.3V
SN74AUP1G04
12V
VCC
MR
RESET
GND
DMN2005K-7
GND
TPS3847085
GND
GND
GND
图8-1. DLPA300 Typical Application
8.2.1 Design Requirements
For the correct operation of a display system based on the 9-μm pixel family of DMDs, the DLPA300
micromirror driver must be controlled by the DLPC4420 or DLPC4430 display controller. The embedded software
in the DLPC4430 or DLPC4420 display controller coordinates the video data to the DMD and the bias, offset and
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reset waveforms created by the DLPA300 micromirror driver that are input to the MBRST pins on the DMD. This
results in the highest possible image quality and system efficiency.
The key design requirements are power supply sequencing for power up and power down. The 9-μm family of
DMDs require that the VCC2 supply be turned on after the 1.8-V supply is full on and stable. Similarly, on power
down, the DMDs require that the VCC2 supply be full off before the 1.8-V supply is begins its power off ramp.
The DLPA300 micromirror driver imparts one power supply sequencing constraint. Because VRESET is generated
by an external supply, the DLPC4430 display controller cannot control this supply directly by software. Therefore,
it is necessary to use the VBIAS supply to control the power up and power down of the external VRESET power
supply.
These power supply sequencing requirements necessitate external circuitry to control the VRESET and VCC2
power supply sequencing, as seen in 图8-1.
8.2.2 Detailed Design Procedure
The DLPC4430 or DLPC4420 display controller configures the VBIAS and VOFFSET voltage regulators in the
DLPA300 micromirror driver through the SCP bus. VBIAS is then used to generate the enable signal for the
VRESET external voltage regulator, LM43601 step-down voltage converter. When the VBIAS is enabled, it turns on
the two-transistor buffer amplifier. The 2N7002 and BSS84-7-F FETs isolate VBIAS from the VRESET_RAIL and shift
the voltage reference to VRESET_RAIL
.
The thermal pad on the DLPA300 micromirror controller and the LM43601 step-down voltage converter are
electrically connected to the VRESET_RAIL. Furthermore, the AGND and PGND pins on the LM43601 step-down
voltage converter are also connected to the VRESET_RAIL. Therefore, the logic levels and analog voltage levels for
LM43601 step-down voltage converter are referenced to the –16.5-V VRESET_RAIL
.
The LM43601 data sheet provides details for the component selection for the components in the voltage
regulator circuit connected to the VRESET_RAIL. The output of the regulator is set to the VRESET value of –16.5
V. The selection of the resistors in the resistor divider sets the output voltages, 6.49 kΩand 100 kΩ.
The DLP780NE power sequencing requires that the VCC2 power supply ramps up after the 1.8-V supply is
powered on and stable, and VOFFSET is powered up and stable. The two conditions are met by the wired-or of
the ERROR signal from the LP38513-1.8 ultra-low dropout linear regulator and an enable signal generated from
VOFFSET. The 2N7002 enhancement mode FET acts as an inverter and level shifter from VOFFSET to a 3.3-V logic
level.
In the event of a power supply failure (such as a pull-the-plug event), VCC2 must be driven low before the 1.8-V
supply starts to drop voltage. To achieve this, the TPS3847 12-V voltage monitor triggers a shunt-to-ground
power FET to pull VCC2 to ground.
8.2.2.1 Component Selection Guidelines
表8-1. 5-V Regulator
COMPONENT
VALUE
TYPE OR PART NUMBER
CONNECTION 1
CONNECTION 2
Positive Terminal:
P12V, pin 11
(locate near pin 11)
10 to 33 µF, 20 VDC,
Negative Terminal:
Ground
P12V filter capacitor
Tantalum or ceramic
1Ωmax ESR
0.1 µF, 50 VDC,
0.1Ωmax ESR
P12V, pin 11
(locate near pin 11)
P12V bypass capacitor
V5REG filter capacitor
Ceramic
Tantalum or ceramic
Ceramic
Ground
Positive Terminal:
V5REG, pin 47
(locate near pin 47)
0.1(1) to 1.0 µF, 10 VDC,
Negative Terminal:
Ground
2.5Ωmax ESR
0.1 µF(1), 16 VDC,
0.1Ωmax ESR
V5REG bypass
capacitor
V5REG, pin 47
(locate near pin 47)
Ground
(1) To ensure stability of the linear regulator, use a capacitance with a value not less than 0.1 µF.
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表8-2. Bias Voltage Boost Converter
TYPE OR PART
NUMBER
COMPONENT
LHI filter capacitor
LHI bypass capacitor
VALUE
CONNECTION 1
CONNECTION 2
Positive Terminal:
VBIAS_LHI, pin 10
(locate near pin 10)
10 µF, 20 VDC,
1-Ωmax ESR
Negative Terminal:
Ground
Tantalum or ceramic
0.1 µF, 50 VDC,
0.1-Ωmax ESR
VBIAS_LHI, pin 10
(locate near pin 10)
Ceramic
Ceramic
Ceramic
Ground
Ground
1 µF, 50 VDC,
0.1-Ωmax ESR
VBIAS_RAIL filter
capacitor (2 required)
VBIAS_RAIL, pins 30 and 71
(locate near pins 30 and 71)
0.1 µF, 50 VDC,
0.1Ωmax ESR
VBIAS_RAIL bypass
capacitors (2 required)
VBIAS_RAIL, pins 30 and 71
(locate near pins 30 and 71)
Ground
22 µH, 0.5 A,
160 mΩESR
Coil Craft DT1608C-223
(or equivalent)
Inductor
VBIAS_LHI, pin 10
VBIAS_SWL, pin 8
OnSemi MBR0540T1G or
STMicroelectronics
STPS0540Z, STPS0560Z
(or equivalent)
Anode:
VBIAS_SWL, pin 8
Cathode:
VBIAS, pin 9
Schottky diode
0.5 A, 40 V (minimum)
表8-3. Offset Voltage Regulator
TYPE OR PART
COMPONENT
VALUE
CONNECTION 1
CONNECTION 2
NUMBER
Positive Terminal:
VOFFSET, pin 49
(1st Cap near pin 49)
Positive Terminal:
DMDVCC2 pins
Negative Terminal:
Ground at DLPA300
Negative Terminal:
VSS (Ground) at DMD
1(1) to 4.7(2) µF, 35 VDC,
VOFFSET
filter capacitors
Tantalum or ceramic
1Ωmax ESR
( 2nd Cap at DMD)
VOFFSET
bypass capacitors
(3 required)
0.1 µF, 50 VDC,
0.1Ωmax ESR
VOFFSET, pin 49
(locate 1 near pin 49)
Ground at DLPA300
Ground at DMD
Ceramic
Micro Commercial
Components
3SMBJ5926B-TP
or equivalent
11V
3W
Zener Diode
VOFFSET
Ground
(1) To ensure stability of the linear regulator, the absolute minimum output capacitance must not be less than 1.0 µF.
(2) Recommended value is 3.3 µF each. Different values are acceptable, provided that the sum of the two is 6.8 µF maximum.
表8-4. Pullup Resistors
COMPONENT
TYPE OR PART NUMBER
CONNECTION 1
CONNECTION 2
VALUE (kΩ)
Chipset controller
3.3-V VDD
Resistor
2.2
SCPDO, pin 42
Chipset Controller
3.3-V VDD
Resistor
2.2
2.2
IRQ, pin 43
OE, pin 6
Chipset Controller
3.3-V VDD
Resistor (optional)
8.2.3 Application Curves
The power supply sequencing for VBIAS, VOFFSET and VRESET are shown in 图 8-2 and 图 8-3. On power-up, the
turn on of VBIAS enables the external VRESET voltage regulator. In power-down, when VBIAS powers off, it
disables the VRESET regulator, which slowly decays to ground.
The power sequencing for VCC2 voltage regulator is shown in 图 8-4 and 图 8-5. The power up of VOFFSET
enables the turn on of the VCC2 voltage regulator. As seen in the zoom out of 图8-4, the 1.8-V supply is already
on and stable. Similarly, the power down of VOFFSET disables the VCC2 voltage regulator. The 1.8-V supply
powers down after both VOFFSET and VCC2 are powered down, as seen in the zoom out of 图8-5.
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图8-2. High Voltage Power-Up Sequence
图8-3. High Voltage Power-Down Sequence
图8-4. VCC2 Power-Up Sequence
图8-5. VCC2 Power-Down Sequence
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9 Power Supply Recommendations
9.1 Power Supply Rail Guidelines
表8-1 through 表8-4 provides discrete component selection guidelines.
• Ensure that the P12V filter and bypass capacitors are distributed and connected to pin 11 and pin 48 and pin
50. Place these capacitors as close to their respective pins as possible and if necessary, place on the bottom
layer.
• The V5REG filter and bypass capacitors must be placed near and connected to pin 47.
• It is best to route the VBIAS_RAIL etch runs in the following order: pin 40, pin 31, pin 30, pin 21, pin 80, pin
71, pin 70, and pin 61. Ensure that the etch runs are short and direct as they must carry 35 ns current spikes
of up to 0.64 A (peak). Locate the bypass capacitors near and connected to pin 30 and pin 71 to provide
bypassing on both sides.
• The VBIAS_LHI filter and bypass capacitors must be placed near and connected to pin 10.
• The VBIAS filter and bypass capacitors must be placed near and connected to pin 9.
• VBIAS pin 9 must also be connected (optionally with a 0-ohm resistor) to VBIAS_RAIL at or between pins 21
and 80.
• Route the VRESET_RAIL etch runs in the following order: pin 36, pin 35, pin 26, pin 25, pin 76, pin 75, pin
66, and pin 65. Ensure the etch runs are short and direct as they must carry 35 ns current spikes of up to
0.64 A (peak). Bypass capacitors must be placed near and connected to pins 35 and 66 to provide bypassing
on both sides.
• The VRESET filter and bypass capacitors must be located near and connected to pin 13. VRESET pin 13
must also be connected (optionally with a 0-Ωresistor) to VRESET_RAIL at or between pin 25 and pin 76.
• Route the VOFFSET_RAIL etch runs in the following order: pin 23, pin 28, pin 33, pin 38, pin 63, pin 68, pin
73, and pin 78. Ensure the etch runs are short and direct as they must carry 35 ns current spikes of up to
0.64 A (peak). Place the bypass capacitors near and connected to pin 28 and pin 73 to provide bypassing on
both sides.
• The VOFFSET filter and bypass capacitors must be placed near and connected to pin 49.
• VOFFSET pin 49 must also be connected (optionally with a 0-Ωresistor) to VOFFSET_RAIL at or between
pin 38 and pin 63.
备注
Aluminum electrolytic capacitors may not be suitable for the DLPA300 application. At the switching
frequencies used in the DLPA300 (up to 1.5 MHz), aluminum electrolytic capacitors drop significantly
in capacitance and increase in ESR resulting in voltage spikes on the power supply rails, which could
cause the device to shut down or perform in an unreliable manner.
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10 Layout
10.1 Layout Guidelines
CAUTION
Board layout and routing guidelines must be followed explicitly and all external components used
must be in the range of values and of the quality recommended for proper operation of the
DLPA300.
CAUTION
Thermal pads must be tied to VRESET_RAIL. Do not connect to ground.
Provide suitable Kelvin connections for the switching regulator feedback pins: VBIAS (pin 9) and VRESET (pin 13).
Make the PCB traces that connect the switching devices: VBIAS_SWL (pin 8) and VRESET_SWL (pin 12) as
short and wide as possible to minimize leakage inductances. Make the PCB traces that connect the switching
converter components (inductors, flywheel diodes and filtering capacitors) as short and wide as possible. Ensure
that the electrical loops that these components form are as small and compact as possible, with the ground
referenced components forming a star connection.
Due to the fast switching transitions appearing on the sixteen reset OUTx pins, it is recommended to keep these
traces as short as possible. Also, to minimize potential cross-talk between outputs, it is advisable to maintain as
much clearance between each of the output traces.
10.1.1 Grounding Guidelines
Ensure that the PWB has an internal ground plane that extends under the DLPA300. All nine ground pins (1, 7,
14, 20, 41, 46, 53, 55, and 60) must be connected to the ground plane using the shortest possible runs and vias.
All filter and bypass capacitors must be placed near the pin being filtered or bypassed for the shortest possible
runs to the part and to the ground plane.
10.2 Thermal Considerations
Thermally bond or solder the DLPA300 package to an external thermal pad on the PWB surface. The
recommended dimensions of the thermal pad are 10 mm × 10 mm centered under the device. The metal bottom
of the package is tied internally to the substrate at the VRESET_RAIL voltage level. Therefore, the thermal pad
on the board must be isolated from any other extraneous circuit or ground and no circuit vias are allowed inside
the pad area. Thermal pads are required on both sides of the PWB. Connect the thermal pads together through
an array of 5 × 5 thermal vias, 0.5 mm in diameter.
Thermal pads and the thermal vias are connected to VRESET_RAIL and must be isolated from ground,
or any other circuit.
Locate an internal P12V plane directly underneath the top layer and have an isolated area under the DLPA300.
This isolated area must be a minimum of 20 cm2 and connect to the thermal pad of the DLPA300 through the
thermal vias. The potential of the isolated area is also at VRESET_RAIL. The internal ground plane must extend
under the DLPA300 to help carry the heat away. Please refer to the PowerPAD Thermally Enhanced Package
application report (SLMA002) for details on thermally efficient package design considerations.
Be careful to place the DLPA300 device away from local PWB hotspots. Heat generated from adjacent
components may impact the DLPA300 thermal characteristics.
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DLPA300
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
The device marking consists of the fields shown in 图11-1.
PART MARKING CODES
LLLLLLLL = Lot trace code or date code
e4 = Pb-Free NiPdAu termial finish
= Pin 1 designator
图11-1. Device Marking (Device Top View)
11.3 Documentation Support
11.3.1 Related Documentation
The following documents contain additional information related to the chipsets supported by the DLPA300
micromirror driver and used in the typical application.
• DLP780NE data sheet
• DLP800RE data sheet
• DLP780TE data sheet
• DLP781NE data sheet
• DLP801RE data sheet
• DLP781TE data sheet
• DLP801XE data sheet
• DLPC4430 data sheet
• DLPC4420 data sheet
• DLPA100 data sheet
• LM43601 data sheet
• LP38513S data sheet
• TPS73801 data sheet
• TPS3847085 data sheet
11.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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English Data Sheet: DLPS227
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPA300PFP
ACTIVE
HTQFP
PFP
80
119
TBD
Call TI
Call TI
0 to 70
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DLPA300PFP
DLP® driver for DLP780NE (0.78 1080p), DLP780TE (0.78 4K UHD), DLP800RE (0.80 WUXGA) DMD | PFP | 80 | 0 to 70
TI
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