DLPA4000_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

DLPA4000

ZHCSIA7 –MAY 2018

DLPA4000 PMIC 和高电流 LED 驱动器

1 特性

3 说明

1

•

高效、高电流 RGB LED 驱动器（具有高侧泵功

能）

DLPA4000 器件是一款高度集成的电源管理驱动器。

它针对 DLP^®LED 投影仪系统进行了优化。DLPA4000

可支持每个 LED 的电流高达 32A 的投影仪，且具有高

侧泵功能。一个集成的高效降压控制器会为该器件供

电。驱动器控制开关可实现红、绿、蓝 LED 排序。该

驱动器包含五个降压转换器，其中两个专用于

•

外部降压 FET 驱动器，驱动电流高达 32A

外部 RGB 开关驱动器

每个通道具有 10 位可编程电流

提供用于选择颜色顺序 RGB LED 的输入

可生成 DMD 高电压电源

DLPC4422 控制器低压电源。另一个专用的稳压电源

为 DLPA200 DMD 微镜驱动器和该 DMD 的三个时序

关键型直流电源（VBIAS、VRST 和 VOFS）供电。

两个高效降压转换器，用于生成 DLPC4422 控制器

和 DMD 电源

•

高效 8 位可编程降压转换器 (PWR6)，可用于风扇

驱动器应用或一般用途

DLPA4000 器件包含多个辅助块。这些辅助块可提高

LED 投影仪设计中的灵活性。8 位可编程降压转换器

可以驱动 RGB 投影仪风扇或辅助电源线。两个 LDO

可以生成至多 200mA 的低电流电源。这些 LDO 的额

定工作电压为 2.5V 和 3.3V。

•

两个 LDO，用于提供辅助电压

模拟多路复用器，用于测量内部和外部节点

保护：热关断、热模、电池电量不足和欠压锁定

(UVLO)

串行协议接口 (SPI) 可寻定 DLPA4000 器件的所有组

成块的地址。这些可寻址特性包括：生成系统复位、

电源排序、用于顺序选择活动 LED 的输入信号、IC 自

我保护以及用于将模拟信息传送到外部 ADC 的模拟多

路复用器。

2 应用

智能 LED 投影仪

无屏电视

数字标牌

舞台照明

器件信息⁽¹⁾

器件号

封装

封装尺寸（标称值）

DLPA4000

HTQFP (100)

14.00mm × 14.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

系统方框图

12- V Regulator

16 V to 20 V DC

HDMI

Power Supplies

and Monitoring

Illumination

Control

Shunt Diodes

PROJ_ON

VGA

Front

End

SPI

PWR_GOOD

PWR_ON

Digital Control Block

External

Power

FETs

High-Side Pump LED

Keypad

I2C

DLPA4000

DMD and

DATA

1.1 V

1.8 V

DMD

Reset

Controller Bucks

Flash

DLPC4422

Voltage

Generator

3.3 V

2.5 V

LDOs

DMD Reset

Voltages and Control

GP Buck

Converter

Measurement

System

Sensors

3.3 V

DLP650NE

or

DLPA200

Control

DLP650LE

DMD Data and Control

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS132

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

8

9

Application and Implementation ........................ 51

8.1 Application Information............................................ 51

8.2 Typical Application .................................................. 51

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 ESD Ratings.............................................................. 8

6.3 Recommended Operating Conditions....................... 8

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics........................................... 9

6.6 SPI Timing Parameters........................................... 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Description................................... 15

7.3 Feature Description................................................. 16

7.4 Device Functional Modes........................................ 36

7.5 Programming........................................................... 38

7.6 Register Maps......................................................... 41

8.3 System Example With DLPA4000 Internal Block

Diagram.................................................................... 54

Power Supply Recommendations...................... 55

9.1 Power-Up and Power-Down Timing........................ 55

10 Layout................................................................... 59

10.1 Layout Guidelines ................................................. 59

10.2 Layout Example .................................................... 68

10.3 Thermal Considerations ....................................... 69

11 器件和文档支持 ..................................................... 71

11.1 器件支持................................................................ 71

11.2 接收文档更新通知 ................................................. 71

11.3 社区资源................................................................ 71

11.4 商标....................................................................... 71

11.5 静电放电警告......................................................... 71

11.6 术语表 ................................................................... 71

12 机械、封装和可订购信息....................................... 72

12.1 Package Option Addendum .................................. 73

7

4 修订历史记录

日期

修订版本

说明

2018 年 5 月

*

最初发布版本。

2

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

5 Pin Configuration and Functions

PFD Package

100-Pin HTQFP

Top View

76

77

78

79

80

81

82

PWR2_BOOST

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_IN_LABB

ACMPR_OUT

ACMPR_REF

PWR_VIN

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PWR7_BOOST

SPI_MOSI

SPI_SS_Z

SPI_MISO

SPI_CLK

SPI_VIN

CW_SPEED_PWM_OUT

CLK_OUT

83

84

85

PWR_5P5V

VINA

THERMAL_PAD

ILLUM_B_COMP2

ILLUM_B_COMP1

ILLUM_A_COMP2

ILLUM_A_COMP1

ILLUM_B_PGND

ILLUM_B_SW

ILLUM_B_FB

AGND

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

PWR3_OUT

PWR3_VIN

DLPA4000

PWR4_OUT

PWR4_VIN

SUP_2P5V

SUP_5P0V

ILLUM_B_VIN

ILLUM_B_BOOST

ILLUM_A_PGND

ILLUM_A_SW

ILLUM_A_VIN

ILLUM_A_FB

PWR1_PGND

PWR1_FB

PWR1_SWITCH

PWR1_VIN

PWR1_BOOST

DMD_VOFFSET

DMD_VBIAS

DMD_VRESET

ILLUM_A_BOOST

ILLUM_LSIDE_DRIVE

ILLUM_HSIDE_DRIVE

3

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Pin Functions

I/O

—

DESCRIPTION

N/C

1

No connect

Connection for the DMD SMPS-inductor (low-side switch).

Filter pin for LDO DMD. Power supply for internal DMD reset regulator, typical 5.5 V.

DRST_LS_IND

DRST_5P5V

DRST_PGND

DRST_VIN

2

I/O

O

3

4

GND Power ground for DMD SMPS. Connect to ground plane.

5

P

I/O

O

P

I

Power supply input for LDO DMD. Connect to system power.

Connection for the DMD SMPS-inductor (high-side switch).

DRST_HS_IND

ILLUM_5P5 V

ILLUM_VIN

6

7

Filter pin for LDO ILLUM. Power supply for internal ILLUM block, typical 5.5 V.

Supply input of LDO ILLUM. Connect to system power.

8

CH1_SWITCH

RLIM_1

9

Low-side MOSFET switch for LED Cathode. Connect to RGB LED assembly.

Connection to LED current sense resistor for CH1 and CH2.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

I

O

I

RLIM_BOT_K_2

RLIM_K_2

Kelvin sense connection to ground side of LED current sense resistor.

Kelvin sense connection to top side of current sense resistor.

Kelvin sense connection to ground side of LED current sense resistor.

Kelvin sense connection to top side of current sense resistor.

Connection to LED current sense resistor for CH1 and CH2.

I

RLIM_BOT_K_1

RLIM_K_1

I

RLIM_1

O

I

CH2_SWITCH

CH1_GATE_CTRL

CH2_GATE_CTRL

CH3_GATE_CTRL

RLIM_2

Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.

Gate control of CH1 external MOSFET switch for LED cathode.

Gate control of CH2 external MOSFET switch for LED cathode.

Gate control of CH3 external MOSFET switch for LED cathode.

Connection to LED current sense resistor for CH3.

I

O

I

RLIM_2

Connection to LED current sense resistor for CH3.

CH3_SWITCH

ILLUM_HSIDE_DRIVE

ILLUM_LSIDE_DRIVE

Low-side MOSFET switch for LED Cathode. Connect to RGB LED assembly.

Gate control for external high-side MOSFET for ILLUM Buck converter.

Gate control for external low-side MOSFET for ILLUM Buck converter.

I

O

Supply voltage for high-side N-channel MOSFET gate driver. A 100 nF capacitor (typical) must

be connected between this pin and ILLUM_A_SW.

ILLUM_A_BOOST

28

I

ILLUM_A_FB

ILLUM_A_VIN

29

30

I

Input to the buck converter loop controlling I_LED

.

P

Power input to the ILLUM Driver A.

Switch node connection between high-side NFET and low-side NFET. Serves as common

connection for the flying high side MOSFET driver.

ILLUM_A_SW

31

I/O

ILLUM_A_PGND

ILLUM_B_BOOST

ILLUM_B_VIN

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

GND Ground connection to the ILLUM Driver A.

I

P

Supply voltage for high-side N-channel MOSFET gate driver.

Power input to the ILLUM driver B.

ILLUM_B_FB

I

Input to the buck converter loop controlling I_LED

.

ILLUM_B_SW

I/O

Switch node connection between high-side NFET and low-side NFET.

ILLUM_B_PGND

ILLUM_A_COMP1

ILLUM_A_COMP2

ILLUM_B_COMP1

ILLUM_B_COMP2

THERMAL_PAD

CLK_OUT

GND Ground connection to the ILLUM driver B.

I/O

Connection node for feedback loop components

GND Thermal pad. Connect to clean system ground.

O

I

Color wheel clock output

Color wheel PWM output

Supply for SPI interface

SPI clock input

CW_SPEED_PWM_OUT

SPI_VIN

SPI_CLK

I

4

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Pin Functions (continued)

I/O

DESCRIPTION

SPI_MISO

SPI_SS_Z

SPI_MOSI

47

48

49

O

I

SPI data output

SPI chip select (active low)

SPI data input

I

Charge-pump-supply input for the high-side MOSFET gate drive circuit. Connect 100 nF

capacitor between PWR7_BOOST and PWR7_SWITCH pins.

PWR7_BOOST

50

I

PWR7_FB

51

52

53

54

55

56

57

58

59

60

61

62

63

64

I

Converter feedback input. Connect to converter output voltage.

Power supply input for converter.

PWR7_VIN

PWR7_SWITCH

PWR7_PGND

ACMPR_LABB_SAMPLE

PROJ_ON

P

I/O

Switch node connection between high-side NFET and low-side NFET.

GND Ground pin. Power ground return for switching circuit.

I

Control signal to sample voltage at ACMPR_IN_LABB.

I

Input signal to enable/disable the IC and DLP projector.

RESET_Z

O

Reset output to the DLP system (active low). Pin is held low to reset DLP system.

Interrupt output signal (open drain, active low). Connect to pull-up resistor.

INT_Z

DGND

GND Digital ground. Connect to ground plane.

CH_SEL_0

I

Control signal to enable either of CH1,2,3.

CH_SEL_1

PWR6_PGND

PWR6_SWITCH

PWR6_VIN

GND Ground pin. Power ground return for switching circuit.

I/O

P

Switch node connection between high-side NFET and low-side NFET.

Power supply input for converter.

Charge-pump-supply input for the high-side MOSFET gate drive circuit. Connect 100 nF

capacitor between PWR6_BOOST and PWR6_SWITCH pins.

PWR6_BOOST

65

I

PWR6_FB

66

67

68

I

Converter feedback input. Connect to output voltage.

Power supply input for converter.

PWR5_VIN

P

PWR5_SWITCH

I/O

Switch node connection between high-side NFET and low-side NFET.

Charge-pump-supply input for the high-side MOSFET gate drive circuit. Connect 100nF

capacitor between PWR5_BOOST and PWR5_SWITCH pins.

PWR5_BOOST

69

I

PWR5_PGND

PWR5_FB

70

71

72

73

74

75

GND Ground pin. Power ground return for switching circuit.

I

Converter feedback input. Connect to output voltage.

PWR2_FB

PWR2_PGND

PWR2_SWITCH

PWR2_VIN

GND Ground pin. Power ground return for switching circuit.

I/O

P

Switch node connection between high-side NFET and low-side NFET.

Power supply input for converter.

Charge-pump-supply input for the high-side MOSFET gate drive circuit. Connect 100 nF

capacitor between PWR2_BOOST and PWR2_SWITCH pins.

PWR2_BOOST

76

I

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_IN_LABB

ACMPR_OUT

ACMPR_REF

PWR_VIN

77

78

79

80

81

82

83

84

85

86

87

88

89

90

I

Input for analog sensor signal.

I

Input for analog sensor signal.

I

Input for ambient light sensor, sampled input

Analog comparator out

O

I

Reference voltage input for analog comparator

Power supply input for LDO_Bucks. Connect to system power.

Filter pin for LDO_BUCKS. Internal analog supply for buck converters, typical 5.5 V.

Input voltage supply pin for Reference system.

P

O

P

PWR_5P5V

VINA

AGND

GND Analog ground pin.

PWR3_OUT

PWR3_VIN

PWR4_OUT

PWR4_VIN

O

P

O

P

Filter pin for LDO_2 DMD/DLPC/AUX, typical 2.5 V.

Power supply input for LDO_2. Connect to system power.

Filter pin for LDO_1 DMD/DLPC/AUX, typical 3.3 V.

Power supply input for LDO_1. Connect to system power.

5

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Pin Functions (continued)

SUP_2P5V

I/O

O

DESCRIPTION

91

92

93

94

95

96

Filter pin for LDO_V2V5. Internal supply voltage, typical 2.5 V.

Filter pin for LDO_V5V. Internal supply voltage, typical 5 V.

SUP_5P0V

O

PWR1_PGND

PWR1_FB

GND Ground pin. Power ground return for switching circuit.

I

Converter feedback input. Connect to output voltage.

Switch node connection between high-side NFET and low-side NFET.

Power supply input for converter.

PWR1_SWITCH

PWR1_VIN

I/O

P

Charge-pump-supply input for the high-side MOSFET gate drive circuit. Connect 100nF

capacitor between PWR1_BOOST and PWR1_SWITCH pins.

PWR1_BOOST

97

I

DMD_VOFFSET

DMD_VBIAS

98

99

O

VOFS output rail. Connect to ceramic capacitor.

VBIAS output rail. Connect to ceramic capacitor.

VRESET output rail. Connect to ceramic capacitor.

DMD_VRESET

100

6

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature (unless otherwise noted).⁽¹⁾

MIN

–0.3

–2

MAX

28

30

7

UNIT

ILLUM_A,B_BOOST

ILLUM_A,B_BOOST (10 ns transient)

ILLUM_A,B_BOOST vs ILLUM_A,B_SWITCH

ILLUM_LSIDE_DRIVE

7

ILLUM_HSIDE_DRIVE

28

7

ILLUM_A_BOOST vs ILLUM_HSIDE_DRIVE

ILLUM_A,B_SW

-0.3

–2

22

27

ILLUM_A,B_SW (10 ns transient)

–3

PWR_VIN, PWR1_VIN, PWR2_VIN, PWR3_VIN, PWR4_VIN, PWR5_VIN,

PWR6_VIN, PWR7_VIN, VINA, ILLUM_VIN, ILLUM_A,B_VIN, DRST_VIN

–0.3

–2

22

28

30

22

PWR1_BOOST, PWR2_BOOST, PWR5_BOOST, PWR6_BOOST,

PWR7_BOOST

PWR1_BOOST, PWR2_BOOST, PWR5_BOOST, PWR6_BOOST,

PWR7_BOOST (10 ns transient)

PWR1_SWITCH, PWR2_SWITCH, PWR5_SWITCH, PWR6_SWITCH,

PWR7_SWITCH

PWR1_SWITCH, PWR2_SWITCH, PWR5_SWITCH, PWR6_SWITCH,

PWR7_SWITCH (10 ns transient)

–3

27

PWR1_FB, PWR2_FB, PWR5_FB, PWR6_FB, PWR7_FB

–0.3

6.5

PWR1_BOOST, PWR2_BOOST, PWR5_BOOST, PWR6_BOOST,

PWR7_BOOST vs PWR1_SWITCH, PWR2_SWITCH, PWR5_SWITCH,

PWR6_SWITCH, PWR7_SWITCH

–0.3

6.5

Voltage

V

CH1_SWITCH, CH2_SWITCH, CH3_SWITCH, DRST_LS_IND, ILLUM_A,B_FB

ILLUM_A,B_COMP1, ILLUM_A,B_COMP2, INT_Z, PROJ_ON

DRST_HS_IND

–0.3

–18

20

7

ACMPR_IN_1, ACMPR_IN_2, ACMPR_IN_3, ACMPR_REF, ACMPR_IN_LABB,

ACMPR_LABB_SAMPLE, ACMPR_OUT

–0.3

3.6

SPI_VIN, SPI_CLK, SPI_MOSI, SPI_SS_Z, SPI_MISO, CH_SEL_0, CH_SEL_1,

RESET_Z

–0.3

3.6

RLIM_K_1, RLIM_K_2, RLIM_1, RLIM_2

DGND, AGND, DRST_PGND, ILLUM_A,B_PGND, PWR1_PGND,

PWR2_PGND, PWR5_PGND, PWR6_PGND, PWR7_PGND, RLIM_BOT_K_1,

RLIM_BOT_2

–0.3

0.3

DRST_5P5V, ILLUM_5P5V, PWR_5P5, PWR3_OUT, PWR4_OUT, SUP_5P0V

–0.3

–18

7

CH1 _GATE_CTRL,CH2_GATE_CTRL, CH3_GATE_CTRL

CLK_OUT

3.6

7

CW_SPEED_PWM

SUP_2P5V

3.6

12

20

7

DMD_VOFFSET

DMD_VBIAS

DMD_VRESET

RESET_Z, ACMPR_OUT

SPI_DOUT

1

Source current

mA

5.5

1

RESET_Z, ACMPR_OUT

SPI_DOUT, INT_Z

Storage temperature

Sink current

T_stg

mA

ºC

5.5

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN

MAX

UNIT

PWR_VIN, PWR1_VIN, PWR2_VIN, PWR3_VIN, PWR4_VIN,

PWR5_VIN, PWR6_VIN, PWR7_VIN, VINA, ILLUM_VIN,

ILLUM_A_VIN,ILLUM_B_VIN, DRST_VIN

16

20

CH1_SWITCH, CH2_SWITCH, CH3_SWITCH, ILLUM_A,B_FB,

INT_Z, PROJ_ON

–0.1

8.6

6

PWR1_FB, PWR2_FB, PWR5_FB, PWR6_FB, PWR7_FB

5

ACMPR_REF, CH_SEL_0, CH_SEL_01, SPI_CLK, SPI_MOSI,

SPI_SS_Z

Input voltage range

V

–0.1

3.6

RLIM_BOT_K_1, RLIM_BOT_K_2

ACMPR_IN_1, ACMPR_IN_2, ACMPR_IN_3, LABB_IN_LABB

SPI_VIN

–0.1

1.7

–0.1

0

0.1

1.5

3.6

RLIM_K_1, RLIM_K_2

0.25

5.7

ILLUM_A,B_COMP1, ILLUM_A,B_COMP2

Ambient temperature range

70

°C

Operating junction temperature

0

120

6.4 Thermal Information

DLPA4000

THERMAL METRIC⁽¹⁾

PFD (HTQFP)

UNIT

100 PINS

7.0

(2)

(3)

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

0.7

Junction-to-board thermal resistance

N/A

(4)

ψ_JT

Junction-to-top characterization parameter

0.6

(5)

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.4

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, but

because the device is intended to be cooled with a heatsink from the top case of the package, the simulation includes a fan and

heatsink attached to the DLPA4000 device . The heatsink is a 22 mm × 22 mm × 12 mm aluminum pin fin heatsink with a 12 × 12 × 3

mm stud. Base thickness is 2 mm and pin diameter is 1.5 mm with an array of 6 × 6 pins. The heatsink is attached to the DLPA4000

device with 100 um thick thermal grease with 3 W/m-K thermal conductivity. The fan is 20 × 20 × 8 mm with 1.6 cfm open volume flow

rate and 0.22 in. water pressure at stagnation.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the

fan and heatsink described in note 2.

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7), but modified to include the

fan and heatsink described in note 2.

8

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

6.5 Electrical Characteristics

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

SUPPLIES

MIN

TYP

MAX

UNIT

INPUT VOLTAGE

V_IN

Input voltage range

Low battery warning threshold

Hysteresis

VINA – pin

16⁽¹⁾

3.9

19.5

90

20

V

VINA falling (via 5 bit trim function, 0.5

V steps)

18.4

V_{LOW_BAT}

VINA rising

mV

V

VINA falling (via 5 bit trim function, 0.5

V steps)

UVLO threshold

Hysteresis

3.9

6

18.4

V_UVLO

VINA rising

90

mV

V

DMD_VBIAS, DMD_VOFFSET,

DMD_VRESET loaded with 10 mA

V_STARTUP

Startup voltage

INPUT CURRENT

I_IDLEIdle current

IDLE mode, all VIN pins combined

15

µA

STANDBY mode, analog, internal

supplies and LDOs enabled, DMD,

ILLUMINATION and BUCK

I_STD

Standby current

3.7

mA

CONVERTERS disabled.

Quiescent current DMD block (in

addtion to I_STD), VINA + DRST_VIN

I_{Q_DMD}

Quiescent current (DMD)

0.49

21

mA

Quiescent current ILLUM block (in

addtion to I_STD), V_openloop= 3 V

(0x18, ILLUM_OLV_SEL), VINA +

ILLUM_VIN + ILLUM_A_VIN +

ILLUM_B_VIN

I_{Q_ILLUM}

Quiescent current (ILLUM)

Quiescent current per BUCK converter

(in addtion to I_STD), Normal mode, VINA

+ PWR_VIN + PWR1,2,5,6,7_VIN,

PWR1,2,5,6,7_VOUT = 1 V

4.3

15

Quiescent current per BUCK converter

(in addtion to I_STD), Normal mode, VINA

+ PWR_VIN + PWR1,2,5,6,7_VIN,

PWR1,2,5,6,7_VOUT = 5 V

Quiescent current

(per BUCK)

I_{Q_BUCK}

mA

Quiescent current per BUCK converter

(in addtion to I_STD), Cycle-skipping

mode, VINA + PWR_VIN +

0.41

0.46

38

PWR1,2,5,6,7_VIN = 1 V

Quiescent current per BUCK converter

(in addtion to I_STD), Cycle-skipping

mode, VINA + PWR_VIN +

PWR1,2,5,6,7_VIN = 5 V

Typical Application: ACTIVE mode, all

VIN pins combined, DMD,

ILLUMINATION and PWR1,2 enabled,

PWR3,4,5,6,7 disabled.

I_{Q_TOTAL}

Quiescent current (Total)

mA

INTERNAL SUPPLIES

V_{SUP_5P0V}Internal supply, analog

V_{SUP_2P5V}Internal supply, logic

5

V

2.5

DMD - LDO DMD

(1) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA4000 device to fully

operate. While 15.5 V is the min VIN voltage supported, TI recommends that the UVLO is never set below 16 V. 16 V gives margin

above the minimum to protect against the case where someone suddenly removes VIN’s power supply which causes the VIN voltage to

drop rapidly. Failure to keep VIN above 16.0 V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut

down can result in permanent damage to the DMD. Because 16 V is 500 mV above 15.5 V, when UVLO trips there is time for the

DLPA4000 device and DLPC343x to park the DMD mirrors and do a fast shut down of supplies VOFS, VRST, and VBIAS. Regardless

of the UVLO setting, , include enough bulk capacitance on VIN inside the projector to maintain VIN above 15.5 V for at least 100 µs

after VIN power supply is suddenly removed causing a UVLO fault.

9

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

12

MAX

UNIT

V

V_{DRST_VIN}

6

20

V_{DRST_5P5V}

5.5

V

Rising

Faling

80%

60%

PGOOD

OVP

Power good DRST_5P5V

Overvoltage protection

DRST_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽²⁾

At 25 mA, VDRST_VIN= 5.5 V

56

mV

mA

300

340

400

3%

DMD - BUCK CONVERTERS

OUTPUT VOLTAGE

V_{PWR_1_VOUT}Output Voltage

V_{PWR_2_VOUT}

1.1

1.8

V

Output Voltage

DC output voltage accuracy

I_OUT= 0 mA

–3%

MOSFET

25°C, V_{PWR_1,2_Boost}– V_{PWR1,2_SWITCH}

= 5.5 V

R_ON,H

High side switch resistance

Low side switch resistance⁽²⁾

150

85

mΩ

R_ON,L

25°C

LOAD CURRENT

Allowed Load Current.

Current limit⁽²⁾

3

A

I_OCL

L_OUT= 3.3 μH

3.2

3.6

4.2

ON-TIME TIMER CONTROL

t_ON

On time

Minimum off time⁽²⁾

V_IN= 12 V, V_O= 5 V

T_A= 25°C, V_FB= 0 V

120

270

ns

t_OFF(MIN)

START-UP

Soft start

1

2.5

4

ms

PGOOD

Ratio_OV

Ratio_PG

Overvoltage protection

120%

72%

Relative power good level

Low to High

ILLUMINATION - LDO ILLUM

V_{ILLUM_VIN}

6

12

5.5

20

V

V_{ILLUM_5P5V}

Rising

Falling

80%

60%

PGOOD

OVP

Power good ILLUM_5P5V

Overvoltage protection

ILLUM_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽²⁾

At 25 mA, V_{ILLUM_VIN}= 5.5 V

53

mV

mA

300

6

340

400

20

ILLUMINATION - DRIVER A,B

V_{ILLUM_A,B_IN}

PWM

Input supply voltage range

Oscillator frequency

12

V

ƒ_SW

3 V < V_IN< 20 V

600

28

kHz

ns

HDRV off to LDRV on, TRDLY = 0

HDRV off to LDRV on, TRDLY = 1

LDRV off to HDRV on, TRDLY = 0

t_DEAD

Output driver dead time

40

35

OUTPUT DRIVERS

(2) Not production tested.

10

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Electrical Characteristics (continued)

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{ILLUM_A,B_BOOT}– V_{ILLUM_A,B_SW}= 5 V,

I_HDRV= –100 mA

R_HDHI

High-side driver pull-up resistance

4.9

Ω

High-side driver pull-down

resistance

V_{ILLUM_A,B_BOOT}– V_{ILLUM_A,B_SW}= 5 V,

I_HDRV= 100 mA

R_HDLO

R_LDHI

R_LDLO

3

3.1

2.4

Ω

Low-side driver pull-up resistance I_LDRV= –100 mA

Low-side driver pull-down

I_LDRV= 100 mA

resistance

t_HRISE

t_HFALL

t_LRISE

t_LFALL

High-side driver rise time⁽²⁾

High-side driver fall time⁽²⁾

Low-side driver rise time⁽²⁾

Low-side driver fall time⁽²⁾

C_LOAD= 5 nF

23

19

23

17

ns

OVERCURRENT PROTECTION

High-Side Drive Over Current

threshold

HSD OC

External switches, V_DSthreshold⁽²⁾

.

185

mV

V

BOOT DIODE

V_DFWD

Bootstrap diode forward voltage

Undervoltage protection

I_BOOT= 5 mA

0.75

89%

30

PGOOD

RatioUV

INTERNAL RGB STROBE CONTROLLER SWITCHES

R_ON

I_LEAK

I_MAX

ON-resistance

CH1,2,3_SWITCH

V_DS= 5.0 V

45

mΩ

µA

A

OFF-state leakage current

Maximum current

0.1

6

DRIVERS EXTERNAL RGB STROBE CONTROLLER SWITCHES

ILLUM_SW_ILIM_EN[2:0] = 7, register

0x02, I_SINK= 400 µA

4.35

5.25

55

CHx_GATE_C

NTR_HIGH

Gate control high level

Gate control low level

V

ILLUM_SW_ILIM_EN[2:0] = 0, register

0x02, I_SINK= 400 µA

ILLUM_SW_ILIM_EN[2:0] = 7, register

0x02, I_SINK= 400 µA

CHx_GATE_C

NTR_LOW

mV

ILLUM_SW_ILIM_EN[2:0] = 0, register

0x02, I_SINK= 400 µA

55

LED CURRENT CONTROL

V_{LED_ANODE}

LED Anode voltage⁽²⁾

Ratio with respect to V_{ILLUM_A,B_VIN}

(Duty cycle limitation).

0.85x

8.6

32

V

A

V_{ILLUM_A,B_VIN}≥ 8 V. See register

SWx_IDAC[9:0] for settings.

I_LED

LED currents

1

DC current offset,

CH1,2,3_SWITCH

R_LIM= 4 mΩ

–150

0

150

mA

20% higher than I_LED. Min-setting,

R_LIM= 4 mΩ.

11%

Transient LED current limit range

(programmable)

20% higher than I_LED. Max-setting,

R_LIM= 4 mΩ. Percentage of max

current.

133%

I_LEDfrom 5% to 95%, I_LED= 600 mA,

t_RISE

Current rise time

50

20

µs

transient current limit disabled⁽²⁾

.

BUCK CONVERTERS - LDO_BUCKS

Input voltage range

PWR1,2,5,6,7_VIN

V_{PWR_VIN}

16

19.5

5.5

V

V_{PWR_5P5V}

PWR_5P5V

11

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

80%

60%

MAX

UNIT

Rising

Falling

PGOOD

OVP

Power good PWR_5P5V

Overvoltage Protection

PWR_5P5V

7.2

V

Regulator dropout

Regulator current limit⁽²⁾

At 25 mA, V_{PWR_VIN}= 5.5 V

41

mV

mA

300

340

400

(3)

BUCK CONVERTERS - GENERAL PURPOSE BUCK CONVERTERS

OUTPUT VOLTAGE

V_{PWR_5,6,7_VOU}Output Voltage (General Purpose

8-bit programmable

I_OUT= 0 mA

1

5

V

Buck1,2,3)

T

DC output voltage accuracy

–3.5%

3.5%

MOSFET

25°C, V_{PWR5,6,7_Boost}– V_{PWR5,6,7_SWITCH}

= 5.5 V

R_ON,H

High-side switch resistance

Low-side switch resistance⁽²⁾

150

85

mΩ

R_ON,L

25°C

LOAD

CURRENT

Allowed load current PWR6.

2

A

Allowed load current PWR5,

PWR7.

Current limit⁽²⁾

Buck converters should not be used.

I_OCL

L_OUT= 3.3 μH

3.2

3.6

4.2

ON-TIME

TIMER

CONTROL

t_ON

On time

Minimum off time⁽²⁾

V_IN= 12 V, V_O= 5 V

T_A= 25°C, V_FB= 0 V

120

270

ns

t_OFF(min)

START-UP

t_SS

310

4

Soft-start period

1

2.5

ms

PGOOD

Ratio_OV

Ratio_PG

Overvoltage protection

120%

72%

Relative power good level

Low to High

AUXILIARY LDOs

LDO1 (PWR4), LDO2 (PWR3)

V_{PWR3,4_VIN}

PGOOD

Input voltage range

3.3

12

80%

60%

7

20

V

Power good PWR3_VOUT,

PWR4_VOUT

PWR3_VOUT and PWR4_VOUT rising

PWR3_VOUT and PWR4_VOUT falling

Overvoltage Protection

PWR3_VOUT, PWR4_VOUT

OVP

DC output voltage accuracy

PWR3_VOUT, PWR4_VOUT

Regulator current limit⁽²⁾

I_OUT= 0 mA

–3%

300

3%

340

40

400

mA

µs

to 80% of V_OUT= PWR3 and PWR4, C

= 1 µF

t_ON

Turn-on time

LDO2 (PWR3)

V_{PWR3_VOUT}

Output Voltage PWR3_VOUT

Load Current capability

2.5

200

–70

V

mA

DC Load regulation PWR3_VOUT V_OUT= 2.5 V, 5 ≤ I_OUT≤ 200 mA

mV/A

(3) General Purpose Buck2 (PWR6) currently supported, others may be available in the future.

12

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Electrical Characteristics (continued)

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT= 2.5 V, I_OUT= 5 mA, 3.3 ≤

PWR3_VIN ≤ 20 V

DC Line regulation PWR3_VOUT

30

µV/V

LDO1 (PWR4)

V_{PWR4_VOUT}

Output Voltage PWR4_VOUT

Load Current capability

3.3

200

–70

V

mA

DC Load regulation PWR4_VOUT V_OUT= 3.3 V, 5 ≤ I_OUT≤ 200 mA

mV/A

V_OUT= 3.3 V, I_OUT= 5 mA, 4 ≤

DC Line regulation PWR4_VOUT

30

48

µV/V

mV

PWR4_VIN ≤ 20 V

I_OUT= 25 mA, V_OUT= 3.3 V, V_{PWR4_VIN}

=

Regulator dropout

3.3 V

MEASUREMENT SYSTEM

AFE

AFE_GAIN[1:0] = 01

1

9.5

18

G

Amplifier gain (PGA)

AFE_GAIN[1:0] = 10

AFE_GAIN[1:0] = 11

PGA, AFE_CAL_DIS = 1⁽²⁾

Comparator⁽²⁾

V/V

mV

–1

1

+1.5

67

V_OFS

Input referred offset voltage

Settling time

–1.5

To 1% of final value⁽²⁾

To 0.1% of final value⁽²⁾

.

46

69

τ_RC

µs

V

.

100

Input voltage Range

ACMPR_IN_1,2,3

V_{ACMPR_IN_1,2,3}

0

1.5

LABB

To 1% of final value⁽²⁾

To 0.1% of final value⁽²⁾

.

4.6

7

6.6

10

τ_RC

Settling time

µs

.

Input voltage range

ACMPR_IN_LABB

V_{ACMPR_IN_LABB}

0

7

1.5

28

V

Sampling window

ACMPR_IN_LABB

Programmable per 7 µs

µs

COLOR WHEEL PWM

CLK_OUT

Clock output frequency

2.25

MHz

V

V_{CW_SPEED_PW}Voltage range

M_OUT

Average value programmable in 16 bits

0

5

CW_SPEED_PWM_OUT

DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS

V_SPI

SPI supply voltage range

Output low-level

SPI_VIN

1.7

3.6

0.3

V

RESETZ, CMP_OUT, CLK_OUT. I_O

0.3 mA sink current

=

0

0.3 ×

V_SPI

V_OL

SPI_DOUT. I_O= 5 mA sink current

INTZ. I_O= 1.5 mA sink current

0

0.3 ×

V_SPI

RESETZ, CMP_OUT, CLK_OUT. I_O

0.3 mA source current

=

1.3

2.5

V_OH

Output high-level

V

0.7 ×

V_SPI

SPI_DOUT. I_O= 5 mA source current

PROJ_ON, LED_SEL0, LED_SEL1

SPI_CSZ, SPI_CLK, SPI_DIN

V_SPI

0.4

0

V_IL

Input low-level

Input high-level

V

0.3 ×

V_SPI

0

PROJ_ON, LED_SEL0, LED_SEL1

SPI_CSZ, SPI_CLK, SPI_DIN

1.2

V_IH

0.7 ×

V_SPI

13

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range. V_IN= 19.5 V, T_A= 0 to +40°C, typical values are at T_A= 25°C, Configuration

according to Typical Application (V_IN=19.5 V, I_OUT= 32 A, LED, external MOSFETs ) (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_BIAS

Input bias current

V_IO= 3.3 V, any digital input pin

0.1

µA

Normal SPI mode,

DIG_SPI_FAST_SEL = 0, ƒ_OSC= 9

MHz

0

36

40

SPI_CLK

SPI clock frequency⁽⁴⁾

Deglitch time

MHz

Fast SPI mode, DIG_SPI_FAST_SEL =

1, V_SPI> 2.3 V, ƒ_OSC= 9 MHz

20

t_DEGLITCH

LED_SEL0, LED_SEL1⁽²⁾

.

300

9

ns

INTERNAL OSCILLATOR

ƒ_OSC

Oscillator frequency

Frequency accuracy

MHz

T_A= 0 to 70°C

–5%

5%

THERMAL SHUTDOWN

Thermal warning (HOT threshold)

Hysteresis

120

10

T_WARN

°C

Thermal shutdown (TSD

threshold)

150

15

T_SHTDWN

Hysteresis

(4) Maximum depends linearly on oscillator frequency f_OSC

.

6.6 SPI Timing Parameters

SPI_VIN = 3.6 V ± 5%, T_A= 0 to 40ºC, C_L= 10 pF (unless otherwise noted).

MIN

0

NOM

MAX

UNIT

MHz

ns

f_CLK

t_CLKL

t_CLKH

t_t

Serial clock frequency

40

Pulse width low, SPI_CLK, 50% level

Pulse width high, SPI_CLK, 50% level

Transition time, 20% to 80% level, all signals

SPI_SS_Z falling to SPI_CLK rising, 50% level

SPI_CLK falling to SPI_CSZ rising, 50% level

SPI_MOSI data setup time, 50% level

SPI_MOSI data hold time, 50% level

SPI_MISO data setup time, 50% level

SPI_MISO data hold time, 50% level

SPI_CLK falling to SPI_MISO data valid, 50% level

SPI_CSZ rising to SPI_MISO HiZ

10

0.2

8

ns

4

1

ns

t_CSCR

t_CFCS

t_CDS

t_CDH

t_iS

ns

7

6

ns

10

0

ns

t_iH

ns

t_CFDO

t_CSZ

13

6

ns

14

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

7 Detailed Description

7.1 Overview

The DLPA4000 device is a highly integrated power management driver optimized for DLP 1500 to 3000 lumen

LED projectors . It targets accessory applications up to several hundreds of lumen and is designed to support a

wide variety of high-current LEDs. Functional Block Description shows a typical DLP high-side pumped LED

1500-3000 lumen projector implementation.

Part of the projector is the projector module, which is an optimized combination of components consisting of, for

instance, LEDs, DMD, control chip, memory, and optional sensors and fans. The front-end chip controls the

projector module. More information about the system and projector module configuration can be found in a

separate application note.

The device blocks are listed below and discussed in detail in this data sheet:

•

Supply and Monitoring: Creates internal supply and reference voltages and has functions such as thermal

protection

•

Illumination: Block to control the light. Contains drivers, strobe decoder for the LEDs and power conversion

External Power FETs: Capable for 32 A and High-Side Pump

DMD Supply: Generates voltages and their specific timing for the DMD. Contains regulators and DMD/DLPC

buck converters

•

Buck Converter: General purpose buck converter

Auxiliary LDOs: Fixed voltage LDOs for customer usage

Measurement System: Analog front end to measure internal and external signals

Programming: SPI interface, digital control

7.2 Functional Block Description

12- V Regulator

16 V to 20 V DC

Power Supplies

and Monitoring

Illumination

Control

HDMI

Shunt Diodes

PROJ_ON

VGA

Front

End

SPI

PWR_GOOD

PWR_ON

Digital Control Block

External

Power

FETs

High-Side Pump LED

Keypad

I2C

DLPA4000

DMD and

DATA

1.1 V

1.8 V

DMD

Reset

Controller Bucks

Flash

DLPC4422

Voltage

Generator

3.3 V

2.5 V

LDOs

DMD Reset

Voltages and Control

GP Buck

Converter

Measurement

System

Sensors

3.3 V

DLP650NE

or

DLPA200

Control

DLP650LE

DMD Data and Control

15

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

7.3 Feature Description

7.3.1 Supply and Monitoring

This block generates internal supply voltages and monitors device behavior.

7.3.1.1 Supply

The specified input supply voltage for main supply (VIN) is between 16 V and 20 V. The typical specification is

19.5 V. When the device energizes, several internal power supplies become energized sequentially.(Figure 1). A

sequential startup ensures that all the different blocks start in a certain order and prevent excessive startup

currents. The main control to start the device is the control pin PROJ_ON. Once set high the basic analog

circuitry is started that is needed to operate the digital and SPI interface. This circuitry is supplied by two LDO

regulators that generate 2.5 V (SUP_2P5V) and 5 V (SUP_5P0V). These regulator voltages internal only. Do not

load these regulator voltages externally. Make sure the output capacitance is 2.2 µF for the 2.5-V LDO (pin 91)

and 4.7 µF for the 5-V LDO, (pin 92). After the LDO voltages reach the regulator levels, the digital core starts,

and the Digital State Machine (DSM) controls the device.

Subsequently, the 5.5-V LDOs for various blocks start: PWR_5V5V, DRST_5P5V and ILLUM_5P5V. Then the

DLPC buck converters (PWR_1 & PWR_2) start and followed by the DMD LDOs (PWR_3 & PWR_4).The device

enables and is controllable by the DLPC (indicated by RESET_Z going high). At this point the general purpose

buck converter (PWR_6) can start. Lastly the regulator that supplies the DMD starts. The DMD regulator

generates the timing critical VOFFSET, VBIAS, and VRESET supplies.

16

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Feature Description (continued)

VIN

Note: Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under

SPI control.

Figure 1. Powerup Timing

17

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Feature Description (continued)

7.3.1.2 Monitoring

The DLPA4000 device monitors and reports faults occurrence and fault type. Register 0x0C stores the fault type

.The device generates an interrupt signal whenever a fault occurs. The user can configure fault conditions in

0x0D.

7.3.1.2.1 Block Faults

The device can detect fault conditions for supplies such as the low voltage supplies (SUPPLY_FAULT).

ILLUM_FAULT monitors correct supply and voltage levels in the illumination block. DMD_FAULT monitors a

correctly functioning DMD block. The PROJ_ON_INT bit indicates when PROJ_ON asserts.

7.3.1.2.2 Low Battery and UVLO

The low voltage warning signal (BAT_LOW_WARN) and voltage low shutdown (BAT_LOW_SHUT) signal

monitor the input voltage (VIN) (see Figure 2). These signals warn for a low VIN supply voltage or automatically

shutdown the device when the VIN supply drops below a predefined level. The threshold levels for these fault

conditions can be set from 3.9 V to 18.4 V by writing to registers 0x10<4:0> (LOWBATT) and 0x11<4:0>

(BAT_LOW_SHUT_UVLO). Figure 3 shows the threshold level hysteresis and its dependence on the selected

threshold voltage. Set the low voltage higher than the undervoltage lockout threshold to generate a warning

before the device shuts down.

ꢃꢄꢅ

ꢘꢂ

ꢃꢉꢊꢋ

ꢀ8ꢀꢁj`

ꢀꢂꢁꢃ

ꢌ6ꢌꢖ\ꢗ]

ꢔꢆꢕZꢐꢑꢓZꢒ!ꢏꢕ

ꢌ6ꢍꢍ\ꢎ7ꢌ]

ꢏꢃꢐꢑZꢒꢊꢐ

ꢌ6ꢌꢖ\ꢀ]

ꢔꢆꢕZꢐꢑꢓZꢓꢆꢉꢅ

ꢌ6ꢍꢌ\ꢎ7ꢌ]ꢁ

ꢆꢇꢅꢈ

ꢐꢑꢓꢔꢆꢕꢕZꢒꢊꢐ

ꢘꢙ

Figure 2. Voltage Monitoring

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

4

6

8

10

12

14

16

18

20

TRIM SETTING (V)

D002

Figure 3. Hysteresis on V_{LOW_BAT}and V_UVLO

18

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Feature Description (continued)

7.3.1.2.3 Thermal Protection

The device constantly monitors the chip temperature to prevent overheating. There are two levels of fault

condition for register 0x0C. The first level is an overheat warning (TS_WARN). The overheat warning indicates

when the chip reaches a critically high temperature. The second level (TS_SHUT) indicates when the chip

reaches a higher temperature than the TS_WARN level. The device shuts down the device to prevent permanent

damage when it reaches the TS_SHUT level. Both temperature faults have hysteresis levels to prevent rapid

switching when the temperature is near the threshold.

7.3.2 Illumination

The illumination function includes all blocks needed to generate light for the DLP system. The device uses a

control loop to accurately set the current through the LEDs (see Figure 4). Use IDAC[9:0] to set the intended

LED current. The Illumination driver controls the LED anode voltage V_LEDand as a result a current flows through

one of the LEDs. The voltage across the sense resistor (R_LIM) measures the LED current. Based on the

difference between the actual and intended current, the loop controls the output of the buck converter (V_LED

)

higher or lower. Switches P, Q, and R control the LED which conducts the current. The Openloop feedback

circuitry" confirms that the control loop can be closed for cases when there is no path via the LED (for instance,

when I_LED= 0 A).

VIN

LDO

ꢋ

ILLUMINATION

DRIVER

100n

25V

ILLUM

A (B)

L_OUT

ꢌ

C_OUT

V_LED

“Openloop”

feedback

circuitry

ꢉ

ꢀꢁꢂ

ꢊ

ꢃꢄꢀꢅꢂꢆ

ꢇꢆꢈꢅꢇꢆꢀ

SHUNT

ꢀ

GPIO (From

Controller)

R_LIM

IDAC[0:9]

Figure 4. Illumination Control Loop

These blocks comprise the illumination control loop.

Programmable gain block

•

19

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Feature Description (continued)

•

LDO illum, analog supply voltage for internal illumination blocks

Illumination driver A, primary driver for the external FETs

RGB strobe decoder, driver for external switches to control the on-off rhythm of the LEDs and measures the

LED current

7.3.2.1 Programmable Gain Block

IDAC registers 0x03h to 0x08h determine the current through the LEDs, which is measured through the sense

resistor R_LIM. The device compares the voltage across R_LIMwith the current setting from the IDAC registers. The

loop regulates the current to the set value.

L_OUT

V_LED

ILLUMINATION

Buck Converter

Gain

C_OUT

r_LED

R_WIRE

R_ON

V_RLIM

R_LIM

Figure 5. Programmable Gain Block in the Illumination Control Loop

When current flows through an LED, a forward voltage builds up across the LED. The LED acts as a (low)

differential resistance that is part of the load circuit for V_LED. Together with the wire resistance (R_WIRE) and the

on-resistance (R_ON) of the MOSFET switch, the device creates a voltage divider with the R_LIMresistor that is a

factor in the loop gain of the I_LEDcontrol. During normal conditions, the loop produces a well-regulated LED

current up to 32 A.

Because this voltage divider is a component of the control loop, make sure to consider issues such as resistance

and attenuation. For instance, when the application includes two LEDs connected in series, or when the

application has relatively high wiring resistance, the loop gain reduces due to the extra attenuation caused by the

increased series resistance of r_LED+ R_WIRE+R_ON. As a result, the loop response time lowers. To compensate for

this increased attenuation, increase the loop gain by selecting a higher gain for the programmable gain block.

Use register 0x25h [3:0] to set the gain increase.

During normal operation the default gain setting (00h) suffices. In case of two LEDs connected in series a gain

setting 01h or 02h suffices.

Wiring resistance also impacts the control-loop performance. Avoid unnecessary large wire length in the loop.

Maintain a wiring resistance as low as possible to yield the highest efficiency. When wiring resistance continues

to impact the response time of the loop, select an appropriate setting of the gain block. Also be aware of

connector resistance and PCB tracks. Every milli-ohm of resistance counts.

7.3.2.2 LDO Illumination

A dedicated regulator to the illumination block provides an analog power supply of 5.5 V to the internal circuitry.

Add a 1-µF capacitor to the input of the LDO and to the output of the LDO.

20

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Feature Description (continued)

7.3.2.3 Illumination Driver A

The illumination driver of the DLPA4000 comprises a buck controller for driving two external low-ohmic N-

channel MOSFETs Figure 6). The application note Understanding Buck Power Stages in Switchmode Power

Supplies (SLVA057) explains buck converter operation theory. Proper operation requires careful selection of the

external components, especially the inductor L_OUTand the output capacitor C_OUT. For best efficiency and ripple

performance, choose an inductor and capacitor with low equivalent series resistance (ESR).

0.47 µF

50 V

VIN

ILLUM_A_FB

3x10 µF

50 V

29

30

28

ILLUM_A_VIN

ILLUM_A_BOOST

3 Ω

0.47 µF/50 V

3x10 µF/50 V

0.1 uF

25 V

3.9 Ω

L

ILLUM_HSIDE_DRIVE

26

31

2700 pF

ILLUM_A_SW

50 V

ILLUMINATION

2 Ω

1000 pF

50 V

M

ILLUM_LSIDE_DRIVE

DRIVER

A

27

32

38

2200 pF

50 V

CSD87350Q5D

2x

ILLUM_A_PGND

ILLUM_A_COMP1

2xB240A-13-F

V_LED

2xB0540WS-7

15 pF

50V

1 µH

32 A

ILLUM_A_COMP2

6x22 µF

25 V

3300 pF

50 V

39

1.3 Ω

0.4 W

Figure 6. Typical Illumination Driver Configuration

Several factors determine the component selection of the buck converter, including input voltage (VIN), desired

output voltage (V_LED) and the allowed output current ripple. The first step of the configuration is to select the

inductor L_OUT

.

Select the value of the inductance of a buck power stage so that the peak-to-peak ripple current flowing in the

inductor remains within a certain range. Here, the target is set to have an inductor current ripple, k_{I_RIPPLE}, less

than 0.174 (17.4%). The minimum inductor value can be calculated given the input and output voltage, output

current, switching frequency of the buck converter (ƒ_SWITCH= 600 kHz), and inductor ripple of 0.174 (17.4%):

V_OUT

∂ (V_IN- V_OUT

)

V_IN

k_{I _ RIPPLE}∂I_OUT∂ f_SWITCH

L_OUT

=

(1)

Example: V_IN= 19.5 V, V_OUT= 4.3 V, I_OUT= 32 A results in an inductor value of L_OUT= 1µH

Determine the output capacitor, C_OUTafter selecting the inductor. Calculate the value considering that the

frequency compensation of the illumination loop is designed for an LC-tank resonance frequency of 13.8 kHz:

1

f_RES

=

2

π

L_OUTC_OUT

(2)

Example: C_OUT= 132 µF given that L_OUT= 1 µH. A practical value is 6 × 22 µF. Here, a parallel connection of two

capacitors is chosen to lower the ESR even further.

The selected inductor and capacitor determine the output voltage ripple. The resulting output voltage ripple

V_{LED_RIPPLE}is a function of the inductor ripple k_{I_RIPPLE}, output current I_OUT, switching frequency ƒ_SWITCHand the

capacitor value C_OUT

:

21

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Feature Description (continued)

k_{I_RIPPLE}∂I_OUT

V_{LED _RIPPLE}

=

8∂ f_SWITCH∂C_OUT

(3)

Example: K_{I_RIPPLE}= 0.174, I_OUT= 32 A, ƒ_SWITCH= 600 kHz and C_OUT= 6 x 22 µF results with an appropriately

small level of 8.8 mVpp.

It is strongly advised to keep the capacitance value low. The larger the capacitor value the more energy is

stored. When the LED voltage falls, stored energy must dissipate. Current discharges when stored energy

dissipates. Use Equation 4 to calculate the theoretical peak reverse current caused by a large voltage drop.

C_OUT

:: ;²

× V₁F V₂

:

;²; : ;²

+ I₁

I_{2 max}= ¨

:

;

L_OUT

where

•

V₁is the starting V_LED

V₂is the ending V_LED

I₁is the LED current

(4)

7.3.2.4 External MOSFETs

Depending on the type of external MOSFETs selected, consider adding any or all of the components described

in this section. TI recommends the user include placeholders for these components in the board design.

7.3.2.4.1 Gate series resistor (R_G)

Use gate series resistors to slow the turn-on transient of the power FET, if needed. Because the device switches

large currents, a fast turn-on transient time potentially risks switch-node ringing. Slowing down the turn-on

transient time reduces the edge steepness of the drain current waveform, The reduction of the edge steepness

results in a reduction of the induced inductive ringing. A resistance of a few Ohms typically suffices.

7.3.2.4.2 Gate series diode (D_G)

The turn-off transient time of the power FET includes gate series resistance also. This resistance potentially

affects on the non-overlap timing negatively. In order to maintain a fast turn-off transient time for the power FET,

use a diode in parallel with the gate series resistance. The cathode of the diode shunts the current at the gate

series resistor which results in a fast turn-off transient time. to the DLPA4000 device which results in a fast turn-

off transient time.

7.3.2.4.3 Gate parallel capacitance (C_G)

Use gate parallel capacitance specifically for higher supply voltages. The gate of a disabled power MOSFET can

be pulled high parasitically due to a large drain voltage swing and the drain-gate capacitance,

In the low-side MOSFET this voltage swing can happen at the end of the non-overlap time while the power

converter supplies current. In this case the switch node is low at the end of the non-overlap time. The switch

node pulls high when the high-side MOSFET starts. Due to the large and steep waveform edge of the switch

node current, the drain-gate capacitance of the low-side MOSFET injects the charge into the gate of the low-side

FET. This situation causes the low-side MOSFET to operate for a short period of time causing a shoot-through

current.

A similar situation exists with high-side FET. While the power converter discharges the LED voltage (V_LED) the

device directs the power converter current inward. At the end of the non-overlap time the switch node is high. If

at that moment the low-side MOSFET is enabled, via the gate-drain capacitance of the high-side MOSFET

charge is being injected into the gate of the high-side MOSFET potentially causing the device to switch on for a

short amount of time. That switch-on behavior causes a shoot through current as well.

Add more gate-source filter capacitance to reduce the effect of the charge injection via the drain-source

capacitance. In the case where a linear voltage division exists between gate-source capacitance and gate-drain

capacitance, and for a 20-V supply voltage, maintain a ratio of gate-source capacitance and gate-drain

capacitance to approximately 1:10 or larger. Make sure to test the gate-drive signals and the switch node for

potential cross conduction.

22

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Feature Description (continued)

Sometimes a design can include dual MOSFETs to dissipate power (heat). Consider the configurations shown in

Figure 7 tp prevent parasitic gate-oscillation a structure. In this example, the device isolates each gate with a

resistor (R_ISO) to dampen potential oscillations. A resistance of 1 Ω is typically sufficient.

D_G

R_ISO

R_G

R_ISO

C_G

Figure 7. Using R_ISOto Prevent Gate Oscillations When Using Power MOSFETs in Parallel

A buck converter design requires at least two capacitors. Make sure that the value of the input-capacitor pin

(ILLUM_A_VIN) is equal or greater than the selected output capacitance C_OUT, in this case ≥ 2 × 68 µF.

7.3.2.5 RGB Strobe Decoder

The DLPA4000 can sequentially control the three color-LEDs (red, green and blue). This circuitry consists of

three drivers to control external switches, the actual strobe decoder and the LED current control (Figure 8). The

N-channel MOSFET switches are connected to the cathode terminals of the external LED package. These

switches start and stop the currents through the LEDs.

23

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Feature Description (continued)

From ILLUM_A_FB

(V_LED

)

From LDO_ILLUM

OSRAM P2 LEDs

CH1_GATE_CTRL

CH2_GATE_CTRL

V_LED

19

20

2

CH3_GATE_CTRL

9

10

CH1_SWITCH

CH2_SWITCH

4x ESDA18-1k

17

18

P

CH3_SWITCH

24

25

Q

4x CSD17556Q5B

RGB

STROBE

DECODER

R

RLIM_1

RLIM_2

11

16

SHUNT

GPIO

4.7 nF

50V

(From

Controller)

22

23

RLIM_K_1

15

14

100 Ω

RLIM_BOT_K_1

4 mΩ

5W

RLIM_K_2

13

12

RLIM_BOT_K_2

CH_SEL_0

CH_SEL_1

60

61

From host

Figure 8. Switch Connection for a Common-Anode LED Assembly

The CH_SEL_0 and CH_SEL_1 pins control the N-channel MOSFET P, Q, and R signals. The CH_SEL[1:0]

registers typically receive a rotating code switching from RED to GREEN to BLUE and then back to RED.

Table 1 lists the relationship between CH_SEL[0:1] and the switch positions.

Table 1. Switch Positions for Common Anode RGB LEDs

SWITCH

PINS CH_SEL[1:0

IDAC REGISTER

P

Q

R

00

01

10

11

Open

Closed

Open

Closed

Open

Closed

N/A

0x03 and 0x04 SW1_IDAC[9:0]

0x05 and 0x06 SW2_IDAC[9:0]

0x07 and 0x08 SW3_IDAC[9:0]

CH_SEL[1:0] functions to start one of the switches, CH_SEL[1:0] but it also selects a 10-bit current setting for the

control IDAC that is used as the set current for the LED. The device uses this set current in addition to the

measured current through R_LIMto control the illumination driver to the appropriate V_LED. Registers 0x03 to 0x08

(Table 1). independently set the current through the three LEDs.

Each current level can be set from off to 150mV/R_LIMin 1023 steps:

Bit Value + 1 150 mV

I_LED

=

×

A

1024

R_LIM

(5)

24

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

The maximum current for R_LIMis 4.7 mΩ, so the I_LEDAis 32 A. However, the reference design includes a more

common 4-mΩ value with a less than maximum IDAC value for 32 A.

The device requires a minimum LED current of 5% of I_{LED_MAX}to operate correctly.

7.3.2.5.1 Break Before Make (BBM)

The operation of the three LED N-channel MOSFET switches (P, Q, R) follows a break-before-make control. The

device returns a switch to the OPEN position first before the device sets the subsequent switch to the CLOSED

position (BBM), Figure 9. The BBM register (0x0E) controls the dead-time between closing one swtich and

opening another. Switches that are intended to remain closed do not opened during the BBM delay time.

BBM dead time (0x0E)

P

Q

R

P

Figure 9. Break-Before-Make Timing

7.3.2.5.2 Openloop Voltage

in some case, there is no control loop for the buck converter through the LED. To prevent the output voltage of

the buck converter to vary inconsistently, use an internal resistive divider to close the loop is closed as shown in

Figure 4. Open loop voltage control is active:

•

during the BBM period. Transitions from one LED to another implies that during the BBM time all LEDs are

off.

•

when the current setting for all three LEDs is 0.

It’s important to set the open loop voltage to approximately equal the lowest LED forward voltage. Use register

0x18 to set the open loop voltage between 3 V and 18 V in steps of 1 V.

7.3.2.5.3 Transient Current Limit

Typically the forward voltages of the green diodes and the blue diodes are equivalent to each other (between 3 V

and 5 V). However the forward voltage of the red diode is significantly lower (2 V to 4 V). This difference can lead

to a current spike in the RED diode when the strobe controller switches from green or blue to red. The spike

occurs because the LED voltage (V_LED) is initially higher than required to drive the red diode. DLPA4000 limits

the transient current for each switch in the LEDs during the transition. Use register 0x02 (ILLUM_ILIM) to control

the transient current limit. A typical application requires this limit for only for the RED diode. Set the value for

ILLUM_ILIM to at least 20% higher than the DC regulation current. Use the three bits of register 0x02

(ILLUM_SW_ILIM_EN) to select which switch controls the transient current limiting feature. Figure 10 and

Figure 11 show the effect of the transient current limit on the LED current.

For high-side pump applications, where there are two series stacked LEDs for green, sequence precautions are

needed to avoid damaging the LEDS. Always transition from high-side pump green to blue, avoid following the

green with red.

25

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Transient

current

limit

Current

overshoot

ILLUM_ILIM

SW_IDAC

active

SW_IDAC

Time

Figure 10. LED Current Without Transient Current

Limit

Figure 11. LED Current With Transient Current

Limit

7.3.2.6 Illumination Monitoring

The device continuously monitors the illumination block for system failures to prevent damage to the system and

the LEDs. The device protects from a broken control loop and a too high or too low output voltage V_LED. Register

0x0C (ILLUM_FAULT) controls the overall illumination fault bit. If the device report either

ILLUM_BC1_PG_FAULT (powergood) or ILLUM_BC1_OV_FAULT (overvoltage), make sure the ILLUM_FAULT

bit is not set too high:

7.3.2.6.1 Power Good

Both the Illumination driver and the Illumination LDO have a power good indication. The power good for the

driver indicates if the output voltage (V_LED) is within a defined window indicating that the LED current has

reached the set point. If for some reason the LED current cannot be controlled to the intended value, this fault

occurs. Subsequently, the device sets bit ILLUM_BC1_PG_FAULT in register 0x27 to high. When the device

energizes the power good of the LDO, it indicates that the LDO voltage is below a pre-defined minimum of 80%

(for the rising edge) or 60% (for the falling edge). Register 0x27 stores the power good indication for the LDO

(V5V5_LDO_ILLUM_PG_FAULT).

7.3.2.6.2 RatioMetric Overvoltage Protection

The DLPA4000 device protects the illumination driver LED outputs against open circuit use. When no LED is

connected and the device receives a signal to set the LED current to a specific level, the LED voltage

(ILLUM_A_FB) quickly rises and potentially saturates to VIN. The device triggers OVP protection circuit when

V_LEDcrosses the specified threshold to prevent this dangerous situation. The OVP protection fault disables the

DLPA4000 device.

The device triggers a fault when the supply voltage (VINA) falls too low. A comparator senses both the LED

voltage and the V_INAsupply voltage The fraction of the VINA is connected to the minus input of the comparator

while the fraction of the V_LEDvoltage is connected to the plus input. The OVP fault occurs when the plus input

rises above the minus input. Set the fraction of the VINA between 1 V and 4 V to ensure proper operation of the

comparator.

26

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

ILLUM_A_FB

(V_LED

VINA

)

Settings:

reg 0x19h [4:0]

reg 0x0Bh [4:0]

V_LED/ V_{LED_RATIO}

OVP_trigger

+

V_INA/ V_{INA_RATIO}

1V< V_IN-<4V

Figure 12. Ratio Metric OVP

Use register 0x19h bits [4:0] to set the fraction of the ILLUM_A_FB voltage. Use register 0x0Bh bits [4:0] to set

the fraction of the VINA voltage. In general the device issues an OVP fault when either Equation 6 or Equation 6

occurs.

V_LED

V

INA

RATIO

R

õ V_LEDR V

×

INA

V

INA

RATIO

(6)

(7)

V_LED

4.98

5.85

RATIO

V_LEDR V

×

R V

×

= 0.85 × V

INA

V

INA

RATIO

Because the OVP level is ratio-metric it can be set to a fixed fraction of V_INA

.

For example: to maintain a V_LEDlevel below 85% of V_INA, use these settings:

reg 0x19h [4:0] = 01h (4.98)

reg 0x0Bh [4:0] = 07h (5.85)

Additionally for V_{IN_RATIO}= 5.85 the V_IN–input voltage for the comparator is between 1 V and 3.4 V for a supply

voltage between 6 V and 20 V.

7.3.3 External Power MOSFET Selection

The DLPA4000 requires five external N-type Power MOSFETs for proper operation. Two Power MOSFETs are

required for the illumination buck converter section (FETs L_EXTand M_EXT图 22) and three power MOSFETs are

required for the LED selection switches (FETs P_EXT, Q_EXTand R_EXTin 图 22). This section discusses the

selection criteria for these MOSFETs.

•

Threshold voltage

Gate charge

Gate gate timing

On-resistance, (R_DS(on)

)

7.3.3.1 Threshold Voltage

The DLPA4000 has one drive output for each of the five power MOSFETs. Select MOSFETs that can be

energized with a gate-source voltage of 5 V because signal swing at these outputs is approximately 5 V. For the

three LED selection outputs (CHx_GATE_CTRL) and the low-side drive (ILLUM_LSIDE_DRIVE), the drive signal

refers to ground. The signal swing of the ILLUM_HSIDE_DRIVE output refers to the switch node of the converter,

ILLUM_A_SW. Use only N-channel MOSFETS.

7.3.3.2 Gate Charge and Gate Timing

Power MOSFETs typically specify the total gate charge required to energize and de-energize parameter. The

total gate charge informs the gate-to-source rise times and fall times. Make sure the maximum gate-to-source

rise times and fall times maximum are approximately between 20 ns and 30 ns. Because the typical high-side

driver pull-up resistance is approximately 5 Ω, use a maximum gate capacitance between 4 nF and 6 nF . Design

a maximum total gate charge between 20 nC and 30 nC.

27

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Internal non-overlap timing prevents both the high-side and low-side MOSFET of the illumination buck converter

from energizing simultaneously. Typical non-overlap timing of approximately 35 ns usually gives sufficient

margins. The DLPA4000 device measures the gate-to-source voltage of the external MOSFETs to determine

whether a MOSFET energized or not. This measurement is done at the pins of the DLPA4000. For the low-side

MOSFET this measurement is done between ILLUM_LSIDE_DRIVE and ILLUM_A_GND. Similarly, for the high-

side MOSFET the device measures the gate-to-source voltage between the ILLUM_HSIDE_DRIVE pin and the

ILLUM_A_SW pin. Because of the location of these measurement nodes, do not insert any additional drivers or

circuitry between the DLPA4000 and the external power MOSFETs of the buck converter. Delays can lead to

incorrect on-off detection of the FETs and cause shoot-through currents if the user inserts additional circuitry.

Shoot-through currents reduce efficiency, and more seriously damage the power MOSFETs.

LED selection switches require no specific criteria regarding the gate charge or gate timing. Timing of the LED

selection signals is in the microsecond range rather than nanosecond range.

7.3.3.3 On-resistance R_DS(on)

Consider two issues relative to the drain-to-source on-resistance (R_DS(on)) to select a MOSFET. The first

consideration is for the high-side MOSFET of the illumination buck-converter the R_DS(ON)is a factor in the over-

current detection. Secondly, for the other four MOSFETs the power dissipation drives the choice of the

MOSFETs R_DS(on)

.

The DLPA4000 measures the drain-to-source voltage drop of the high-side MOSFET when energized to detect

an overcurrent situation. When the device detection circuit triggers, and de-energizes the high-side FET, the

high-side drive over current threshold (V_DC-Th) is 185 mV . Use Equation 8 to calculate the actual current level,

(I_OC) that trigger the overcurrent detection.

V_DCF Th 185 mV

I_OC

=

×

R_{DS on}

: ;

:

;

(8)

Use the on-resistance specification listed in the MOSFET datasheet for a high-temperature condition.For

example, the CSD87350Q5D NexFET specifies the on-resistance of 5 mΩ at 125 °C. The overcurrent level for a

design that uses this MOSFET is 37 A. This MOSFET is a good choice for a 32-A application.

Power dissipation due to conduction losses determines the on-resistance selection for the low-side MOSFET and

the three LED selection MOSFETs. Use Equation 9 to calculate the power dissipated in these MOSFETs.

2

:

;

P_DISS= ± I_DS× R_{DS on}

:

;

P

where

•

I_DSis the FET current

(9)

The lower the on-resistance the lower the power dissipation. For example, the on-resistance specified for the

CSD17556Q5B MOSFET is 1.2 mΩ. For a drain-to-source current of 32 A with a duty cycle of 25% (when the

MOSFET is used as LED selection switch) the dissipation is approximately 0.3 W.

7.3.4 DMD Supplies

Figure 13 shows the supplies needed for the DMD and DLPC block.

•

LDO_DMD: for internal supply

DMD_HV: regulator generates high voltage supplies

Two buck converters: for DLPC/DMD voltages

28

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

ꢀꢁꢂꢃꢄ7ꢅꢆꢇꢀ

ꢀꢑꢖꢄ7ꢅꢗ8ꢘꢀ

ꢀꢋꢄꢐ7ꢅRꢆꢙꢀ

ꢈꢉꢈꢅꢊꢀꢅ

ꢋꢌꢍꢎꢏꢃꢐꢑꢋ

ꢏꢈꢑꢅꢈꢉꢈ

ꢁꢎꢒꢓꢆ7ꢅꢈꢉꢈLꢈꢏꢔꢒꢅ^ꢔꢕꢋꢆ_

ꢆ8ꢆꢀꢅ^ꢈꢏꢔꢒ_ꢅ

ꢆ8ꢗꢀꢅ^ꢈꢏꢔꢒ_

ꢁꢎꢒꢓꢚ7ꢅꢈꢉꢈLꢈꢏꢔꢒꢅ^ꢔꢕꢋꢚ_

Figure 13. DMD Supplies Blocks

The DMD supplies block operates with the 0.65 DLP650NE DMD and the related DLPC4422. In addition to the

three high voltage supplies to power the DLPA4000, the DMD and the related DLPC4422 each require a supply,

Two buck converters provide the power.

The EEPROM of the DLPA4000 is factory programmed for a certain configuration, such as the type of buck

converter used. Use register 0x26 to read the EEPROM configuration using these bits:

•

DMD_BUCK1_USE

DMD_BUCK2_USE

Table 8 describes the function of register 0x26.

7.3.4.1 LDO DMD

The LDO DMD is a regulator dedicated to the DMD supplies block. The LDO DMD provides an analog supply

voltage of 5.5 V to the internal circuitry.

7.3.4.2 DMD HV Regulator

The DMD HV regulator generates three high voltage supplies: DMD_VRESET, DMD_VBIAS, and

DMD_VOFFSET (see Figure 14). The DMD HV regulator uses a switching regulator (switch A through switch D),

when the inductor shares time between all three supplies. The inductor charges to the current limit threshold and

then discharged into one of the three supplies. The regulator distributes available charge time between those

supplies that require a charge and when not all supplies require a charge.

29

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

LDO DMD

(DRST_5P5V)

A

MBR0540

DRST_HS_IND

DRST_LS_IND

DMD_VRESET

6

VRST

1 µF

35 V

2

10 µH

1.25 A

D

100 nF

25 V

100

C

G

100 nF

25 V

DMD

470 nF

50 V

B

HIGH VOLTAGE

REGULATOR

DRST_PGND

DMD_VBIAS

4

VBIAS

VOFS

99

98

DMD_VOFFSET

1 µF

50 V

100 nF

25 V

F

E

Figure 14. DMD High Voltage Regulator

7.3.4.3 DMD/DLPC Buck Converters

Each of the two DMD buck converters creates a supply voltage for the DLPC device. The values of the voltages

for the DMD and DLPC used, for instance:

•

DMD+DLPC4422: 1.1 V and 1.8 V

The topology of the buck converters is the same topology for the general purpose buck converters. See the Buck

Converters section for inductor and capacitor configuration .

A typical configuration uses a value of 3.3 µH for the inductor and a value of 2 × 22 µF for the output capacitor.

30

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

PWR1_BOOST

PWR1_VIN

97

96

95

100 nF

25 V

VIN

470 pF

H

I

2x10 µF

50 V

470 nF

50V

10 Ω

50V

PWR1_SWITCH

DMD/DLPC

PWR1

3.3 µH

3 A

PWR1_PGND

PWR1_FB

93

94

V_DMD-DLPC-1

2x22 µF

25 V

Low_ESR

PWR2_BOOST

PWR2_VIN

76

75

100 nF

25 V

VIN

470 pF

J

470 nF

50 V

10 Ω

2x22 µF

50 V

PWR2_SWITCH

DMD/DLPC

PWR2

74

K

3.3 µH

3 A

PWR2_PGND

PWR2_FB

73

72

V_DMD-DLPC-2

2x22 µF

25 V

Low_ESR

Figure 15. DMD and DLPC Buck Converters

31

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

7.3.4.4 DMD Monitoring

The device continuously monitors the DMD block for failures in order to prevent damage and to regulate the

DMD voltages. Potential failures include but are not limited to a broken control loop or a too high or too low

converter output voltage. Register 0x0C stores the overall DMD fault bit, DMD_FAULT. If any of the failures in

Table 2 occur, the device sets the DMD_FAULT bit to high.

Table 2. DMD FAULT Indication

POWER GOOD (REGISTER 0x29)

BLOCK

REGISTER BIT

THRESHOLD

DMD_RESET: 90%,

DMD_OFFSET and DMD_VBIAS: 86% rising, 66% falling

HV Regulator

DMD_PG_FAULT

PWR1

PWR2

BUCK_DMD1_PG_FAULT

BUCK_DMD2_PG_FAULT

Ratio: 72%

LDO_GP2_PG_FAULT /

LDO_DMD1_PG_ FAULT

PWR3 (LDO_2)

PWR4 (LDO_1)

80% rising, 60% falling

LDO_GP1_PG_FAULT /

LDO_DMD1_PG_ FAULT

OVER-VOLTAGE (REGISTER 0x2A)

BLOCK

PWR1

PWR2

REGISTER BIT

THRESHOLD (V)

Ratio: 120%

BUCK_DMD1_OV_FAULT

BUCK_DMD2_OV_FAULT

Ratio: 120%

LDO_GP2_OV_FAULT /

LDO_DMD1_OV_FAULT

PWR3 (LDO_2)

PWR4 (LDO_1)

7

LDO_GP1_OV_FAULT /

LDO_DMD1_OV_FAULT

7.3.4.4.1 Power Good

The DLPA4000 has power good indication for the DMD high-voltage (HV) regulator, DMD buck converters, DMD

LDOs, and the LDO_DMD that supports the high-voltage regulator.

The DLPA4000 device continuously monitors the DMD HV regulator output rails DMD_RESET, DMD_VOFFSET

and DMD_VBIAS. The DLP4000 device sets the DMD_ PG_FAULT bit in register 0x29 if either one of the output

rails drops out of regulation. This situation can be due to a shorted output or an overload. The DMD_RESET

threshold is 90%. The DMD_OFFSET and DMD_VBIAS thresholds are 86% (rising edge) and 66% (falling edge).

The power good signal for the two DMD buck converters indicate if each output voltage (PWR1_FB and

PWR2_FB) maintains a specified range. The relative power good ratio is 72%, which indicates the level (output

voltage falls below) at which the power good fault bit is asserted. The power good fault bits are in register 0x29,

BUCK_DMD1_PG_FAULT and BUCK_DMD2_PG_FAULT.

The device monitors the output voltage of the DMD_LDO1 pin and the DMD_LDO2 pin. The power good fault of

the LDO is asserted when the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended

value. The power good fault indication for the LDOs is in register 0x29, LDO_GP1_PG_FAULT,

LDO_DMD1_PG_FAULT, LDO_GP2_PG_FAULT, LDO_DMD2_PG_FAULT.

The LDO_DMD pin regulates the DMD HV. The device asserts the power good fault of the LDO_DMD when the

LDO voltage goes below 80% (rising edge) or 60% (falling edge) of its intended value. Register 0x29 stores the

power good fault indication for this LDO as V5V5_LDO_DMD_PG_FAULT.

7.3.4.4.2 Overvoltage Fault

An overvoltage fault occurs when an output voltage rises above a specified threshold. The device indicates

overvoltage faults for the DMD buck converters, DMD LDOs and the LDO_DMD that support the DMD HV

regulator. The device does not include overvoltage fault of LDO1 and LDO2 in the overall DMD_FAULT when the

LDOs are used as general purpose LDOs. Table 2 provides an overview of the DMD overvoltage faults and

threshold levels.

32

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

7.3.5 Buck Converters

The DLPA4000 contains three general purpose buck converters and a supporting LDO (LDO_BUCKS). The

three programmable 8-bit buck converters generate a voltage between 1 V and 5 V. The buck converters have

an output current limit of 2 A. The device supports only General Purpose Buck2 (PWR6) types. Figure 16 shows

one of the buck converters and the LDO_BUCKS.

The two DMD or DLPC buck converters discussed earlier in DMD Supplies have the same architecture as these

three buck converters and can be configured in the same way.

1 µF/16 V

1 µF/6.3 V

PWR_VIN

83

84

VIN

LDO

BUCKS

PWR_5P5V

PWR6_BOOST

PWR6_VIN

65

64

63

100 nF

25 V

VIN

2x10 µF

16 V

R_SNx

C_SNx

PWR6_SWITCH

General Purpose

BUCK2

L_OUT

3.3 µH

3 A

PWR6_PGND

PWR6_FB

62

66

V_OUT

C_OUT

2x22 µF

6.3 V

Low_ESR

Figure 16. Buck Converter

7.3.5.1 LDO Bucks

This regulator supports the three general purpose buck converters and the 2 DMD or DLPC buck converters The

regulator provides an analog voltage of 5.5 V to the internal circuitry.

7.3.5.2 General Purpose Buck Converters

Register 0x01 (BUCK_GP2_EN) controls the general purpose buck converters (GP2) (Figure 16).

Use register 0x14 to configure the converter outpout voltage between 1 V and 5 V with an 8-bit resolution.

The device supports only General Purpose Buck2 (PWR6) types. has a current capability of 2 A. The device

does not support other buck converters such as PWR5 or PWR7.

33

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

The buck converter operates in one of two switching modes; Normal mode (600 kHz switching frequency), mode

and skip mode. Applications operate with an increase in light-load efficiency in skip mode. As the output current

decreases from a heavy-load condition, the inductor current decreases. The inductor current eventually

decreases to a point where the ripple valley touches zero. Zero is the boundary between continuous conduction

and discontinuous conduction modes. The device de-energizes the rectifying MOSFET when it detects zero

inductor current. The converter transitions into discontinuous conduction mode as the load current further

decreases. Because the device maintains the on-time, it takes longer to discharge the output capacitor with a

smaller load current to the level of the reference voltage. Skip mode operation can toggle per buck converter in

register 0x16.

7.3.5.3 Buck Converter Monitoring

The device continuously monitors the buck converter block to prevent damage to the DLPA4000 and peripherals.

The device monitors several pin voltages. 表 3 summarizes the buck converter fault indications.

表 3. Buck Converter Fault Indication

POWER GOOD (REGISTER 0X27)

BLOCK

REGISTER BIT

THRESHOLD (RISING EDGE)

Ratio 72%

Gen.Buck1

Gen.Buck2

Gen.Buck3

BUCK_GP1_PG_FAULT

BUCK_GP2_PG_FAULT

BUCK_GP3_PG_FAULT

Ratio 72%

OVERVOLTAGE (REGISTER 0X28)

BLOCK

REGISTER BIT

THRESHOLD (RISING EDGE)

Ratio 120%

Gen.Buck1

Gen.Buck2

Gen.Buck3

BUCK_GP1_OV_FAULT

BUCK_GP2_OV_FAULT

BUCK_GP3_OV_FAULT

Ratio 120%

7.3.5.3.1 Power Good

The device has individual power good indication for each buck converter and the supporting LDO_BUCK pin.

The power good indication for the buck converter monitors the output voltage (PWR6_FB) is within a defined

window. The relative power good ratio is 72%. This means that if the output voltage is below 72% of the set

voltage the PG_fault bit is set high. The power good bits of the buck converter are in register 0x27 bit:

•

BUCK_GP2_PG_FAULT for BUCK2 (PWR6)

The LDO_BUCKS that supports the buck converters has its own power good indication. The power good of the

LDO_BUCKS is asserted if the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended

value. The power good indication for the LDO_BUCKS is in register 0x29, V5V5_LDO_BUCK_PG_FAULT.

7.3.5.3.2 Overvoltage Fault

An over-voltage fault occurs when an output voltage rises above the specified threshold. The device indicates

overvoltage faults for the buck converters, and the LDO_BUCKS pin. The device asserts an overvoltage fault of

the LDO_BUCKS pin when the LDO voltage goes abve 7.2 V. Use register 0x2A,

V5V5_LDO_BUCK_OV_FAULT. The overvoltage of the general purpose buck converters is 120% of the set

value.

Register

0x28

stores

the

BUCK_GP1_OV_FAULT,

BUCK_GP2_OV_FAULT,

and

BUCK_GP3_OV_FAULT faults.

7.3.6 Auxiliary LDOs

Use the two auxiliary LDOs (LDO_1 and LDO_2) for external applications. Use all other LDOs for internally only.

Do not load these internal LDOs . LDO1 (PWR4) has a fixed voltage of 3.3 V. LDO2 (PWR3) has a fixed voltage

of 2.5 V. Both LDOs deliver 200 mA of output current.

34

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

7.3.7 Measurement System

图 17 shows the circuitry that senses internal and external nodes. The implemented AFE comparator converts

the nodes to digital signals. Use the 0x0A register to enable AFE_EN. The reference signal for this comparator,

ACMPR_REF, is a low pass filtered PWM signal coming from the DLPC. A variable gain amplifier (VGA) is

added with three gain settings (1x, 9.5x, and 18x) allows the device to receive a wide range of input signals . Use

register 0x0A, to set the VGA gain (AFE_GAIN). The maximum input voltage of the VGA is 1.5 V. The device

reduces some large internal voltage to accomodate the VGA function.

ACMPR_REF

82

From host

SYSPWR/xx

ILLUM_A_FB/xx

ILLUM_B_FB/xx

CH1_SWITCH

CH2_SWITCH

CH3_SWITCH

RLIM_K1

RLIM_K2

VREF_1V2

MUX

81 ACMPR_OUT

VOTS

VPROG1/12

VPROG2/12

V_LABB

To host

ACMPR_IN_LABB

80

55

S/H

ACMPR_IN_1

ACMPR_IN_2

ACMPR_IN_3

ACMPR_LABB_SAMPLE

AFE

AFE_SEL[3:0] AFE_GAIN [1:0]

ACMPR_IN_1

77

From light sensor

ACMPR_IN_2 78

ACMPR_IN_3 79

From temperature sensor

图 17. Measurement System Schematic

The device connects a multiplexer (MUX) to a wide range of nodes. Use egister 0X0A, to select the MUX input

(AFE_SEL) . Choose settings from these options:

•

System input voltage, SYSPWR

LED anode cathode voltage, ILLUM_A_FB

LED cathode voltage, CHx_SWITCH

V_R_LIMto measure LED current

Internal reference, VREF_1V2

Die Temperature represented by voltage VOTS

EEPROM programming voltage, VPROG1,2/12

LABB sensor, V_LABB

External sense pins, ACMPR_IN_1, ACMPR_IN_2, ACMPR_IN_3

The system input voltage VIN can be measured by selecting the SYSPWR/xx input of the MUX. the The device

must divide the voltage before the device supplies system input voltage to the MUX. Applications require this

process because the variable gain amplifier (VGA) handles voltages up-to 1.5 V but system voltages can be as

high as 20 V. The device combines the division factor selection (VIN division factor) with the auto LED turn off

functionality of the illumination driver . Use register 0x18 to ILLUM_LED_AUTO_OFF_SEL.

The device measures the LED voltages by monitoring the common anode of the LEDs and the cathode of each

LED individually. The device senses the feedback pin of the illumination driver (ILLUM_A_FB) to measure the

LED anode voltage (V_LED). The device must divide the LED anode voltage before the device supplies input

voltage to the MUX. The device combines the division factor with the overvoltage fault level of the illumination

driver. Use register 0x19 to set VLED_OVP_VLED_RATIO. The device feeds the cathode voltages for

CH1_SWITCH, CH2_SWITCH,and CH3_SWITCH directly to the MUX without a division factor.

You can determine the LED current if you know the value of the sense resistor R_LIMand the voltage across the

resistor. Measure the voltage at the high-side of the sense resistor can be measured by selecting MUX-input

RLIM_K1. The bottom-side of the resistor connects to GND.

The VOTS pin connects to an on-chip temperature sensor. The VOTS voltage measures the device junction

temperature:

35

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

T_J= 300 × V_VOTS– 270

(10)

The DLPA4000 has two EEPROM blocks for storage of trim bits, 0x30 to 0x35). Use these bytes for USER

EEPROM also. Use MUX input VPROG1/12 to measure the programming voltage of EEPROM block 1. Use

VPROGR2/12 to measure the programming voltage of EEPROM block 2. The device divides the EEPROM

programming voltage by 12 and then supplies the value to the MUX to prevent a too large voltage on the MUX

input. The EEPROM programming voltage is approximately 12 V.

The local area brightness boost (LABB) function increases brightness while maintaining good contrast and

saturation. Connect the sensor to pin ACMPR_IN_LABB. The device samples the light sensor signal. The device

holds the sample value separate from the sensor timing. Make sure the application uses these setting for LABB

oepration.

•

The AFE block is enabled (0x0A, AFE_EN = 1)

The LABB input is selected (0x0A, AFE_SEL<3:0>=3h)

The AFE gain is set appropriately to have AFE_Gain x VLABB < 1.5 V (0x0A, AFE_GAIN<1:0>)

Use one of the following methods to sample the signal.

•

Write to register 0x0B by specifying the sample time window (TSAMPLE_SEL) and set bit SAMPLE_LABB=1

to start sampling. The device automatically restes the SAMPLE_LABB bit in register 0x0B to 0 at the end of

the sample period to prepare for a next sample request.

•

Use the input ACMPR_LABB_SAMPLE-pin as a sample signal. The signal on ACMPR_IN_LABB is tracked

while it is high. After the ACMP_LABB_SAMPLE goes lowm the value the device holds the value.

ACMPR_IN_1, ACMPR_IN_2,and ACMPR_IN_3 measure external signals from components such as a light

sensor or a temperature sensor. Make sure that the voltage on the input doe not exceed 1.5 V.

7.4 Device Functional Modes

表 4. Modes of Operation

MODE

OFF

DESCRIPTION

This is the lowest-power mode of operation. All power functions are de-energized, registers are reset to their default values,

and the IC does not respond to SPI commands. RESET_Z pin is pulled low. The IC enters OFF mode whenever the

PROJ_ON pin is low.

The DMD regulators and LED power (V_LED) are turned off, but the IC does respond to the SPI. The device enters WAIT mode

whenever PROJ_ON is set high, DMD_EN⁽¹⁾bit is set to 0 or a FAULT is resolved.

WAIT

The device also enters STANDBY mode when a fault condition is detected⁽²⁾. (See also section Interrupt). Once the fault

condition is resolved, WAIT mode is entered.

STANDBY

ACTIVE1

ACTIVE2

The DMD supplies are enabled but LED power (V_LED) is disabled. PROJ_ON pin must be high, DMD_EN bit must be set to 1,

and ILLUM_EN⁽³⁾bit is set to 0.

DMD supplies and LED power are enabled. PROJ_ON pin must be high and DMD_EN and ILLUM_EN bits must both be set

to 1.

(1) Settings can be done through register 0x01

(2) Power-good faults, over-voltage, over-temperature shutdown, and undervoltage lockout

(3) Settings can be done through register 0x01, bit is named ILLUM_EN

表 5. Device State as a Function of Control-Pin Status

PROJ_ON Pin

STATE

LOW

OFF

WAIT

STANDBY

ACTIVE1

ACTIVE2

HIGH

(Device state depends on DMD_EN and ILLUM_EN bits and whether there are any fault

conditions.)

36

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

POWERDOWN

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

Valid power source connected

PROJ_ON = low

OFF

SPI interface disabled

D_CORE_EN = low

RESET_Z = low

All registers set to default values

PROJ_ON = high

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

DMD_EN = 0

||

PROJ_ON = low

FAULT = 0

WAIT

VRESET = OFF

VBIAS = OFF

VOFFSET = OFF

VLED = OFF

SPI interface enabled

D_CORE_EN = high

RESET_Z = low

DMD_EN = 1

FAULT = 0

STANDBY

&

DMD_EN = 0

||

VRESET = ON

VBIAS = ON

VOFFSET = ON

VLED = OFF

PROJ_ON = low

FAULT = 1

ACTIVE 1

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

VLED_EN = 1

VLED_EN = 0

VRESET = ON

VBIAS = ON

VOFFSET = ON

VLED = ON

DMD_EN = 0

||

PROJ_ON = low

FAULT = 1

ACTIVE 2

SPI interface enabled

D_CORE_EN = high

RESET_Z = high

A. || = OR, & = AND

B. FAULT = Undervoltage on any supply, thermal shutdown, or UVLO detection

C. UVLO detection, per the diagram, causes the DLPA4000 to go into the standby state. Standby state is not the lowest

power state. If the application requires lower power, set PROJ_ON low.

D. DMD_EN register bit can be reset or set by SPI writes. DMD_EN defaults to 0 when PROJ_ON goes from low to high

and then the DLPC4422 software automatically sets it to 1. Also, FAULT = 1 causes the DMD_EN register bit to be

reset.

E. D_CORE_EN is a signal internal to the DLPA4000. This signal turns on the VCORE regulator.

图 18. State Diagram

37

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

7.5 Programming

This section discusses the serial protocol interface (SPI) of the DLPA4000 as well as the interrupt handling,

device shutdown and register protection.

7.5.1 SPI

The DLPA4000 provides a 4-wire SPI port that supports two SPI clock frequency modes: 0 MHz to 36 MHz and

20 MHz to 40MHz. The clock frequency mode can be set in register 0x17, DIG_SPI_FAST_SEL. The interface

supports both read and write operations. The SPI_SS_Z input serves as the active low chip select for the SPI

port. The SPI_SS_Z input must be forced low for writing to or reading from registers. When SPI_SS_Z is forced

high, the data at the SPI_MOSI input is ignored, and the SPI_MISO output is forced to a high-impedance state.

The SPI_MOSI input serves as the serial data input for the port; the SPI_MISO output serves as the serial data

output. The SPI_CLK input serves as the serial data clock for both the input and output data. Data at the

SPI_MOSI input is latched on the rising edge of SPI_CLK, while data is clocked out of the SPI_MISO output on

the falling edge of SPI_CLK. 图 19 illustrates the SPI port protocol. Byte 0 is referred to as the command byte,

where the most significant bit is the write/not-read bit. For the W/nR bit, a 1 indicates a write operation, while a 0

indicates a read operation. The remaining seven bits of the command byte are the register address targeted by

the write or read operation. The SPI port supports write and read operations for multiple sequential register

addresses through the implementation of an auto-increment mode. As shown in 图 19, the auto-increment mode

is invoked by simply holding the SPI_SS_Z input low for multiple data bytes. The register address is

automatically incremented after each data byte transferred, starting with the address specified by the command

byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.

Set SPI_CS_Z=1 here to write/read one register location

Hold SPI_CS_Z=0 to enable auto-increment mode

SPI_SS_Z

Header

Register Data (write)

SPI_MOSI

SPI_MISO

SPI_CLK

Byte0

Byte1

Byte2

Byte3

ByteN

Register Data (read)

Data for A[6:0]

Data for A[6:0]+1

Data for A[6:0]+(N-2)

Byte0

Set high for write, low for read

Byte1 <un-used address space>

SPI_MOSI

SPI_CLK

W/nR

A6

A5

A4

A3

A2

A1

A0

N7

N6

N5

N4

N3

N2

N1

N0

Register Address

图 19. SPI Protocol

38

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Programming (接下页)

SPI_SS_Z

t

CFCS

CSCR

CLKL

CLKH

SPI_CLK

t

CDH

CDS

SPI_MOSI

t

iH

t

CSZ

CFDO

t

iS

SPI_MISO

Hi-Z

图 20. SPI Timing Diagram

7.5.2 Interrupt

The DLPA4000 has the capability to flag for several faults in the system, such as overheating, low battery, power

good and over voltage faults. If a certain fault condition occurs one or more bits in the interrupt register (0x0C)

gets set. The setting of a bit in register 0x0C triggers an interrupt event, which pulls down the INT_Z pin.

Interrupts can be masked by setting the respective MASK bits in register 0x0D. Setting a MASK bit prevents the

INT_Z from pulling low for the particular fault condition. Some high-level faults are composed of multiple low-level

faults. The high-level faults can be read in register 0x0C, while the lower-level faults can be read in register

0x027 through 0x2A. An overview of the faults and how they are related is given in 表 6.

表 6. Interrupt Registers

HIGH-LEVEL

MID-LEVEL

LOW-LEVEL

DMD_PG_FAULT

BUCK_DMD1_PG_FAULT

BUCK_DMD1_OV_FAULT

BUCK_DMD2_PG_FAULT

BUCK_DMD2_OV_FAULT

DMD_FAULT

LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT

LDO_GP1_OV_FAULT / LDO_DMD1_OV_FAULT

LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT

LDO_GP2_OV_FAULT / LDO_DMD2_OV_FAULT

SUPPLY_FAULT

BUCK_GP2_PG_FAULT

BUCK_GP2_OV_FAULT

ILLUM_BC1_PG_FAULT

ILLUM_BC1_OV_FAULT

ILLUM_BC2_PG_FAULT

ILLUM_BC2_OV_FAULT

ILLUM_FAULT

PROJ_ON_INT

BAT_LOW_SHUT

BAT_LOW_WARN

39

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Programming (接下页)

表 6. Interrupt Registers (接下页)

HIGH-LEVEL

TS_SHUT

MID-LEVEL

LOW-LEVEL

TS_WARN

7.5.3 Fast-Shutdown in Case of Fault

The DLPA4000 has 2 shutdown-down modes: a normal shutdown initiated after pulling PROJ_ON level low and

fast power-down mode. The fast shutdown feature can be enabled/disabled via register 0x01,

a

FAST_SHUTDOWN_EN. By default the mode is enabled.

When the fast power-down feature is enabled, a fast shutdown is initiated for specific faults. This shutdown

happens autonomously from the DLPC. The DLPA4000 enters the fast-shutdown mode only for specific faults,

thus not for all the faults flagged by the DLPA4000. The faults for which the DLPA4000 goes into fast-shutdown

are listed in 表 7.

表 7. Faults that Trigger a Fast-Shutdown

HIGH-LEVEL

BAT_LOW_SHUT

TS_SHUT

LOW-LEVEL

DMD_PG_FAULT

BUCK_DMD1_PG_FAULT

BUCK_DMD1_OV_FAULT

BUCK_DMD2_PG_FAULT

DMD_FAULT

BUCK_DMD2_OV_FAULT

LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT

LDO_GP1_OV_FAULT / LDO_DMD1_OV_FAULT

LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT

LDO_GP2_OV_FAULT / LDO_DMD2_OV_FAULT

ILLUM_BC1_OV_FAULT

ILLUM_FAULT

ILLUM_BC2_OV_FAULT

7.5.4 Protected Registers

By default all regular USER registers are writable, except for the READ ONLY registers. Registers can be

protected though to prevent accidental write operations. By enabling the protecting, only USER registers 0x02

through 0x09 are writable. Protection can be enabled/ disabled via register 0x2F, PROTECT_USER_REG.

7.5.5 Writing to EEPROM

The DLPA4000 has an EEPROM mainly intended for default settings and factory trimming parameters. Registers

0x30 through 0x35 can freely be used for customer convenience though, to write a serial number or version

information for instance. Writing to EEPROM requires a couple of steps. First the EEPROM needs to be

unlocked. Unlock the EEPROM by writing 0xBAh to register 0x2E followed by writing 0xBE to the same register.

Both writes must be consecutive, that is, there must be no other read or write operation in between sending

these two bytes. Once the password has been successfully written, register 0x30h through 0x35h are unlocked

and can be write accessed using the regular SPI protocol. They remain unlocked until any byte other than

0xBABE is written to PASSWORD register 0x2E or the part is power cycled. To permanently store the written

data in EEPROM write a 1 to register 0x2F, EEPROM_PROGRAM, > 250 ms later followed by writing a 0 to the

same register.

To check if the registers are unlocked, read back the PASSWORD register 0x2E. If the data returned is 0x00h,

the registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.

40

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

7.6 Register Maps

Register Address, Default, R/W, Register name. Boldface settings are the hardwired defaults.

Table 8. Register Map

NAME

0x00, E3, R/W, Chip Identification

CHIPID

BITS

DESCRIPTION

[7:4] Chip identification number: E (hex)

[3:0] Revision number, 3 (hex)

REVID

0x01, 82, R/W, Enable Register

0: Fast shutdown disabled

[7]

FAST_SHUTDOWN_EN

1: Fast shutdown enabled

0: Color wheel circuitry disabled

1: Color wheel circuitry enabled

CW_EN

[6]

Reserved

[5]

0: General purpose buck2 disabled

1: General purpose buck2 enabled

BUCK_GP2_EN

Reserved

[4]

[3]

0: Illum_led_auto_off_en disabled

1: Illum_led_auto_off_en enabled

ILLUM_LED_AUTO_OFF_EN

[2]

0: Illum regulators disabled

[1]

ILLUM_EN

1: Illum regulators enabled

0: DMD regulators disabled

[0]

DMD_EN

1: DMD regulators enabled

0x02, 70, R/W, IREG Switch Control

[7]

Reserved, values don't care

Rlim voltage top-side (mV). Illum current limit = Rlim voltage / Rlim

0000: 17

0001: 20

0010: 23

1000: 73

1001: 88

1010: 102

1011: 117

1100: 133

1101: 154

1110: 176

1111: 197

ILLUM_ILIM

[6:3] 0011: 25

0100: 29

0101: 37

0110: 44

0111: 59

Bit2: CH3, MOSFET R transient current limit (0:disabled, 1:enabled)

[2:0] Bit1: CH2, MOSFET Q transient current limit (0:disabled, 1:enabled)

Bit0: CH1, MOSFET P transient current limit (0:disabled, 1:enabled)

ILLUM_SW_ILIM_EN

0x03, 00, R/W, SW1_IDAC(1)

[7:2] Reserved, values don't care

Led current of CH1(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x03 and 0x04).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

SW1_IDAC<9:8>

[1:0]

11 1111 1111 [150mV/Rlim]

41

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0x04, 00, R/W, SW1_IDAC(2)

Led current of CH1(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x03 and 0x04).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

SW1_IDAC<7:0>

[7:0]

11 1111 1111 [150mV/Rlim]

0x05, 00, R/W, SW2_IDAC(1)

[7:2] Reserved, value don’t care.

Led current of CH2(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x05 and 0x06).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

SW2_IDAC<9:8>

[1:0]

….

11 1111 1111 [150mV/Rlim]

0x06, 00, R/W, SW2_IDAC(2)

SW2_IDAC<7:0>

Led current of CH2(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x05 and 0x06).

00 0000 0000 [OFF]

[7:0]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

11 1111 1111 [150mV/Rlim]

0x07, 00, R/W, SW3_IDAC(1)

[7:2] Reserved, value don’t care.

Led current of CH3(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Most significant bits of 10

bits register (register 0x07 and 0x08).

00 0000 0000 [OFF]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

SW3_IDAC<9:8>

[1:0]

….

11 1111 1111 [150mV/Rlim]

0x08, 00, R/W, SW3_IDAC(2)

SW3_IDAC<7:0>

Led current of CH3(A) = ((Bit value + 1)/1024) × (150 mV / Rlim), Least significant bits of 10

bits register (register 0x07 and 0x08).

00 0000 0000 [OFF]

[7:0]

00 0011 0011 [(52/1024) × (150mV/Rlim)], Minimum code.

….

11 1111 1111 [150mV/Rlim]

0x09, 00, R/W, Switch ON/OFF Control

Only used if DIRECT MODE is enabled (see register 0x2F)

SW3

SW2

SW1

[7]

0: SW3 disabled

1: SW3 enabled

Only used if DIRECT MODE is enabled (see register 0x2F)

0: SW2 disabled

1: SW2 enabled

[6]

[5]

Only used if DIRECT MODE is enabled (see register 0x2F)

0: SW1 disabled

1: SW1 enabled

[4:0] Reserved, value don’t care.

0x0A, 00, R/W, Analog Front End (1)

0: Analog front end disabled

[7]

AFE_EN

1: Analog front end enabled

0: Calibrated 18x AFE_VGA

[6]

AFE_CAL_DIS

1: Uncalibrated 18x AFE_VGA

Gain analog front end gain

00: Off

[5:4] 01: 1x

10: 9.5x

AFE_GAIN

11: 18x

42

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

Selected analog multiplexer input

0000: ILLUM_A_FB/xx, where xx is controlled by VLED_OVP_VLED_RATIO <4:0>

(reg0x19)

0001: ILLUM_B_FB/xx, where xx is controlled by VLED_OVP_VLED_RATIO <4:0> (reg0x19)

0010: VIN/xx, where xx is controlled by ILLUM_LED_AUTO_OFF_SEL <3:0> (reg0x18)

0011: V_LABB

0100: RLIM_K1

0101: RLIM_K2

0110: CH1_SWITCH

0111: CH2_SWITCH

AFE_SEL

[3:0]

1000: CH3_SWITCH

1001: VREF_1V2

1010: VOTS (Main temperature sense block output voltage)

1011: VPROG1/12 (EEPROM block1 programming voltage divided by 12)

1100: VPROG2/12 (EEPROM block2 programming voltage divided by 12)

1101: ACMPR_IN_1

1110: ACMPR_IN_2

1111: ACMPR_IN_3

0x0B, 00, R/W, Analog Front End (2)

Samples time LABB Sensor (µs)

00: 7

TSAMPLE_SEL

[7:6] 01: 14

10: 21

11: 28

0: LABB SAMPLING disabled

1: START LABB SAMPLING (auto reset to 0 after TSAMPLE_SEL time).

SAMPLE_LABB

[5]

OVP_VIN Division factor.

00000: 3.33

00001: 4.98

00010: 5.23

01000: 6.10

01001: 6.23

01010: 6.67

01011: 7.11

01100: 7.50

01101: 7.96

01110: 8.34

01111: 8.77

10000: 9.16

10001: 9.60

10010: 9.99

10011: 10.41

10100: 10.88

10101: 11.26

10110: 11.67

10111: 12.11

11000: 12.51

11001: 12.94

11010: 13.31

11011: 13.70

11100: 14.11

11101: 14.56

11110: 15.04

11111: 15.41

VLED_OVP_VIN_RATIO

[4:0] 00011: 5.32

00100: 5.42

00101: 5.52

00110: 5.62

00111: 5.85

0x0C, 00, R, Main Status Register

0: No PG or OV failures for any of the LV Supplies

1: PG failures for a LV Supplies

SUPPLY_FAULT

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

0: ILLUM_FAULT = LOW

1: ILLUM_FAULT = HIGH

ILLUM_FAULT

PROJ_ON_INT

DMD_FAULT

0: PROJ_ON = HIGH

1: PROJ_ON = LOW

0: DMD_FAULT = LOW

1: DMD_FAULT = HIGH

0: VIN > UVLO_SEL<4:0>

1: VIN < UVLO_SEL<4:0>

BAT_LOW_SHUT

BAT_LOW_WARN

TS_SHUT

0: VIN > LOWBATT_SEL<4:0>

1: VIN < LOWBATT_SEL<4:0>

0: Chip temperature < 132.5°C and no violation in V5V0

1: Chip temperature > 156.5°C, or violation in V5V0

0: Chip temperature < 121.4°C

1: Chip temperature > 123.4°C

TS_WARN

0x0D, F5, Interrupt Mask Register

SUPPLY_FAULT_MASK

0: Not masked for SUPPLY_FAULT interrupt

1: Masked for SUPPLY_FAULT interrupt

[7]

43

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0: Not masked for ILLUM_FAULT interrupt

1: Masked for ILLUM_FAULT interrupt

ILLUM_FAULT_MASK

[6]

0: Not masked for PROJ_ON_INT interrupt

1: Masked for PROJ_ON_INT interrupt

PROJ_ON_INT_MASK

DMD_FAULT_MASK

BAT_LOW_SHUT_MASK

BAT_LOW_WARN_MASK

TS_SHUT_MASK

[5]

[4]

[3]

[2]

[1]

[0]

0: Not masked for DMD_FAULT interrupt

1: Masked for DMD_FAULT interrupt

0: Not masked for BAT_LOW_SHUT interrupt

1: Masked for BAT_LOW_SHUT interrupt

0: Not masked for BAT_LOW_WARN interrupt

1: Masked for BAT_LOW_WARN interrupt

0: Not masked for TS_SHUT interrupt

1: Masked for TS_SHUT interrupt

0: Not masked for TS_WARN interrupt

1: Masked for TS_WARN interrupt

TS_WARN_MASK

0x0E, 00, R/W, Break-Before-Make Delay

Break before make delay register (ns), step size is 111 ns

0000 0000: 0

0000 0001: 333

0000 0010: 444

BBM_DELAY

[7:0] 0000 0011: 555

….

1111 1101: 28305

1111 1110: 28416

1111 1111: 28527

0x0F, 07, R/W, Fast Shutdown Timing

VOFS/RESETZ_DEL

AY (µs)

0000: 4.000 – 4.445

0001: 8.010 – 8.900

1000: 6.230 – 7.120

1001: 12.46 – 14.24

1010: 24.89 – 28.44

1011: 49.77 – 56.88

1100: 99.5 – 113.8

1101: 199.1 – 227.6

1110: 398.3 – 455.2

0010: 16.02 – 17.80

VOFS/RESETZ_DELAY

[7:4] 0011: 32.00 – 35.55

0100: 63.99 – 71.10

0101: 128.0 – 142.2

0110: 256.0 – 284.5

1111: 1024.2 –

1138.0

0111: 512.1 – 569.0

VBIAS/VRST_DELAY

(µs)

0000: 4.000 – 4.445

0001: 8.010 – 8.900

1000: 6.230 – 7.120

1001: 12.46 – 14.24

1010: 24.89 – 28.44

1011: 49.77 – 56.88

1100: 99.5 – 113.8

1101: 199.1 – 227.6

1110: 398.3 – 455.2

0010: 16.02 – 17.80

VBIAS/VRST_DELAY

[3:0] 0011: 32.00 – 35.55

0100: 63.99 – 71.10

0101: 128.0 – 142.2

0110: 256.0 – 284.5

1111: 1024.2 –

1138.0

0111: 512.1 – 569.0

0x10, C0, R/W, VOFS State Duration

44

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

Duration of VOFS state (ms)

000: 1

001: 5

010: 10

VOFS_STATE_DURATION

[7:5] 011: 20

100: 40

101: 80

110: 160

111: 320

Low Battery level Selection

00000: 3.93

00001: 5.92

01000: 7.27

01001: 7.43

01010: 7.95

01011: 8.46

01100: 8.93

01101: 9.47

01110: 9.92

01111: 10.42

10000: 10.94

10001: 11.46

10010: 11.92

10011: 12.42

10100: 12.97

10101: 13.42

10110: 13.91

10111: 14.43

11000: 14.96

11001: 15.47

11010: 15.91

11011: 16.37

11100: 16.87

11101: 17.40

11110: 17.96

11111: 18.41

00010: 6.21

LOWBATT_SEL

[4:0] 00011: 6.32

00100: 6.43

00101: 6.55

00110: 6.67

00111: 6.93

0x11, 00, R/W, VBIAS State Duration

Duration of VBIAS state (ms)

000: bypass

001: 5

010: 10

VBIAS_STATE_DURATION

[7:5] 011: 20

100: 40

101: 80

110: 160

111: 320

Under Voltage Lockout level Selection

00000: 3.93

00001: 5.92

01000: 7.27

01001: 7.43

01010: 7.95

01011: 8.46

01100: 8.93

01101: 9.47

01110: 9.92

01111: 10.42

10000: 10.94

10001: 11.46

10010: 11.92

10011: 12.42

10100: 12.97

10101: 13.42

10110: 13.91

10111: 14.43

11000: 14.96

11001: 15.47

11010: 15.91

11011: 16.37

11100: 16.87

11101: 17.40

11110: 17.96

11111: 18.41

00010: 6.21

UVLO_SEL

[4:0] 00011: 6.32

00100: 6.43

00101: 6.55

00110: 6.67

00111: 6.93

45

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0x14, 00, R/W, GP2 Buck Converter voltage Selection

General purpose2 buck output voltage = 1+ bit value * 15.69 (stepsize = 15.69 mV)

00000000 1 V

….

BUCK_GP2_TRIM

[7:0]

11111111 5 V

0x16, 00, R/W, Buck Skip Mode

[7:5] Reserved, value don’t care.

Skip Mode:

Bit4: Buck_GP3 (0:disabled, 1:enabled)

Bit3: Buck_GP1 (0:disabled, 1:enabled)

Bit2: Buck_GP2 (0:disabled, 1:enabled)

BUCK_SKIP_ON

[4:0]

Bit1: Buck_DMD1 (0:disabled, 1:enabled)

Bit0: Buck_DMD2 (0:disabled, 1:enabled)

0x17, 02, R/W, User Configuration Selection Register

0: SPI Clock from 0 to 36 MHz

1: SPI Clock from 20 to 40 MHz

DIG_SPI_FAST_SEL

[7]

[6]

[5]

Reserved, value don’t care.

0: Current limiting disabled (External FETs mode)

1: Current limiting enabled (External FETs mode)

ILLUM_EXT_LSD_CUR_LIM_EN

Reserved

[4]

[3]

ILLUM_3A_INT_SWITCH_SEL

Illum Configuration: most significant bit is ILLUM_EXT_SWITCH_CAP<6> (Reg0x26). Other

4 bits are <3:0> of this register. “x” is don’t care.

x xx00: Off

x x110: 2 x 3 A Internal FETs

x 0010: 1 x 6 A Internal FETs

x 1010: 1 x 3 A Internal FETs

ILLUM_DUAL_OUTPUT_CNTR_SE

L

[2]

[1]

ILLUM_INT_SWITCH_SEL

0 xx0x: Off

0 x11x: 2 x 3 A Internal FETs

0 001x: 1 x 6 A Internal FETs

ILLUM_EXT_SWITCH_SEL

[0]

0 101x: 1 x 3 A Internal FETs

0 xxx1: External FETs

0x18, 00, R/W, OLV -ILLUM_LED_AUTO_OFF_SEL

Illum openloop voltage (V) = 3 + bit value * 1 (stepsize = 1 V)

0000: 3 V

0001: 4 V

...

ILLUM_OLV_SEL

[7:4]

1110: 17 V

1111: 18 V

46

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

Led Auto Off Level

(V)

Bit value

VIN division factor

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

3.93

5.92

6.21

6.32

6.43

6.55

6.67

6.93

7.27

7.95

8.93

9.92

10.94

11.92

12.97

13.91

3.33

4.98

5.23

5.32

5.42

5.52

5.62

5.85

6.10

6.67

7.50

8.34

9.16

9.99

10.88

11.67

ILLUM_LED_AUTO_OFF_SEL

[3:0]

0x19, 1F, R/W, Illumination Buck Converter Overvoltage Fault Level

Reserved

[7:5]

Bit value / OVP VLED Division factor

00000: 3.33

00001: 4.98

00010: 5.23

01000: 6.10

10000: 9.16

10001: 9.60

10010: 9.99

10011: 10.41

10100: 10.88

10101: 11.26

10110: 11.67

10111: 12.11

11000: 12.51

01001: 6.23

01010: 6.67

01011: 7.11

01100: 7.50

01101: 7.96

01110: 8.34

01111: 8.77

11001: 12.94

11010: 13.31

11011: 13.70

11100: 14.11

11101: 14.56

11110: 15.04

11111: 15.41

VLED_OVP_VLED_RATIO

[4:0] 00011: 5.32

00100: 5.42

00101: 5.52

00110: 5.62

00111: 5.85

0x1B, 00, R/W, Color Wheel PWM Voltage(1)

Least significant 8 bits of 16 bits register (register 0x1B and 0x1C) Average color wheel PWM

voltage (V), step size = 76.294 µV

CW_PWM <7:0>

[7:0] 0x0000 0 V

....

0xFFFF 5 V

47

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0x1C, 00, R/W, Color Wheel PWM Voltage(2)

Most significant 8 bits of 16 bits register (register 0x1B and 0x1C) Average color wheel PWM

voltage (V), step size = 76.294 µV

CW_PWM <15:8>

[7:0] 0x0000 0 V

....

0xFFFF 5 V

0x25, 00, R/W, ILLUM BUCK CONVERTER BANDWIDTH SELECTION

reserved

[7:4]

ILED CONTROL LOOP BANDWIDTH INCREASE (dB)

00: 0

ILLUM_BW_BC1

[3,2] 01: 1.9

10: 4.7

11: 9.3

ILED CONTROL LOOP BANDWIDTH INCREASE (dB)

00: 0

[1,0] 01: 1.9

10: 4.7

ILLUM_BW_BC2

11: 9.3

0x26, DF, R, Capability register

0: LED_AUTO_TURN_OFF_CAP disabled

1: LED_AUTO_TURN_OFF_CAP enabled

LED_AUTO_TURN_OFF_CAP

[7]

[6]

0: No external switch control capability

1: External switch control capability included

ILLUM_EXT_SWITCH_CAP

0: No color wheel capability

1: Color wheel capability included

CW_CAP

[5]

[4]

[3]

Reserved

0: LDO1 not used for DMD, voltage set by user register

1: LDO1 used for DMD, voltage set by EEPROM

DMD_LDO1_USE

0: LDO2 not used for DMD, voltage set by user register

1: LDO2 used for DMD, voltage set by EEPROM

DMD_LDO2 _USE

DMD_BUCK1 _USE

DMD_BUCK2 _USE

[2]

[1]

[0]

0: DMD Buck1 disabled

1: DMD Buck1 used

0: DMD Buck2 disabled

1: DMD Buck2 used

0x27, 00, R, Detailed status register1 (Power good failures for general purpose and illumination blocks)

0: No fault

BUCK_GP3_PG_FAULT

[7]

1: Focus motor buck power good failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP1_PG_FAULT

[6]

1: General purpose buck1 power good failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP2_PG_FAULT

Reserved

[5]

[4]

[3]

1: General purpose buck2 power good failure. Does not initiate a fast shutdown.

0: No fault

ILLUM_BC1_PG_FAULT

1: Illum buck converter1 power good failure. Does not initiate a fast shutdown.

0: No fault

ILLUM_BC2_PG_FAULT

[2]

1: Illum buck converter2 power good failure. Does not initiate a fast shutdown.

[1]

[0]

Reserved, value always 0

0x28, 00, R, Detailed status register2 (Overvoltage failures for general purpose and illum blocks)

0: No fault

BUCK_GP3_OV_FAULT

[7]

1: Focus motor buck overvoltage failure. Does not initiate a fast shutdown.

48

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0: No fault

BUCK_GP1_OV_FAULT

[6]

1: General purpose buck1 overvoltage failure. Does not initiate a fast shutdown.

0: No fault

BUCK_GP2_OV_FAULT

[5]

[4]

[3]

1: General purpose buck2 overvoltage failure. Does not initiate a fast shutdown.

Reserved, value always 0

0: No fault

ILLUM_BC1_OV_FAULT

ILLUM_BC2_OV_FAULT

1: Illum buck converter1 overvoltage failure. Does not initiate a fast shutdown.

0: No fault

[2]

1: Illum buck converter2 overvoltage failure. Does not initiate a fast shutdown.

[1]

[0]

Reserved, value always 0

0x29, 00, R, Detailed status register3 (Power good failure for DMD related blocks)

[7]

Reserved, value always 0

0: No fault

DMD_PG_FAULT

[6]

1: VBIAS, VOFS and/or VRST power good failure. Initiates a fast shutdown.

0: No fault

BUCK_DMD1_PG_FAULT

BUCK_DMD2_PG_FAULT

[5]

[4]

1: Buck1 (used to create DMD voltages) power good failure. Initiates a fast shutdown.

0: No fault

1: Buck2 (used to create DMD voltages) power good failure. Initiates a fast shutdown.

[3]

[2]

Reserved, value always 0

0: No fault

LDO_GP1_PG_FAULT /

LDO_DMD1_PG_FAULT

[1]

[0]

1: LDO1 (used as general purpose or DMD specific LDO) power good failure. Initiates a fast

shutdown.

0: No fault

LDO_GP2_PG_FAULT /

LDO_DMD2_PG_FAULT

1: LDO2 (used as general purpose or DMD specific LDO) power good failure. Initiates a fast

shutdown.

49

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Register Maps (continued)

Table 8. Register Map (continued)

NAME

BITS

DESCRIPTION

0x2A, 00, R, Detailed status register4 (Overvoltage failures for DMD related blocks and Color Wheel)

[7]

[6]

Reserved, value always 0

0: No fault

BUCK_DMD1_OV_FAULT

BUCK_DMD2_OV_FAULT

[5]

[4]

1: Buck1 (used to create DMD voltage) overvoltage failure

0: No fault

1: Buck2 (used to create DMD voltage) overvoltage failure

[3]

[2]

Reserved, value always 0

LDO_GP1_OV_FAULT /

LDO_DMD1_OV_FAULT

0: No fault

[1]

[0]

1: LDO1 (used as general purpose or DMD specific LDO) overvoltage failure

LDO_GP2_OV_FAULT /

LDO_DMD2_OV_FAULT

0: No fault

1: LDO2 (used as general purpose or DMD specific LDO) overvoltage failure

0x2B, 01, R, Chip ID extension

CHIP_ID_EXTENTION

[7:0] ID extension to distinguish between various configuration options.

0x2C, 00, R/W, ILLUM_LED_AUTO_TURN_OFF_DELAY SETTINGS

Reserved

[7:4] TBD

ILLUM_LED_AUTO_TURN_OFF_DELAY (µsec)

0000: 4.000-4.445

0100: 63.99-71.10

0101: 128.0-142.2

0110: 256.0-284.5

0111: 512.1-569.0

1000: 6.230-7.120

1001: 12.46-14.24

1010: 24.89-28.44

1011: 49.77-56.88

1100: 99.5-113.8

ILLUM_LED_AUTO_TURN_OFF_D

ELAY

[3:0] 0001: 8.010-8.900

0010: 16.02-17.80

1101: 199.1-227.6

1110: 398.3-455.2

1111: 1024.2-1138.0

0011: 32.00-35.55

0x2E, 00, R/W, User Password

USER PASSWORD (0xBABE)

[7:0] Write Consecutively 0xBA and 0xBE to unlock.

0x2F, 00, R/W, User Protection Register

[7:3] Reserved, value don’t care.

0: EEPROM programming disabled

1: Shadow register values programmed to EEPROM

EEPROM_PROGRAM

DIRECT_MODE

[2]

[1]

0: Direct mode disabled

1: Direct mode enabled (register 0x09 to control switched)

0: ALL regular USER registers are WRITABLE, except for READ ONLY registers

1: ONLY USER registers 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, and 0x09 are

WRITABLE

PROTECT_USER_REG

[0]

0x30, 00, R/W, User EEPROM

Register

USER_REGISTER1

[7:0] User EEPROM Register1

0x31, 00, R/W, User EEPROM Register

USER_REGISTER2

[7:0] User EEPROM Register2

0x32, 00, R/W, User EEPROM Register

USER_REGISTER3

[7:0] User EEPROM Register3

0x33, 00, R/W, User EEPROM Register

USER_REGISTER4

[7:0] User EEPROM Register4

0x34, 00, R/W, User EEPROM Register

USER_REGISTER5

[7:0] User EEPROM Register5

0x35, 00, R/W, User EEPROM Register

USER_REGISTER6

[7:0] User EEPROM Register6

50

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

In display applications, using the DLPA4000 provides all needed analog functions including all analog power

supplies and the RGB LED driver (up to 32A per LED) with high-side Pump functionality to provide a robust and

efficient display solution. Each DLP application is derived primarily from the optical architecture of the system

and the format of the data coming into the DLPC4422 controller.

8.2 Typical Application

A common application combines the DLPA4000 with the 0.65 WXGA DMD (DLP650LE) or a 0.65 1080P DMD

(DLP650NE) and a DLPC4422 controller to create a high resolution, LED projector. The DLPC4422 in the

projector typically receives images from a PC or video player using HDMI or VGA analog as shown in 图 21.

Card readers and Wi-Fi can receive images when the application includes the appropriate peripheral

components. The DLPA4000 sequences the power-supply and controls the RGB LED currents in this application.

12- V Regulator

16 V to 20 V DC

HDMI

Power Supplies

and Monitoring

Illumination

Control

Shunt Diodes

PROJ_ON

VGA

Front

End

SPI

PWR_GOOD

PWR_ON

Digital Control Block

External

Power

FETs

High-Side Pump LED

Keypad

I2C

DLPA4000

DMD and

DATA

1.1 V

1.8 V

DMD

Reset

Controller Bucks

Flash

DLPC4422

Voltage

Generator

3.3 V

2.5 V

LDOs

DMD Reset

Voltages and Control

GP Buck

Converter

Measurement

System

Sensors

3.3 V

DLP650NE

or

DLPA200

Control

DLP650LE

DMD Data and Control

图 21. Typical Setup Using DLPA4000

8.2.1 Design Requirements

A high resolution LED projector can be created by using a DLP chip set comprised of a 0.65 WXGA DMD

(DLP650LE) or a 0.65 1080p DMD (DLP650NE), a DLPC4422 controller, and the DLPA4000 PMIC/LED Driver.

The DLPC4422 does the digital image processing, the DLPA4000 provides the needed analog functions for the

projector, and the DMD is the display device for producing the projected image. In addition to the three DLP

chips in the chip set, other components is required. At a minimum a Flash part is needed to store the software

and firmware to control the DLPC4422. The illumination light that is applied to the DMD is typically from red,

green, and blue LEDs. These are often contained in three separate packages, but sometimes more than one

color of LED die may be in the same package to reduce the overall size of the projector. Power MOSFETs are

needed external to the DLPA4000 so that high LED currents can be supported. For connecting the DLPC4422 to

the front end chip for receiving images, the parallel interface is typically used. Connect the front end chip to the

parallel interface, I²C to input commands to the DLPC4422.

51

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Typical Application (接下页)

The DLPA4000 has three built-in buck switching regulators to serve as projector system power supplies. Two of

the regulators are fixed to 1.1 V and 1.8 V for powering the DLP chip set. The remaining buck regulator is

available for general purpose use and its voltages are programmable. The regulators can be used to a drive

variable-speed fans or to power other projector chips such as the front-end chip. The only power supply needed

at the DLPA4000 input is SYSPWR from an external DC power supply or internal battery. The entire projector

can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is high, the projector turns

on and begins displaying images. When PROJ_ON is set low, the projector turns off and draws just microamps

of current on SYSPWR.

8.2.2 Detailed Design Procedure

To connect the 0.65 WXGA DMD (DLP650LE) or 0.65 1080p DMD (DLP650NE), DLPC4422 controller and

DLPA4000, see the reference design schematic. When a circuit board layout is created from this schematic a

very small circuit board is possible. An example small board layout is included in the reference design data base.

Comply with the layout guidelines to achieve reliable projector operation. The optical engine that has the LED

packages and the DMD mounted to it is typically supplied by an optical OEM who specializes in designing optics

for DLP projectors.

The component selection of the buck converter is mainly determined by the output voltage. 表 9 shows the

recommended value for inductor L_OUTand capacitor C_OUTfor a given output voltage.

表 9. Recommended Buck Converter L_OUTand C_OUT

V_OUT(V)

L_OUT(µH)

TYP

C_OUT(µF)

MIN

1.5

2.2

3.3

MAX

4.7

MIN

22

MAX

68

1 - 1.5

1.5 - 3.3

3.3 - 5

2.2

3.3

4.7

22

68

4.7

22

68

Use 公式 11 to calculate the inductor peak-to-peak ripple current. Use 公式 12 the peak current. Use 公式 13to

calculate teh RMS current. The inductor saturation current rating must be greater than the calculated peak

current. The RMS or heating current rating of the inductor must be greater than the calculated RMS current.

V_OUT

× kV

_;F V_OUTo

:

IN max

V

:

;

IN max

I_L

=

OUT

RIPPLE

L_OUT× f_SW

P FP

where

•

the switching frequency of the buck converter is approximately 600 kHz

(11)

(12)

I_L

FP

OUT

RIPPLE

P

I_L

= I_L

+

OUT

PEAK

2

I_L

=

kI_L_OUTo +

× @I_L

OUT

_FPA²

1

2

¨

OUT

RMS

RIPPLE

P

12

(13)

The capacitor value and ESR determines the level of output voltage ripple. Use ceramic or other low ESR

capacitors. Recommended values range from 22 to 68 μF. Use 公式 14 to determine the required RMS current

rating for the output capacitor.

:

;

V_OUT× V F V_OUT

IN

I_C

=

;

:

OUT rms

12 × V × L

× f_SW

¾

IN

OUT

(14)

One other component for the buck converter configuration is needed. Use a charge pump capacitor between

PWRx_SWITCH and PWRx_BOOST to drive the high-side MOSFET. The recommended value for the charge

pump capacitor is 100 nF.

52

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Because the switching edges of the buck converter are relatively fast, voltage overshoot and ringing can become

a problem. To overcome this problem a snubber network is used. The snubber circuit consists of a resistor and

capacitor that are connected in series from the switch node to ground. The snubber circuit is used to damp the

parasitic inductances and capacitances during the switching transitions. This circuit reduces the ringing voltage

and also reduces the number of ringing cycles. The snubber network is formed by RSNx and CSNx. More

information on controlling switch-node ringing in synchronous buck converters and configuring the snubber can

be found in Analog Applications Journal.

8.2.2.1 Component Selection for General-Purpose Buck Converters

The theory of operation of a buck converter is explained in application note, Understanding Buck Power Stages

in Switchmode Power Supplies, SLVA057. This section is limited to the component selection. For proper

operation, selection of the external components is very important, especially the inductor L_OUTand the output

capacitor C_OUT. Choose inductor and capacitors with low equivalent series resistance (ESR) specifications to

ensure the best efficiency and ripple performance.

53

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

8.3 System Example With DLPA4000 Internal Block Diagram

SUP_2P5V

SUP_5P0V

LDO_V2V5

91

92

2.2 µF/25 V

N/C

1

LDO_V5V

4.7 µF/25 V

2.2 µF/25 V

Thermal Pad

42

VIN

ILLUM_VIN

8

7

VIN

LDO

ILLUM

ILLUM_5P5V

VINA

10 µF/10 V

VIN

85

VREF

ꢀ6ꢀꢎ\ꢏ]

ILLUM_A_FB

0.47 µF/50 V

3x10 µF/50 V

ꢋꢌꢍZꢅꢆꢊZꢇꢐꢃꢍ

29

30

28

2.2 µF/25 V

ꢀ6ꢁꢁ\ꢂ7ꢀ]

ILLUM_A_VIN

ILLUM_A_BOOST

ꢃꢄꢅꢆZꢇꢈꢅ

ꢀ6ꢀꢎ\ꢑ]

ꢋꢌꢍZꢅꢆꢊZꢊꢌꢒꢓ

0.47 µF/50 V

3

ꢀ6ꢁꢀ\ꢂ7ꢀ]ꢉ

0.1 µF

25 V

ꢅꢆꢊꢋꢌꢍꢍZꢇꢈꢅ

3x10 µF/50 V

3.9 Ω

L

ILLUM_HSIDE_DRIVE

ILLUM_A_SW

AGND

26

31

86

2700 pF

50 V

ILLUMINATION

2 Ω

1000 pF

50 V

DRIVER

A

M

AFE_GAIN [1:0]

AFE_SEL[3:0]

ILLUM_LSIDE_DRIVE

ILLUM_A_PGND

27

32

2200 pF

50 V

CSD87350Q5D

2x

2xB240A-13-F

2xB0540WS-7

AFE

10

k

Ω

10 kΩ

ACMPR_REF

ACMPR_OUT

From host

To host

82

81

ILLUM_A_COMP1

38

39

15p

MUX

ILLUM_A_COMP2

3300 pF

50 V

1 µH

32 A

6x22 µF

25 V

0.1 uF/25

V

1.3 Ω

0.4 W

ILLUM_B_FB

ILLUM_B_VIN

35

34

VIN

10Ω

ILLUM_B_BOOST

33

ACMPR_IN_LABB

V_LABB

S/H

80

55

10 µF

50 V

ACMPR_LABB_SAMPLE

N

O

10Ω

ILLUM_B_SW

36

ACMPR_IN_1

ACMPR_IN_2

ILLUMINATION

DRIVER

B

From light sensor

77

78

79

From temperature sensor

OSRAM P2 LEDs

V_LED

ACMPR_IN_3

ILLUM_B_PGND

ILLUM_B_COMP1

ILLUM_B_COMP2

37

40

41

10 µF/10 V

DRST_5P5V

DRST_VIN

3

5

LDO

DMD

VIN

4x ESDA18-1k

CH1_GATE_CTRL

CH2_GATE_CTRL

19

20

21

10 µF/50 V

4x CSD17556Q5B

CH3_GATE_CTRL

A

B

0.47 µF/50 V

MBR0540T1

0.1 µF/25 V

1 µF/35 V

DRST_HS_IND

DRST_LS_IND

6

2

GPIO

(From

Controller)

CH1_SWITCH

CH2_SWITCH

9/10

17/

18

10 µF/1.25 A

DMD_VRESET

P

D

CH3_SWITCH

24/

25

Q

VRST

100

C

RGB

STROBE

DECODER

0.1 µF/25 V

R

DMD

HIGH VOLTAGE

REGULATOR

RLIM_1

RLIM_2

11/

16

DRST_PGND

DMD_VBIAS

470 nF/50 V

4

4.7 nF

50 V

VBIAS

VOFS

99

98

22/

23

DMD_VOFFSET

RLIM_K_1

15

14

100 Ω

RLIM_BOT_K_1

1 µF/35 V

G

RLIM_K_2

4m Ω

5 W

0.1 µF/25 V

13

12

F

RLIM_BOT_K_2

98

E

PWR1_BOOST

PWR1_VIN

PWR5_BOOST

PWR5_VIN

69

67

68

97

96

95

0.1 µF

25 V

VIN

0.47 µF 470 pF

0.47 µF

50 V

General

Purpose

H

I

S

T

2x10 µF

50 V

2x10 µF

50 V

PWR1_SWITCH

10 Ω

PWR5_SWITCH

DMD/DLPC

PWR1

BUCK1

3.3 µH

3 A

PWR1_PGND

PWR1_FB

PWR5_PGND

PWR5_FB

70

71

93

94

V_DMD-DLPC-1

2x22 µF

25 V

Low_ESR

PWR2_BOOST

PWR2_VIN

PWR6_BOOST

PWR6_VIN

76

75

74

65

64

63

0.1 µF

25 V

0.1 µF

25 V

VIN

2x10 µF

50 V

0.47 µF

50 V

10 Ω

470 pF

50 V

0.47 µF

50 V

470 pF

50 V

General

Purpose

J

U

V

2x22 µF

50 V

10 Ω

PWR2_SWITCH

DMD/DLPC

PWR2

PWR6_SWITCH

K

BUCK2

3.3 µH

3 A

3.3 µH

3 A

PWR2_PGND

PWR2_FB

PWR6_PGND

PWR6_FB

73

72

62

66

1-5V / 8bit

V_DMD-DLPC-2

2x22 µF

25 V

Low_ESR

PWR4_VIN

90

3.3 V-20 V

2.2 µF/25 V

50

52

53

LDO_1

DMD/DLPC/AUX

PWR7_VIN

VIN

PWR4_OUT

0.47 µF

50 V

89

88

General

Purpose

W

X

2x10 µF

50 V

10 µF/10 V

PWR3_VIN

2.2 µF/25 V

3.3 V-20 V

BUCK3

PWR7_PGND

54

51

LDO_2

DMD/DLPC/AUX

PWR3_OUT

87

10 µF/10 V

2.2 µF/25 V

VIN

PWR_VIN

83

84

CW_SPEED_PWM_OUT

CLK_OUT

44

43

LDO

BUCKS

Color Wheel

PWM

PWR_5P5V

10 µF/10 V

PROJ_ON

CH_SEL_0

CH_SEL_1

RESET_Z

From host

56

60

61

57

To system

1 µF/35 V

0.1 µF/25 V

SPI_VIN

DIGITAL

CORE

45

48

46

47

49

From host

SPI_SS_Z

SPI_CLK

SPI_MISO

INT_Z

DGND

To DLPC

(optional)

58

59

SPI

Y

From host

To host

30.1

Ω

SPI_MOSI

From host

图 22. Typical Application: V_IN= 19.5 V, I_OUT= 32 A, LED, External MOSFETs

54

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

9 Power Supply Recommendations

The DLPA4000 operates over a range of 16 V to 20 V input voltage supply or battery. The power supply design

may require additional bulk capacitance. Additional bulk capacitance helps avoid insufficient supply current due

to line drop, ringing due to trace inductance at the VIN terminals, or supply peak current limitations, When the

interaction of the ceramic input capacitors causes ringing, an electrolytic or tantalum type capacitor may be

needed for damping.

Evaluate the bulk capacitance required so that the input voltage remains within the specified range long enough

for a proper fast shutdown to occur for the VOFFSET, VRESET, and VBIAS supplies. The shutdown period

begins when the input voltage goes below the programmable UVLO threshold. Shutdown occurs when the

external power suddenly discontinues.

9.1 Power-Up and Power-Down Timing

The power-up and power-down sequence ensures a correct operation of the DLPA4000 and to prevent damage

to the DMD. The DLPA4000 controls the correct sequencing of the DMD_VRESET, DMD_VBIAS, and

DMD_VOFFSET to ensure a reliable operation of the DMD.

The general startup sequence of the supplies is described earlier in Supply and Monitoring. The power-up

sequence of the high voltage DMD lines is especially important in order not to damage the DMD. A too large

delta voltage between DMD_VBIAS and DMD_VOFFSET could cause the damage and should therefore be

prevented.

After the device pulls PROJ_ON high, the DMD buck converters and LDOs energize (PWR1, PWR2, PWR3,

PWR4) the DMD high voltage lines (HV) sequentially enable. At the end of this sequence, the DLPA4000

becomes fully powered and ready for projection.

1. DMD_VOFFSET

2. delay

3. VOFS_STATE_DURATION (register 0x10) DMD_VBIAS

4. delay

5. VBIAS_STATE_DURATION (register 0x11) DMD_VRESET

For shutdown there are two sequences, normal shutdown (图 23) and a fault fast shutdown used in case a fault

occurs (图 24).

This is the shutdown sequence during normal mode operation

1. 25-ms delay

2. PROJ_ON pin goes low

3. DMD_VBIAS and DMD_VRESET stop regulating

4. 10 ms delay

5. DMD_OFFSET stops regulating

6. RESET_Z goes low

7. 1 ms delay

8. all three voltages discharge

9. all other supplies de-energized

10. INT_Z remains high

INT_Z remains high during the shutdown sequence because no fault occurred. During the power-down sequence

the device makes sure the HV levels do not violate the DMD specifications on these three lines. For this it is

important to select the capacitors such that C_VOFFSETis equal to C_VRESETand C_VBIASis ≤ C_VOFFSET, C_VBIAS

.

The fast shutdown mode (图 24) sequence starts in case a fault occurs (INT_Z is pulled low), for instance due to

overheating.

55

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Power-Up and Power-Down Timing (接下页)

Use register 0x01 to enable and disable fast shutdown mode (FAST_SHUTDOWN_EN). Fast shutdown mode is

the default mode. After the fault occurs, regulation of DMD_VBIAS and DMD_VRESET is stopped. The time

(delay) between fault and stop of regulation can be controlled via register 0x0F (VBIAS/VRST_DELAY). The

delay can be selected between 4 µs and approximately 1.1 ms, where the default is approximately 540 µs. A

defined delay-time after the regulation stopped, all three high voltages lines are discharged and RESET_Z is

pulled low. The delay can be controlled via register 0x0F (VOFS/VRESETZ_DELAY). Delay can be selected

between 4 µs and approximately1.1ms. The default is ~4 µs. Finally the internal DMD_EN signal is pulled low.

The DLPA4000 device remains in standby state until the fault resolves. The device restarts then the fault

resolves. The restart sequence begins when the device energizes the PWR_3 pin and follows the same steps as

the regular startup sequence (see 图 24). select capacitors so that C_VOFFSETis equal to C_VRESETand C_VBIASis ≤

C_VOFFSET, C_VBIAS. This selection criteria ensures proper discharge timing and discharge levels.

56

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Power-Up and Power-Down Timing (接下页)

VIN

Initiated by DLPC

PROJ_ON

SUP_5P0V

SUP_2P5V

D_CORE_EN

(INTERNAL_SINGAL)

PWR_5P5V

DRST_5P5V

ILLUM_5P5V

PWR_1

PWR_2

PWR_3

PWR_4

PWR_6

INT_Z

RESET_Z

Initiated by DLPC

via SPI

DMD_EN

(INTERNAL_SIGNAL)

STOP

REGULATING

DMD_VOFFSET

STOP

REGULATING

DMD_VBIAS

DMD_VRESET

STOP

REGULATING

Note: Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under

SPI control.

图 23. Power Sequence Normal Shutdown Mode

57

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Power-Up and Power-Down Timing (接下页)

VIN

Initiated by DLPC

PROJ_ON

SUP_5P0V

SUP_2P5V

D_CORE_EN

(INTERNAL_SINGAL)

PWR_5P5V

DRST_5P5V

ILLUM_5P5V

PWR_1

Supplies are not turned off,

Unless PROJ_ON is set low

PWR_2

PWR_3

PWR_4

PWR_6

Initiated by

FAULT

INT_Z

RESET_Z

Initiated by

DLPC via SPI

DMD_EN

(INTERNAL_SIGNAL)

DMD_VOFFSET

DMD_VBIAS

DMD_VRESET

Note: Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under

SPI control.

图 24. Power Sequence Fault Fast Shutdown Mode

58

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

10 Layout

10.1 Layout Guidelines

Make sure to consider high peak currents and high switching frequencies when designing the layout to avoid

instability and EMI problems.

•

Use wide and short traces for high-current paths and for high-current return power ground paths.

Place, the input capacitor, output capacitor, and the inductor of the DMD HV regulator as close as possible to

the DLPA4000 device.

•

Separate the ground traces and connect them together at a central point undermeath the device package.

This design minimizes ground noise coupling between different buck converters

The recommended value for the DMD capacitors is 1 µF for VRST and VOFS, 470 nF for VBIAS. The

inductor value is 10 µH.

The currents of the buck converters are highest near pins VIN, SWITCH and PGND (). The voltage at the pins

VIN, PGND and FB are DC voltages. the SWITCH pin voltage a value betweent eh value of the VIN viltage and

teh PGND voltage. The red line in 图 25 indicates the current flow when the MOSFET between pin 52 and pin 53

is closed. The blue line indicates the current flow when the MOSFET between pin 53 and pin 54 is closed.

The buck converter paths carry the highest currents. Make sure the buck converter paths are as short as

possible.

For the LDO DMD, it is recommended to use a 1-µF, 16-V capacitor on the input and a 10-µF, 6.3-V capacitor on

the output of the LDO assuming a battery voltage of 12 V.

For LDO bucks, it is recommended to use a 1-µF, 16-V capacitor on the input and a 1-µF, 6.3-V capacitor on the

output of the LDO.

50

PWR7_BOOST

100n

6.3V

52 PWR7_VIN

SYSPWR

General

Purpose

2x10µ

16V

R_SN7

C_SN7

53 PWR7_SWITCH

BUCK3

3.3µH

3A

PWR7_FB

51

54

Regulated Output

Voltage

2x22µ

6.3V

Low_ESR

PWR7_PGND

图 25. High AC Current Paths in a Buck Converter

The trace to the VIN pin in this design has high AC currents that prevents voltage drop across the trace. Make

sure the trace to the VIN pin has low resistance.

Place the decoupling capacitors as close to the VIN pin as possible.

The SWITCH pin alternates connection to the VIN pin or GND. The SWITCH pin voltage waveform is square with

an amplitude equal to VIN. The SWITCH pin voltage containing high frequencies. This situation causes EMI

problems unless properly mitigated. Reduce EMI by creating a snubber network (R_SN7and C_SN7) Place the

resistor and capacitor at the SWITCH pin to prevent or suppress unwanted high-frequency ringing during

switching.

59

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Layout Guidelines (接下页)

The PGND pin sinks high current. Connect the PGND pin to a star ground point so that it does not interfere with

other ground connections.

The FB pin is the sense connection for the regulated DC output voltage. No current flows through the FB pin.

The device compares the voltage on the FB pin with the internal reference voltage. This comparison controls the

loop. Make the FB connection at the load so that the I-R drop does not affect the sensed voltage.

10.1.1 LED Driver

The layout of the LED driver area of the PCB affects the performance of the DLPA4000 as an LED driver.

Incorrect layout can cause high-current voltage ringing. High-current rining damages electronics and causes

visible effects on the illumination.

10.1.1.1 PowerBlock Gate Control Isolation

|--------------------- Keep this trace < 5nH ----------------------|

Minimize

ILLUM_HS_DRV

Design trace 15nH to ꢀ

D20 and R45

near DLPA4000

D23

D25

Trace Length

TGR1

TGR2

R49

ILLUM_A_BOOST

TG1

TG2

R70

R71

R43 near DLPA4000

GND

C183

C184

~5nH dedicated trace

ꢀꢁꢂꢃꢄꢅꢆ

ꢇJꢈꢉQ]ꢈꢄ:7V`

C170

ILLUM_A_SW

~5nH dedicated trace

R42 near DLPA4000

R69

R68

PGND1 PGND2

BG1

BG2

D24

D29

C185

C186

ILLUM_LS_DRV

D21 and R46

near DLPA4000

|--------------------- Keep this trace < 5nH ----------------------|

Design trace 15nH to ꢀ

图 26. DLPA4000 Illumination Bottom Layout

The two power blocks Synchronous Buck NexFET™ Power Block MOSFET Pair in the reference design

connects Q11 and Q12 in parallel. This design feature reduces current loss and power loss in the application.

Place the two power blocks close to each other. Implement the gate control isolation topologies in the reference

design to prevent feedback and ringing on the gate control line from the DLPA4000.

Place a single-shared ILLUM_HS_DRV trace from the PMIC to the two separate gate filtering and isolation

component sets (D23, R70, and C183) and (D25, R71, and C184). Place each set close to the the power block

high-side MOSFET pins. Minimize the ILLUM_HS_DRV route length. Minimize coupling to other routes.

Terminate the ILLUM_HS_DRV from the PMIC in a T-junction. Make sure this termination is very close to the

power blocks. Minimize the route beyond the T-junction that goes between the two filter and isolation component

sets. Make sure the routing inductance is 5 nH or less on the trace between the filter and isolation sets.

60

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Layout Guidelines (接下页)

Place D23, R70, and C183 very close together and underneath Q11 with the goal of minimizing the net

connecting D23, R70, C183, and the high-side MOSFET pin (Q11 Pin 3). The high-side MOSFET return pin (Q11

Pin 4) requires an independent 5-nH trace before merging with the Top Gate Return of Q12. Make sure that the

merged Top Gate Return trace has an inductance of 15 nH on the return to the R-C filter (C170 and R49) near

the DLPA4000 device. The isolation components near the Top Gate pin of Q12 (D25, R71, and C184) must

follow the same requirements as those isolating Q11 (D23, R70, and C183). The inductance of the high-side

illumination driver net connecting D25 to D23 must maintain a value below 5 nH. The high-side MOSFET return

pin (Q12 pin 4) requires a 5-nH independent trace before merging with the Q11 Top Gate Return path back to

the RC filter.

Route a single-shared ILLUM_LS_DRV trace from the PMIC to the two separate gate filtering and isolation

component sets (D29, R68, and C185) and (D24, R69, and C186). Place each component set close to the power

block low-side MOSSFET pins. Minimize the ILLUM_LS_DRV route length. Minimize coupling the

ILLUM_LS_DRV route to other routes. Terminate the ILLUM_LS_DRV from the PMIC in a T-junction. Make sure

this termination is very close to the power blocks. Minimize the route beyond the T-junction that goes between

the two filter and isolation component sets. Make sure the routing inductance is 5 nH or less on the trace

between the filter and isolation sets)

Make sure the inductance of the trace from D21 and R46 to D29 is as close to 15 nH as possible. Place D29,

C185, and R68 directly underneath Q11 to minimize trace impedance. Similarly, place D24, C186, and R69

underneath and as close as possible to Q12. Make sure the inductance of the trace connecting D24 to D29 is

less than 15 nH.

10.1.1.2 VIN to PowerBlocks

Create a dedicated VIN path (in addition to an internal VIN plane) directly to the power blocks (Q11 and Q12) on

the top layer of the board. Use 2 oz. (7 mm or larger) copper in the layout for VIN, the dedicated VIN return

(bottom layer), and all other high-power nets. Tie the two planes at the input power connector only. This

connection significantly reduces the 32-A switching noise from the power blocks on the internal VIN plane for the

rest of the DLPA4000 integrated switching power supplies.

61

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Layout Guidelines (接下页)

图 27. Dedicated VIN Path

10.1.1.3 Return Current from LEDs and RSense

The R_SENSEresistor (R72) senses the LED current. Connect the RLIM_K_1 and RLIM_K_2 lines close to the top

side of the measurement resistor to accurately measure the LED current. Connect the RLIM_BOT_K_1 and

RLIM_BOT_K_2 lines close to the bottom side of the measurement resistor to accurately measure the LED

current.

The switched LED current flows through the R_LIMresistor and the R_SENSEresistor. Design a low-ohmic ground

connection from the R_SENSEresistor that retuns to the input voltage connector. Make sure the PGND return has a

dedicated plane on the top layer that returns to the connector. However, the PGND top layer must have vias

placed from inside the top layer to the internal PGND plane. Make sure the PGND vias underneath the power

block are compliant with the power block layout thermal guidelines. See CSD87350Q5D data sheet for

guidelines..

Make sure the designer considers the entire return path for current from the LED connector through the R_LIM

resistor plane and the R_SENSEresistor (R72) during layout. Any obstacles between the LED connectors and the

PGND on the input power connector can cause power reduction. Similar obstacles can cause possible image

artifacts due to slow LED turn-on times. See the reference design for a suggested placement and plane sizes.

62

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Layout Guidelines (接下页)

图 28. Current Return Path

10.1.1.4 RC Snubber

Proper operation requires snubber networks. The switching frequency can vary from several hundreds of kHz to

frequencies in the MHz range. To switch currents from zero to several amperes requires only nanoseconds,

equivalent to even much higher frequencies. EMI can occur when ringing occurs on the edges. This ringing can

have higher amplitude and frequency than the switching voltage. All DLP4000 buck converters require a snubber

network to prevent ringing. The snubber network comprises a resistor and a capacitor in series.

Place an R-C snubber network (C32 and R56) to reduce ringing on the switching node. Place the capacitor on

top of a large plane for the switching node directly next to the PGND plane. This resistor placement eliminates

the gap between the switching node and the PGND plane used by the PowerBlocks.

63

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Layout Guidelines (接下页)

图 29. RC Snubber Layout

10.1.1.5 Capacitor Choice

Be aware of the voltage coefficient of the decoupling capacitors. Physically undersized ceramic capacitors (with

respect to the capacitance value to physical size ratio) experiences a large reduction in capacitance. Depending

on the VIN voltage chosen and the voltage rating of the capacitors, physically undersized capacitors can

experience up to a 90% reduction in capacitance, leading to insufficient decoupling.

Choose decoupling capacitors (C17 and C119) with a value of 0.1 µF and a size of 0402. Place the decoupling

capacitors as close as possible to the power block VIN pins. Even an increased distance as small as 1 mm in

compared to the reference design can cause a large increase in voltage ringing amplitude. Because the parasitic

inductance of the route combined with the effective inductance of the capacitor affects the switching node, select

capacitors with a higher SRF rating. Place the VIN decoupling capacitors on the top layer very close to the power

blocks to minimize parasitic inductance. Place the 10-µF decoupling capacitors (C18, C114, C115, C116, C117,

and C118) near the power blocks, They do not need to be as close as the 0.1-µF capacitors.

64

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Layout Guidelines (接下页)

10.1.2 General Purpose Buck 2

Use short traces. Separate individual power grounds to avoid ground shift problems. Ground shift problems occur

when ground currents of different buck converters interfere. High currents flow through the inductor (L7) and the

output capacitors (C130, C131).Make the traces to and from inductor and capacitors as short as possible to

avoid losses due to trace resistance. Use high-quality capacitors with a low ESR value to minimize losses in the

capacitors and to maintain an acceptable amount of voltage ripple.

The next paragraph explains how to place and connect components near PWR6 Buck converter which are those

component connected to pins 62, 63, 64, 65, and 66.

Connect the supply voltage i to pin 64 with sufficient copper to make it stable and of low resistance. Use multiple

vias to the ground layer to connect pin 62 to ground. Use multiple layers create low resistive paths. Make sure

the ground connection of the output capacitors and the ground connection of the DLPA4000 (pin 62) are close

together. Connect both points using a wide trace. All buck converters in the layout use a separated ground trace

to their respective ground connection on the DLPA4000. All these ground connections are connected together on

the ground plane below the DLPA4000 package.

图 30 shows the position of the converter inductor and the accompanying capacitors (L7, C130, and C131)

positioned as close as possible to pin 62 and pin 64 using the thickest traces that are feasible. Make these

ground connections by using multiple vias to the ground layer to ensure a low-resistance path.

图 30. General Purpose Buck Layout

10.1.3 SPI Connections

The SPI interface comprises several digital lines and the SPI supply. Communication errors can occur if interface

lines are not routed properly. Prevent interference on the SPI lines by placing noisy and interfering sources away

from the interface.

Prevent noise by routing the SPI ground line with the digital lines to the respective pins as much as possible.

Connect the SPI interface with a separate ground connection to the DGND pin of the DLPA4000 device. This

design style prevents ground noise between SPI ground references of DLPA4000 and DLPC due to the high

current in the system.

65

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Layout Guidelines (接下页)

CLK

MISO

MOSI

SS_Z

ꢀQJꢁ`QCCV`

ꢂꢃꢄꢅ

ꢄJꢁV`ꢆ:HV

SPI_GND

DLPA4000

DGND

GND

VIN

- V_GND-DROP+

I

DLPA4000 PCB

图 31. SPI Connections

Separate interfering sources from the interface lines. For example, high-current lines such as those near the

PWR_7 pin and the SPI_CLK pin are too close, false clock pulses and communication errors can occur.

10.1.4 R_LIMRouting

The resistor R_LIMsenses the LED current. Connect the RLIM _K_1 and RLIM _K_2 lines close to the high-side of

measurement resistor R_LIMto accurately measure the LED current. Connect the RLIM_BOT_K_1 pin and the

RLIM_BOT_K_2 pin close to the high-side of measurement resistor R_LIM

.

The switched LED current flows through the R_LIMresistor. Use a low-ohmic ground connection for R_LIM

.

10.1.5 LED Connection

Large switched currents flow through the wiring from the external RGB switches to the LEDs. Consider these two

specifications to optimize the LED-to-RGB switches wiring layout:

1. wiring resistancce, R_SERIES

2. wiring inductance, L_SERIES

图 32 shows the parasitic series impedances.

66

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Layout Guidelines (接下页)

V_LED

R_SERIES

C_DECOUPLE

L_SERIES

Close to

V_LED, R_LIM

SW

V_RLIM

R_LIM

图 32. Parasitic Inductance (L_Series) and Resistance (R_series) in Series with LED

Currents up to 32 A can flow through the wires connecting the LEDs to the RGB switches. The layout can cause

noticeable dissipation. Every 10 mΩ of series resistances implies a parasitic power dissipation of 5 W for a 32 A

(avg) LED current . This dissipation can cause an increase in PCB temperature, and more importantly,

deterioration of overall system efficiency.

The wiring resistance may impact the control dynamics of the LED current. The LED current control loop includes

the routing resistance. The LED voltage (V_LED) controlls the LED current. Use 公式 15 to calculate the total

differential resistance of a path R_SERIES

.

¿V_LED

¿I_LED

=

r_LED+ R_series+ R_ON

+ R_LIM

,Q,R

SW

P

where

•

ΔI_LEDis the LED current variation

ΔV_LEDis a small change in V_LED

r_LEDis the differential resistance of the LED

R_{on_SW_P,Q,R}the on-resistance of the strobe decoder switch

L_SERIESis ignored

(15)

公式 15 ignores L_SERIESbecause realistic values are usually sufficiently low to cause any noticeable impact on

the dynamics

All differential resistance values range from about 4 mΩ to several hundreds of mΩ. Applications can yield a

series resistance of 100 mΩ if the layout guidelines are not followed. Make sure the application series resistance

is <10 mΩ.

The series inductance plays an important role when considering the switched nature of the LED current. the

current switches through R,G and B LEDs quickly. The turn-off time is significantly fast. A current of 32 A goes to

0 A in 50 ns. This speed causes a voltage spike of approximately 1 V for every 5 nH of parasitic inductance.

Minimize the series inductance of the LED wiring by designing an application that has these features:

•

Short wires

Thick wires or multiple parallel wires

Small enclosed area of the forward and return current path

67

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Layout Guidelines (接下页)

Use a diode when the application cannot be designed to yield a sufficiently low inductance. Use a Zener diode to

clamp the drain voltage of the RGB switch so that it remains below the absolute maximum rating. Choose a

clamping voltage between the maximum expected V_LEDand the absolute maximum rating. Make sure the

clamping voltage has sufficient margin relative to the minimum and maximum voltage.

10.2 Layout Example

图 33 shows an example of a proper buck converter layout. It shows the routing and placing of the components

near the DLPA4000 for optimal performance. A register sets the output voltage of the converters used by the

DLPA4000. The DLPA4000 uses the feedback pin to compare the output voltage with an internal setpoint.

图 33. Practical Layout Example

Use short traces. Separate individual power grounds to avoid ground shift problems. Ground shift problems occur

when ground currents of different buck converters interfere. High currents flow through the inductor (L7) and the

output capacitors (C130, C131).Make the traces to and from inductor and capacitors as short as possible to

avoid losses due to trace resistance. Use high-quality capacitors with a low ESR value to minimize losses in the

capacitors and to maintain an acceptable amount of voltage ripple.

In order to prevent problems with switching high currents at high frequencies the layout is very critical and

snubber networks are advisable. The switching frequency can vary from several hundreds of kHz to frequencies

in the MHz range. Keep in mind that it takes only nanoseconds to switch currents from zero to several amperes

which is equivalent to even much higher frequencies. Those switching moments causes EMI problems if not

properly handled, especially when ringing occurs on the edges, which can have higher amplitude and frequency

as the switching voltage itself. To prevent this ringing the DLPA4000 buck converters all need a snubber

network, consisting of a resistor and a capacitor in series implemented on the board to reduce this unwanted

behavior. The snubber network is in this case placed on the bottom-side of the PCB (thus not visible here)

connected to the trace of L9 routing to the switch node.

In order to make more clear what plays a role when laying out a buck converter, this paragraph explains the

connections and placing of the parts around the buck converter connected to the pins 50-54. The supply voltage

is connected to pin 52 which is laid out on a mid layer (purple colored) and is connected to this pin using 3 via’s

to make sure a stable and low resistance connection is made. The decoupling is done by capacitor C43 & C44

visible on the bottom right of 图 33 and the connection to the supply and the ground layer is done using multiple

vias. The ground connection on pin 54 is also done using multiple vias to the ground layer which is visible as the

blue areas in 图 33. By using different layers it is possible to create low resistive paths. Ideally the ground

connection of the output capacitors and the ground connection of the part (pin54) should be close together. The

layout connects both points together using a wide trace on the bottom layer (blue colored area) which is also

suitable to bring both connections together. All buck converters in the layout have the same layout structure and

68

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

Layout Example (接下页)

use a separated ground trace to their respective ground connection on the part. All these ground connections are

connected together on the ground plane below the DLPA4000 itself. shows the position of the converter inductor

and its accompanying capacitors (L9 & C46, C47) as close as possible positioned to the pins 51 and 53 using

traces as thick as possible. The ground connections of these capacitors is done using multiple via’s to the ground

layer to ensure a low resistance path.

10.3 Thermal Considerations

Integrated circuits in low-profile and fine-pitch surface-mount packages typically require special attention to

power dissipation. Many different system-dependent issues affect the power dissipation limits of individual

component. These issues include

•

thermal coupling

airflow

added heat sinks

added convection surfaces

other heat-generating components

These three basic approaches enhance thermal performance.

•

Improve the heat sinking capability of the PCB

Increase heat sink capability on top of the package

Increase airflow in the system

The DLPA4000 device has efficient power converters. But because the power delivered to the LEDs can be quite

large (more than 50 W in some case) the power dissipation in the DLPA4000 device can be high. Use proper

temperature calculation to minimize power dissipation in the application.

It is important to maintain the junction temperature below the maximum recommended value of 120°C during

operation. Calculate P_DISS, to determine the junction temperature of the DLPA4000. P_DISSis a summation of all

power dissipation. Use 公式 16 to calculate T_J.

T = T_A+ P_DISS× R_ꢀJA

J

where

•

T_Ais the ambient temperature

_θJAis the thermal resistance from junction-to-ambient

R

(16)

The total power dissipation varies depending on the application specifications. The main variances in the

DLPA4000 circuitry are:

•

Buck converters

LDOs

Use 公式 17 to calculate the dissipation for the buck converter.

≈

∆

«

’

1

÷

-1

P_{diss _buck}= P -P_out= P_out

in

÷

h_buck

◊

where

•

η_BUCKis the efficiency of the buck converter

P_INthe power delivered at the input of the buck converter

P_OUTthe power delivered to the load of the buck converter

(17)

shows efficiency for buck converters PWR1, PWR2, PWR5, PWR6, and PWR7.

Buck converters require high power efficiency because they typically handle the highest power levels. Linear

regulators,(for example, LDOs) handle lower power levels. Because the efficiency of an LDO can be relative low,

the related power dissipation can be significant.

Use 公式 18 to calculate the power dissipation of an LDO, P_DISS(ldo)

.

:

;

× I_LOAD

P_{DISS ldo}= V F V

:

;

IN

OUT

69

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

Thermal Considerations (接下页)

where

•

V_INis the input supply voltage

V_OUTis the output voltage of the LDO

I_LOADis the load current of the LDO

(18)

Because the voltage decrease over the LDO (V_IN– V_OUT) can be relative large, a relatively small load current can

yield significant power dissipation in the DLPA4000 device. In this case, consider using one of the general

purpose bucks to have a more power-efficient solition (in other words, a less dissipation solution).

It is important to consider the power dissipation of the LDO that supplies the boost power converter (the LDO

DMD). The boost converter supplies high voltages for the DMD. This voltages are V_BIAS, V_OFS, V_RST.The

maximum simultaneous load current I_LOAD(max)for these lines is 10 mA . So, the maximum related power level is

moderate. Use 公式 19 An efficiency rate of 80% for the boost converter, η_BOOST, implies a maximum boost

converter dissipation, P_{DISS (DMD_boost,MAX)}

.

1

:

ꢀ

ꢀ;

P_{DISS @DMD}

= I_{LOAD max}_;× V

+ V_OFS+ V_RST× l

ꢁ 1p ꢀ räs 7

:

BIAS

A

boost

D_BOOST

MAX

(19)

The level of power dissipation of the illumination buck converter this is likely negligible. The term that might count

to the total power dissipation is P_{diss_LDO_DMD}. The input current of the DMD boost converter is supplied by this

LDO. In case of an high supply voltage, a non negligible dissipation term is obtained. The worst case load

current for the LDO is given by:

:

ꢀ

ꢀ;

1

V_BIAS+ V_OFS+ V_RST

I_LOAD

=

;

×

× I_{LOAD max}_;ꢀ srr ≠!

:

LDO max

D_BOOST

V_DRST

5P5V

where

•

the output voltage of the LDO is V_{DRST_5P5V}is 5.5 V

(20)

Dissipation of power in the LDO can be up to 1.5 W for an input supply voltage of 19.5 V. Power dissipation of

1.5 W is a worst case scenario. In most cases the load current of the LDO DMD is significantly less. Make sure

to confirm the LDO current level for the specific application.

The DLPA4000 draws a quiescent current. The power supply voltage does not affect this quiescent current. For

the buck converters the quiescent current is comprised in the efficiency numbers. For the LDOs a quiescent

current on the order of 0.5 mA can be used. For the rest of the DLPA4000 circuitry, not included in the buck

converters or LDOs, a quiescent current on the order of 3 mA applies. Use 公式 21 to estimate dissipation,

P_{diss_DLPA4000}in the DLPA4000 device.

P_{DISS DLPS4000}= Í P

+ Í P

LDO

:

;

BUCK

(21)

Use to calculate the maximum ambient temperature,

T_A= T _{: ;}F P_DISS× R_ꢀJA= 120°C ꢀ2.5 W × 7°C/W = 102.5°C

J max

(22)

Use to calculate the junction temperature of the DLPA4000 device after you know the dissipated power and the

ambient temperature.

Use Thermal Information to calculate the junction temperature for heat sink configuration and airflow.

T = T_A+ P

× R_ꢀJA=50°C+4 W × 7°C/W = 78°C

J

DISS

(23)

Use one of these three design features if the combination of ambient temperature and DLPA4000 power

dissipation does not yield an acceptable junction temperature ( <120°C).

1. Use a larger heat sink, which increases airflow, to reduced R_θJA

,

2. Use lower load current through the internal general purpose buck converters..

3. Use an external general purpose buck converter instead of an internal one. This design reduces power

dissipation in the DLPA4000 device

70

DLPA4000

www.ti.com.cn

ZHCSIA7 –MAY 2018

11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

DLPA4000

图 34. 封装标记 DLPA4000（顶视图）

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

71

DLPA4000

ZHCSIA7 –MAY 2018

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。

72

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPA4000
厂家：	TEXAS INSTRUMENTS
描述：	适用于 DMD 的 DLP® PMIC/LED 驱动器驱动集成电源管理电路驱动器
文件：	总78页 (文件大小：2711K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPA4000 [TI]

相关型号：

DLPA4000PFD

DLPA4000PFDR

DLPC100

DLPC100ZCT

DLPC120-Q1

DLPC120ZXSQ1

DLPC120ZXSRQ1

DLPC1438

DLPC1438ZEZ

DLPC150

DLPC150ZEZ

DLPC200