DLPC100_技术文档

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

®

DLP Digital Controller for the DLP1700 DMD

Check for Samples: DLPC100

1

FEATURES

•

Optimized to Operate With DLPR100 and

DLP1700

–

Frame Rate Conversion

LED Current Control Adjustment

Programmable Degamma

Single 24-Bit Input Port (RGB or BT656-YUV)

With Pixel Clock Support up to 30 MHz

Spatial-Temporal Multiplexing (Dithering)

Automatic Gain Control

Input Image Size 320 x 240 (QVGA), 480 x 320

(HVGA), or 640 x 480 (VGA)

•

60 MHz Double Data Rate (DDR) DMD Interface

Three RGB Input Color Bit-Depth Options:

RGB888, RGB666, RGB565

External Memory Support: 100 MHz SDR

SDRAM

•

Supports 1 Hz to 60 Hz Frame Rates

I²C Control Interface for Device Configuration

Pixel Data Processing:

•

Serial FLASH Interface

System Control:

–

Programmable LED Currents

–

Color Space Conversion

DMD Power and Reset Driver Control

DMD Horizontal and Vertical Image Flip

Built-in Test Pattern Generation

Chroma Interpolation for 4:2:2 to 4:4:4

Conversion

–

Color Coordinate Adjustment

Image Resizing (Scaling)

•

JTAG with Boundary Scan Test Support

Packaged in 256-Pin Ultra Fineline Ball-Grid

Array (uBGA)

De-Interlacing Via Field Scaling

DESCRIPTION

The DLPC100 performs all the image processing and control, along with DMD data formatting, for driving a 0.17

HVGA DMD (DLP1700).

The DLPC100 is one of three components in the 0.17 HVGA Chipset (see Figure 1). Proper function and

operation of the DLP1700 requires that it be used in conjunction with the other components of the 0.17 HVGA

Chip-Set. Refer to the 0.17 HVGA Chip-Set Data Sheet for further details (TI literature number DLPS017).

In DLP electronics solutions, image data is 100% digital from the DLPC100 input port to the image projected on

to the display screen. The image stays in digital form and is never converted into an analog signal. The

DLPC100 processes the digital input image and converts the data into a format needed by the DMD. The DMD

then reflects light to the screen using binary pulse-width-modulation (PWM) for each pixel mirror.

Commands can be input to the DLPC100 over an I²C interface.

The digital input interface switching levels, for image data, is nominally 1.8 V, 2.5 V, or 3.3 V. The switching level

used is selected by setting pin INTFPWR to 1.8 V, 2.5 V, or 3.3 V. The input image interface and I²C interface

switching levels must be the same.

Related Documents

DOCUMENT

TI LITERATURE NUMBER

DLPS017

DLP 0.17 HVGA Chip-Set data sheet

DLPR100 Configuration PROM data sheet

DLP1700 0.17 HVGA DMD data sheet

DLPS020

DLPS018

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

24-bit RGB DATA

Digital Video

VSYNC

HSYNC

DVI

Receiver

2

I C

2

5VDC

Voltage Control

Voltage

Regulator

2

I C

2

Control

MSP430

Control

RED STROBE

GREEN STROBE

BLUE STROBE

Illumination

Optics

Projection

Optics

Configuration

DLPC100

DLPR100

LED

DLP1700

Driver

RED PWM

GREEN PWM

BLUE PWM

Mobile

SDR

Memory

OSC

Figure 1. Typical Application

SDRAM

I/F

FORMAT

CONVERSION

IMAGE

ENHANCEMENT

ARTIFACT

MITIGATION

DMD

FORMATTING

DMD DDR Data

10

RGB (YUV) Data

RGB Control

• Chroma interpolation

• Color space conversion

• Gamma correction

• Degamma

• Automatic gain control

• Image scaling

• Spatial-temporal

multiplexing

• Memory management/

control

• DMD I/F processing

• Horizontal and vertical

flip processing

24

DMD DDR Control

Flash I/F

I²C Bus

CONTROL

DMD Reset Control

Oscillator

SYSTEM CLOCK AND RESET SUPPORT

Figure 2. Functional Block Diagram

2

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

Projector Image Port Signal Sharing

Figure 2 illustrates the basic processing that occurs in the controller. The DLPC100 provides a single input port

for graphics and motion video inputs. The signals listed below support two input interface modes. Thus some

signals have different uses depending on the input interface mode being used.

Below are the two input image interface modes, signal descriptions, and pins needed on the DLPC100. describes

all the signals in the DLPC100.

•

BT.656, 9 pins

–

PDATA(7-0) – Projector Data

PCLK – Projector Clock (rising edge to capture input data)

•

Parallel Bus, 20 pins or 22 pins or 28 pins

–

PDATA(15-0) or PDATA(17-0) or PDATA(23-0) – Projector Data

HSYNC – Horizontal Sync

VSYNC – Vertical Sync

DATEN – Data En (active high)

PCLK – Projector Clock (rising edge, or falling edge, to capture input data)

The Terminal Functions table describes the input/output characteristics of signals that interface to the DLPC100

by functional groups. Signals are referenced by names shown in the Pico Projector Formatter Reference

Schematic, TI drawing 2509552. The voltage characteristics of various I/O types are described in the I/O

Characteristics table.

ZCT PACKAGE

(BOTTOM VIEW)

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

Submit Documentation Feedback

3

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

NAME

CFG_DATA

CFG_DCLK

I/O

TYPE

CLOCK

SYSTEM

DESCRIPTION

NO.

H2

I1

CFG_DCLK

Data input from DLPR100 device

DLPR100 data clock

H1

O1

CFG_ASDO

Serial data output. This pin sends address and control

information to the DLPR100 during configuration.

C1

O1

CFG_DCLK

MSEL_2

MSEL_1

MSEL_0

CE

G12

H12

H13

J3

I1

Asynch

Mode selection signals. (Must be tied low for proper operation)

Mode selection signals. (Must be tied high for proper operation)

Mode selection signals. (Must be tied low for proper operation)

Configuration chip enable. Active low.

CFG

Configuration control. Configuration will start when a low to high

transition is detected at this pin.

H5

F4

I1

Asynch

NSTATUS

B1

CFG_DCLK

Configuration status pin.

CFG_DONE

Configuration Done status pin. Signal goes high at the end of

configuration.

H14

Board Level Test & Debug

JTAG_TDI

H4

H3

J5

I2

I3

JTAG_TCK

N/A

JTAG, serial data in

JTAG_TCK

JTAG, serial data clock

JTAG, test mode select

JTAG, serial data out

JTAG_TMS

JTAG_TDO

System Interfaces

CLK_IN

I2

JTAG_TCK

J4

O1

E16

L8

I4

I5

N/A

Async

N/A

Input oscillator clock (60 MHz)

Device reset (active low)

RESET

PWRGOOD

P_SCL

T3

I5

System power good indicator

I²C clock

I²C data

I²C address selection (low = device address x36)

Reserved. Must be tied to GND for DLPC100.

Not used. Pin reserved for future use.

R3

B2

I4

P_SDA

L3

N/A

I2C_ADDR_SEL

Reserved

R9

Async

M16

G15

I4

Reserved

I4

Test/Debug Interfaces

SpareIn_B8

SpareIn_B9

SpareIn_E1

SpareIn_E15

SpareIn_E2

SpareIn_M1

SpareIn_M15

SpareIn_M2

SpareIn_A9

SpareIn_T9

B8

B9

E1

E15

E2

I1,4,5

N/A

Reserved. Should be tied to GND to minimize power.

M1

M15

M2

A9

T9

4

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

I/O

TYPE

CLOCK

SYSTEM

DESCRIPTION

NO.

P6

AUXSYNC0

TEST1

P11

P14

L14

J13

J15

J16

D16

G16

F14

D15

C16

C11

C15

B16

F13

D1

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

AUXSYNC1

AUXSYNC2

AUXSYNC3

AUXSYNC4

TEST12

TEST13

TEST14

TEST15

TEST16

TEST17

TEST18

TEST19

TEST20

TEST21

TEST22

TESTx outputs are Reserved for factory testing. AUXSYNC0-4

are available for Pattern Display Synchronization. See

associated application note.

O1,3,4

N/A

F16

F15

G15

G1

M8

N8

Submit Documentation Feedback

5

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

I/O

TYPE

CLOCK

SYSTEM

DESCRIPTION

NO.

Main Video Data & Control

PARALLEL RGB

Clock

BT.656

Clock

PCLK

R8

T5

R4

N3

T4

T2

R5

P2

N5

N2

P8

L2

I5

I6

O5

I5

N/A

VSYNC_WE

HSYNC_CS

DATEN_CMD

Reserved_RFU

PDATA0

PCLK

Vsync

Unused

Data0

Hsync

Active data

Unused

Data

PDATA1

Data⁽¹⁾

Data1

PDATA2

Data2

PDATA3

Data3

PDATA4

Data4

PDATA5

Data5

PDATA6

Data6

PDATA7

T7

K2

R7

J2

Data7

PDATA8

Unused

PDATA9

PDATA10

PDATA11

PDATA12

PDATA13

PDATA14

PDATA15

PDATA16

PDATA17

PDATA18

PDATA19

PDATA20

PDATA21

PDATA22

PDATA23

DMD Interface

DMD_D0

DMD_D1

DMD_D2

DMD_D3

DMD_D4

DMD_D5

DMD_D6

DMD_D7

DMD_D8

DMD_D9

DMD_DCLK

DMD_LOADB

DMD_SCTRL

M7

R1

L7

P1

M6

N1

N6

L1

P3

K1

R6

J1

T6

P9

O3

DMD_CLK

N/A

R16

R13

R12

R11

L15

J14

L13

N16

N15

N12

N9

DMD data pins. DMD Data pins are double data rate (DDR)

signals that are clocked on both edges of DMD_DCLK.

DMD data clock

DMD_CLK

DMD data serial control signal

DMD data load signal

P16

(1) 24-bit data is mapped according to RGB565/RGB666/RGB888 pixel format. See Figure 3.

Submit Documentation Feedback

6

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

I/O

TYPE

CLOCK

SYSTEM

DESCRIPTION

NO.

T10

T11

T14

T12

K16

T15

R10

T13

L16

K15

R14

G5

DMD_TRC

DMD_A0

O3

I4

DMD_CLK

N/A

DMD data toggle rate control

DMD reset address 0

DMD reset address 1

DMD reset address 2

DMD reset select 0

DMD_A1

DMD_A2

DMD_SEL0

DMD_SEL1

DMD reset select 1

DMD_MODE

DMD_STROBE

DMD_SACBUS

DMD_SACCLK

DMD_OEZ

DMD_PWR_EN

RESERVED

SDRAM Interface

MEM_A0

DMD reset mode

DMD reset strobe

DMD serial bus data

DMD serial bus clock

DMD reset output enable

DMD power regulator enable

Pin reserved for future use

Not used. Pin reserved for future use.

H16

H15

N/A

D12

B12

B14

C14

D14

A15

A13

B13

A14

B3

O2

B3

MEM_CLK

N/A

Multiplexed row and column address 0 for the SDRAM

Multiplexed row and column address 1 for the SDRAM

Multiplexed row and column address 2 for the SDRAM

Multiplexed row and column address 3 for the SDRAM

Multiplexed row and column address 4 for the SDRAM

Multiplexed row and column address 5 for the SDRAM

Multiplexed row and column address 6 for the SDRAM

Multiplexed row and column address 7 for the SDRAM

Multiplexed row and column address 8 for the SDRAM

Multiplexed row and column address 9 for the SDRAM

Multiplexed row and column address 10 for the SDRAM

Multiplexed row and column address 11 for the SDRAM

Bank select for the SDRAM

MEM_A1

MEM_A2

MEM_A3

MEM_A4

MEM_A5

MEM_A6

MEM_A7

MEM_A8

MEM_A9

MEM_A10

MEM_A11

MEM_BA0

MEM_BA1

MEM_RAS

MEM_CAS

MEM_CKE

MEM_CS

A12

D11

B11

A11

C9

Bank select for the SDRAM

Row address strobe. Active low.

D9

Column address strobe. Active low.

E9

Clock enable. Active high.

B10

A10

D8

Chip select. Active low.

MEM_HDQM

MEM_LDQM

MEM_WE

Data mask high byte.

Data mask low byte

F8

Write enable. Active low.

MEM_CLK

MEM_DQ0

MEM_DQ1

MEM_DQ2

MEM_DQ3

MEM_DQ4

MEM_DQ5

MEM_DQ6

MEM_DQ7

MEM_DQ8

F9

Memory clock. Generated by internal PLL. 100 MHz

Bidirectional data 0 for the SDRAM

A3

MEM_CLK

B4

Bidirectional data 1 for the SDRAM

A5

Bidirectional data 2 for the SDRAM

A6

Bidirectional data 3 for the SDRAM

B6

Bidirectional data 4 for the SDRAM

E6

Bidirectional data 5 for the SDRAM

A7

Bidirectional data 6 for the SDRAM

C8

Bidirectional data 7 for the SDRAM

E8

Bidirectional data 8 for the SDRAM

Submit Documentation Feedback

7

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

MEM_DQ9

I/O

TYPE

CLOCK

SYSTEM

DESCRIPTION

NO.

B7

E7

A2

D6

B5

D5

A4

B3

MEM_CLK

Bidirectional data 9 for the SDRAM

MEM_DQ10

MEM_DQ11

MEM_DQ12

MEM_DQ13

MEM_DQ14

MEM_DQ15

LED Driver Interface

BLU_PWM

Bidirectional data 10 for the SDRAM

Bidirectional data 11 for the SDRAM

Bidirectional data 12 for the SDRAM

Bidirectional data 13 for the SDRAM

Bidirectional data 14 for the SDRAM

Bidirectional data 15 for the SDRAM

C6

C3

D3

F1

G2

F2

A8

O3

O1

I4

CLK_IN

Async

Blue LED PWM signal used to control the LED current

Red LED PWM signal used to control the LED current

RED_PWM

GRN_PWM

Green LED PWM signal used to control the LED current

Blue LED enable

BLU_STROBE

RED_STROBE

GRN_STROBE

LED_FAULT

Red LED enable

Green LED enable

LED fault indication. Signal forces LEDDRV_ON low and RGB

strobes low

LED_ENABLE

T8

I5

Async

LED enable. Signal forces LEDDRV_ON low and RGB strobes

low.

LEDDRV_ON

RESERVED

Impedance Control⁽²⁾

RUP2

F3

B1

C2

O1

I1

CLK_IN

Async

LED driver enable

Not used. Reserved for future use.

O1

PWR

N/A

Bank 4 control

Bank 5 control

Bank 7 control

RDN2

RUP3

RDN3

RUP4

RDN4

Power and Ground⁽²⁾

P1P2V

PWR

N/A

1.2 V core power

P2P5V_DPLL

P1P8V

2.5 V filtered power for internal PLL

1.8 V I/O power

P2P5V

2.5 V I/O power

P3P3V

3.3 V I/O power

GND

Common digital ground

Common PLL ground

GNDA

(2) To see how these are connected, see the reference schematic

8

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

16-Bit Input Bus, RGB565 (Parallel Bus)

PDATA(15–0), the input data bus

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Bus Assignment Mapping

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

RGB565 format

18-Bit Input Bus, RGB666 (Parallel Bus)

PDATA(17–0),

PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Bus Assignment Mapping

B0

RGB666 format

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

24-Bit Input Bus, RGB888 (Parallel Bus Only)

PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

R0

G7

G6

G5

G4

G3 G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

R7

R6

R5

R4

R3 R2

R1

RGB888 format

Figure 3. Pixel Mapping

Submit Documentation Feedback

9

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

I/O CHARACTERISTICS⁽¹⁾

all inputs/outputs are LVCMOS

I/O TYPE

CONDITIONS

V_IL

V_IH

MIN

V_OL

V_OH

UNIT

MIN

-0.3

MAX

0.8

MAX

V_CCIO+0.3

MIN

MAX

I1

I2

I3

Input

V_CCIO= 2.5 V

1.7

V

Input

V_CCIO= 2.5 V

0.8

V_CCIO= 2.5 V, internal

pulldown resistor

0.8

V

I4

I5

I6

Input

V_CCIO= 1.8 V

-0.3

0.35 * V_CCIO

0.65 * V_CCIO

V_CCIO+0.3

V

V_CCIO= 1.8 to 3.3 V

V_CCIO= 1.8 to 3.3 V,

internal pullup resistor

V

O1

O2

O3

O4

B1

Output 8 mA

Output 4 mA

Output 8 mA

Output 4 mA

V_CCIO= 2.5 V

0.4

0.45

0.4

2

V_CCIO– 0.45

V

V_CCIO= 1.8 V

V_CCIO= 1.8 to 3.3 V

Bi-directional output, V_CCIO= 2.5 V

open drain

-0.3

0.8

0.35 * V_CCIO

1.7

0.65 * V_CCIO

V_CCIO+0.3

V

B2

B3

Bi-directional output, V_CCIO= 1.8 to 3.3 V

open drain

0.45

Bi-directional output, V_CCIO= 1.8 V

4 mA

V_CCIO– 0.45

(1) Cross reference to IO assignments

POWER AND GROUND PINS

NAME

DESCRIPTION

PIN NUMBER(S)

Input Power and Ground Pins

F7, F11, G6, G7, G8, G9, G10, H6, H11,

J6, J12, K7, K9, K10, K11, L6, M9, M11

VCC12

1.2-V power supply for core logic

2.5-V power supply for internal PLLs

VCC25_DPLL

F5, F12, L5, L12

A1, A16, C4, C7, C10, C13, E14, G14,

VCCIO18

1.8-V power supply for I/Os on banks 4-8

K14,

M14, P10, P13, T16

2.5-V or 3.3-V power supply for bank I/Os (Serial configuration FLASH

interface) Bank 1

E3, G3

FLASHPWR

INTFPWR

1.8V, 2.5V or 3.3V power supply for I/Os on Video Interface Banks 2-3

1.2V power supply for DLL

K3, M3, P4, P7, T1

N4, D13, D4, N13

VCCD_PLL1-4

B2, B15, C5, C12, D7, D10, E4, E13, F6,

F10, G4, G11, G13, H7, H8, H9, H10,

J7,

GND

Common ground

Analog ground

J8, J9, J10, J11, K4, K6, K8, K12, K13,

L9,

L10, L11, M4, M13, N7, N10, P5, P12,

R2, R15

GNDA1-4

M5, E12, E5, M12

Input Signals Tied to a Fixed Level

GND

Virtual GND output pins that are driven to a low level for noise reduction.

none

On-Chip Series Termination with Calibration⁽¹⁾

RDN1, RUP1

RDN2, RUP2

RDN3, RUP3

RDN4, RUP4

Bank 2 - Not connected

L4, K5

Bank 4 DMD interface support

Bank 5 DMD interface support

Bank 7 and 8 memory interface support

N11, M10

P15, N14

E10, E11

(1) The device supports on-chip series termination with calibration in all banks. The on-chip series termination calibration circuit compares

the total impedance of the I/O buffer to the external 50 Ω ±1% resistors connected to the RUP and RDN pins, and dynamically adjusts

the I/O buffer impedance until they match. OCT with calibration is achieved using the OCT calibration block circuitry. There is one OCT

calibration block in bank 2, 4, 5, and 7.

10

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

Video Input Pixel Interface

TIMING REQUIREMENTS⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

1

MAX

UNIT

MHz

ns

f_clock

t_t

Clock frequency, PCLK

30

Transition time, t_t= t_f/t_rPCLK

20% to 80% reference points (signal)

50% to 50% reference points (signal)

1.0

11

t_w(H)

t_w(L)

t_j

Pulse duration, high

ns

Pulse duration, low

ns

(2)

Clock period jitter, PCLK

See

ns

(3)

t_su

t_h

Setup time, PDATA(23-0) valid before PCLK

Hold time, PDATA(23-0) valid after PWCLK

Setup time, VSYNC_WE valid before PCLK

Hold time, VSYNC_WE valid after PCLK

Setup time, HSYNC_CS valid before PCLK

Hold time, HSYNC_CS valid after PCLK

See

3.0

ns

(3)

See

ns

(3)

t_su

t_h

See

ns

(3)

See

ns

(3)

t_su

t_h

See

ns

(3)

See

ns

(3)

t_su

t_h

Setup time, DATEN_CMD valid before PCLK See

ns

(3)

Hold time, DATEN,_CMD valid after PCLK

See

ns

(1) Contact TI for I²C, LED driver, power-up and power=down timing information.

(2) PCLK may be inverted from that shown in Figure 4. In that case the same specifications in the table are valid except now referenced to

the falling edge of the clock. If the falling edge of PCLK is to be used, an I²C command is needed to tell the DLPC100 to use the falling

edge of PCLK.

(3) Use the following formula to obtain the jitter. Jitter = [1/frequency – 30 ns]. Setup and hold must still be met.

t

c

t

w(L)

w(H)

t

PCLK

(input)

80%

20%

50%

t

su

h

PDATA

VSYNC_WE

HSYNC_CS

DATEN_CMD

Valid

(inputs)

Figure 4. Input Port Interface

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 5). After the Start condition, the device address byte

is sent, MSB first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during

the high of the ACK-related clock pulse.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 6).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 5).

Submit Documentation Feedback

11

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 7). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

S

P

Start Condition

Stop Condition

Figure 5. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 6. Bit Transfer

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

1

2

8

9

S

Start

Clock Pulse for

Condition

Acknowledgment

Figure 7. Acknowledgment on I²C Bus

12

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

I²C INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

0

MAX UNIT

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

400

kHz

ms

ns

1

20

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C output fall time

I²C bus free time between Stop and Start conditions

I²C Start or repeated Start condition setup

I²C Start or repeated Start condition hold

I²C Stop condition setup

100

20

30

1.3

1

ns

300

200

ns

t_ocf

t_buf

t_sts

t_sth

t_sph

50 pF

ns

ms

pF

1

Valid-data time

SCL low to SDA output valid

1

t_vd

Valid-data time of ACK condition

I²C bus capacitive load

ACK signal from SCL low to SDA (out) low

t_sph

0

100

Submit Documentation Feedback

13

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

V

CC

R

L

= 1 kΩ

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 7

(MSB)

Data

Bit 0 Condition

(LSB)

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

PHL

t

icf

t

buf

t

sp

PLH

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 8. I²C Interface Load Circuit and Voltage Waveforms

14

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

I²C Bus Transactions

Data is exchanged between the master and the DLPC100 through write and read commands.

Writes

Data is transmitted to the DLPC100 by sending the device address and setting the least-significant bit to a logic

0. The data bytes are sent after the address and determines which register receives the data that follows the

address byte. Data is clocked into the register on the rising edge of the ACK clock pulse. .

Reads

The bus master first must send the DLPC100 address with the least-significant bit set to a logic 0. The read

address byte is sent after the device address and read command (x15) and the read address determines which

register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set

to a logic 1. Data from the register defined by the read address byte then is sent by the DLPC100. See

Programmers guide for a full description of the register read/write protocol and available registers.

Flash Memory Interface

The DLPC100 controller flash memory interface consists of a SPI flash serial interface at 33.3 MHz (nominal).

FLASH INTERFACE TIMING REQUIREMENTS

PARAMETER

Clock frequency, SPI_CLK

Clock period, SPI_CLK

TEST CONDITIONS

MIN

33.3266

29.994

MAX

33.34

30.006

200

UNIT

MHz

ns

(1)

f_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

t_{p_wl}

See

50% reference points

Max f_clock

Clock jitter, SPI_CLK

ps

Pulse width low, SPI_CLK

Pulse width high, SPI_CLK

Transition time – all signals

50% reference points

20% to 80% reference points

10

ns

t_t

0.2

10

4

1

ns

Setup Time – SPI_DIN valid before SPI_CLK rising

edge

ns

t_{p_su}

t_{p_h}

t_{p_clqv}

t_{p_clqx}

50% reference points

Hold Time – SPI_DIN valid after SPI_CLK rising

edge

0

ns

SPI_CLK clock low to output valid time – SPI_DOUT

& SPI_CSZ

SPI_CLK clock low output hold time – SPI_DOUT &

SPI_CSZ

-1

(1) This range include the 200 ppm of the external oscillator

t_{p_clkper}

t_{p_wh}

t_{p_wl}

SPI_CLK

t_{p_h}

t_{p_su}

SPI_DATA

Figure 9. Flash Memory Interface Timing

Submit Documentation Feedback

15

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

DMD Interface

The DLPC100 ASIC DMD interface consists of a 60.0 MHz (nominal) DDR output-only interface with LVCMOS

signaling.

DMD INTERFACE TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

MHz

ns

(1)

f_clock

Clock frequency, DMD_DCLK & DMD_SAC_CLK

Clock period, DMD_DCLK & DMD_SAC_CLK

Clock jitter, DMD_DCLK & DMD_SAC_CLK

Pulse width low, DMD_DCLK & DMD_SAC_CLK

Pulse width high, DMD_DCLK & DMD_SAC_CLK

See

60.05

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

50% reference points

Max f_clock

16.5

200

ps

50% reference points

7.5

0.3

ns

t_{p_wl}

ns

20% to 80% reference

points

2.0

1.5

ns

t_t

Transition time – all signals

Output setup time – DMD_D(14:0), DMD_SCTRL,

DMD_LOADB & DMD_TRC relative to both rising and

falling edges of DMD_DCLK

ns

tp_su

50% reference points

Output hold time – DMD_D(14:0), DMD_SCTRL,

DMD_LOADB & DMD_TRC signals relative to both rising

and falling edges of DMD_DCLK DMD

1.5

t_{p_h}

Data skew – DMD_D(14:0), DMD_SCTRL, DMD_LOADB &

DMD_TRC signals relative to each other

0.20

ns

t_{p_d1_skew}

t_{p_clk_skew}

50% reference points

Clock skew – DMD_DCLK & DMD_SAC_CLK relative to

each other DAD/ SAC

Data Skew - DMD_SAC_BUS, DMD_DAD_OEZ,

t_{p_d2_skew}DMD_DAD_BUS & DMD_DAD_STRB signals relative to

DMD_SAC_CLK

50% reference points

(1) This range include the 200 ppm of the external oscillator

tp_d1_skew

DMD_D(1:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

tp_h

tp_su

DMD_DCLK

tp_wl

tp_wh

tclk_skew

DMD_SAC_CLK

tp_d2_skew

DMD_SAC_BUS

DMD_DAD_OEZ

DMD_DAD_BUS

DMD_DAD_STRB

Figure 10. DMD I/F Timing

16

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

Mobile SDR Memory Interface

The DLPC100 Controller Mobile SDR Memory interface consists of a 16-bit wide, mobile SDR interface (i.e.

LVCMOS signaling) operated at 100.0 MHz (nominal).

MOBILE SDR MEMORY INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

10

3

MAX

UNIT

ns

t_CYCLE

t_CH

Cycle time reference

CK high pulse width⁽¹⁾

CK low pulse width⁽¹⁾

Command setup

Command hold

t_CL

3

t_CMS

t_CMH

t_AS

1.5

1

Address setup

1.5

1

t_AH

Address hold

t_DS

Write data setup

Write data hold

2.5

1

t_DH

t_AC

Read data access time

Read data hold time

8

t_OH

t_LZ

2.5

1

Read data low impedance time

Read data high impedance time

t_HZ

(1) CK and DQS pulse width specs for the DLPC100 assume it is interfacing to a 125 MHz m_DDRdevice. Even though these memories are

only operated at 100.0 MHz, according to memory vendors, the rated t_CKspec (i.e. 8 ns) can be applied to determine minimum CK and

DQS pulse width requirements to the memory.

tCYCLE

MEM_CLK

tCH

tCL

tAS

tAH

MEM_A(11:0)

MEM_BA(11:0)

MEM_xDQM

MEM_RAS\

MEM_CAS\

MEM_WE\

MEM_CS\

tCMS

tCMH

MEM_CKE

tDS

tDH

MEM_DQ(15:0)

mSDR Memory Write Data Timing

Figure 11. Mobile SDR Memory I/F Write Timing

Submit Documentation Feedback

17

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

tCYCLE

MEM_CLK

tCH

tCL

tAS

tAH

MEM_A(11:0)

MEM_BA(11:0)

MEM_xDQM

tCMS

MEM_RAS\

tCMH

MEM_CAS\

MEM_WE\

MEM_CS\

MEM_CKE

tAC

tOH

Valid

Data

MEM_DQ(15:0)

tLZ

tHZ

mSDR Memory Read Data Timing

Figure 12. Mobile SDR Memory I/F Read Timing

18

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

SDRAM Memory

The DLPC100 requires an external Mobile SDR SDRAM. The DLPC100 can support either a 128 Mbit or a 64

Mbit SDRAM. The basic requirements for the SDRAM are:

•

SDRAM type: mobile SDR

Speed: 125 MHz minimum

16-bit interface size: 64 Mbit or 128 Mbit

Supply voltage: 1.8 V

Supported SDRAM Devices shows the SDRAM parts that have been tested by TI. All have been found to work

properly and are therefore recommended for production use with the DLPC100.

Table 1. Supported SDRAM Devices

PART NUMBER

K4M64163PK-BG750JR

K4M28163PH-BG750JR

MT48H4M16LFB4-8

MT48H8M16LFB4-8

MANUFACTURER

Samsung

Micron

SIZE

64 Mbit

128 Mbit

64 Mbit

128 Mbit

Micron

Submit Documentation Feedback

19

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

VALUE

UNIT

V_CC12

–0.5 V to 1.80

–0.5 V to 3.90

–0.5 V to 3.75

–0.5 V to 3.90

-0.5 V to 1.80

–0.5 V to 3.95

0.300

V_CCIO18

(2)

V_{CCA25_DPLL}

INTFPWR

V_{CCD_PLL1-4}

V_I

Supply voltage range

V

Input voltage range⁽³⁾

1.8 V, 2.5V, 3.3V

V

Continuous total power dissipation: typical

Operating junction temperature range

Storage temperature range

W

°C

T_J

–40°C to 125

–60°C to 150

T_stg

HBM

Electrostatic discharge voltage using the Human

Body Model

+/- 2000

+/- 500

V

CD

Electrostatic discharge voltage using the Charged

Device Model

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND, and at the device not at the power supply.

(3) Applies to external input and bidirectional buffers.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

1.15

1.71

NOM

1.2

MAX

1.25

1.89

UNIT

V_CC12

V_CC18

1.2-V Supply voltage, core logic

V

1.5-V supply voltage, HSTL output

buffers

1.8

V

V_{CCA25_DPLL}

INTFPWR

V_{CCD_PLL1-4}

V_IH

2.5-V analog voltage for PLL regulator

At 1.8-V IO rail

2.375

1.71

2.5

1.8

2.5

3.3

1.2

2.625

1.89

V

At 2.5-V IO rail

2.375

3.15

2.625

3.45

At 3.3-V IO rail

1.2-V supply voltage, for PLL

High-level input voltage

1.15

1.25

1.8V LVCMOS

2.5V LVCMOS

3.3VLVCMOS

1.8V LVCMOS

2.5V LVCMOS

3.3VLVCMOS

0.65*V_CCIO

1.7

V

1.7

V_IL

Low-level input voltage

0.35*V_CCIO

0.8

V_I

Input voltage

-0.5

0

3.6

V

V_O

t_Ramp

T_J

Output voltage

VCCIO

3 ms

85

Power supply ramptime

Operating junction temperature

50 us

-20

-

°C

Thermal Considerations

The underlying thermal limitation for the DLPC100 is that the maximum operating junction temperature (T_J) not

be exceeded (see Recommended Operating Conditions). This temperature is dependent on operating ambient

temperature, airflow, PCB design (including the component layout density and the amount of copper used),

power dissipation of the DLPC100 and power dissipation of surrounding components. The DLPC100’s package

is designed primarily to extract heat through the power and ground planes of the PCB, thus copper content and

airflow over the PCB are important factors.

20

Submit Documentation Feedback

Product Folder Link(s): DLPC100

DLPC100

www.ti.com

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

Device Marking

Device marking should be as shown below.

25094xx – AB

DPP150x

®

Date Code

Country of Origin

Assy. Lot Number

Trace code

25094xx = 2509408 or 2509427; DPP150x = DPP1500 or DPP1505

Marking Key:

Line 1 : TI Reference Number

Line 2 : Device Name

Line 3 : DLP® logo

Line 4 : Date Code

Line 5 : Country of Origin

Line 6 : Assembly Lot Number

Line 7 : Trace Code

Submit Documentation Feedback

21

Product Folder Link(s): DLPC100

DLPC100

DLPS019B –DECEMBER 2009–REVISED DECEMBER 2010

www.ti.com

Table 2. Revision History

REVISION

SECTION(S)

COMMENT

*

All

Initial release

I²C Interface,

I²C Bus Transactions,

Flash Memory Interface,

DMD Interface,

Added description, graphics, and timing requirements, status changed to Production

Data

A

Mobile SDR Memory Interface,

22

Submit Documentation Feedback

Product Folder Link(s): DLPC100

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Transportation and Automotive www.ti.com/automotive

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC100
厂家：	TEXAS INSTRUMENTS
描述：	DLPÂ® Digital Controller for the DLP1700 DMD DLPÂ®数字控制器的DLP1700 DMD 控制器
文件：	总25页 (文件大小：495K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC100 [TI]

相关型号：

DLPC100ZCT

DLPC120-Q1

DLPC120ZXSQ1

DLPC120ZXSRQ1

DLPC1438

DLPC1438ZEZ

DLPC150

DLPC150ZEZ

DLPC200

DLPC200ZEW

DLPC200ZEWCM

DLPC200ZEWT