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DLPC300

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®

DLP Digital Controller for the DLP3000 DMD

Check for Samples: DLPC300

1

FEATURES

23

•

Supports Reliable Operation of the DLP3000

DMD

–

Integrated DMD Reset Driver Control

DMD Horizontal and Vertical Display Image

Flip

•

Multi-Mode, 24-Bit Input Port:

–

Supports Parallel RGB With Pixel Clock Up

to 33.5 MHz and 3 Input Color Bit-Depth

Options:

•

Low Power Consumption: Only 93 mW

(Typical)

External Memory Support:

–

24-Bit RGB888 or 4:4:4 YCrCb888

18-Bit RGB666 or 4:4:4 YCrCb666

16-Bit RGB565 or 4:2:2 YCrCb565

–

166-MHz Mobile DDR SDRAM

33.3-MHz Serial FLASH

•

176-Pin, 7 × 7 mm with 0.4-mm Pitch VFBGA

Package

–

Supports 8-Bit BT.656 Bus Mode With Pixel

Clock Up to 33.5 MHz

APPLICATIONS

•

Supports Input Resolutions 608x684, 864x480,

854x480 (WVGA), 640x480 (VGA), 320x240

(QVGA)

•

Machine Vision

Industrial Inline Inspection

3D Scanning

Pattern Input Mode

–

One-to-One Mapping of Input Data to

Micromirrors

3D Optical Metrology

Automated Fingerprint Identification

Face Recognition

–

1-Bit Binary Pattern Rates up to 4000-Hz

8-Bit Grayscale Pattern Rates up to 120-Hz

Augmented Reality

Embedded Display

Interactive Display

Information Overlay

Spectroscopy

•

Video Input Mode with Pixel Data Processing

–

Supports 1Hz to 60Hz Frame Rates

Programmable Degamma

Spatial-Temporal Multiplexing (Dithering)

Automatic Gain Control

Chemical Analyzers

Medical Instruments

Photo-Stimulation

Virtual Gauges

Color Space Conversion

•

Output Trigger Signal for Synchronizing with

Camera, Sensor, or Other Peripherals

System Control:

–

I²C Control of Device Configuration

Programmable Current Control of up to 3

LEDs

DESCRIPTION

The DLPC300 digital controller, part of the DLP 0.3 WVGA chipset, supports reliable operation of the DLP3000

DMD. The DLPC300 controller also provides a convenient, multi-functional interface between user electronics

and the DMD, enabling high-speed pattern rates (up to 4 kHz binary), providing LED control and data formatting

for multiple input resolutions. The DLPC300 also outputs a trigger signal for synchronizing displayed patterns

with a camera, sensor, or other peripherals.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

DLP is a registered trademark of Texas Instruments.

DLP is a registered trademark of Texas Insturments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DLPC300

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION CONTINUED

The DLPC300 controller enables integration of the DLP 0.3 WVGA chipset into small-form-factor and low-cost

light steering applications. Example end equipments for the 0.3 WVGA chipset include 3D scanning or metrology

systems with structured light, interactive displays, chemical analyzers, medical instruments, and other end

equipments requiring spatial light modulation (or light steering and patterning).

The DLPC300 is one of the two devices in the 0.3 WVGA chipset (see Figure 1). The other device is the

DLP3000 DMD. After RESET is released, the DLPC300 controller reads the configuration information stored in

the serial FLASH. The configuration information is available for download from DLPR300 product folder. See the

0.3 WVGA Chip-Set data sheet (TI literature number DLPZ005) for further details.

DLPC300

DLP3000

DATA(14:0)

LOADB

Data

Interface

CMOS

MEMORY

ARRAY

TRC

MICROMIRROR

ARRAY

SCTRL

SCL

SDA

SAC_BUS

SAC_CLK

PARK

RESET

GPIO4_INTF

PLL_REFCLK

DRC_BUS

DRC_OE

Memory

Interface

DRC_STROBE

VOFFSET

VBIAS

VRESET

VDD10

VCC18

VCC_INTF

GND

VDD_PLL

RTN_PLL

VCC

VSS

Illumination

Interface

SPICLK

VCC

VSS

SPICSZ0

SPIDOUT

SPIDIN

Serial

FLASH

Camera

Trigger

CAMERA

TRIGGER

VCC_FLSH

Figure 1. Chipset Block Diagram

In DLP-based solutions, image data is 100% digital from the DLPC300 input port to the image on the DMD. The

image stays in digital form and is never converted into an analog signal. The DLPC300 processes the digital

input image and converts the data into a format needed by the DLP3000. The DLP3000 then steers light by

using binary pulse-width-modulation (PWM) for each pixel mirror. Refer to DLP3000 Data Sheet (TI literature

number DLPS022) for further details.

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Figure 2 is the DLPC300 functional block diagram. As part of the pixel processing functions, the DLPC300 offers

format conversion functions: chroma interpolation for 4:2:2 and 4:4:4, color-space conversion, and gamma

correction. The DLPC300 also offers several image-enhancement functions: programmable degamma, automatic

gain control, and image resizing. Additionally, the DLPC300 offers an artifact migration function through spatial-

temporal multiplexing (dithering). Finally, the DLPC300 offers the necessary functions to format the input data to

the DMD. The pixel processing functions allow the DLPC300 and DLP3000 to support a wide variety of

resolutions including NTSC, PAL, QVGA, QWVGA, VGA, and WVGA. The pixel processing functions can be

optionally bypassed with the native 608 × 684 pixel resolution.

When accurate pattern display is needed, the native 608x684 input resolution pattern has a one-to-one

association with the corresponding micromirror on the DLP3000. The DLPC300 enables high-speed display of

these patterns: up to 1440 Hz for binary (1-Bit) patterns and up to 120 Hz for 8-Bit patterns. This functionality is

well-suited for techniques such as structured light, rapid manufacturing, or digital exposure.

mDDR I/F

FORMAT CONVERSION

IMAGE ENHANCEMENT

ARTIFACT MIGRATION

DMD FORMATTING

– Chroma Interpolation

– Color Space Conversion

– Gamma Correction

– Degamma

– Automatic Gain Control

– Image Scaling

– Spatial-Temporal

Multiplexing

– Memory Management

– DMD I/F Processing

– Horiz and Vert Flip

– Display Rotation

24

15

RGB Data

DMD DDR Data

DMD DDR Control

RGB Control

Flash I/F

I²C Bus

DMD Reset Control

CONFIGURATION CONTROL

Reference Clock

RESET

SYSTEM CLOCK AND RESET SUPPORT

PARK

Figure 2. DLPC300 Functional Block Diagram

Commands can be input to the DLPC300 over an I²C interface.

The DLPC300 takes as input 16-, 18- or 24-bit RGB data at up to 60-Hz frame rate. This frame rate is composed

of three colors (red, green, and blue) with each color equally divided in the 60-Hz frame rate. Thus, each color

has a 5.55 ms time slot allocated. Because each color has 5-, 6-, or 8-bit depth, each color time slot is further

divided into bit-planes. A bit-plane is the 2-Dimensional arrangement of one-bit extracted from all the pixels in the

full color 2D image. See Figure 3.

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8 Red Bit-Planes

8-bit Red Image

8-bit Green Image

8-bit Blue Image

24-bit RGB Image

8 Green Bit-Planes

8 Blue Bit-Planes

Figure 3. Bit Slices

The length of each bit-plane in the time slot is weighted by the corresponding power of 2 of its binary

representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has

three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of all bit

planes in the time slot equal to 256. See Figure 4 for an illustration of this partition of the bits in a frame.

b1

bit 7

bit plane

b

3

bit 4

bit 5

bit 6

b0 b2

16

32

64

128

256

Figure 4. Bit Partition in a Frame for an 8-Bit Color

Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on

or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With the binary

pulse-width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror

is on. For a 24-bit RGB frame image inputted to the DLP300, the DLPC300 creates twenty-four bit planes, stores

them on the mDDR, and sends them to the DLP3000 DMD, one bit-plane at a time. Depending on the bit weight

of the bit-plane, the DLPC300 controls the time this bit-plane is exposed to light, controlling the intensity of the

bit-plane. To improve image quality in video frames, these bit-planes, time slots, and color frames are intertwined

and interleaved with spatial-temporal algorithms by the DLPC300.

For other applications where this image enhancement is not desired, the video processing algorithms can be

bypassed and replaced with a specific set of bit-planes. The bit-depth of the pattern is then allocated into the

corresponding time slots. Futhermore, an output trigger signal is also synchronized with these time slots to

indicate when the image is displayed. For structured light applications this mechanism provides the capability to

display a set of patterns and signal a camera to capture these patterns overlayed on an object.

4

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Figure 5 illustrates the bit planes and corresponding output triggers for 3-bit, 6-bit, and 12-bit RBG. Table 1

shows the allowed pattern combinations in relation to the bit depth of the pattern.

Figure 5. Bit Planes and Output Trigger for 3-, 6-, and 12-Bit RGB Input

Table 1. Allowed Pattern Combinations

NUMBER OF

IMAGES

PER FRAME

FRAME

RATE

External Video Sequence

PATTERN RATE

1 bit per pixel

2 bits per pixel

3 bits per pixel

24

12

24 × Frame Rate

12 × Frame Rate

15, 30, 40, or

60 Hz

15, 30, 45, or

60 Hz

8

6

8 × Frame Rate

6 × Frame Rate

4 bits per pixel

15, 30, 40, or

60 Hz

Monochrome

5 bits per pixel

6 bits per pixel

7 bits per pixel

4

4 × Frame Rate

15, 30, 45, or

60 Hz

15, 30, 40, or

60 Hz

3

2

8

3 × Frame Rate

2 × Frame Rate

8 × Frame Rate

8 bits per pixel

1-bit per color pixel

(3-bit per pixel)

2-bit per color pixel

(6-bit per pixel)

4

2

4 × Frame Rate

2 × Frame Rate

4-bit per color pixel

(12-bit per pixel)

15, 30, 45, or

60 Hz

RGB

5/6/5-bit RGB pixel

(16-bit per pixel)

6-bit per color pixel

(18-bit per pixel)

1

Frame Rate

8-bit per color pixel

(24-bit per pixel)

An optional FPGA (see the DLPR300 Software Folder) can be added to the system to manage the bit-planes

stored in the mDDR. The mDDR accomodates four 608 × 684 images of 24-bit RGB data or 96 bit-planes (24 bit-

planes × 4 images). By pre-loading the mDDR with these bit-planes, faster frame rates can be achieved. The 96

bit-plane buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces

the oldest stored bit-plane. Figure 6 shows the overall system with the optional FPGA.

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With this FPGA, the pattern frame rate can be calculated with the following equation:

(1)

where:

typical first bit plane load time = 215 µs

typical buffer rotate overhead = 135 µs

Table 2 shows the maximum pattern rate that can be achieved by using a single FPGA internal buffer in

continuous mode.

Table 2. Maximum Pattern Rate with Optional FPGA

MAXIMUM NUMBER OF

PATTERNS

MAXIMUM PATTERN

RATE

COLOR MODE

1 bit per pixel

96

48

32

24

16

12

4000 Hz

1100 Hz

590 Hz

550 Hz

450 Hz

365 Hz

210 Hz

115 Hz

2 bits per pixel

3 bits per pixel

4 bits per pixel

5 bits per pixel

6 bits per pixel

7 bits per pixel

8 bits per pixel

Monochrome

6

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Figure 6 illustrates the chipset with the optional FPGA.

Data

Interface

PARALLEL

RGB 1

DLPC300

DLP3000

DATA(14:0)

Data

Interface

Data

Interface

Optional

FPGA

LOADB

RD_BUF(1:0)

TRC

CMOS

MEMORY

ARRAY

FLASH

INTERFACE

BUFFER_SWAP

SCTRL

SAC_BUS

SCL

SDA

SAC_CLK

PARK

RESET

Serial

FLASH

GPIO4_INTF

PLL_REFCLK

DRC_BUS

DRC_OE

Memory

Interface

DRC_STROBE

MICROMIRROR

ARRAY

VOFFSET

VBIAS

VDD10

VCC18

VRESET

VCC_INTF

GND

VCC

VSS

VDD_PLL

RTN_PLL

SPICLK

Illumination

Interface

VCC

VSS

Serial

FLASH

SPICS0

SPIDOUT

SPIDIN

CAMERA

TRIGGER

Output

Trigger

VCC_FLSH

Figure 6. DLP3000 Chipset With Optional FPGA

The digital RGB input interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_INTF supply.

The SPI flash interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_FLSH supply. The

DMD and mDDR interface operates at 1.8 V nominal (VCC18). The core transistors operates at 1 V nominal

(VDD10). The analog PLL operates at 1 V nominal (VDD_PLL).

Typical System Application

A typical embedded system application using the DLPC300 is shown in Figure 7. In this configuration, the

DLPC300 controller supports a 24-bit parallel RGB, typical of LCD interfaces, from the main processor chip. This

system supports both still and motion video sources. For this configuration, the controller only supports periodic

sources. This is ideal for motion video sources, but can also be used for still images by maintaining periodic

syncs but only sending a frame of data when needed. The still image must be fully contained within a single

video frame and meet frame timing constraints. The DLPC300 refreshes the displayed image at the source frame

rate and repeats the last active frame for intervals in which no new frame has been received.

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Mobile DDR RAM

Optical

Sensor

ADDR(13)

DATA(16)

CTL(9)

Connectivity

(USB,

Ethernet, etc.)

PWM(3)

LED

Drivers

PCLK

LEDs

RGB_EN(3)

HSYNC, VSYNC,

PDM, DATAEN

Illumination

Optics

Volatile and

Main

Non-Volatile

Processor

Storage

LS_Ctrl(2)

LS_OUT

DATA(16/18)

I2C(2)

LED

Sensor

CLK, Control(3)

Data(15)

DLPC300

User

Interface

DLP3000

OSC

CTL

CLK, BSA, DAD Ctl(3)

FLASH

Data(2)

DMD™

Voltage

Supplies

BAT

PARK

Power Management

DC_IN

Figure 7. Typical Embedded System Block Diagram

Related Documents

DOCUMENT

TI LITERATURE NUMBER

DLP3000 0.3 WVGA Series 220 DMD data sheet

DLP^®0.3 WVGA Chipset

DLPS022

DLPZ005

DLPU004

DLPC300 Programmer's Guide

Device Part Number Nomenclature

Figure 8 provides a legend for reading the complete device name for any DLP device.

DLPC300ZVB

Package Type

Device Descriptor

Figure 8. Device Nomenclature

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Device Marking

The device marking consists of the fields shown in Figure 9.

DLP Device Name

DLP Logo

DLPC300ZVB

Trace Code

LLLLLLLL.ZZ

KOREAYYWW

Assembly Lot Number

Ball Material

G8

Pin #1 ID

Figure 9. Device Marking

SIGNAL FUNCTIONAL DESCRIPTIONS

This section describes the input/output characteristics of signals that interface to the DLPC300 by functional

groups. Table 3 includes I/O power and type characteristic references which are further described in subsequent

sections.

Table 3. Functional Pin Descriptions

TERMINAL

NAME

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

DLPC300 power-on reset. Self configuration starts when a

low-to-high transition is detected on this pin. All device

power and clocks must be stable and within

recommended operating conditions before this reset is de-

asserted. Note that the following 7 signals are high-

impedance while RESET is asserted:

RESET

J14

VCC18

I₁

Async

DMD_PWR_EN,

LEDDVR_ON,

LED_SEL_0,

LED_SEL_1, SPICLK, SPIDOUT, SPICS0

External pullups/-downs should be added as needed to

these signals to avoid floating inputs where these signals

are driven.

DMD park control (active-low). Is set high to enable

normal operation. PARK must be set high within 500 µs

after releasing RESET. PARK must be set low a minimum

of 500 µs before any power is to be removed from the

DLPC300 or DLP3000. See System Power-Up/Down

Sequence for more details.

PARK

B8

VCC_ INTF

I₃

Async

Reference clock crystal Input. If an external oscillator is

used in place of a crystal, then this pin should be used as

the oscillator input.

PLL_REFCLK_I

PLL_REFCLK_O

K15

J15

VCC18 (filter)

I₄

N/A

Reference clock crystal return. If an external oscillator is

used in place of a crystal, then this pin should be left

unconnected (floating).

O₁₄

FLASH INTERFACE⁽¹⁾

(1) Each device connected to the SPI bus must operate from VCC_FLSH.

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

SPICLK

A4

VCC_FLSH

O₂₄

I₂

N/A

SPI Master Clock output.

Serial data input from the external SPI slave FLASH

device.

SPIDIN

B4

A5

C6

SPICLK

SPICS0

O₂₄

SPI Master Chip Select 0 output. Active-low

Not used. Reserved for future use. Should be left

unconnected

RESERVED

Serial data output to the external SPI slave FLASH

device. This pin sends address and control information as

well as data when programming.

SPIDOUT

C5

VCC_FLSH

O₂₄

SPICLK

CONTROL

Not used. Reserved for future use. Should be pulled up to

VCC_INTF.

RESERVED0

B10

A10

VCC_ INTF

I₃

SCL

N/A

I²C clock. Bidirectional, open-drain signal. An external

pull-up is required. No I²C activity is permitted for a

minimum of 100 ms after PARK and RESET are set high.

SCL

SDA

B₃₈

I²C data. Bidirectional, open-drain signal. An external pull-

up is required.

C10

VCC_ INTF

B₃₈

SCL

General-purpose I/O 4. Primary usage is to indicate when

auto-initialization is complete (also called INIT-DONE,

which is when GPIO4 transitions high then low following

release of RESET) and to flag a detected error condition

GPIO4_INTF

RESERVED1

C9

B9

VCC_ INTF

B₃₄

Async

in the form of

a logic-high, pulsed interrupt flag

subsequent to INIT-DONE.

B₃₄

Reserved for future use. This pin should be left

unconnected.

PARALLEL RGB INTERFACE

PARALLEL RGB MODE

BT.656 I/F MODE

PCLK

D13

VCC_ INTF

I₃

N/A

Pixel clock⁽²⁾

Not used, pull-down

through an external

resistor.

Not used, pull-down through

an external resistor.

PDM

H15

B34

ASYNC

VSYNC

H14

H13

G15

G14

G13

F15

F14

F13

E15

E14

E13

D15

D14

C15

C14

C13

B15

B14

VCC_ INTF

I₃

ASYNC

PCLK

VSync⁽³⁾

Unused⁽⁴⁾

Data0⁽⁵⁾

(3)

HSYNC

HSync

DATEN

Data valid⁽²⁾

Data0⁽⁵⁾

PDATA[0]

PDATA[1]

PDATA[2]

PDATA[3]

PDATA[4]

PDATA[5]

PDATA[6]

PDATA[7]

PDATA[8]

PDATA[9]

PDATA[10]

PDATA[11]

PDATA[12]

PDATA[13]

PDATA[14]

(5)

Data1

(5)

Data2

(5)

Data3

Data4⁽⁵⁾

(5)

Data5

(5)

Data6

Data7⁽⁵⁾

Data8⁽⁵⁾

Data7⁽⁵⁾

Unused⁽⁴⁾

(5)

Data9

(5)

Data10

Data11⁽⁵⁾

(5)

Data12

(5)

Data13

(5)

Data14

(2) Pixel clock capture edge is SW programmable.

(3) VSYNC, HSYNC and data valid polarity is SW programmable.

(4) Unused inputs should be pulled down to ground through an external resistor.

(5) PDATA[23:0] bus mapping is pixel-format and source-mode dependent. See later sections for details.

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

PDATA[15]

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

A15

A14

B13

A13

C12

B12

A12

C11

B11

VCC_ INTF

I₃

PCLK

Data15⁽⁵⁾

Unused⁽⁴⁾

PDATA[16]

PDATA[17]

PDATA[18]

PDATA[19]

PDATA[20]

PDATA[21]

PDATA[22]

PDATA[23]

DMD INTERFACE

DMD_D0

Data16⁽⁵⁾

Data17⁽⁵⁾

Data18⁽⁵⁾

Data19⁽⁵⁾

Data20⁽⁵⁾

Data21⁽⁵⁾

Data22⁽⁵⁾

Data23⁽⁵⁾

M15

N14

M14

N15

P13

P14

P15

R15

DMD_D1

DMD_D2

DMD_D3

DMD_D4

DMD_D5

DMD data pins. DMD data pins are double data rate

(DDR) signals that are clocked on both edges of

DMD_D6

DMD_D7

VCC18

O₅₈

DMD_DCLK DMD_DCLK.

DMD_D8

R12

d

All 15 DMD data signals are use to interface to the

DLP3000.

DMD_D9

N11

P11

R11

N10

P10

R10

N13

DMD_D10

DMD_D11

DMD_D12

DMD_D13

DMD_D14

DMD_DCLK

VCC18

O₅₈

N/A

DMD data clock (DDR)

DMD data load signal (active-low). This signal requires an

external pullup to VCC18.

DMD_LOADB

R13

DMD_DCLK

DMD_SCTRL

DMD_TRC

R14

P12

VCC18

O₅₈

DMD_DCLK DMD data serial control signal

DMD_DCLK DMD data toggle rate control

DMD_SAC_CL DMD reset control bus data

K

DMD_DRC_BUS

L13

VCC18

O₅₈

DMD_SAC_CL DMD reset control bus strobe

K

DMD_DRC_STRB K13

DMD reset control enable (active-low). This signal

requires an external pullup to VCC18.

DMD_DRC_OE

M13

Async

DMD_SAC_CL DMD stepped-address control bus data

K

DMD_SAC_BUS

DMD_SAC_CLK

L15

L14

VCC18

O₅₈

N/A

DMD stepped-address control bus clock

DMD power regulator enable (active-high). This is an

active-high output that should be used to control DMD

V_OFFSET, V_BIAS, and V_RESETvoltages. DMD_PWR_EN is

driven high as a result of the PARK input signal being set

high. However, DMD_PWR_EN is held high for 500 µs

after the PARK input signal is set low before it is driven

low. A weak external pulldown resistor is recommended to

keep this signal at a known state during power-up reset.

DMD_PWR_EN

K14

VCC18

O₁₄

Async

SDRAM INTERFACE

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

D1

E1

P1

R3

R1

R2

A1

B1

A2

B2

D2

A3

P2

B3

D3

M3

P3

P4

R4

R5

J3

MEM_CLK_P

VCC18

O₇₄

N/A

mDDR memory, differential memory clock

MEM_CLK_N

MEM_A0

MEM_A1

MEM_A2

MEM_A3

MEM_A4

MEM_A5

MEM_A6

VCC18

O₆₄

MEM_CLK

mDDR memory, multiplexed row and column address

MEM_A7

MEM_A8

MEM_A9

MEM_A10

MEM_A11

MEM_A12

MEM_BA0

MEM_BA1

MEM_RAS

MEM_CAS

MEM_WE

MEM_CS

VCC18

O₆₄

MEM_CLK

mDDR memory, bank select

VCC18

O₆₄

B₆₄

O₆₄

B₆₄

O₆₄

MEM_CLK

N/A

mDDR memory, row address strobe (active-low)

mDDR memory, column address strobe (active-low)

mDDR memory, write enable (active-low)

mDDR memory, chip select (active-low)

MEM_CKE

MEM_LDQS

MEM_LDM

MEM_UDQS

MEM_UDM

MEM_DQ0

MEM_DQ1

MEM_DQ2

MEM_DQ3

MEM_DQ4

MEM_DQ5

MEM_DQ6

MEM_DQ7

MEM_DQ8

MEM_DQ9

MEM_DQ10

MEM_DQ11

MEM_DQ12

MEM_DQ13

MEM_DQ14

MEM_DQ15

C1

J2

mDDR memory, clock enable (active-high)

mDDR memory, lower byte, R/W data strobe

J1

MEM_LDQS mDDR memory, lower byte, write data mask

N/A mDDR memory, upper byte, R/W data strobe

G1

H1

N1

M2

M1

L3

MEM_UDQS mDDR memory, upper byte, write data mask

VCC18

B₆₄

MEM_LDQS mDDR memory, lower byte, bidirectional R/W data

L2

K2

L1

K1

H2

G2

H3

F3

F1

E2

F2

E3

VCC18

B₆₄

MEM_UDQS mDDR memory, upper byte, bidirectional R/W data

LED DRIVER INTERFACE

RPWM

N8

VCC18

O₁₄

Async

Red LED PWM signal used to control the LED current⁽⁶⁾

Green LED PWM signal used to control the LED

.

GPWM

P9

current⁽⁶⁾

.

(6) All LED PWM signals are forced high when LEDDRV_ON = 0, SW LED control is disabled, or the sequence stops.

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

BPWM

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

R8

VCC18

O₁₄

Async

Blue LED PWM signal used to control the LED current⁽⁶⁾

.

LED enable SELECT. Controlled by DMD sequence

timing.

LED_SEL(1:0) Selected LED

LED_SEL_0

R6

N6

00

01

10

11

None

Red

VCC18

O₁₄

Async

Green

Blue

LED_SEL_1

A decode circuit is required to decode the selected LED

enable.

LED driver master enable. Active-high output control to

external LED driver logic. This signal is driven high 100

ms after LED_ENABLE is driven high. Driven low

immediately when either LED_ENABLE or PARK is driven

low.

LEDDRV_ON

P7

VCC18

O₁₄

Async

LED enable (active-high input). A logic low on this signal

forces LEDDRV_ON low and LED_SEL(1:0) = 00b. These

signals are enabled 100 ms after LED_ENABLE

transitions from low to high.

LED_ENABLE

RED_EN

A11

VCC_ INTF

I₃

When not used with an optional FPGA, this signal should

be connected to the RED LED enable circuit. When

RED_EN is high, the red LED is enabled. When RED_EN

is low, the red LED is disabled. When used with the

optional FPGA, this signal should be pulled down to

ground through an external resistor. This signal is

configured as output and driven low when the DLPR300

serial FLASH PROM is loaded by the DLPC300, but the

signal is not enabled. To enable this output, a write to I²C

LED Enable and Buffer Control register.

B5

A7

C8

GREEN_EN

When not used with an optional FPGA, this signal should

be connected to the green LED enable circuit. When

GREEN_EN is high, the green LED is enabled. When

GREEN_EN is low, the green LED is disabled. When

used with the optional FPGA, this signal should be pulled

down to ground through an external resistor. This signal is

configured as output and driven low when the DLPR300

serial FLASH PROM is loaded by the DLPC300, but the

signal is not enabled. To enable this output, a write to I²C

LED Enable and Buffer Control register.

VCC18

B₁₈

Async

BLUE_EN

When not used with an optional FPGA, this signal should

be connected to the blue LED enable circuit. When

BLUE_EN is high, the blue LED is enabled. When

BLUE_EN is low, the blue LED is disabled. When used

with the optional FPGA, this signal should be pulled down

to ground through an external resistor. This signal is

configured as output and driven low when the DLPR300

serial FLASH PROM is loaded by the DLPC300, but the

signal is not enabled. To enable this output, a write to I²C

LED Enable and Buffer Control register.

WHITE POINT CORRECTION LIGHT SENSOR I/F

Successive approximation ADC comparator output

(DLPC300 input). Assumes a successive approximation

ADC is implemented with a light sensor and/or

thermocouple feeding one input of an external comparator

and the other side of the comparator driven from the

DLPC300 CMP_PWM pin. If not used, this signal should

be pulled down to ground .

CMP_OUT

A6

VCC18

I₁

Async

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

Successive approximation comparator pulse-width

modulation input. Supplies a PWM signal to drive the

successive approximation ADC comparator used in light-

to-voltage light sensor applications. Should be left

unconnected if this function is not used.

CMP_PWM

B7

VCC18

O₁₄

Async

Power control signal for the WPC light sensor and other

analog support circuits using the DLPC300 ADC.

Alternatively, it provides general purpose I/O to the WPC

microprocessor internal to the DLPC300. Should be left

unconnected if not used.

GPIO0_CMPPWR

P5

B₁₄

TRIGGER CONTROL

OUTPUT_TRIGGE

R

Trigger output. Indicates that a pattern or image is

displayed on the screen and is ready to be captured. With

an optional FPGA, this signal is connected to the FPGA

trigger input. This signal is configured as output and

driven low when the DLPR300 serial FLASH PROM is

loaded by the DLPC300, but the signal is not enabled. To

enable this output, a write to I²C LED Enable and Buffer

Control register. If not used, this signal should be pulled

down to ground through an external resistor.

N9

VCC18

B₁₈

Async

PATTERN CONTROL

PATTERN_INVER

T

Inverts the current 1-bit pattern held in the DLPC300

buffer. When used with an optional FPGA, this signal

should be connected to DMC_TRC of the FPGA. This

signal is configured as output and driven low when the

DLPR300 serial FLASH PROM is loaded by the

DLPC300, but the signal is not enabled. To enable this

output, a write to I²C LED Enable and Buffer Control

register. If not used, this signal should be pulled down to

ground through an external resistor.

C7

VCC18

B₁₈

Async

OPTIONAL FPGA BUFFER MANAGEMENT INTERFACES

14

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

RD_BUF0

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

When not used with an optional FPGA, this signal should

be pulled down to ground through an external resistor.

When used with an optional FPGA, this signal should be

connected to RD_PTR_SDC[0] of the FPGA. RD_BUFF1

and RD_BUFF0 indicate to the FPGA one of the four

buffers currently in use. This signal is configured as output

and driven low when the DLPR300 serial FLASH PROM is

loaded by the DLPC300, but the signal is not enabled. To

enable this output, a write to I²C LED Enable and Buffer

Control register.

B6

RD_BUF1/I2C_AD

DR_SEL

This signal is sampled when RESET is de-asserted to

choose between two pre-defined 7-bit I²C slave

Addresses. If I2C_ADDR_SEL signal is pulled-low, then

the DLPC300's I²C slave address is 1Bh. If

I2C_ADDR_SEL signal is pulled-high, then the DLPC300's

I²C slave address is 1Dh. When used with an optional

FPGA, this signal should be connected to

R9

VCC18

B₁₈

Async

RD_PTR_SDC[1] of the FPGA. RD_BUFF1 and

RD_BUFF0 indicate to the FPGA one of the four buffers

currently in use. This signal is set to input upon de-

assertion of RESET and configured as output and driven

low when the DLPR300 serial FLASH PROM is loaded by

the DLPC300, but the signal is not enabled. To enable this

output, a write to I²C LED Enable and Buffer Control

register.

BUFFER_SWAP

When not used with an optional FPGA, this signal should

be pulled down to ground through an external resistor.

When used with an optional FPGA, this signal should be

connected to BUFF_SWAP_SEQ of the FPGA.

BUFFER_SWAP indicates to the FPGA when to advance

the buffer. This signal is configured as output and driven

low when the DLPR300 serial FLASH PROM is loaded by

the DLPC300, but the signal is not enabled. To enable this

output, a write to I²C LED Enable and Buffer Control

register.

A8

CONTROLLER MANUFACTURER TEST SUPPORT

TEST_EN A9 VCC_INTF

Reserved for test. Should be connected directly to ground

on the PCB for normal operation. Includes weak internal

pulldown

I₃

N/A

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Table 3. Functional Pin Descriptions (continued)

TERMINAL

NAME

I/O

POWER

I/O

TYPE

CLK

SYSTEM

DESCRIPTION

NO.

BOARD LEVEL TEST AND DEBUG

JTAGTDI

JTAGTCK

JTAGTMS

JTAGTDO

P6

N5

N7

R7

VCC18

I₁

JTAGTCK

N/A

JTAG, serial data in. Includes weak internal pullup

JTAG, serial data clock. Includes weak internal pullup

JTAG, test mode select. Includes weak internal pullup

JTAG, serial data out

I₁

JTAGTCK

I₁₄

JTAG, RESET (active-low). Includes weak internal pullup.

This signal must be tied to ground, through an external

15-kΩ or less resistor for normal operation.

JTAGRSTZ

P8

VCC18

I₁

ASYNC

Power and Ground Pins

Power and ground connections to the DLPC300 are made up of the groupings shown in Table 4.

Table 4. Power and Ground Pin Descriptions⁽¹⁾

POWER

GROUP

PIN NUMBER(S)

DESCRIPTION

1-V core logic power supply (9)

D5, D9, F4, F12, J4,

J12, M6, M8, M11

VDD10

VDD_PLL

H12

1-V power supply for the internal PLL (1)

C4, D8, E4, G3, K3,

K12, L4, M5, M9, M12,

N4, N12

1.8-V power supply for all I/O other than the host/ video

interface and the SPI flash buses. (12)

VCC18

VCC_FLSH

VCC_INTF

D6

1.8- , 2.5- or 3.3-V power supply for SPI flash bus I/O. (1)

1.8- , 2.5- or 3.3-V power supply for all I/Os on the host/video

interface (includes I²C, PDATA, video syncs, PARK and

LED_ENABLE pins) (2)

D11, E12

D4, D7, D10, D12, G4,

GND

G12, H4, K4, L12, M4, Common ground (12)

M7, M10

Analog ground return for the PLL (This should be connected to

the common ground GND through a ferrite (1)

RTN_PLL

Reserved

J13

B10, C2, C3, C6, N2, No connects. Other signals can be routed through these pins

N3 (vs going around them) to ease routing if desired (6).

(1) 132 total signal I/O pins, 38 total power/ground pins, 6 total reserved pins

16

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ABSOLUTE MAXIMUM RATING

over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under "Absolute Maximum

Ratings” may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional

performance of the device at these or any other conditions beyond those indicated under “ Recommended Operating

Conditions” is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability.

PARAMETER

CONDITIONS

MIN

MAX UNIT

Electrical

VDD10

Voltage applied to VDD10⁽¹⁾

Voltage applied to VDD_PLL⁽¹⁾

Voltage applied to VCC18⁽¹⁾

Voltage applied to VCC_FLSH⁽¹⁾

Voltage applied to VCC_INTF⁽¹⁾

Voltage applied to all other input terminals⁽¹⁾

–0.5

-0.5

1.32

2.75

3.60

V

VDD_PLL

VCC18

VCC_FLSH

VCC_INTF

Environmental

T_J

Junction temperature

-30

-40

105

125

ºC

V

T_stg

ESD

Storage temperature

Electrostatic discharge immunity⁽²⁾

Human Body Model (HBM)

2000

500

Charged Device Model (CDM)

V

(1) All voltages referenced to VSS (ground).

(2) Tested in accordance with JESD22-A114-B Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM).

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this

data sheet is achieved when operating the device by the Recommended Operating Conditions. No level of performance is

implied when operating the device above or below the Recommended Operating Conditions limits.

PARAMETER

CONDITIONS

MIN

NOM

MAX UNIT

Electrical

VDD10

Core logic supply voltage

Analog PLL supply voltage

0.95

1

1.05

V

VDD_PLL

VCC18

I/O supply voltage (except FLASH and 24-

bit RGB interface signals)

1.71

1.8

1.89

VCC_FLSH

VCC_INTF

V_I

Configuration and control I/O supply voltage 1.8 V LVCMOS

1.71

2.375

3.135

1.71

1.8

2.5

3.3

1.8

2.5

3.3

1.89

2.625

3.465

1.89

V

2.5 V LVCMOS

3.3 V LVCMOS

24-bit RGB interface supply voltage

1.8 V LVCMOS

2.5 V LVCMOS

3.3 V LVCMOS

2.375

3.135

–0.3

2.625

3.465

Input voltage, all other pins

Output voltage, all other pins

VCCIO⁽¹⁾

+

0.3

VCCIO⁽¹⁾

V_O

0

V

Environmental

T_J

Operating junction temperature

–20

85

ºC

(1) VCCIO represents the actual supply voltage applied to the corresponding I/O.

POWER CONSUMPTION

Table 5 lists the typical current and power consumption of the individual supplies. This table assumes the

transfer of a 12 × 6 checkerboard image in 864 × 480 landscape mode at periodic 30 frames per second over the

Parallel RGB interface at 25ºC. Note that VCC_FLSH power is zero since the serial FLASH is only accessed

upon device configuration and not during normal operation.

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Table 5. Power Consumption

PARAMETER

VCC_INTF

CONDITIONS

MIN

NOM

0.1

0

MAX

UNIT

mW

1.8 V

VCC_FLSH

VCC18

2.5 V

1.8 V

1.0 V

50.8

2.8

39

VDD_PLL

VDD10

I/O Characteristics

Voltage and current characteristics for each I/O type signal listed in Table 3, Functional Pin Descriptions, are

summarized in Table 6. All inputs and outputs are LVCMOS.

Table 6. I/O Characteristics

PARAMETER

CONDITIONS

MIN

MAX UNIT

B₆₄inputs

V_CC= 1.8 V

1.19 V_CC+ 0.3

1.2 V_CC+ 0.3

1.7 V_CC+ 0.3

I₁, I₂, I₃, I₄, B₁₄, B₁₈, B₃₄, B₃₈

inputs

High-level input

voltage

V_IH

V

I₂, I₃, B₃₄, B₃₈inputs

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 1.8 V

2

V_CC+ 0.3

I₁, I₂, I₃, I₄, B₁₄, B₁₈, B₃₄, B₃₈

inputs

–0.3

0.5

Low-level input

voltage

B₆₄inputs

–0.3

1.25

1.53

1.7

0.57

0.7

V_IL

I₂, I₃, B₃₄, B₃₈inputs

O₁₄, O₂₄, B₁₄, B₃₄outputs

O₅₈outputs

V_CC= 2.5 V

V_CC= 3.3 V

0.8

I_OH= –2.58 mA

I_OH= = –6.41 mA

I_OH= = –5.15 mA

I_OH= = –4 mA

I_OH= = –6.2 mA

I_OH= –12.4 mA

I_OH= –10.57 mA

I_OH= –-5.29 mA

I_OL= 4 mA

V_CC= 1.8 V,

B₁₈, B₃₈outputs

O₆₄, O₇₄, B₆₄outputs

O₂₄, B₃₄outputs

B₃₈outputs

High-level output

voltage

V_OH

V

V_CC= 2.5 V,

V_CC= 3.3 V,

1.7

B₃₈outputs

2.4

B₃₈outputs

1.25

2.4

O₂₄, B₃₄outputs

O₆₄, O₇₄, B₆₄outputs

O₁₄, O₂₄, B₁₄, B₃₄outputs

B₁₈, B₃₈outputs

O₅₈outputs

0.19

0.4

0.7

0.4

I_OL= 2.89 mA

I_OL= 5.72 mA

I_OL= 5.78 mA

I_OL= 6.3 mA

V_CC= 1.8 V,

Low-level output

voltage

V_OL

V

O₂₄, B₃₄outputs

B₃₈outputs

V_CC= 2.5 V,

V_CC= 3.3 V,

I_OL= 12.7 mA

I_OL= 9.38 mA

I_OL= 18.68 mA

O₂₄, B₃₄outputs

B₃₈outputs

18

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Interface Timing Requirements

This section defines the timing requirements for the external interfaces for the DLPC300 Controller.

I²C Electrical Data/Timing

Table 7. I²C INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

0

MAX UNIT

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C output fall time

I²C bus free time between stop and start conditions

I²C start or repeat start condition setup

I²C start or repeat start condition hold

I²C stop condition setup

400

kHz

µs

ns

µs

pF

1

20

t_sds

t_sdh

t_icr

100

30

1.3

1

t_ocf

t_buf

t_sts

t_sth

t_sph

50 pF

200

1

Valid-data time

SCL low to SDA output valid

1

t_vd

Valid-data time of ACK condition

I²C bus capacitive load

ACK signal from SCL low to SDA (out) low

t_sch

0

100

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V

CC

R

L

= 1 kΩ

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 7

(MSB)

Data

Bit 0 Condition

(LSB)

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

PHL

t

icf

t

buf

t

sp

PLH

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

Figure 10. I²C Interface Load Circuit and Voltage Waveforms

Parallel Bus Interface

Parallel bus interface supports six data transfer formats:

•

16-bit RGB565

18-bit RGB666

18-bit 4:4:4 YCrCb666

24-bit RGB888

24-bit 4:4:4 YCrCb888

20

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•

16-bit 4:2:2 YCrCb (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)

The required PDATA(23:0) bus mapping for these 6 data transfer formats are as shown in Figure 11 .

Parallel Bus Mode – RGB 4:4:4 Source

PD ATA(15:0) – RGB565 Mapping to RGB888

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(15:0) of the Input Pixel data bus

BusAssignment Mapping

R4

R3

R2

R1

R0

G5 G4

G3 G2 G1

G0 B4

B3

B2

B1

B0

Data bit mapping on the DLPC300

PD ATA(17:0) – RGB666 Ma pping to RGB888

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(17:0) of the Input Pixel data bus

BusAssignment Mapping

R5

R4

R3

R2

R1

R0

G5 G4

G3 G2 G1

G0 B5

B4

B3

B2

B1

B0

Data bit mapping on the DLPC300

PD ATA(23:0) – RGB888 Ma pping

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(23:0) of the Input Pixel data bus

Bus Assignment Mapping

R7

R6

R5

R4

R3

R2

R1

R0

G7 G6 G5

G4 G3 G2

G1 G0 B7

B6

B5

B4

B3

B2

B1

B0

Data bit mapping on the DLPC300

Parallel Bus Mode - YCrCb 4:2:2 Source

PD ATA(23:0) – Cr/CbY880 Mapping

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(23:0) of the Input Pixel data bus

BusAssignment Mapping

Cr/

Cb

7

Cr/

Cb

6

Cr/

Cb

5

Cr/

Cb

4

Cr/

Cb

3

Cr/

Cb

2

Cr/

Cb

1

Cr/

Cb

0

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

n/a n/a

n/a n/a n/a

Data bit mapping on the pins of the DLPC300

Figure 11. PDATA Bus – Parallel I/F Mode Bit Mapping

The parallel bus interface complies with the standard graphics interface protocol, which includes a vertical sync

signal (VSYNC), horizontal sync signal (HSYNC), optional data-valid signal (DATAEN), a 24-bit data bus

(PDATA), and a pixel clock (PCLK). The polarities of both syncs are programmable, as is the active edge of the

clock. The relationship of these signals is shown in Figure 12. The data-valid signal (DATAEN) is optional, in that

the DLPC300 provides auto-framing parameters that can be programmed to define the data-valid window, based

on pixel and line counting relative to the horizontal and vertical syncs.

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1

Frame

t_{p _ vsw}

VSYNC

( This diagram assumes the VSYNC

active edge is the Rising edge)

t_{p _ vbp}

t _{p _vfp}

HSYNC

DATAEN

1

Line

t_{p _hsw}

HSYNC

(This diagram assumes the HSYNC

active edge is the Rising edge)

t_{p _}

t_{p_ hfp}

hbp

DATAEN

P

n -2

P

PDATA (23/15:0)

P 0

P 1

P 2

P 3

Pn

1

n-

PCLK

Figure 12. Parallel I/F Frame Timing

Table 8. Parallel Interface Frame Timing Requirements

PARAMETER

TEST CONDITIONS

50% reference points

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

Pulse duration – VSYNC high

1

lines

Vertical back porch – time from the leading edge of

VSYNC to the leading edge HSYNC for the first active

line⁽¹⁾

2

1

lines

Vertical front porch – time from the leading edge of the

HSYNC following the last active line in a frame to the

leading edge of VSYNC⁽¹⁾

50% reference points

t_{p_vfp}

Total vertical blanking – time from the leading edge of

HSYNC following the last active line of one frame to the

leading edge of HSYNC for the first active line in the next

frame. [This is equal to the sum of vertical back porch

(t_{p_vbp}) + vertical front porch (t_{p_vfp})]

t_{p_tvb}

12

lines

t_{p_hsw}

t_{p_hbp}

t_{p_hfp}

t_{p_thh}

Pulse duration – HSYNC high

50% reference points

4

128

PCLKs

Horizontal back porch – time from rising edge of HSYNC 50% reference points

to rising edge of DATAEN

Horizontal front porch – time from falling edge of

DATAEN to rising edge of HSYNC

50% reference points

8

PCLKs

Total horizontal blanking – sum of horizontal front and

back porches⁽²⁾

50% reference points

(1) The programmable parameter Vertical Sync Line Delay (I²C: 0x23) must be set such that: 6 – Vertical Front Porch (t_{p_vfp}) (min 0) ≤

Vertical Sync Line Delay ≤ Vertical Back Porch (t_{p_vbp}) -2 (max 15). The default value for Vertical Sync Line Delay is set to 5; thus, only

a Vertical Back Porch less than 7 requires potential action.

(2) Total horizontal blanking is driven by the maximum line rate for a given source, which is a function of resolution and orientation. See

Table 10 for the maximum line rate for each source/display combination. t_{p_thb}= Roundup[(1000 × f_clock)/LR] – APPL where f_clock= pixel

clock rate in MHz, LR = line rate in kHz and APPL is the number of active pixels per (horizontal) line. If t_{p_thb}is calculated to be less

than t_{p_hbp}+ t_{p_hfp}, then the pixel clock rate is too low or the line rate is too high and one or both must be adjusted.

22

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t

p_clkper

t

p_wi

p_wh

PCLK

t

p_h

t

p_su

Figure 13. Parallel and BT.656 I/F General Timing

Table 9. Parallel Interface General Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

1

MAX

33.5

UNIT

MHz

ns

f_clock

Clock frequency, PCLK

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

Clock period, PCLK

Clock jitter, PCLK⁽¹⁾

50% reference points

Maximum f_clock

29.85

1,000

Pulse duration low, PCLK

Pulse duration high, PCLK

50% reference points

10

ns

t_{p_wl}

Setup time – HSYNC, DATEN, PDATA(23:0) valid before

the active edge of PCLK⁽²⁾⁽³⁾

t_{p_su}

3

ns

Hold time – HSYNC, DATEN, PDATA(23:0) valid after the 50% reference points

active edge of PCLK⁽²⁾⁽³⁾

t_{p_h}

t_t

3

ns

Transition time – all signals

20% to 80% reference points

0.2

4

(1) Clock jitter (in ns) should be calculated using this formula: Jitter = [ 1/ f_clock– 28.35 ns ]. Setup and hold times must be met during clock

jitter.

(2) The active (capture) edge of PCLK for HSYNC, DATEN and PDATA(23:0) is SW programmable but defaults to the rising edge.

(3) See .

Table 10. Parallel I/F Maximum Supported Horizontal Line Rate

LANDSCAPE FORMAT

PORTRAIT FORMAT

PARALLEL BUS

SOURCE RESOLUTION

DMD

RESOLUTION

MAX LINE RATE

(kHz)

RESOLUTION

MAX LINE RATE

(kHz)

(H×V)

NSTC⁽¹⁾

PAL⁽¹⁾

720 × 240

720 × 288

320 × 240

427 × 240

640 × 430

640 × 480

720 × 480

752 × 480

800 × 480

852 × 480

853 × 480

854 × 480

864 × 480

608 × 684

17

20

17

30

34

48

Not supported

240 × 320

N/A

22

QVGA

QWVGA

240 × 427 (2)

430 × 640

27

3:2 VGA

45

4:3 VGA

480 × 640

45

WVGA-720

WVGA-752

WVGA-800

WVGA-852

WVGA-853

WVGA-854

WVGA-864

Optical test

480 × 720

51

0.3 WVGA

diamond

480 × 752

53

480 × 800

56

480 × 852

56

480 × 853

56

480 × 854

56

480 × 864

56

Not supported

N/A

(1) NTSC and PAL are assumed to be interlaced sources.

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BT.656 Interface

The DLPC300 controller input interface supports the industry standard BT.656 parallel video interface. See the

appropriate ITU-R BT.656 specification for detailed interface timing requirements.

Table 11. BT.565 I/F General Timing Requirements⁽¹⁾

PARAMETER

Clock frequency, PCLK

Clock period, PCLK

TEST CONDITIONS

MIN

1

MAX UNIT

f_clock

33.5

MHz

ns

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

50% reference points

29.85

1,000

Clock jitter, PCLK⁽²⁾

Maximum f_clock

Pulse duration low, PCLK

Pulse duration high, PCLK

50% reference points

10

ns

t_{p_wl}

Setup time – HSYNC, DATEN, PDATA(23:0)

valid before the active edge of PCLK

t_{p_su}

3

ns

Hold time – HSYNC, DATEN, PDATA(23:0) valid 50% reference points

after the active edge of PCLK

t_{p_h}

t_t

3

ns

Transition time – all signals

20% to 80% reference points

0.2

4

(1) The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard via PDATA(7:0) on the active edge of

PCLK (i.e., programmable) as shown in Figure 13.

(2) Clock jitter (in ns) should be calculated using this formula: Jitter = [ 1/ f_clock– 28.35 ns ]. Setup and hold times must be met during clock

jitter.

BT.656 data bits should be mapped to the DLPC300 PDATA bus as shown in Figure 14.

BT.656 Bus Mode - YCrCb 4:2:2 Source

PDATA(23:0) - BT.656 Mapping

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(7:0) of the Input Pixel data bus

Bus Assignment Mapping

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

n/a

Data bit mapping on the pins of the ASIC

Figure 14. PDATA Bus – BT.656 I/F Mode Bit Mapping

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Flash Memory Interface

DLPC300 uses an external 16-Mbit SPI serial flash slave memory device for configuration support. The

contents of this flash memory can be downloaded from the DLPC300 product folder. The DLPC300 uses a

single SPI interface, employing SPI mode 0 protocol, operating at a nominal frequency of 33.3 MHz.

When RESET is released, the DLPC300 reads the contents of the serial flash memory and executes an

auto-initialization routine. During this time, GPIO4_INTF is set high to indicate auto-initialization is busy.

Upon completion of the auto-initialization routine, the DLPC300 sets GPIO4_INTF low to indicate that the

auto-initialization routine successfully completed.

The DLPC300 should support any flash device that is compatible with standard SPI mode 0 protocol and meet

the timing requirement shown in Table 14. However, the DLPC300 does not support the normal (slow) read

opcode, and thus cannot automatically adapt protocol and clock rate based on the electronic signature ID of the

flash. The flash instead uses a fixed SPI clock and assumes certain attributes of the flash have been ensured by

PCB design. The DLPC300 also assumes the flash supports address auto-incrementing for all read operations.

The specific Instruction opcode and timing compatibility requirements for a DLPC300-compatible flash are listed

in Table 12.

Table 12. SPI Flash Instruction OpCode and Timing Compatibility Requirements

SPI FLASH COMMAND

OPCODE (hex)

ADDRESS BYTES

DUMMY BYTES

CLOCK RATE

Fast READ

(single output)

0x0B

3

1

33.3 MHz

All others

Can vary

33.3 MHz

The DLPC300 does not have any specific page, block or sector size requirements except that programming via

the I²C interface requires the use of page-mode programming. If, however, the user would like to dedicate a

portion of the serial flash for storing external data (such as calibration data) and access it through the DLPC300's

I²C interface, then the minimum sector size must be considered, as it drives minimum erase size. Note that use

of serial flash for storing external data may impact the number of features that can be supported in Table 13.

Note that the DLPC300 does not drive the HOLD (active-low hold) or WP (active-low write protect) pins on the

flash device, and thus these pins should be tied to a logic high on the PCB via an external pullup.

The DLPC300 supports 1.8-, 2.5- or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the

corresponding voltage. Table 13 contains a list of 1.8-, 2.5- and 3.3-V compatible SPI serial flash devices

supported by DLPC300.

Table 13. Compatible SPI Flash Device Options⁽¹⁾

TABLE 21

OPCODE AND

TIMING

SUPPLY

VOLTAGE

SUPPORTED

MIN CHIP

SELECT HIGH

TIME (t_CSH)

MAX FAST

READ FREQ

DENSITY

VENDOR

PART NUMBER

COMPATIBLE

4 Mbit

8 Mbit

16 Mbit

8 Mbit

Macronix

Winbond

Macronix

MX25U4035

MX25U8035

1.65 V–2 V

2.3 V–3.6 V

2.7 V–3.6 V

30 ns

40 MHz

50 MHz

66 MHz

Yes

W25Q16BLxxxx

MX25L8005ZUx-xxG

100 ns

(1) All the SPI devices listed have been verified to be compatible with DLPC300.

Table 14. Flash Interface Timing Requirements⁽¹⁾⁽²⁾

PARAMETER

Clock frequency, SPICLK⁽³⁾

TEST CONDITIONS

MIN

MAX

UNIT

f_clock

33.3266

33.34

MHz

(1) Standard SPI protocol is to transmit data on the falling edge of SPICLK and to capture data on the rising edge. The DLPC300 does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. DLPC300 hold capture timing has been set to facilitate reliable operation with standard external SPI

protocol devices.

(2) With the above output timing, DLPC300 provides the external SPI device 14-ns input setup and 14-ns input hold relative to the rising

edge of SPICLK.

(3) This range includes the 200 ppm of the external oscillator (but no jitter).

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Table 14. Flash Interface Timing Requirements⁽¹⁾⁽²⁾(continued)

PARAMETER

Clock period, SPICLK

TEST CONDITIONS

50% reference points

MIN

29.994

10

MAX

UNIT

ns

t_{p_clkper}

t_{p_wh}

t_{p_wl}

t_t

30.006

Pulse duration low, SPICLK

Pulse duration high, SPICLK

Transition time – all signals

50% reference points

20% to 80% reference points

50% reference points

ns

10

ns

0.2

4

ns

Setup time – SPIDIN valid before SPICLK falling

edge

t_{p_su}

10

0

ns

t_{p_h}

Hold time – SPIDIN valid after SPICLK falling edge 50% reference points

t_{p_clqv}

SPICLK clock low to output valid time – SPIDOUT 50% reference points

and SPICS0

1.0

t_{p_clqx}

SPICLK clock low output hold time – SPI_DOUT

and SPICS0

50% reference points

–1

ns

t

clkper

SPICLK

(ASIC Inputs)

t

wh

wi

t

p_h

t

p_su

SPIDIN

(ASIC Inputs)

t

p_ciqv

SPIDOUT, SPICS0

(ASIC Outputs)

t

p_cixv

Figure 15. Flash Interface Timing

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DMD Interface

The DLPC300 controller DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with

LVCMOS signaling.

Table 15. DMD Interface Timing Requirements⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

76.198

13.123

6.2

MAX

76.206

15

UNIT

MHz

ns

f_clock

t_{p_clkper}

t_{p_wh}

t_{p_wl}

t_t

Clock frequency, DMD_DCLK and DMD_SAC_CLK⁽²⁾

Clock period, DMD_DCLK and DMD_SAC_CLK

Pulse duration low, DMD_DCLK and DMD_SAC_CLK

50% reference points

ns

Pulse duration high, DMD_DCLK and DMD_SAC_CLK 50% reference points

6.2

ns

Transition time – all signals

20% to 80% reference points

0.3

2

ns

Output setup time – DMD_D(14:0), DMD_SCTRL,

DMD_LOADB and DMD_TRC relative to both rising and

falling edges of DMD_DCLK⁽³⁾⁽⁴⁾

50% reference points

t_{p_su}

1.5

ns

Output hold time – DMD_D(14:0), DMD_SCTRL,

DMD_LOADB and DMD_TRC signals relative to both

rising and falling edges of DMD_DCLK⁽³⁾⁽⁴⁾

t_{p_h}

1.5

DMD data skew – DMD_D(14:0), DMD_SCTRL,

DMD_LOADB, and DMD_TRC signals relative to each

other⁽⁵⁾

t_{p_d1_skew}

t_{p_clk_skew}

t_{p_d2_skew}

0.2

ns

Clock skew – DMD_DCLK and DMD_SAC_CLK relative 50% reference points

to each other

DAD/SAC data skew - DMD_SAC_BUS,

DMD_DRC_OE, DMD_DRC_BUS, and

50% reference points

DMD_DRC_STRB signals relative to DMD_SAC_CLK

(1) Assumes a 30-Ω series termination for all DMD interface signals

(2) This range includes the 200 ppm of the external oscillator (but no jitter).

(3) Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns

(4) Output setup/hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold need be considered in

system timing analysis.

(5) Assumes DMD data routing skew = 0.1 ns max

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t_{p_d1_skew}

DMD_D(14:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

t_{p_su}

t_{p_h}

DMD_DCLK

t_{p_wl}

t_{clk_skew}

t_{p_wh}

DMD_SAC_CLK

t_{p_d2_skew}

DMD_SAC_BUS

DMD_DRC_OE

DMD_DRC_BUS

DMD_DRC_STRB

Figure 16. DMD Interface Timing

Mobile DDR Memory Interface

The DLPC300 stores bit plane data in external mobile dual data rate memory (mDDR). The mDDR

compatibility requirements for the DLPC300 are:

•

SDRAM memory type: Mobile-DDR

Size: 128 Mbit minimum. DLPC300 can only address 128 Mb; use of larger memories requires bit A13 to

be grounded.

•

Organization: N × 16-bits wide with 4 equally sized banks

Burst length: 4

Refresh period: ≥ 64 ms

Speed Grade t_CK: 6 ns max

CAS latency (C_L), t_RCD,t_RPparameters (clocks): 3, 3, 3

Table 16 shows the mobile-DDR DRAM devices recommended for use with the DLPC300.

Table 16. Compatible Mobile DDR DRAM Device Options⁽⁶⁾

CAS LATENCY (C_L)

t_RCD,t_RP

PARAMETERS

(CLOCKS)

SPEED GRADE⁽⁸⁾

VENDOR

PART NUMBER⁽⁷⁾

SIZE

ORGANIZATION

(t_CK

)

Elpida

Samsung

Micron

EDD25163HBH-6ELS-F

K4X56163PN-FGC6

256 Mbit

16M × 16

6 ns

3, 3, 3

MT46H16M16LFBF-6IT:H

H5MS2562JFR-J3M

Hynix

The DLPC300 controller mobile DDR memory interface consists of a 16-bit wide, mobile DDR interface (i.e.,

LVCMOS signaling) operated at 133.33 MHz (nominal).

(6) All the SDRAM devices listed have been verified to be compatible with the DLPC300.

(7) These part numbers reflect a Pb-free package.

(8) A 6-ns speed grade corresponds to a 166-MHz mDDR device.

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Table 17. Mobile DDR Memory Interface Timing Requirements^(1)(2)(3)

PARAMETER

MIN

7500

2700

–2870

MAX

UNIT

ps

t_CYCLE

t_CH

Cycle-time reference

CK high pulse duration⁽⁴⁾

CK low pulse duration⁽⁴⁾

DQS high pulse duration⁽⁴⁾

DQS low pulse duration⁽⁴⁾

ps

t_CL

ps

t_DQSH

t_DQSL

t_WAC

t_QAC

ps

CK to address and control outputs active

CK to DQS output active

2870

200

ps

t_DAC

DQS to DQ and DM output active

Input (read) DQS and DQ skew⁽⁵⁾

–1225

1225

1000

ps

t_DQSRS

ps

(1) This includes the 200 ppm of the external oscillator (but no jitter).

(2) Output setup/hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered in

system timing analysis.

(3) Assumes a 30-Ω series termination on all signal lines

(4) CK and DQS pulse duration specs for the DLPC300 assume it is interfacing to a 166-MHz mDDR device. Even though these memories

are only operated at 133.33 MHz, according to memory vendors, the rated t_CKspec (i.e., 6 ns) can be applied to determine minimum CK

and DQS pulse duration requirements to the memory.

(5) Note that DQS must be within the t_DQSRSread data-skew window but need not be centered.

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tCYCLE

MEM_CK_P

MEM_CK_N

tCH

tCL

MEM_ADDRS (12:0)

MEM_BA (1:0)

MEM_RASZ

MEM_CASZ

MEM_WES

MEM_CSZ

MEM_CKE

tWAC

mDDR Memory Address and Control Timing

tCYCLE

MEM_CK_P

MEM_CK_N

tCH

tCL

tQAC

(tDQSCK)

tCYCLE

tDQSH

tDQSL

MEM_xDQS

tDAC

MEM_xDQ(7:0)

MEM_xDQ(15:8)

tDAC

MEM_xDM

mDDR Memory Write Data Timing

tCYCLE

MEM_xDQS

tDQSH

tDQSL

MEM_xDQ(first)

MEM_xDQ(last)

tDQSRS

MEM_xDQ(7:0)

Data Valid Window

mDDR Memory Read Data Timing

Figure 17. Mobile DDR Memory Interface Timing

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Power-Up Initialization Sequence

It’s assumed that an external power monitor holds the DLPC300 in system reset during power up. It must do this

by driving RESET to a logic-low state. It should continue to assert system reset until all controller voltages have

reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time,

most controller outputs are driven to an inactive state and all bidirectional signals are configured as inputs to

avoid contention. Controller outputs that are not driven to an inactive state are in the high-impedance state.

These include DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0.

Once power is stable and the PLL_REFCLK clock input to the DLPC300 is stable, then RESET should be

deactivated (set to a logic high). The DLPC300 then performs a power-up initialization routine that first locks its

PLL followed by loading self-configuration data from the external flash. On release of RESET, all DLPC300 I/Os

become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to indicate

that the auto initialization routine is in progress. On completion of the auto-initialization routine, the DLPC300

drives GPIO4_INTF low to signal INITIALIZATION DONE (also called INIT DONE).

Note that the host processor can start sending standard I²C commands after GPIO4 (INIT_DONE) goes low, or a

100-ms timer expires in the host processor, whichever is earlier.

An active-high pulse on GPIO 4_INTF following the initialization

period indicates an error condition has been detected. The

source of the error is reported in the system status.

RESET

100 m s max

(ERR IRQ)

(INIT_BUSY)

GPIO 4_INFT

5ms max

0ms min

3

ms min

I²C access to DLPC300 should not start until GPIO 4_INTF

(INIT_BUSY flag) goes low (this should occur within 100 ms

from the release of RESET if the Motor Control function is

not used. If Motor Control is used, this may take several

seconds.)

GPIO 4_INTF is driven high within 5 ms

after RESET is released to indicate

Auto-Initialization is busy.

I²C or DBI-C traffic

(SCL, SDA, CSZ)

Figure 18. Initialization Timeline

System Power-Up/Down Sequence

Although the DLPC300 requires an array of power supply voltages, (e.g., VDD, VDD_PLL, VCC_18, VCC_FLSH,

VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing to avoid damaging

the DLPC300. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time

between powering up or powering down the different supplies feeding the DLPC300. Note, however, that it is not

uncommon for there to be power-sequencing requirements for the devices that share the supplies with the

DLPC300.

Although there is no risk of damaging the DLPC300 as a result of a given power sequence, from a functional

standpoint there is one specific power-sequencing recommendation to ensure proper operation. In particular, all

controller power should be applied and allowed to reach minimum specified voltage levels before RESET is de-

asserted to ensure proper power-up initialization is performed. All I/O power should remain applied as long as 1-

V core power is applied and RESET is de-asserted.

Note that when VDD10 core power is applied but I/O power is not applied, additional leakage current may be

drawn.

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VDD10

Point at which ALL supplies

reach 95% of the their

specified nominal value

VDD_PLL

PARK must be set high within

500 μs after RESET is released

to support Auto-initialization.

VCC_INTF (1.8 V–3.3 V)

VCC_FLSH (1.8 V–3.3 V)

VCC18

PARK

VCC18 must remain active for a minimum of

100 ms after DMD_PWR_EN is de-asserted to

satisfy DMD power sequence requirements.

Per DMD

Power

Sequencing

Requirement

500 μs Max

DMD_PWR_EN

(ASIC Output Signal)

500 ±5 μs

PARK must be set

low a minimum of

500 μs before any

power is removed,

before PLL_REFCLK

is stopped, and

before RESET is

asserted to allow

time for the DMD

mirrors to be parked.

PLL_REFCLK

PLL_REFCLK may

be active before

power is applied.

Tstable

RESET

100 ms Min

I²C

(SCL, SDA)

GPIO 4_INTF will be

driven high shortly after

RESET is released to

indicate Auto-

500 μs

Min

0 μs

500 μs

Min

Initialization is Busy

GPIO 4_INTF

(INIT_BUSY)

I²C access CAN start immediately after GPIO 4_INTF (INIT_BUSY flag)

goes low (this should occur within 100 ms from the release of RESET

if the Motor Control function is not used. If Motor Control is used, it

may take several seconds.)

The minimum requirement to set RESET = 1 is any time

after PLL_REFCLK becomes stable. For external

oscillator applications, this is oscillator-dependent; for

crystal applications, it is crystal-dependent

.

Figure 19. Power-Up/Down Timing

System Power I/O State Considerations

Note that:

•

If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non fail-safe) and non-

mDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state.

If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output

signals associated with these inactive I/O supplies are in a high-impedance state.

If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals

associated with these inactive I/O supplies are in a high-impedance state.

If VDD10 Core power is applied but VCC18 I/O power is not applied,, then all mDDR (non fail-safe) and non-

mDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state;

however, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance

state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes.

32

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Power-Good (PARK) Support

The PARK signal is defined to be an early warning signal that should alert the controller 500 µs before dc supply

voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the

integrity of future operation. Note that the reference clock should continue to run and RESET should remain de-

activated for at least 500 µs after PARK has been deactivated (set to a logic low) to allow the park operation to

complete.

Hot-Plug Usage

Note that the DLPC300 provides fail-safe I/O on all host-interface signal (signals powered by VCC_INTF). This

allows these inputs to be driven high even when no I/O power is applied. Under this condition, the DLPC300

does not load the input signal nor draw excessive current that could degrade controller reliability. Thus for

example, the I²C bus from the host to other components would not be affected by powering off VCC_INTF to the

DLPC300. Note that weak pullups or pulldowns are recommended on signals feeding back to the host to avoid

floating inputs.

Maximum Signal Transition Time

Unless otherwise noted, the maximum recommended 20%–80% rise/fall time to avoid input buffer oscillation is

10 ns. This applies to all DLPC300 input signals. Note, however, that the PARK input signal includes an

additional small digital filter that ignores any input-buffer transitions caused by a slower rise/ fall time for up to

150 ns.

Configuration Control

The primary configuration control mechanism for the DLPC300 is the I²C interface. See the DLPC300 Software

Programmer's Guide, TI Literature Number DLPU004, for details on how to configure and control the DLPC300.

Thermal Considerations

The underlying thermal limitation for the DLPC300 is that the maximum operating junction temperature (T_J) not

be exceeded (see Recommended Operating Conditions). This temperature is dependent on operating ambient

temperature, airflow, PCB design (including the component layout density and the amount of copper used),

power dissipation of the DLPC300, and power dissipation of surrounding components. The DLPC300 package is

designed primarily to extract heat through the power and ground planes of the PCB, thus copper content and

airflow over the PCB are important factors.

Table 18. Package Thermal Resistance

PARAMETER

MIN

NOM

MAX

19.52

64.96

UNIT

ºC/W

R_θJC

R_θJA

Thermal resistance, junction-to-case

Thermal resistance, junction-to-air, with no forced airflow

External Clock Input Crystal Oscillator

The DLPC300 requires an external reference clock to feed its internal PLL. This reference may be supplied via a

crystal or oscillator. The DLPC300 accepts a reference clock of 16.667 MHz with a maximum frequency variation

of 200 ppm (including aging, temperature and trim component variation). When a crystal is used, several discrete

components are also required as shown in Figure 20.

PLL_REFCLK_I

PLL_REFCLK_O

CL = Crystal load capacitance (Farads)

CL1 = 2 * (CL – Cstray_pll_refclk_i)

CL2 = 2 * (CL – Cstray_pll_refclk_o)

R

FB

Where:

R

S

Cstray_pll_refclk_i = Sum of package and PCB srtay

capacitance at the crystal pin associated with the ASIC

pin pll_refclk_i.

Crystal

Cstray_pll_refclk_o = Sum of package and PCB srtay

capacitance at the crystal pin associated with the ASIC

pin pll_refclk_o.

C

L2

L1

Figure 20. Recommended Crystal Oscillator Configuration

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Table 19. Crystal Port Electrical Characteristics

PARAMETER

NOM

4.5

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

4.5

pF

Table 20. Recommended Crystal Configuration

PARAMETER

RECOMMENDED

Parallel resonant

UNIT

Crystal circuit configuration

Crystal type

Fundamental (first harmonic)

16.667

Crystal nominal frequency

MHz

PPM

Crystal frequency tolerance (including accuracy, temperature, aging and trim

sensitivity)

±200

Crystal drive level

100 max

uW

Ω

Crystal equivalent series resistance (ESR)

Crystal load

80 max

12

100

pF

Ω

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

PCB layout

1

MΩ

pF

See Figure 20

A ground isolation ring around the crystal is

recommended

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC300

controller, and the PLL_REFCLK_O pins should be left unconnected. The benefit of an oscillator is that it can be

made to provide a spread-spectrum clock that reduces EMI. Note, however, that the DLPC300 can only accept

between 0% to –2% spreading (i.e., down spreading only) with a modulation frequency between 20kHz and 65

KHz and a triangular waveform.

Similar to the crystal option, the oscillator input frequency is limited to the 16.667 MHz.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.

PLL

The DLPC300 contains one internal PLL that has a dedicated analog supply (VDD_PLL , VSS_PLL). As a

minimum, the VDD_PLL power and VSS_PLL ground pins should be isolated using an RC-filter consisting of two

50-Ω series ferrites and two shunt capacitors (to widen the spectrum of noise absorption). It is recommended that

one capacitor be a 0.1-µf capacitor and the other be a 0.01-µf capacitor. All four components should be placed

as close to the controller as possible, but it is especially important to keep the leads of the high-frequency

capacitors as short as possible. Note that both capacitors should be connected across VDD_PLL and VSS_PLL

on the controller side of the ferrites.

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLL must be a single trace from the DLPC300 to both capacitors and then through the

series ferrites to the power source. The power and ground traces should be as short as possible, parallel to each

other and as close as possible to each other.

34

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Signal VIA

PCB Pad

ASIC Pad

11

VIA to Common Analog

Digital Board Power Plane

VIA to Common Analog

Digital Board Ground Plane

12

13

14

15

A

Local

Decoupling

for the PLL

Digital Supply

G

VDD_

PLL

1.0V

PWR

Signal

H

J

FB

PLL_

REF

CLK_O

VSS_

PLL

VDD

GND

PLL_

REF

CLK_I

Crystal Circuit

Signal

K

Figure 21. PLL Filter Layout

General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, it is recommended that unused

controller input pins be tied through a pullup resistor to its associated power supply or through a pulldown to

ground. For controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external

pullup/pulldown unless specifically recommended. Note that internal pullup and pulldown resistors are weak and

should not be expected to drive the external line. The DLPC300 implements very few internal resistors and these

are noted in the pin list.

Unused output-only pins can be left open.

When possible, it is recommended that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then they should be

pulled up (or down) using an appropriate resistor.

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REVISION HISTORY

Changes from Original (January 2012) to Revision A

Page

•

Changed Features Item From: Supports Input Resolutions 608x684, 854x480 (WVGA), 640x480 (VGA), 320x240

(QVGA) To: Supports Input Resolutions 608x684, 864x480, 854x480 (WVGA), 640x480 (VGA), 320x240 (QVGA) ......... 1

Changed ............................................................................................................................................................................... 6

Changed unit values from ms to µs in Table 7. .................................................................................................................. 19

•

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型号：	DLPC300_15
厂家：	TEXAS INSTRUMENTS
描述：	DLP Digital Controller
文件：	总39页 (文件大小：726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLPC300_15 [TI]

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