DLPC7540_技术文档

DLPC7540

DLPS206 – MAY 2021

DLPC7540 High Resolution Controller

•

JTAG boundary scan test support

LED, RGB Laser and Laser Phosphor illuminations

1 Features

•

DLPC7540 controller using DLP471TE,

DLP471NE, DLP650TE or DLP651NE digital

micromirror device (DMD) supports

– Up to 4K UHD at 60 Hz

– Up to 1080p at 240 Hz (2D) and 120 Hz (3D)

Provides single V-by-One^®HS video input port

with one, two, four, or eight lanes

– Up to 600 MHz Pixel clock support

– Up to 3.0 Gbps input transmission rate

Two OpenLDI (FPD-Link I) video input ports with

6-lanes (5 data) per port

2 Applications

•

Enterprise projector

Laser TV

Smart projector

Digital signage

•

3 Description

The DLPC7540 is a digital display controller for the

4K UHD and 1080p display chipsets, which comprises

of DLPC7540 controller, DLP471TE, DLP471NE,

DLP650TE or DLP651NE DMDs and DLPA100

Power and Motor driver. This solution targets display

systems that require high resolution and high

brightness in a small form factor. To ensure reliable

operation, the DLPC7540 controller must always be

used with the DLP471TE, DLP471NE, DLP650TE

or DLP651NE DMDs and the DLPA100 power

management integrated circuit in each application.

•

Input formats supported

– RGB, YCbCr and ICtCp

– 4:4:4, 4:2:2, 4:2:0

Internal Arm Cortex-R4F processor with FPU

•

– 88 configurable GPIOs

– Programmable PWM generator

– Programmable capture and delay timers

– USB 2.0 high-speed OTG controller

– SPI primary/secondary controllers

– I²C primary/secondary controllers

– UART and interrupt controllers

Warping engine

– Improved 1D, 2D and 3D keystone correction

– Optical distortion correction (radial and lateral

color distortion e.g. for short throw )

– Warping (multi-point manual warp and full warp

map access 62x32 points)

– Blending (manual blending and full bleding map

access 63x32 points)

Additional image processing

– DynamicBlack

– TI DLP^®BrilliantColor™

Device Information⁽¹⁾⁽²⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DLPC7540ZDC

P-HBGA (676) 31.00 mm × 31.00 mm

(1) For all available packages, see the orderable addendum.

(2) Includes embedded heat slug.

LS_Interface

HSSI Macro A Data Pair

8

DMD DCLKA

HSSI Macro B Data Pair

DLP471TE

8

Or

DLP471NE

Or

DMD DCLKB

DLPC7540

Display

Controller

Vx1

DLP650TE

Or

DLP651NE

HSSI DMD

V

OFFSET

BIAS

– HDR10 (PQ and HLG) support

– Frame rate conversion

– Color coordinate adjustment

SPI

Power

Management

RESET

– White color temperature adjustment

– Programmable degamma

1.8 V

– Spatial-temporal multiplexing

– Integrated support for 3-D display

Splash screen display and capture

Integrated 2G-bit frame memory eliminates need

for external high-speed memory

External memory support

VREG

•

Figure 3-1. Typical Standalone System

•

– Parallel flash for µP and PWM sequences

– Secondary flash for Splash Capture, Warping

System control

•

– DMD power and reset driver control

– DMD horizontal and vertical image flip

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLPC7540

DLPS206 – MAY 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications................................................................ 23

6.1 Absolute Maximum Ratings...................................... 23

6.2 ESD Ratings............................................................. 23

6.3 Recommended Operating Conditions.......................24

6.4 Thermal Information..................................................26

6.5 Power Electrical Characteristics............................... 27

6.6 Pin Electrical Characteristics.................................... 29

6.7 DMD HSSI Electrical Characteristics........................32

6.8 DMD Low-Speed LVDS Electrical Characteristics.... 32

6.9 V-by-One Interface Electrical Characteristics........... 33

6.10 FPD-Link LVDS Electrical Characteristics.............. 33

6.11 USB Electrical Characteristics ............................... 33

6.12 System Oscillator Timing Requirements.................35

6.13 Power Supply and Reset Timing Requirements..... 36

6.14 DMD HSSI Timing Requirements........................... 40

6.15 DMD Low-Speed LVDS Timing Requirements....... 41

6.16 V-by-One Interface General Timing

6.22 JTAG Boundary Scan Interface Timing

Requirements (Debug Only)........................................50

6.23 JTAG ARM Multi-Ice Interface Timing

Requirements (Debug Only)........................................51

6.24 Multi-Trace ETM Interface Timing Requirements... 52

7 Detailed Description......................................................53

7.1 Overview...................................................................53

7.2 Functional Block Diagram.........................................53

7.3 Feature Description...................................................54

7.4 Device Operational Modes........................................77

8 Application and Implementation..................................78

8.1 Application Information............................................. 78

8.2 Typical Application.................................................... 79

9 Power Supply Recommendations................................81

9.1 Power Supply Management......................................81

9.2 Hot Plug Usage.........................................................81

9.3 Power Supplies for Unused Input Source

Interfaces.....................................................................81

9.4 Power Supplies.........................................................81

10 Layout...........................................................................82

10.1 Layout Guidelines................................................... 82

10.2 Thermal Considerations..........................................95

11 Device and Documentation Support..........................96

11.1 Device Support........................................................96

11.2 Trademarks............................................................. 97

11.3 Electrostatic Discharge Caution..............................97

11.4 Glossary..................................................................97

12 Mechanical, Packaging, and Orderable

Requirements .............................................................41

6.17 FPD-Link Interface General Timing

Requirements..............................................................43

6.18 Source Frame Timing Requirements...................... 45

6.19 Synchronous Serial Port Interface Timing

Requirements .............................................................46

6.20 Master and Slave I²C Interface Timing

Information.................................................................... 99

12.1 Package Option Addendum..................................100

Requirements .............................................................49

6.21 Programmable Output Clock Timing

Requirements..............................................................49

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

May 2021

*

Initial Release

2

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5 Pin Configuration and Functions

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 1617 18 19 20 21 22 23 24 25 26 27 28 29 30

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

Figure 5-1. ZDC Package 676-Pin PBGA Top View

Table 5-1. Initialization, Board Level Test, and Debug

I/O

DESCRIPTION

(1)

NAME

NO.

Power-On Sense: Signal provided from external voltage monitoring circuit

('0' = All Controller supply voltages not at valid level, '1' = All Controller supply voltages have reached 90%

specified minimum voltage)

Drive this signal to inactive (low) after the falling edge of PWRGOOD as specified. See Section 6.13 for

specific timing requirements as well as the required power up and power down sequence.

This pin includes hysteresis

POSENSE

AE27

I₈

Power Good: Signal provided from external power supply of voltage monitor

A high value indicates all power is within operating voltage specifications and the system is safe to exit

its reset state. A transition from high to low indicates that the Controller or DMD supply voltage drops

below its rated minimum level. This transition must occur prior to the supply voltage dropping per the timing

specified, as this is an early warning of an imminent power loss condition.

This warning is required to enhance long term DMD reliability. When PWRGOOD goes low for the

PWRGOOD

AG30

I₈specified minimum time, a DMD park and full Controller reset are performed, protecting the DMD. Note

that both Controller and DMD supply voltages must be within operating voltage levels to successfully

execute the DMD park. The minimum PWRGOOD de-assertion time is used to protect the system input

from glitches. When PWRGOOD is low, the Controller is held in its reset state.

See Section 6.13 for specific timing requirements as well as the required power up and power down

sequence.

This pin includes hysteresis

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Table 5-1. Initialization, Board Level Test, and Debug (continued)

I/O

DESCRIPTION

(1)

NAME

NO.

External Reset: General purpose reset output

('0' = Reset, '1' = Normal Operation)

This output is asserted low immediately upon POSENSE being asserted low, and remains low while

O₈POSENSE remains low. This signal remains low after POSENSE is set high, until released by software.

This signal is also asserted low approximately 5 µs after the detection of PWRGOOD going low, or any

internally generated reset. In all cases, this signal remains active low for a minimum of 2ms.

Note: this signal can also be independently driven via software register.

EXT_ARSTZ

AF29

Color Wheel Motor Controller Reset: Color wheel motor controller reset output

('0' = Reset, '1' = Normal Operation)

This output is asserted low immediately upon POSENSE being asserted low, and remains low while

O₈POSENSE remains low. This signal remains low after POSENSE is set high, until released by software.

This signal is also asserted low approximately 5 µs after the detection of PWRGOOD going low, or any

internally generated reset. In all cases, this signal remains active low for a minimum of 2ms.

Note: this signal can also be independently driven via software register.

MTR_ARSTZ

AF27

AK19

JTAG, ARM-ICE, and CPU MBIST Serial Data Clock.

This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only)

operation

TCK

I₈

Includes a weak internal pulldown.

JTAG Test Mode Select

Includes weak internal pullup.

TMS1

TMS2

TMS3

AH20

AJ20

AK20

I₈

ARM-ICE Test Mode Select

For normal operation, this pin must be left open or unconnected. Includes a weak internal pullup.

I₈

CPU MBIST Test Mode Select

For normal operation this pin must be left open or unconnected. Includes a weak internal pullup.

I₈

JTAG, ARM-ICE, and CPU MBIST Reset.

This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only)

operation.

TRSTZ

AG21

I₈For normal operation, this pin must be pulled to ground through an external resistor with value 8 kΩ or

less. Failure to pull this pin low during normal operation causes start-up and initialization problems.

For JTAG Boundary Scan, ARM-ICE Debug operation, or CPU MBIST, this pin must be pulled-up or left

disconnected. Includes a weak internal pullup and Hysteresis.

JTAG, ARM-ICE, and CPU MBIST: Serial Data In

Includes weak internal pullup.

TDI

AG20

AG19

AH19

I₈

TDO1

TDO2

O₈JTAG Serial Data Out.

ARM-ICE Serial Data Out

For normal operation, this pin must be left open or unconnected.

O₈

CPU MBIST Serial Data Out

For normal operation, this pin must be left open or unconnected.

TDO3

AJ19

C30

D30

O₈

ETM_TRACE

CLK

O₈TI internal use. Must be left unconnected. (Clock for Trace debug)

ETM_TRACE

CTL

O₈TI internal use. Must be left unconnected. (Control for Trace Debug)

IC Tristate Enable (Active high)

Asserting this signal transitions all outputs into tristate (except for the JTAG interface).

Includes a weak internal pulldown, however, an external pulldown is recommended for added protection.

Also includes hysteresis.

ICTSEN

ICTSE

K26

M26

I₈

TI internal use. Includes a weak internal pulldown, however, an external pulldown is recommended for

added protection. Also includes hysteresis.

I₈

Test pin 0

This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted

B₈below) with a value of ≤ 10 kΩ.

TSTPT_0

E29

Tri-stated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in

Section 7.3.8.

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Table 5-1. Initialization, Board Level Test, and Debug (continued)

I/O

DESCRIPTION

(1)

NAME

NO.

Test pin 1

This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted

B₈below) with a value of ≤ 10 kΩ.

TSTPT_1

E30

Tri-stated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in

Section 7.3.8.

Test pin 2

This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted

B₈below) with a value of ≤ 10 kΩ.

TSTPT_2

TSTPT_3

F26

F27

Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in

Section 7.3.8.

Test pin 3

This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted

B₈below) with a value of ≤ 10 kΩ.

Tri-stated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in

Section 7.3.8.

Test pin 4

This pin requires an external pulldown resistor (≤ 10 kΩ).

Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in

Section 7.3.8.

TSTPT_4

TSTPT_5

TSTPT_6

TSTPT_7

F28

F29

G26

B₈

Test pin 5

This pin requires an external pulldown resistor (≤ 10 kΩ).

Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in

Section 7.3.8.

B₈

Test pin 6

This pin requires an external pulldown resistor (≤ 10 kΩ).

Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in

Section 7.3.8.

B₈

Test pin 7

This pin requires an external pulldown resistor (≤ 10 kΩ).

Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in

Section 7.3.8.

G28

L26

B₈

Manufacturing test enable signal.

I₈This signal must be connected directly to ground on the PCB for normal operation.

Includes weak internal pulldown and hysteresis.

HWTEST_EN

(1) See Table 5-13 for more information on I/O definitions.

Table 5-2. Analog Front End (Not Supported in DLPC7540)

I/O

DESCRIPTION

(1)

NAME

NO.

K2

K3

K4

K5

J1

AFE_ARSTZ

AFE_CLK

O₈Reserved.

I₈Reserved.

AFE_IRQ

ALF_VSYNC

ALF_HSYNC

ALF_CSYNC

J2

(1) See Table 5-13 for more information on I/O definitions.

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Table 5-3. V-by-One Interface Input Data and Control

I/O

DESCRIPTION ^{(2) (3)}

(1)

NAME

NO.

VX1_DATA0_P

VX1_DATA0_N

VX1_DATA1_P

VX1_DATA1_N

VX1_DATA2_P

VX1_DATA2_N

VX1_DATA3_P

VX1_DATA3_N

VX1_DATA4_P

VX1_DATA4_N

VX1_DATA5_P

VX1_DATA5_N

VX1_DATA6_P

VX1_DATA6_N

VX1_DATA7_P

VX1_DATA7_N

C18

D18

A19

B19

C20

D20

A21

B21

C22

D22

A23

B23

C24

D24

A25

B25

I₁V-by-One interface data lanes.

V-by-One interface hot plug detect (controller receiver pulls this signal low to indicate its

O₄presence to the transmitter)

VX1_HTPDN

VX1_LOCKN

E17

E19

This signal is open drain at the controller output. A pullup resistor is required at the transmitter.

V-by-One interface clock detect lock (controller receiver pulls this signal low to indicate clock

O₄extraction lock to the transmitter)

This signal is open drain at the controller output. A pullup resistor is required at the transmitter.

VX1_CM_CKREF0

VX1_CM_CKREF1

VX1_CM_CKREF2

VX1_CM_CKREF3

E20

E21

E23

E24

I₁V-by-One reserved: Tie these reserved pins to ground.

VX1_CM_AMOUT0

VX1_CM_AMOUT1

VX1_CM_AMOUT2

VX1_CM_AMOUT3

F19

F21

F22

F23

O₁V-by-One reserved: These pins are reserved and must remain unconnected

(1) See Table 5-13 for more information on I/O definitions.

(2) The system supports 1 lane, 2 lane, 4 lane, or 8 lane operation, based on the bandwidth requirement of the input source. The inputs

for any un-used data lanes must be left open.

(3) The V-by-One port supports limited lane remapping to help optimize board layout. The details are described in Section 7.3.4.

Table 5-4. OpenLDI (FPD-Link I) Ports Input Data and Control

I/O

DESCRIPTION^{(2) (3)}

(1)

NAME

NO.

FPDA_CLK_P

FPDA_CLK_N

H3

H4

I₅FPD-Link Port A Clock Lane

I₅FPD-Link Port A Data Lanes

I₅FPD-Link Port B Clock Lane

FPDA_DATAA_P

FPDA_DATAA_N

FPDA_DATAB_P

FPDA_DATAB_N

FPDA_DATAC_P

FPDA_DATAC_N

FPDA_DATAD_P

FPDA_DATAD_N

FPDA_DATAE_P

FPDA_DATAE_N

G1

G2

F3

F4

E1

E2

D3

D4

C1

C2

FPDB_CLK_P

FPDB_CLK_N

A4

B4

6

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Table 5-4. OpenLDI (FPD-Link I) Ports Input Data and Control (continued)

I/O

DESCRIPTION^{(2) (3)}

(1)

NO.

FPDB_DATAA_P

FPDB_DATAA_N

FPDB_DATAB_P

FPDB_DATAB_N

FPDB_DATAC_P

FPDB_DATAC_N

FPDB_DATAD_P

FPDB_DATAD_N

FPDB_DATAE_P

FPDB_DATAE_N

C5

D5

A6

B6

C7

D7

A8

B8

C9

D9

I₅FPD-Link Port B Data Lanes

FPDC_CLK_P

FPDC_CLK_N

A10

I₅FPD-Link Port C - Reserved for Parallel Port use only.

B10

FPDC_DATAA_P

FPDC_DATAA_N

FPDC_DATAB_P

FPDC_DATAB_N

FPDC_DATAC_P

FPDC_DATAC_N

FPDC_DATAD_P

FPDC_DATAD_N

FPDC_DATAE_P

FPDC_DATAE_N

C11

D11

A12

B12

C13

D13

A14

B14

C15

D15

I₅FPD-Link Port C Data Lanes - Reserved for Parallel Port use only.

(1) See Table 5-13 for more information on I/O definitions.

(2) Throughout this document the terms FPD and FPD-Link refer to OpenLDI (FPD-Link I).

(3) Tie the inputs for any un-used port(s) to ground, or pull to ground through an external resistor.

Table 5-5. Parallel Port Input Data and Control (Not Supported in DLPC7540)

I/O

DESCRIPTION

PARALLEL RGB MODE

(1)

NAME

NO.

B6

PCLK (FPDB_DATAB_N)

VSYNC (FPDA_DATAE_P)

HSYNC (FPDA_DATAE_N)

DATEN (FPDB_DATAE_N)

FIELD (FPDC_DATAE_P)

3D_REF (FPDC_DATAE_N)

I₆Reserved.

I₆Reserved. ⁽²⁾

I₆Reserved.

C1

C2

D9

C15

D15

PDATA_A0 (FPDA_CLK_P)

PDATA_A1 (FPDA_CLK_N)

PDATA_A2 (FPDA_DATAA_P)

PDATA_A3 (FPDA_DATAA_N)

PDATA_A4 (FPDA_DATAB_P)

PDATA_A5 (FPDA_DATAB_N)

PDATA_A6 (FPDA_DATAC_P)

PDATA_A7 (FPDA_DATAC_N)

PDATA_A8 (FPDA_DATAD_P)

PDATA_A9 (FPDA_DATAD_N)

H3

H4

G1

G2

F3

F4

E1

E2

D3

D4

I₆Reserved.

PDATA_B0 (FPDB_CLK_P)

PDATA_B1 (FPDB_CLK_N)

PDATA_B2 (FPDB_DATAA_P)

PDATA_B3 (FPDB_DATAA_N)

PDATA_B4 (FPDB_DATAB_P)

PDATA_B5 (FPDB_DATAC_P)

PDATA_B6 (FPDB_DATAC_N)

PDATA_B7 (FPDB_DATAD_P)

PDATA_B8 (FPDB_DATAD_N)

PDATA_B9 (FPDB_DATAE_P)

A4

B4

C5

D5

A6

C7

D7

A8

B8

C9

I₆Reserved.

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Table 5-5. Parallel Port Input Data and Control (Not Supported in DLPC7540) (continued)

I/O

DESCRIPTION

PARALLEL RGB MODE

(1)

NAME

NO.

PDATA_C0 (FPDC_CLK_P)

PDATA_C1 (FPDC_CLK_N)

PDATA_C2 (FPDC_DATAA_P)

PDATA_C3 (FPDC_DATAA_N)

PDATA_C4 (FPDC_DATAB_P)

PDATA_C5 (FPDC_DATAB_N)

PDATA_C6 (FPDC_DATAC_P)

PDATA_C7 (FPDC_DATAC_N)

PDATA_C8 (FPDC_DATAD_P)

PDATA_C9 (FPDC_DATAD_N)

A10

B10

C11

D11

A12

B12

C13

D13

A14

B14

I₆Reserved.

(1) See Table 5-13 for more information on I/O definitions.

(2) If the DATEN is not actively driven, then it must be pulled up to 3.3V with a weak pull up resistor (50k Ohm max).

Table 5-6. DMD Reset and Low Speed Interfaces

I/O

DESCRIPTION

(1)

NAME

NO.

DMD_LS0_CLK_P

DMD_LS0_CLK_N

AH17

AG17

O₂DMD low speed differential interface, Port 0 Clock

O₂DMD low speed differential interface, Port 0 Write Data

O₂DMD low speed differential interface, Port 1 Clock ⁽²⁾

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

AK16

AJ16

DMD_LS1_CLK_P

DMD_LS1_CLK_N

AH15

AG15

DMD_LS1_WDATA_P

DMD_LS1_WDATA_N

AK14

AJ14

O₂DMD low speed differential interface, Port 1Write Data ⁽²⁾

DMD_LS0_RDATA

AH13

I₃DMD, low speed single ended serial interface, Port 0 Read Data ⁽³⁾

DMD, low speed single ended serial interface, Port 1 Read Data ^{(2) (3)}. If this port

I₃not used, this signal requires an external pullup or pulldown to keep this input

from floating.

DMD_LS1_RDATA

AG13

DMD driver enable signal / Active Low Asynchronous Reset

('1' = Enabled, '0' = Reset)

This signal is driven low after the DMD is parked and before power is removed

O₃from the DMD.

DMD_DEN_ARSTZ

AK12

If the 1.8-V power to the DLPC7540 is independent of the 1.8-V power to the

DMD, then an external pulldown resistor must be used to hold the signal low in

the event the DLPC7540 power is inactive while DMD power is applied.

(1) See Table 5-13 for more information on I/O definitions.

(2) DMD LS1 port is reserved for single controller, two DMD applications.

(3) All control interface reads make use of the single ended low speed signals. The read data is clocked by the low speed differential

write clock.

Table 5-7. DMD HSSI (High Speed Serial Interface)

PIN ⁽¹⁾

I/O

DESCRIPTION

(2)

NAME

NO.

DMD_HSSI0_CLK_P

DMD_HSSI0_CLK_N

AK25

AJ25

O₇DMD high speed serial interface, Port 0 Clock Lane.

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Table 5-7. DMD HSSI (High Speed Serial Interface) (continued)

PIN ⁽¹⁾

I/O

DESCRIPTION

(2)

NO.

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

AK29

AJ29

AH28

AG28

AK27

AJ27

AH26

AG26

AH24

O₇DMD high speed serial interface, Port 0 Data Lanes.

AG24

AK23

AJ23

AH22

AG22

AK21

AJ21

DMD_HSSI1_CLK_P

DMD_HSSI1_CLK_N

AH7

O₇DMD high speed serial interface, Port 1 Clock Lane.

AG7

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

AH11

AG11

AK10

AJ10

AH9

AG9

AK8

AJ8

AK6

AJ6

AH5

AG5

AK4

AJ4

AK2

AJ2

O₇DMD high speed serial interface, Port 1 Data Lanes.

HSSI_ATETEST

AJ12

O₇Manufacturing Test use only - Must be left open (i.e. unconnected)

(1) A number of pin remapping options are available for the HSSI high speed channels to aid with optimizing board signal routing. See

Section 7.3.5 for information on these pin remapping options.

(2) See Table 5-13 for more information on I/O definitions.

Table 5-8. Program Memory (FLASH ) Interface

I/O ⁽¹⁾

DESCRIPTION

NAME

NO.

T27

T28

T29

T30

U26

U27

U29

U30

V29

V28

V27

V26

W30

PM_CSZ_0

PM_CSZ_1

PM_CSZ_2

PM_ADDR_0

PM_ADDR_1

PM_ADDR_2

PM_ADDR_3

PM_ADDR_4

PM_ADDR_5

PM_ADDR_6

PM_ADDR_7

PM_ADDR_8

PM_ADDR_9

O₈

Chip select: Boot FLASH Only (Boot FLASH must use this chip select)

Chip select: Additional Peripheral Device

Address bit (LSB)

Address bit

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Table 5-8. Program Memory (FLASH ) Interface (continued)

I/O ⁽¹⁾

DESCRIPTION

NAME

NO.

W29

W28

W26

Y30

PM_ADDR_10

PM_ADDR_11

PM_ADDR_12

PM_ADDR_13

PM_ADDR_14

PM_ADDR_15

PM_ADDR_16

PM_ADDR_17

PM_ADDR_18

PM_ADDR_19

PM_ADDR_20

PM_ADDR_21

PM_ADDR_22

O₈

Address bit

Y29

Y28

Y27

Y26

AA30

AA29

AA27

AA26

AB29

PM_ADDR_23

(GPIO_47)

AB28

B₈

Address bit (MSB) ⁽²⁾

PM_WEZ

PM_OEZ

R28

R29

O₈

Write Enable (active low)

Output Enable (active low)

Lower Byte (7:0) Enable (active low) - only applicable to devices using

PM_CSZ_1 or PM_CSZ_2

PM_BLSZ_0

PM_BLSZ_1

R30

T26

O₈

Upper Byte (15:8) Enable (active low) - only applicable to devices using

PM_CSZ_1 or PM_CSZ_2

PM_Data_0

PM_Data_1

PM_Data_2

PM_Data_3

PM_Data_4

PM_Data_5

PM_Data_6

PM_Data_7

PM_Data_8

PM_Data_9

PM_Data_10

PM_Data_11

PM_Data_12

PM_Data_13

PM_Data_14

PM_Data_15

L29

L30

L28

M27

M28

M29

M30

N26

N27

N29

N30

P26

P27

P28

P29

R26

B₈

Data bit

(1) See Table 5-13 for more information on I/O definitions.

(2) The Program Memory address bus can be extended by one bit to 24 bits by making use of GPIO_47. Add an external pulldown

resistor when this GPIO is configured for this purpose.

Table 5-9. Peripheral Interfaces

I/O ⁽¹⁾

DESCRIPTION

NAME

NO.

I²C Port 0 (Master-Slave), Typically slave for Host Command and Control to Controller, SCL

(bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this

pullup is 1KΩ .

IIC0_SCL

E27

B₁₃

10

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Table 5-9. Peripheral Interfaces (continued)

I/O ⁽¹⁾

DESCRIPTION

NAME

NO.

I²C Port 0 (Master-Slave), Typically slave for Host Command and Control to Controller, SDA.

(bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this

pullup is 1KΩ

IIC0_SDA

D29

B₁₃

SSP0_TXD

SSP0_RXD

SSP0_CLK

AD27

AD29

AD28

O₈

I₈

SSP/SPI Port 0 Data Out (Master): Transmit data pin

SSP/SPI Port 0 Data In (Master): Receive data pin

SSP/SPI Port 0 Clock (Master): Clock pin

O₈

SPI Port 0 chip select 2 (Master): Chip select (Active Low)

An external pullup resistor (≤ 10 kΩ) is suggested to avoid a floating chip select input to the

external device

SSP0_CSZ_2

SSP0_CSZ_1

SSP0_CSZ_0

AC28

AC26

AB27

O₈

SPI Port 0 chip select 1 (Master): Chip select (Active Low)

An external pullup resistor (≤ 10 kΩ) is suggested to avoid a floating chip select input to the

external device

SPI Port 0 chip select 0 (Master): Chip select (Active Low)

An external pullup resistor (≤ 10 kΩ) is suggested to avoid a floating chip select input to the

external device

UART Port 0 (Slave): Serial Data Transmit

This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required

UART0_TXD

UART0_RXD

UART0_RTSZ

UART0_CTSZ

P4

P5

N2

N3

O₈

I₈

UART Port 0 (Slave): Serial Data Receive

This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required

UART Port 0 (Slave): Ready To Send (Hardware flow control signal (Active Low))

This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required

O₈

I₈

UART Port 0 (Slave): Clear to Send (Hardware flow control signal (Active Low))

This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required

USB_DAT_P

USB_DAT_N

B27

A27

B₁₁

USB OTG Data Lane (Master-Stave)

USB_VBUS

USB_ID

D26

C27

USB OTG 5V Power Supply Detection (Master-Slave)

I_OtherUSB OTG Mini Receptacle Identification (Master-Slave)

USB OTG Reference Resistor

An external reference resistor must be connected as shown in Section 10.1.7

USB_TXRTUNE

USB_XI

C26

A29

B29

C28

B_GND

USB OTG External Oscillator XI - Not used (clock provided internally)

For normal operation this pin must be connected to GND.

I_GND

USB OTG External Oscillator XO - Not used (clock provided internally)

B_GND

USB_XO

For normal operation this pin must be left open (unconnected).

USB OTG Manufacturing Test

B_Other

USB_ANALOGTEST

This pin must be left open (unconnected)

Interrupt from DLPA100 (Active Low)

This signal requires an external pullup. It also has hysteresis

PMD_INTZ

CW_PWM

CW_INDEX

AD26

AE30

AE29

I₈

O₈

I₈

Color Wheel Control PWM

Color Wheel Index

This pin has hysteresis

(1) See Table 5-13 for more information on I/O definitions.

Table 5-10. GPIO Peripheral Interface

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 87: Options:

1. Alt 0: Reserved

GPIO_87

K1

B₈

2. Alt 1: DAO_CLKIN (I)

3. Optional GPIO

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 86: Options:

1. Alt 0: Reserved

GPIO_86

GPIO_85

GPIO_84

GPIO_83

GPIO_82

GPIO_81

GPIO_80

GPIO_79

GPIO_78

GPIO_77

GPIO_76

L5

B₈

2. Alt 1: DAO_DI_1 (I)

3. Optional GPIO

General purpose I/O 85: Options:

1. Alt 0: Reserved

L4

L3

2. Alt 1: DAO_DI_0 (I)

3. Optional GPIO

General purpose I/O 84: Options:

1. Alt 0: Reserved

2. Alt 1: HBT_CLKIN_2 (I)

3. Optional GPIO

General purpose I/O 83: Options:

1. Alt 0: Reserved

L2

2. Alt 1: HBT_DI_2 (I)

3. Optional GPIO

General purpose I/O 82: Options:

1. Alt 0: Reserved

M5

M4

M2

M1

N5

N4

AD5

2. Alt 1: HBT_CLKIN_1 (I)

3. Optional GPIO

General purpose I/O 81: Options:

1. Alt 0: Reserved

2. Alt 1: HBT_DI_1 (I)

3. Optional GPIO

General purpose I/O 80: Options:

1. Alt 0: Reserved

2. Alt 1: HBT_CLKIN_0 (I)

3. Optional GPIO

General purpose I/O 79: Options:

1. Alt 0: Reserved

2. Alt 1: HBT_DI_0 (I)

3. Optional GPIO

General purpose I/O 78: Options:

1. Alt 0: Reserved

2. Alt 1: SEQ_SYNC (B/ OpenDrain)

3. Optional GPIO

General purpose I/O 77: Options:

1. Alt 0: Reserved

2. Alt 1: EFSYNC (O)/ DASYNC (I)

3. Optional GPIO

General purpose I/O 76: Options:

1. Alt 0: AWC1_DACD_PWMB_1 (O)

2. Alt 1: N/A

3. Optional GPIO

12

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 75: Options:

1. Alt 0: AWC1_DACS_PWMA_1 (O)

2. Alt 1: N/A

GPIO_75

AC1

B₈

3. Optional GPIO

General purpose I/O 74: Options:

1. Alt 0: AWC1_DACD_PWMB_0 (O)

2. Alt 1: N/A

GPIO_74

GPIO_73

GPIO_72

GPIO_71

GPIO_70

GPIO_69

GPIO_68

GPIO_67

GPIO_66

GPIO_65

AC2

AC4

AC5

AD1

AD2

AD3

AD4

AF4

AE2

AE3

3. Optional GPIO

General purpose I/O 73: Options:

1. Alt 0: AWC1_DACS_PWMA_0 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 72: Options:

1. Alt 0: AWC1_DACCLK_0_1 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 71: Options:

1. Alt 0: AWC1_OUT_ENZ (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 70: Options:

1. Alt 0: AWC0_DACD_PWMB_1 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 69: Options:

1. Alt 0: AWC0_DACS_PWMA_1 (O)

2. Alt 1: MEMAUX_1 (O) (#2)

3. Optional GPIO

General purpose I/O 68: Options:

1. Alt 0: AWC0_DACD_PWMB_0 (O)

2. Alt 1: IIC2_SDA (B) (#3)

3. Optional GPIO

General purpose I/O 67: Options:

1. Alt 0: AWC0_DACS_PWMA_0 (O)

2. Alt 1: IIC2_SCL (B) (#3)

3. Optional GPIO

General purpose I/O 66: Options:

1. Alt 0: AWC0_DACCLK_0_1 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 65: Options:

1. Alt 0: AWC0_OUT_ENZ (O)

2. Alt 1: N/A

3. Optional GPIO

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 64: Options:

1. Alt 0: OCLKB (O)

2. Alt 1: N/A

GPIO_64

GPIO_63

GPIO_62

GPIO_61

GPIO_60

GPIO_59

GPIO_58

GPIO_57

GPIO_56

GPIO_55

GPIO_54

AE4

B₈

3. Optional GPIO

General purpose I/O 63: Options:

1. Alt 0: PWM_OUT_UVLED (O)

2. Alt 1: OCLKD (O) (#2)

3. Optional GPIO

AG2

AG3

AF1

AF2

AG1

V1

General purpose I/O 62: Options:

1. Alt 0: PWM_OUT_IRLED (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 61: Options:

1. Alt 0: PWM_OUT_BLED (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 60: Options:

1. Alt 0: PWM_OUT_GLED (O)

2. Alt 1: UART2_RXD (I) (#2)

3. Optional GPIO

General purpose I/O 59: Options:

1. Alt 0: PWM_OUT_RLED (O)

2. Alt 1: UART2_TXD (O) (#2)

3. Optional GPIO

General purpose I/O 58: Options:

1. Alt 0: PWM_OUT_STD_2 (O)

2. Alt 1: Reserved

3. Optional GPIO

General purpose I/O 57: Options:

1. Alt 0:

V2

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 56: Options:

1. Alt 0: PWM_OUT_STD_0 (O)

2. Alt 1: N/A

W2

3. Optional GPIO

General purpose I/O 55: Options:

1. Alt 0: PWM_OUT_CW2 (O)

2. Alt 1: Reserved

K29

K28

3. Optional GPIO

General purpose I/O 54: Options:

1. Alt 0: PWM_OUT_CW1 (O)

2. Alt 1: N/A

3. Optional GPIO

14

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 53: Options:

1. Alt 0: Reserved

GPIO_53

W3

B₈

2. Alt 1: LED_DRIVER_ON (O)

3. Optional GPIO

General purpose I/O 52: Options:

1. Alt 0: Reserved

2. Alt 1: N/A

GPIO_52

GPIO_51

GPIO_50

GPIO_49

GPIO_48

GPIO_47

GPIO_46

GPIO_45

GPIO_44

GPIO_43

W4

V5

3. Optional GPIO

General purpose I/O 51: Options:

1. Alt 0: Reserved

2. Alt 1: DMD_PWR_EN (O)

3. Optional GPIO

General purpose I/O 50: Options:

1. Alt 0: SSP0_CSZ_3 (O)

2. Alt 1: N/A

AC29

AC30

AB26

AB28

K27

3. Optional GPIO

General purpose I/O 49: Options:

1. Alt 0: SSP0_CSZ_4 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 48: Options:

1. Alt 0: USB OTG External USB Switch Control (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 47: Options:

1. Alt 0: PM_ADDR_23 (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 46: Options:

1. Alt 0: CW_Index_2 (I) (#1)

2. Alt 1: SSP2_BC_CSZ (O-MST/I-SLV)

3. Optional GPIO

General purpose I/O 45: Options:

1. Alt 0: CW_Index_1 (I) (#1)

2. Alt 1: SSP2_CSZ_2 (O-MST/I-SLV)

3. Optional GPIO

J30

General purpose I/O 44: Options:

1. Alt 0: OCLKC (O) (#1)

J29

2. Alt 1: SSP2_CSZ_1 (O-MST/I-SLV)

3. Optional GPIO

General purpose I/O 43: Options:

1. Alt 0: OCLKD (O) (#1)

J27

2. Alt 1: SSP2_CSZ_0 (O-MST/I-SLV)

3. Optional GPIO

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 42: Options:

1. Alt 0: IIC2_SDA (B) (#1)

2. Alt 1: SSP2_DO (O)

3. Optional GPIO

GPIO_42

GPIO_41

GPIO_40

GPIO_39

GPIO_38

GPIO_37

GPIO_36

GPIO_35

GPIO_34

GPIO_33

GPIO_32

J26

B₈

General purpose I/O 41: Options:

1. Alt 0: IIC2_SCL (B) (#1)

2. Alt 1: SSP2_DI (I)

H30

H29

H28

H27

H26

G30

G29

Y1

3. Optional GPIO

General purpose I/O 40: Options:

1. Alt 0: MEMAUX_1 (O) (#1)

2. Alt 1: SSP2_SCLK (O-MST/I-SLV)

3. Optional GPIO

General purpose I/O 39: Options:

1. Alt 0: UART2_RXD (I) (#1)

2. Alt 1: HBT_CLKOUT (O)

3. Optional GPIO

General purpose I/O 38: Options:

1. Alt 0: UART2_TXD (O) (#1)

2. Alt 1: HBT_DO (O)

3. Optional GPIO

General purpose I/O 37: Options:

1. Alt 0: CW_Index_2 (I) (#2)

2. Alt 1: DAO_CLKOUT (O)

3. Optional GPIO

General purpose I/O 36: Options:

1. Alt 0: CW_Index_1 (I) (#2)

2. Alt 1: DAO_DO_1 (O)

3. Optional GPIO

General purpose I/O 35: Options:

1. Alt 0: OCLKC (O) (#2)

2. Alt 1: DAO_DO_0 (O)

3. Optional GPIO

General purpose I/O 34: Options:

1. Alt 0: WRP_CAMERA_TRIG (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 33: Options:

1. Alt 0: PAUX11 (O) {CW Spoke}

2. Alt 1: IIC2_SDA (B) (#2)

3. Optional GPIO

Y2

General purpose I/O 32: Options:

1. Alt 0: PAUX10 (O) {CW Rev}

2. Alt 1: IIC2_SCL (B) (#2)

3. Optional GPIO

Y4

16

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 31: Options:

1. Alt 0: PAUX9 (O) {XPR-Y}

2. Alt 1: PAUX_INT3 (O)

3. Optional GPIO

GPIO_31

Y5

B₈

General purpose I/O 30: Options:

1. Alt 0: PAUX8 (O) {XPR-X}

2. Alt 1: PAUX_INT2 (O)

3. Optional GPIO

GPIO_30

GPIO_29

GPIO_28

GPIO_27

GPIO_26

GPIO_25

GPIO_24

GPIO_23

GPIO_22

GPIO_21

AA1

AA2

AA3

AA4

AA5

AB2

AB3

AB4

AB5

P3

General purpose I/O 29: Options:

1. Alt 0: PAUX7 (O) {SSI Subframe}

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 28: Options:

1. Alt 0: PAUX6 (O) {UV_LED_EN}

2. Alt 1: LEDSEL_4 (O)

3. Optional GPIO

General purpose I/O 27: Options:

1. Alt 0: PAUX5 (O) {IR_LED_EN}

2. Alt 1: LEDSEL_3 (O)

3. Optional GPIO

General purpose I/O 26: Options:

1. Alt 0: PAUX4 (O) {B_LED_EN}

2. Alt 1: LEDSEL_2 (O)

3. Optional GPIO

General purpose I/O 25: Options:

1. Alt 0: PAUX3 (O) {G_LED_EN}

2. Alt 1: LEDSEL_1 (O)

3. Optional GPIO

General purpose I/O 24: Options:

1. Alt 0: PAUX2 (O) {R_LED_EN}

2. Alt 1: LEDSEL_0 (O)

3. Optional GPIO

General purpose I/O 23: Options:

1. Alt 0: PAUX1 (O) {SEQ Index}

2. Alt 1: PAUX_INT1 (O)

3. Optional GPIO

General purpose I/O 22: Options:

1. Alt 0: PAUX0 (O) {LED SENSE}

2. Alt 1: PAUX_INT0 (O)

3. Optional GPIO

General purpose I/O 21: Options:

1. Alt 0: PWM-IN1 (I)

2. Alt 1: N/A

3. Optional GPIO

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 20: Options:

1. Alt 0: PWM-IN0 (I)

2. Alt 1: N/A

GPIO_20

GPIO_19

GPIO_18

GPIO_17

GPIO_16

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

P2

B₈

3. Optional GPIO

General purpose I/O 19: Options:

1. Alt 0: IR1 (I)

P1

R5

R4

R2

R1

T3

T4

T5

T2

V3

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 18: Options:

1. Alt 0: IR0 (I)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 17: Options:

1. Alt 0: N/A

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 16: Options:

1. Alt 0: UART1_RTSZ (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 15: Options:

1. Alt 0: UART1_CTSZ (I)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 14: Options:

1. Alt 0: UART1_RXD (I)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 13: Options:

1. Alt 0: UART1_TXD (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 12: Options:

1. Alt 0: IIC1_SDA (B)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 11: Options:

1. Alt 0: IIC1_SCL (B)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 10: Options:

1. Alt 0: SAS_INTGTR_EN (O)

2. Alt 1: N/A

3. Optional GPIO

18

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Table 5-10. GPIO Peripheral Interface (continued)

I/O

DESCRIPTION^{(2) (3) (4)}

(1)

NAME

NO.

General purpose I/O 09: Options:

1. Alt 0: SAS_CSZ (O)

2. Alt 1: N/A

GPIO_09

U1

B₈

3. Optional GPIO

General purpose I/O 08: Options:

1. Alt 0: SAS_DO (O)

2. Alt 1: N/A

GPIO_08

GPIO_07

GPIO_06

GPIO_05

GPIO_04

GPIO_03

GPIO_02

GPIO_01

GPIO_00

U2

U4

3. Optional GPIO

General purpose I/O 07: Options:

1. Alt 0: SAS_DI (I)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 06: Options:

1. Alt 0: SAS_CLK (O)

2. Alt 1: N/A

V4

3. Optional GPIO

General purpose I/O 05: Options:

1. Alt 0: SSP1_CSZ_2 (O-MST/I-SLV)

2. Alt 1: N/A

A17

B17

B15

C16

D16

E16

3. Optional GPIO

General purpose I/O 04: Options:

1. Alt 0: SSP1_CSZ_1 (O-MST/I-SLV)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 03: Options:

1. Alt 0: SSP1_CSZ_0 (O-MST/I-SLV)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 02: Options:

1. Alt 0: SSP1_DO (O)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 01: Options:

1. Alt 0: SSP1_DI (I)

2. Alt 1: N/A

3. Optional GPIO

General purpose I/O 00: Options:

1. Alt 0: SSP1_SCLK (O-MST/I-SLV)

2. Alt 1: N/A

3. Optional GPIO

(1) See Table 5-13 for more information on I/O definitions.

(2) This table defines the GPIO capabilities of the DLPC7540. Please see Section 7.3.7 for specific product configuration allocations of

these GPIO.

(3) Most GPIO have at least one alternate hardware functional use in addition to being available as a general purpose I/O. Depending on

the product configuration, GPIO may be reserved specifically for use as an alternate hardware function (and would therefore not be

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available as a general purpose I/O). More information on GPIO allocations for specific product configurations can be found in Section

7.3.7.

(4) All GPIO that are available as a general purpose I/O must be configured as an input, a standard output, or an open-drain output. This

is set in the flash configuration. Configure unused GPIO as a logic zero output and leave unconnected, otherwise an external pullup or

pulldown resistor is required to avoid a floating input. The reset default for all GPIO is as an input signal. An external pullup resistor (≤

10 kΩ) is required for each signal configured as open-drain output.

Table 5-11. Clock and Support

I/O

DESCRIPTION

(1)

NAME

NO.

AJ18

AK18

B16

REFCLKA_I

REFCLKA_O

REFCLKB_I

REFCLKB_O

I₉Crystal A Input: Reference clock crystal input. ^{(2) (3)}

O₁₀Crystal A Output: Reference clock crystal output. ⁽²⁾

I₁₄Crystal B Input: Reference clock crystal input. ^{(2) (3)}

O₁₅Crystal B Output: Reference clock crystal output. ⁽²⁾

A16

General Purpose Output Clock A ⁽⁴⁾

Targeted for driving Color Wheel motor controller. Frequency is software programmable, with a

O₈power-up default frequency of 0.77 MHz.

OCLKA

AD30

Note: the output frequency is not affected by non-power-up reset operations (i.e., the system holds

the last programmed value until system is power cycled).

(1) See Table 5-13 for more information on I/O definitions.

(2) For more information on this signal see Section 6.12

(3) For applications where an external oscillator is used in place of a crystal, use an oscillator to drive this pin

(4) For more information on this signal see Section 6.21

Table 5-12. Power and Ground

I/O ⁽¹⁾

DESCRIPTION

NAME

NO.

VDD115_PLLMA

VDD115_PLLMB

VAD115_PLLS

VAD18_PLLMA

VAD18_PLLMB

VAD33_OSCA

VAD33_OSCB

VAD115_FPD

VDD33_FPD

VAD115_VX1

VAD18_VX1

AE18

F15

PWR 1.15-V digital power for MCG (Master Clock Generator A) PLL

PWR 1.15-V digital power for MCG (Master Clock Generator B) PLL

PWR 1.15-V analog power for SCG doubler PLL

PWR 1.8-V analog power for MCG (Master Clock Generator A) PLL

PWR 1.8-V analog power for MCG (Master Clock Generator B) PLL

PWR 3.3-V analog power for Crystal-OSC

F16

AE19

F14

Y18

L17

PWR 3.3-V analog power for Crystal-OSC

F7,F9,F11,J6,L12

E6,E8,E10,E12,E14,G6,L11,L13

F24,L18

PWR 1.15-V analog power for FPD

PWR 3.3-V digital power for FPD

PWR 1.15-V analog power for VX1

E18,L19

PWR 1.8-V analog power for VX1

VAD33_USB

VDD18_SCS

VDD121_SCS

D27,E26,F25

PWR 3.3-V analog power for USB

L16,R6,T25,AE16

L15,N11,P20,U11,V20,Y16

PWR 1.8-V digital power for SCS DRAM

PWR 1.21-V digital power for SCS SRAM

Y14,Y19,AF7,AF9,AF11,AF13AF21,A

F23,AF25

VAD115_HSSI

PWR 1.15-V analog power for HSSI interface

VAD115_HSSI0_PLL

VAD115_HSSI1_PLL

VDD33_HSSI

AE22

PWR 1.15-V analog power for HSSI-0 PLL

AE10

PWR 1.15-V analog power for HSSI-1 PLL

Y12,Y20,AE8,AE12,AE20,AE24

Y15,AE13,AE14

AF16

PWR 3.3-V digital power for HSSI interface

VAD18_LSIF

PWR 1.8-V analog power for DMD low-speed interface

Manufacturing test use only - must be left open-unconnected

LVDS_VREFTEST

L14,L20,M11,N20,P11,R20,T11,U20,

V11,W20,Y11,Y13,Y17

VDD115

VDD33

PWR 1.15-V core power

H25,K25,L6,M20,M25,N6,P25,R11,T2

0,U6,V25,W6,W11,Y25,AA6,AB25,AC PWR 3.3-V digital power

6,AD25,AE6

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NAME

Table 5-12. Power and Ground (continued)

I/O ⁽¹⁾

DESCRIPTION

NO.

A1,A2,A3,A5,A7,A9,A11,A13,A15,A1

8,A20,A22,A24,A26,A28,A30,B1,B2,B

3,B5,B7,B9,B11,B13,B18,B20,B22,B2

4,B26,B28,B30,C3,C4,C6,C8,C10,C1

2,C14,C17,C19,C21,C23,C25,C29,D

1,D2,D6,D8,D10,D12,D14,D17,D19,D

21,D23,D25,D28,E3,E4,E5,E7,E9,E1

1,E13,E15,E22,E25,E28,F1,F2,F5,F6

,F8,F10,F12,F13,F17,F18,F20,F30,G

3,G4,G5,G27,H1,H2,H5,H6,J3,J4,J5,

J25.J28,K6,K30,L1,L25,L27,M3,M6,

(M12),(M13),(M14),(M15),(M16),

(M17),(M18),(M19),N1,(N12,(N13),

(N14),(N15),(N16),(N17),(N18),

(N19),N25,N28,P6,(P12),(P13),(P14),

(P15),(P16),(P17),(P18),

(P19),P30,R3,(R12),(R13),(R14),

(R15),(R16),(R17),(R18),

(R19),R25,R27,T1,T6,(T12),(T13),

(T14),(T15),(T16),(T17),(T18),

(T19),U3,U5,(U12),(U13),(U14),

(U15),(U16),(U17),(U18),

(U19),U25,U28,V6,(V12),(V13),(V14),

(V15),(V16),(V17),(V18),

GND for all power supplies (Ball numbers in parenthesis are

RTN also used as thermal ball and are located within the package

center region)

VSS

(V19),V30,W1,W5,(W12),(W13),

(W14),(W15),(W16),(W17),(W18),

(W19),W25,W27,Y3,Y6,AA25,AA28,A

B1,AB6,AB30,AC3,AC25,AC27,AD6,

AE1,AE5,AE7,AE9,AE11,AE15,AE17,

AE21,AE23,AE25,AE26,AE28,AF3,A

F5,AF6,AF8,AF10,AF12,AF14,AF15,

AF17,AF18,AF19,AF20,AF22,AF24,A

F26,AF28,AF30,AG4,AG6,AG8,AG10

,AG12,AG14,AG16,AG18,AG23,AG2

5,AG27,AG29,AH1,AH2,AH3,AH4,AH

6,AH8,AH10,AH12,AH14,AH16,AH18

,AH21,AH23,AH25,AH27,AH29,AH30

,AJ1,AJ3,AJ5,AJ7,AJ9,AJ11,AJ13,AJ

15,AJ17,AJ22,AJ24,AJ26,AJ28,AJ30,

AK1,AK3,AK5,AK7,AK9,AK11,AK13,

AK15,AK17,AK22,AK24,AK26,AK28,

AK30

VPGM

G25

Manufacturing use only (efuse). Must be tied to ground.

(1) See Table 5-13 for more information on I/O definitions.

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Table 5-13. I/O Type Subscript Definition

I/O

SUPPLY REFERENCE ESD STRUCTURE

SUBSCRIPT DESCRIPTION

1

2

1.8 V SERDES (VX1)

VAD18_VX1

VAD18_LSIF

VDD33

ESD diode to supply rail and GND

1.8-V LVDS (LS DMD)

ESD diode to supply rail and GND

ESD diode to GND

3

1.8-V LMCMOS (LS DMD)

3.3-V OpenDrain (VX1)

3.3-V LVDS (FPD)

4

5

VDD33_FPD

VAD115_HSSI

VDD33

6

3.3-V LVCMOS (PP)

7

1.15-V HSSI (HS DMD)

3.3-V LVCMOS I/O (8ma output drive - GPIO, etc. )

3.3-V LVCMOS I/O (OSC)

3.3-V USB (USB)

8

9

VAD33_OSCA

VAD33_USB

VDD33

10

11

12

13

14

15

ESD diode to supply rail and GND

ESD diode and LBJT to GND

ESD diode to supply rail and GND

ESD diode to GND

3.3-V LVCMOS (USB)

3.3-V OpenDrain (I2C)

3.3-V LVCMOS I/O (OSC)

VAD33_OSCB

ESD diode to supply rail and GND

TYPE

I

Input

O

B

Output

Bidirectional

Power

N/A

PWR

RTN

Ground return

Table 5-14. Internal Pullup and Pulldown Characteristics⁽¹⁾

INTERNAL PULLUP AND PULLDOWN

RESISTOR CHARACTERISTICS

CONDITIONS

MIN

MAX

UNIT

V_IN= 0.8 V, VDD33 = 3.3 V

V_IN= 2.0 V, VDD33 = 3.3 V

19

12

50

39

kΩ

Weak pullup resistance

(1) An external 5.7-kΩ or less pullup or pulldown resistor (if needed) is sufficient for any voltage condition to correctly override any

associated internal pullup or pulldown resistance.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature (unless otherwise noted)⁽¹⁾

SUPPLY VOLTAGE⁽²⁾

MIN

–0.3

–0.5

–0.3

–0.4

–0.3

–0.5

–0.4

–0.3

MAX

1.6

1.5

1.6

2.5

2.3

2.5

3.9

UNIT

V

V_(VDD115)(Core)

V_{(VDD115_PLLMA)}(Core)

V_{(VDD115_PLLMB)}(Core)

V_{(VDD115_PLLS)}(Core)

V_{(VAD115_FPD)}(Core)

V_{(VAD115_VX1)}(Core)

V_{(VAD115_HSSI)}(Core)

V_{(VAD115_HSSI0_PLL)}(Core)

V_{(VAD115_HSSI1_PLL)}(Core)

V_{(VDD121_SCS)}(Core)

V_{(VAD18_PLLMA)}(Core)

V_{(VAD18_PLLMB)}(Core)

V_{(VAD18_VX1)}(I/O)

V

V_{(VDD18_SCS)}(Core)

V_{(VDD18_LVDS)}(I/O)

V_(VDD33)(I/O)

V

V_{(VAD33_OSCA)}(I/O)

V_{(VAD33_OSCB)}(I/O)

V_{(VDD33_FPD)}(I/O)

V

V_{(VAD33_USB)}(I/O)

V

V_{(VDD33_HSSI)}(I/O)

GENERAL

V

T_J

Operating junction temperature

0

115

108⁽³⁾

100

°C

T_C

I_lat

Operating case temperature

Latch-up

–100

-40

mA

°C

T_stg

Storage temperature range

125

(1) Stresses beyond those listed under Section 6.1 can cause permanent damage to the device. These are stress ratings only, which do

not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to

absolute-maximum-rated conditions for extended periods ca affect device reliability.

(2) All voltage values are with respect to GND.

(3) Value calculated using package parameters defined in Section 6.4.

6.2 ESD Ratings

PARAMETER

VALUE

±1000

±750

UNIT

All pins (except

Vx1_CM_CKREF0, 1, 2, 3)

Human body model (HBM), per

ANSI-ESDA-JEDEC JS-001⁽¹⁾

Vx1_CM_CKREF0, 1, 2, 3

Electrostatic

discharge

V_(ESD)

All pins (except

Vx1_CM_CKREF0, 1, 2, 3)

V

±500

Charged device model (CDM),

per JEDEC specification

JESD22-C101⁽²⁾

+500

-200

Vx1_CM_CKREF0, 1, 2, 3

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TOLERANCE

MIN

NOM

MAX

UNIT

V_(VDD115)(Core)

V_{(VDD115_PLLMA)}(Core)

1.15-V Power

± 4.35% tolerance

1.10

1.15

1.20

V

1.15-V Digital Power -

MCG-A PLL

(Master Clock

Generator)

+4.35/-9.13%

tolerance

1.045

1.15

1.20

V

V_{(VDD115_PLLMB)}(Core)

1.15-V Digital Power -

MCG-B PLL

(Master Clock

Generator)

+4.35/-9.13%

tolerance

V_{(VDD115_PLLS)}(Core)

V_{(VAD115_FPD)}(Core)

V_{(VAD115_VX1)}(Core)

V_{(VAD115_HSSI)}(Core)

ΔV_{(VAD115_HSSI)}(Core)

1.15-V Analog Power +4.35/-9.13%

- SCG Doubler PLL tolerance

1.045

1.15

1.20

V

1.15-V Analog Power +4.35/-9.13%

- FPD tolerance

1.15-V Analog Power +4.35/-9.13%

- VX1 tolerance

1.15-V Analog Power +4.35/-9.13%

- HSSI

tolerance

pk-pkVAD115_HSSI

supply noise @ 10

MHz (sine)

20

mV

V

V_{(VAD115_HSSI0_PLL)}(Core)

ΔV_{(VAD115_HSSI0_PLL)}(Core)

1.15-V Analog Power +4.35/-9.13%

1.045

1.15

1.20

- HSSI0 PLL

tolerance

pk-

pkVAD115_HSSI0_P

LL supply noise @ 10

MHz (sine)

20

1.20

20

mV

V

V_{(VAD115_HSSI1_PLL)}(Core)

ΔV_{(VAD115_HSSI1_PLL)}(Core)

1.15-V Analog Power +4.35/-9.13%

- HSSI1 PLL

tolerance

pk-

pkVAD115_HSSI1_P

LL supply noise @ 10

MHz (sine)

mV

1.21V Digital Power - +7.43/-4.95%

V_{(VDD121_SCS)}(Core)

V_{(VAD18_PLLMA)}(Core)

1.15

1.71

1.21

1.80

1.30

1.89

V

SCS DRAM

tolerance

1.8-V Analog Power -

MCG-A PLL

(Master Clock

Generator)

±5.0% tolerance

V_{(VAD18_PLLMB)}(Core)

1.8-V Analog Power -

MCG-B PLL

±5.0% tolerance

1.71

1.80

1.89

V

(Master Clock

Generator)

V_{(VAD18_VX1)}(I/O)

V_{(VDD18_SCS)}(Core)

V_{(VDD18_LVDS)}(I/O)

1.8-V Analog Power -

VX1 Interface

±5.0% tolerance

1.71

1.80

1.89

V

1.8-V Digital Power -

SCS DRAM

1.8-V Analog Power -

DMD LS Interface

V_(VDD33)(I/O)

3.3-V Digital Power

- (All 3.3-V I/O

±5.0% tolerance

3.135

3.3

3.465

V

without dedicated 3.3-

V supply - e.g. GPIO)

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Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TOLERANCE

MIN

NOM

MAX

UNIT

V_{(VAD33_OSCA)}(I/O)

3.3-V Analog Power

- Crystal-OSCA

Interface

±5.0% tolerance

3.135

3.3

3.465

V

V_{(VAD33_OSCB)}(I/O)

3.3-V Analog Power

- Crystal-OSCB

Interface

3.135

3.3

3.465

V

V_{(VDD33_FPD)}(I/O)

V_{(VAD33_USB)}(I/O)

V_{(VDD33_HSSI)}(I/O)

ΔV_{(VDD33_HSSI)}(I/O)

3.3-V Digital Power -

FPD interface

±5.0% tolerance

3.135

3.3

3.465

V

3.3-V Analog Power -

USB Interface

3.3-V Digital Power -

DMD HSSI Interface

pk-pkVDD33_HSSI

supply noise @ 10

MHz (sine)

60

mV

GENERAL

Operating junction

temperature

T_J

0

115

108

55

°C

Operating case

temperature

T_C

T_A

Operating ambient

temperature ^{(1) (2)}

(1) The operating ambient temperature range values were determined based on the board design parameters described in Section

10.1.1 , rather than using a JEDEC JESD51 standard test card and environment, along with min and max estimated power dissipation

across process, voltage, and temperature. Ambient thermal conditions, which impact R_θJA, vary by application. Thus, maximum

operating ambient temperature varies by application.

a. T_{a_min}= T_{j_min}– (P_{d_min}× R_θJA) = 0°C – (host_min_valueW × host_value°C/W) = –host_calculated_value°C

b. T_{a_max}= T_{j_max}– (P_{d_max}× R_θJA) = +115°C – (host_max_valueW × host_value°C/W) = +host_calculated_value°C

(2) Operating ambient temperature is dependent on system thermal design. Operating case temperature cannot exceed its specified

range across ambient temperature conditions.

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6.4 Thermal Information

ZDC

P-HBGA676

THERMAL METRIC ⁽¹⁾

TEST CONDITIONS ⁽²⁾

UNIT

676 PINS (576

Populated)

0 m/s of forced airflow, without heat-sink

1 m/s of forced airflow, without heat-sink

2 m/s of forced airflow, without heat-sink

1 m/s of forced airflow, with heat-sink, 7 W

2 m/s of forced airflow, with heat-sink, 7 W

1 m/s of forced airflow, with heat-sink,15 W

2 m/s of forced airflow, with heat-sink, 15 W

7.4

6.3

6.0

5.3

4.8

4.0

3.5

Junction-to-air thermal

R_θJA

°C/W

resistance ⁽³⁾

Junction-to-case thermal

R_JC

2.7

3.5

°C/W

resistance ⁽⁴⁾

Junction-to-board thermal

R_JB

resistance ⁽⁴⁾

Temperature variance from

junction to package top center

temperature, per unit power

dissipation.

0 m/s of forced airflow, without heat-sink

1 m/s of forced airflow, without heat-sink

2 m/s of forced airflow, without heat-sink

0.6

(5)

ψ_JT

°C/W

W

0 m/s of forced airflow, without heat-sink

8.10

9.52

10.00

P_MAX

Package - Maximum Power^{(3) (6)}1 m/s of forced airflow, without heat-sink

2 m/s of forced airflow, without heat-sink

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) These test conditions also included a PCB sized at 101.3mm x 152.4mm incorporating the recommended PCB thermal enhancements

specified in Section 10.1.1. In addition, airflow is parallel to the board surface directed at the device.

(3) See Table 6-1 for thermal parameters based on the example heat-sinks listed below

a. Heatsink-7 W: S1525-7W, Size = 25 mm x 25 mm x 7 mm, Pins = 7 x7 = 49 (Vendor: Alpha, Type S Series)

b. Heatsink-15 W: S1530-15W, Size = 30 mm x 3 0mm x 15 mm, Pins = 8 x 8 = 64 (Vendor: Alpha, Type S Series)

(4) Due to the complex internal construction of the DLPC7540 controller, the R_JCand R_JBthermal coefficients do not always produce

an accurate junction temperature estimate. A limited set of comparison scenario data shows that the R_JCand R_JBmodeled junction

temperature can have a +9% to -2% error vs the actual temperature. The amount of this error varies with the use and size of an

external heat sink as well as the amount of external air flow. Validate all thermal estimates based on R_JCand R_JBwith an actual

temperature measurement at the top-center of the package plus the delta-temp defined by ψ_JT

(5) Example: Using the power we expect of 11.31 W

.

11.31 W * 0.6 °C/W = 6.786 °C = > T_C-max= 115 °C - ~7 °C = 108 °C

(6) P_MAX= (T_J-max- T_A-max) / R_θJA

Table 6-1. Thermal Examples using Two Different Heat-sinks

ZDC

THERMAL METRIC ⁽¹⁾

TEST CONDITIONS

P-HBGA676

UNIT

°C/W

W

676 PINS (576 Populated)

1 m/s of forced airflow, with heat-sink, 7 W

2 m/s of forced airflow, with heat-sink, 7 W

1 m/s of forced airflow, with heat-sink, 15 W

2 m/s of forced airflow, with heat-sink, 15 W

5.3

4.8

4.0

3.5

Junction-to-air thermal

resistance

R_θJA

1 m/s of forced airflow, with heat-sink, 7 W

2 m/s of forced airflow, with heat-sink, 7 W

1 m/s of forced airflow, with heat-sink, 15 W

2 m/s of forced airflow, with heat-sink, 15 W

11.32

12.50

15.00

17.14

P_MAX

Package - Maximum Power

(1) This table show examples of what is achievable based on the two example heat-sinks.

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6.5 Power Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX⁽¹⁾

UNIT

V_(VDD115)

1.15-V Power

Maximum current at VDD115 = 1.2 V

5640

mA

V_{(VDD115_PLLMA)}(Core) 1.15-V Digital Power

MCG-A PLL

Maximum current at VDD115_PLLMA =

1.2 V

6

mA

(Master Clock Generator)

V_{(VDD115_PLLMB)}(Core) 1.15-V Digital Power

MCG-B PLL

Maximum current at VDD115_PLLMB =

1.2 V

6

3

mA

(Master Clock Generator)

V_{(VDD115_PLLS)}(Core)

V_{(VAD115_FPD)}(Core) ⁽²⁾

1.15-V Analog Power

SCG Doubler PLL

Maximum current at VDD115_PLLS =

1.2 V

Maximum current at VAD115_FPD = 1.2

V

Ports A and B Active, Port C inactive

1.15-V Analog Power

FPD

99

V_{(VAD115_VX1)}(Core) ⁽²⁾

Maximum current at VAD115_VX1 = 1.2

V

8 Lanes, with total BW = 3.0Gbps)

1.15-V Analog Power

VX1

400

462

1

mA

V_{(VAD115_HSSI)}(Core)

Maximum current at VDD115_HSSI =

1.2 V

Both ports active

1.15-V Digital Power

HSSI

V_{(VAD115_HSSI0_PLL)}

(Core)

Maximum current at

VDD115_HSSI0_PLL = 1.2 V

Both ports active

1.15-V Digital Power

HSSI0 PLL

V_{(VAD115_HSSI1_PLL)}

(Core)

Maximum current at

VDD115_HSSI1_PLL = 1.2 V

Both ports active

1.15-V Digital Power

HSSI1 PLL

1

mA

1.21V Digital Power

SCS DRAM

Maximum current at VDD121_SCS =

1.30 V

V_{(VDD121_SCS)}(Core)

V_{(VAD18_PLLMA)}(Core)

334

10

1.8-V Analog Power

MCG-A PLL

(Master Clock Generator)

Maximum current at VAD18_PLLMA =

1.89 V

V_{(VAD18_PLLMB)}(Core)

1.8-V Analog Power

MCG-B PLL

(Master Clock Generator)

Maximum current at VAD18_PLLMB =

1.89 V

10

41

mA

V_{(VAD18_VX1)}(I/O) ⁽²⁾

Maximum current at VAD18_VX1 = 1.89

V

8 Lanes, with total BW = 3.0Gbps

1.8-V Analog Power

VX1 Interface

V_{(VDD18_SCS)}(Core)

V_{(VDD18_LVDS)}(I/O)

V_(VDD33)(I/O)

1.8-V Digital Power

SCS DRAM

Maximum current at VDD18_SCS =

1.89 V

327

31

mA

1.8-V Analog Power

DMD LS Interface

Maximum current at VDD18_LVDS =

1.89 V

3.3-V Digital Power -

(All 3.3-V I/O without

dedicated 3.3-V supply -

e.g. GPIO)

Maximum current at VDD33 = 1.3456 V

28

mA

V_{(VAD33_OSCA)}(I/O)

V_{(VAD33_OSCB)}(I/O)

V_{(VDD33_FPD)}(I/O) ⁽²⁾

3.3-V Analog Power

Crystal/OSCA Interface

Maximum current at VDD33_OSCA =

1.3456 V

5

mA

3.3-V Analog Power

Crystal-OSCB Interface

Maximum current at VDD33_OSCB =

1.3456 V

Maximum current at VDD33_FPD =

1.3456 V

Ports A and B Active, Port C inactive

3.3-V Digital Power

FPD interface

102

78

mA

V_{(VAD33_USB)}(I/O)

3.3-V Analog Power

USB Interface

Maximum current at VDD33_USB =

1.3456 V

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Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX⁽¹⁾

UNIT

V_{(VDD33_HSSI)}(I/O)

Maximum current at VDD33_HSSI =

1.3456 V

Both ports active, with total BW =

3.0Gbps

3.3-V Digital Power

DMD HSSI Interface

194

mA

(1) Vendor estimate for worst case power PVT condition = corner process, high voltage, high temperature (115°C junction).

(2) The V-by-One interface and FPD-Link receivers are never intended to be simultaneously enabled . Always disable one of these

interfaces.

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6.6 Pin Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

1.05

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

3.3 V LVCMOS

0.8 ×

(I/O type 6 - FPD)

VDD33_FPD

3.3 V LVCMOS

(I/O type 6 - PP)

2.0

High-level input

threshold voltage

V_IH

V

3.3 V LVCMOS

(I/O type 8 - GPIO)

2.0

3.3 V LVCMOS

(I/O type 9 - OSCA)

3.3 V LVCMOS

(I/O type 10 -

OSCB)

2.0

3.3 V OpenDrain

(I/O type 13 - I2C)

0.7 × VDD33

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

0.6

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

3.3 V LVCMOS

(I/O type 6 - FPD)

0.2 × VDD33_FPD

0.8

3.3 V LVCMOS

(I/O type 6 - PP)

Low-level input

threshold voltage

V_IL

V

3.3 V LVCMOS

(I/O type 8 - GPIO)

0.8

3.3 V LVCMOS

(I/O type 9 - OSCA)

3.3 V LVCMOS

(I/O type 10 -

OSCB)

0.8

0.3 × VDD33

10

3.3 V OpenDrain

(I/O type 13 - I2C)

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

V_IN= VAD18_LSIF

–10

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

-10

N/A

10

3.3 V LVCMOS

(I/O type 6 - PP)

High-level input

current

3.3 V LVCMOS

(I/O type 8 - GPIO)

I_IH

V_IN= VDD33

–10

10

µA

3.3 V LVCMOS

(I/O type 9 - OSCA)

10

3.3 V LVCMOS

(I/O type 10 -

OSCB)

V_IN= VDD33

–10

10

3.3 V OpenDrain

(I/O type 13 - I2C)

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UNIT

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6.6 Pin Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_IN= VSS

MIN

TYP

MAX

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

–10

10

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

-10

N/A

10

3.3 V LVCMOS

(I/O type 6 - PP)

Low-level input

current

3.3 V LVCMOS

(I/O type 8 - GPIO)

I_IL

V_IN= VSS

–10

10

µA

3.3 V LVCMOS

(I/O type 9 - OSCA)

10

3.3 V LVCMOS

(I/O type 10 -

OSCB)

V_IN= VSS

–10

10

3.3 V OpenDrain

(I/O type 13 - I2C)

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

VDD18 - 0.6

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

3.3 V LVCMOS

(I/O type 6 - PP)

High-level output

voltage

3.3 V LVCMOS

(I/O type 8 - GPIO)

V_OH

I_OH= 8 mA

VDD33 - 0.6

N/A

V

3.3 V LVCMOS

(I/O type 9 - OSCA)

3.3 V LVCMOS

(I/O type 10 -

OSCB)

N/A

3.3 V OpenDrain

(I/O type 13 - I2C)

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

0.4

3.3 V OpenDrain

(I/O type 4 - VX1)

I_OL= 8 mA

0.4

N/A

0.4

3.3 V LVCMOS

(I/O type 6 - PP)

Low-level output

voltage

3.3 V LVCMOS

(I/O type 8 - GPIO)

V_OL

I_OL= 8 mA

V

3.3 V LVCMOS

(I/O type 9 - OSCA)

N/A

3.3 V LVCMOS

(I/O type 10 -

OSCB)

N/A

0.4

3.3 V OpenDrain

(I/O type 13 - I2C)

3-mA sink

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6.6 Pin Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

N/A

3.3 V OpenDrain

(I/O type 4 - VX1)

N/A

8

3.3 V LVCMOS

(I/O type 6 - PP)

High-level output

current

3.3 V LVCMOS

(I/O type 8 - GPIO)

I_OH

I_OL

I_OZ

V_OH= VDD33 - 0.6 V

mA

3.3 V LVCMOS

(I/O type 9 - OSCA)

N/A

3.3 V LVCMOS

(I/O type 10 -

OSCB)

N/A

8

3.3 V OpenDrain

(I/O type 13 - I2C)

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

3.3 V OpenDrain

(I/O type 4 - VX1)

V_OL= 0.4 V

3.3 V LVCMOS

(I/O type 6 - PP)

N/A

Low-level output

current

3.3 V LVCMOS

(I/O type 8 - GPIO)

8

mA

3.3 V LVCMOS

(I/O type 9 - OSCA)

N/A

-

3.3 V LVCMOS

(I/O type 10 -

OSCB)

N/A

6

3.3 V OpenDrain

(I/O type 13 - I2C)

V_OL= 0.6 V

1.8 V LVCMOS

(I/O type 3 - LS

DMD)

N/A

3.3 V OpenDrain

(I/O type 4 - VX1)

-10

–10

N/A

10

3.3 V LVCMOS

(I/O type 6 - PP)

High-impedance

leakage current

3.3 V LVCMOS

(I/O type 8 - GPIO)

VOUT = VDD33

10

µA

3.3 V LVCMOS

(I/O type 9 - OSCA)

N/A

3.3 V LVCMOS

(I/O type 10 -

OSCB)

N/A

3.3 V OpenDrain

(I/O type 13 - I2C)

(1) The number inside each parenthesis for the I/O refers to the type defined in Table 5-13.

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6.7 DMD HSSI Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

400

590

NOM

MAX

1000

UNIT

Output Peak-to-Peak Differential ^{(1) (3)}

V_DIFF

Data

mVppd

(into floating load R_LOAD= 100 Ω)

Clock

Output common mode⁽³⁾

V_CM

200

700

mV

(into floating load R_LOAD= 100 Ω)

Output differential voltage^{(1) (2)}

(into floating load R_LOAD= 100 Ω)

Data

200

295

80

500

120

60

mV

Ω

|V_OD

|

Clock

R_DIFF

Differential termination resistance

Single-ended termination resistance

100

50

R_TERM

40

Ω

Differential output return loss

(100 MHz to 0.75 × Baud)

SDD22

SCC22

N_CM

-8

-6

dB

Common mode return loss

(100 MHz to 0.75 × Baud)

(7.5% × V_DIFF) +

25 mV

Transmitter common mode noise

mVppd

DJ_DATA

DJ_CLOCK

DCD

Deterministic jitter data (non-DCD)

Deterministic jitter clock (non-DCD)

Duty cycle distortion

0.20

0.16

0.05

0.30

UI pp

TJ

Total jitter (random + DJ)

(1) V_DIFF-pp= (Vp - Vn)cycle_N - (Vp - Vn)cycle_N+1 = 2 × |V_OD

|

See Figure 6-1.

(2) See link to HSSI characteristics

(3) Measured with a interconnect with insertion loss of 3dB at 1.6 GHz.|

Vp

|V_OD/2|

V_CM

Vn

|V_OD|

Figure 6-1. HSSI Differential Voltage Parameters

6.8 DMD Low-Speed LVDS Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

340

NOM

MAX

600

UNIT

mVppd

mV

Output peak-to-peak differential

(into R_LOAD= 100 Ω)

V_DIFF

V_CM

VAD18_LSIF (I/O type 2)

Steady-state common mode voltage

VAD18_LSIF (I/O type 2)

1100

170

1200

1300

300

Differential output voltage

(into R_LOAD= 100 Ω)

(1)

|V_OD

|

mV

|V_OD(Δ) |⁽²⁾

V_CM(Δ)

V_OH

V_ODchange (between logic states)

V_CMchange (between logic states)

Single-ended output voltage high ⁽³⁾

Single-ended output voltage low ⁽³⁾

Internal differential termination

VAD18_LSIF (I/O type 2)

25

mV

Ω

1450

V_OL

950

85

Tx_term

100

115

(1) V_DIFF-pp = (Vp - Vn)cycle_N - (Vp - Vn)cycle_N+1 = 2 × |V_OD

|

See Figure 6-2

(2) |V_OD(Δ)| = | | V_OD|cycle _N - |V_OD|cycle_N+1 |

(3) V_OH= 1300 + 300/2 = 1450; V_OL= 1100- 300/2 = 950

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Vp

V_CM

Vn

|V_OD/2|

|V_OD|

Figure 6-2. DMD Low-Speed Differential Voltage Parameters

6.9 V-by-One Interface Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽¹⁾

MIN

100

50

NOM

MAX

UNIT

mVppd

mV

V_DIFF

|V_ID|

Input peak-to-peak differential⁽²⁾

Differential input voltage⁽²⁾

VAD18_VX1 (I/O type 1)

Rx_term

Internal differential termination

80

100

120

Ω

(1) See the V-by-One interface standard for more information

(2) See link to v-by-one timinig

6.10 FPD-Link LVDS Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER ⁽¹⁾

MIN

200

100

0.25

90

NOM

MAX

UNIT

V_DIFF

|V_ID|

Input peak-to-peak differential

Differential input voltage

VDD33_FPD (I/O type 5)

1200 mVppd

600

2.4

mV

V

V_CM

Steady-state common mode voltage ⁽²⁾VDD33_FPD (I/O type 5)

Rx_term

Internal differential termination VDD33_FPD (I/O type 5)

110

132

Ω

(1) See Figure 6-14

(2) If V_CMfalls below V_CM(min)at the inputs to the receiver, an open input detection circuit is automatically enabled. This detection circuit

disables the receiver until the input V_CMrises above V_CM(min)

.

6.11 USB Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER^{(1) (2)}

MIN

NOM

MAX

UNIT

Low-Speed and Full Speed (Input Level)

Single-ended input voltage high

(driven)

V_IH

2.0

2.7

V

Single-ended input voltage high

(floating)

V_IHZ

3.6

0.8

V_IL

Single-ended input voltage low

Differential input sensitivity

V

V_DI

V_CM

|(DP) - (DM)|

0.2

0.8

Differential common mode voltage

Includes V_DIrange

2.5

Low-Speed and Full Speed (Output Level)

V_OL

Low-level output voltage

with 1.425KΩ pullup to 3.6V

with 14.25KΩ pulldown

0.0

2.8

1.3

0.3

3.6

2.0

V

V_OH

V_CRS

High-level output voltage

Output signal crossover voltage

High-Speed (Input Level)

High-speed squelch detection

threshold

V_HSSQ

100

150

mV

(differential signal amplitude)

High-speed disconnect detection

threshold

(differential signal amplitude)

V_HSDSC

525

-50

626

500

mV

High-speed data signal common mode

voltage

V_HSCM

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UNIT

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Over operating free-air temperature range (unless otherwise noted)

PARAMETER^{(1) (2)}

MIN

NOM

MAX

High-Speed (Output Level)

V_HSOI

V_HSOH

V_HSOL

High-speed idle level

–10.0

360

10.0

440

mV

High-speed data signal - high

High-speed data signal - low

–10.0

10.0

High-speed chirp J level (differential

voltage)

V_CHIRPJ

V_CHIRPK

700

1100

-500

mV

High-speed chirp K level (differential

voltage)

-900

Termination

R_PU

Bus pullup resistor

1.425

14.25

40.5

1.575

15.75

49.5

KΩ

Ω

R_PD

Bus pulldown resistor

Z_HSDRV

High-speed driver output impedance

(1) Referenced to VAD33_USB (I/O type 11)

(2) When used as a master as part of USB OTG, the DLPC7540 requires an External USB Switch to provide the USB 5-V power. The

example shown in Figure 6-3 makes use of a TI TPS2500/2501 device. The example figure does not describe the required ancillary

components (such as, resistors and capacitors). For this information please refer to the USB Switch logic datasheet for the selected

device. The External USB Switch is not required for product configurations that are supporting USB slave mode only.

1.8 V to 5.25 V

IN

EN

ENUSB

USB Power Switch

w/ Boost

Converter

USB

(TPS2500 or TPS2501)

GPIO_48

VBUS

Dœ

USB_VBUS

USB_DAT_N

USB_DAT_P

USB_ID

Micro

AB

Receptable

Controller

D+

ID

GND

Figure 6-3. External USB Switch Example for DLPC7540 Controller as USB OTG Master

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6.12 System Oscillator Timing Requirements

PARAMETER

MIN

NOM

40.000

25.000

MAX

UNIT

MHz

ns

ƒ_clockClock frequency, REFCLKA^{(1) (2)}

t_c

Cycle time, REFCLKA⁽¹⁾

PLLA: 40 MHz

39.9960

24.9975

40.0040

25.0025

PLLA: 40 MHz

50% to 50% reference points (signal)

t_w(H)Pulse duration⁽³⁾, REFCLKA, high

t_w(L)Pulse duration⁽³⁾, REFCLKA, low

11.25

ns

PLLA: 40 MHz

50% to 50% reference points (signal)

PLLA: 40 MHz

20% to 80% reference points (signal)

t_t

Transition time⁽³⁾, REFCLKA, t_t= t_ƒ/ t_r

2.5

18

Long term periodic jitter⁽³⁾, REFCLKA

(that is the deviation in period from

ideal period due solely to high

frequency jitter)

t_jp

PLLA: 40 MHz

ps

f_clockClock frequency, REFCLKB⁽¹⁾

t_c

Cycle time, REFCLKB⁽¹⁾

PLLB: 38 MHz

37.9962

26.3132

38.000

38.0038

MHz

ns

26.3157 26.3184

PLLB: 38 MHz

50% to 50% reference points (signal)

t_w(H)Pulse duration⁽³⁾, REFCLKB, high

t_w(L)Pulse duration⁽³⁾, REFCLKB, low

11.84

ns

PLLB: 38 MHz

50% to 50% reference points (signal)

PLLB: 38 MHz

20% to 80% reference points (signal)

t_t

Transition time⁽³⁾, REFCLKB, t_t= t_ƒ/ t_r

2.63

18

Long term periodic jitter⁽³⁾, REFCLKB

(that is the deviation in period from

ideal period due solely to high

frequency jitter)

t_jp

PLLB: 38 MHz

ps

(1) The REFCLK inputs do not support spread spectrum clock spreading.

(2) Multi-Controller systems require that a single oscillator be used to drive the REFCLKA input for all controllers in the system.

(3) Applies only when driven through an external digital oscillator. This is a 1 sigma RMS value.

t_t

t_c

t_w(H)

t_w(L)

80%

20%

80%

20%

50%

REFCLK

50%

Figure 6-4. System Oscillators

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6.13 Power Supply and Reset Timing Requirements

PARAMETER

MIN

MAX

UNIT

Power supply ramp for each supply

Ramp-up time: TOV × 10% to TOV × 90%

TOV = Typical Operational Voltage

Power supply ramp-up time.

⁽¹⁾Figure 6-5

t_RAMP-UP

0.01

10

ms

Total time within which the 1.15-V, 1.8-V, 1.21-V,

and 3.3-V supplies must complete their ramp-up

from the start of the 1.15-V ramp-up.

Ramp-up time: TOV × 10% to TOV × 90%

TOV = Typical Operational Voltage

Total power supply ramp-up

time.⁽¹⁾

t_{RAMP-UP-TOTAL}

100

ms

Power supply ramp for each supply

Ramp-down time: TOV × 90% to TOV × 10%

TOV = Typical Operational Voltage

Power supply ramp-down

t_RAMP-DOWN

0

100

ms

time. ⁽¹⁾Figure 6-5 Figure 6-6

t_{RAMP-DOWN-TOTAL}Total power supply ramp-

down time.⁽¹⁾

Total time within which the 1.15-V, 1.8-V, 1.21-

V, and 3.3-V supplies must complete their ramp-

down from the start of the 3.3-V ramp-up.

Ramp-down time: TOV × 90% to TOV × 10%

TOV = Typical Operational Voltage

1.8-V Supply Ramp-up Start Delay from 1.15-V supply ramp start to 1.8-V

Delay ⁽²⁾Figure 6-6

supply ramp start.

t_RUSD18

t_RUSD33

t_RUSD12

See ⁽³⁾

10

ms

3.3-V Supply Ramp-up Start Delay from 1.15-V supply ramp start to 3.3-V

Delay ⁽²⁾Figure 6-6

supply ramp start

50

1.21-V Supply Ramp-up Start Delay from 1.8-V supply ramp start to 1.21-V

See ⁽⁴⁾

Delay ⁽²⁾Figure 6-6

supply ramp start.

1.8-V Supply Ramp-down

Start Delay ⁽²⁾Figure 6-6

Delay from 1.21-V supply ramp start to 1.8-V

supply ramp start.

t_RDSD18

See ⁽⁵⁾

See⁽⁸⁾

t_RDSD115

1.15-V Supply Ramp-down

Start Delay ⁽²⁾Figure 6-6

Delay from 3.3-V supply ramp start to 1.15-V

supply ramp start.

PWRGOOD goes inactive low (as an early

warning) prior to any power supply voltage going

below the controller specification

Early Warning Time Figure

6-8

t_EW

t_PH

t_w1

500

500⁽⁹⁾

4

µs

POSENSE remains active after PWRGOOD is

disabled

Power Hold Time Figure 6-8

PWRGOOD inactive time while POSENSE is

active

50% to 50% reference points (signal)

Pulse duration, in-active low,

PWRGOOD Figure 6-7

1000 ⁽⁶⁾

625

Transition time, PWRGOOD

t_t1= t_ƒ1and t_r1

Figure 6-7

Rise and Fall time for PWRGOOD

20% to 80% reference points (signal)

t_t1

µs

ms

µs

POSENCE inactive time while PWRGOOD is

inactive

50% to 50% reference points (signal)

Pulse duration, in-active low,

POSENSE Figure 6-8

t_w2

100

Transition time, POSENSE

t_t1= t_ƒ1and t_r1

Figure 6-8

Rise and Fall time for POSENSE ⁽⁷⁾

20% to 80% reference points (signal)

t_t2

25

60

PWRGOOD Start Delay

Figure 6-7

Time after rising edge of POSENSE before

PWRGOOD effects DLPC7540 operation

t_PSD

51.5

10

ms

t_{PROJ_ON}

PROJ_ON fall time delay to

PWRGOOD Figure 6-8

Fall Delay

PROJ_ON 80% to PWRGOOD 80% fall time

start

t_REFCLKA

Time to stable REFCLKA

Figure 6-7

Time to stable REFLCKA before POSENSE

See ⁽¹⁰⁾

(1) It is assumed that all 1.15-V supplies come from the same source, although some can have additional filtering before entering the

DLPC7540. As such, it is expected these supplies to ramp together (aside from differences caused by filtering). This same expectation

is true for the 1.21-V, 1.8-V, and 3.3-V supplies.

(2) The DLPC7540 has specific power supply sequencing requirements which are listed below, and which also include the timings

specified in this table.

a. Power Up Order:

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i.

1.15-V (Core, Analog) » 1.8-V (I/O, SCS) » 1.21-V (SCS)

ii. 1.15-V (Core, Analog) » 3.3-V (I/O

b. Power Down Order:

i.

3.3-V (I/O) » 1.15-V (Core, Analog)

ii. 1.21-V (SCS) » 1.8-V (I/O, SCS) » 1.15-V (Core, Analog)

(3) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.15-V power

supply ramp-up is started, and the second event is when the 1.15-V supply ramp-up reaches 80% of TOV (at which point the 1.8-V

supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.15-V power supply,

the designer must determine the specific delay time.

(4) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.8-V power supply

ramp-up is started, and the second event is when the 1.8-V supply ramp-up reaches 80% of TOV (at which point the 1.21-V supply can

start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.8-V power supply, the designer

must determine the specific delay time.

(5) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.21-V power

supply ramp-down is started, and the second event is when the 1.21-V supply ramp-down reaches 20% of TOV (at which point the

1.8-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 1.21-V

power supply, the designer must determine the specific delay time.

(6) This max value is only applicable if the 1.8-V power remains ON while PWRGOOD is inactive. Otherwise, there is no maximum limit.

(7) As long as noise on this signal is below the hysteresis threshold

(8) This delay requirement parameter is defined as the time between two events. The first event is the point where the 3.3-V power supply

ramp-down is started, and the second event is when the 3.3-V supply ramp-down and 1.8-V supply ramp down reaches 10% of TOV

(at which point the 1.15-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific

design of the 3.3V and 1.8-V power supply, the designer must determine the specific delay time.

(9) If PROJ_ON is used for power down then Power Hold Time (t_PH) is not required.

(10) This delay requirement parameter is defined by design of RECLKA oscillator. Stable clock must be provided before releasing

POSENSE.

t_RAMP-UP

t_RAMP-DOWN

TOV

90%

10%

Figure 6-5. Power Supply Ramp Time

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t_{RAMP-UP-TOTAL}

t_{RAMP-DOWN-TOTAL}

90%

80%

1.15V (Core/Analog)

t_RDSD115

20%

10%

90%

80%

1.8V (I/O, SCS)

Note 1

t_RUSD18

10%

Note 2

90%

1.21V (SCS)

3.3V (I/O)

t_RUSD12

20%

t_RDSD18

10%

90%

t_RUSD33

10%

(10ms t 50ms)

10%

Note 1: No power up or power down timing dependency between 1.8V and 3.3V

Note 2: No power up or power down timing dependency between 1.21V and 3.3V

Figure 6-6. Power Supply Ramp Sequencing Profiles

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t_REFCLKA

DC Power

Supplies

t_t2

80%

POSENSE

20%

t_t1

80%

50%

80%

50%

PWRGOOD

20%

t_W1

t_PSD

Figure 6-7. Power Up Timing

t_{PROJ_ON}

80%

PROJ_ON

(If applicable)

20%

t_t1

80%

PWRGOOD

20%

t_PH

t_t2

80%

50%

80%

50%

POSENSE

20%

t_W2

t_EW

DC Power

Supplies

Figure 6-8. Power Down Timing

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6.14 DMD HSSI Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

2.4

312.5

50

NOM

MAX

3.2

UNIT

Gbps

ps

Baud

UI

Baud Rate

Unit Interval, 1/Baud

416.7

115

Differential output rise time ^{(1) (2)}

(0% to 100% of minimum eye mask height)

Data

Clock

Data

ps

t_R

50

135

ps

Differential output fall time^{(1) (2)}

(0% to 100% of minimum eye mask height)

50

115

ps

t_F

Clock

50

135

ps

t_X1

maximum eye closure⁽³⁾

at zero crossing

at minimum eye height

0.15

0.375

UI

t_X2

maximum eye closure⁽³⁾

UI

t_EYE

Differential Data Eye⁽³⁾

0.7

UI

t_skln2ln

t_skM2M

f_SSCD

f_MOD

Lane to lane skew within a macro⁽²⁾

Lane to lane skew macro to macro⁽²⁾

|200|

|4UI+200|

1

ps

Spread Spectrum (Down Spreading Only) ⁽⁴⁾When SSCD Enabled

Modulation Frequency ⁽⁴⁾

When SSCD Enabled

%

78.125

KHz

(1) Rise and Fall times are associated with V_DIFF-pp as shown in Figure 6-9

(2) Measured with an interconnect with an insertion loss of 3dB at 1.6 GHz

(3) See Figure 6-10

(4) When SSCD is enabled, the available modulation waveform is: Triangular

+V

/2

DIFF(PP)

100

90

V

OD(min)

80

70

V

DIFF(PP)

60

(0 V) 50

40

30

20

10

0

œV

OD(min)

/2

œV

DIFF(PP)

t_F.

t_R.

V_CMis removed when signals are viewed differentially

Figure 6-9. HSSI Differential Timing Parameters

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V_OD(max)

V_OD(min)

0 V

œV_OD(min)

œV_OD(max)

t_X2

t_X1

t_EYE

0

1 UI

Figure 6-10. HSSI Eye Characteristics

6.15 DMD Low-Speed LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

119.966

NOM

120

MAX

UNIT

fclock

120.034

250

MHz

Differential output rise time

(10% to 90%)

(1)

t_R

ps

Differential output fall time

(10% to 90%)

(1)

t_F

250

55

ps

%

DCD

Duty Cycle Distortion

45

(1) Rise and Fall times are associated with V_DIFF-pp as shown in Figure 6-11

+V

/2

DIFF(PP)

100

90

80

70

V

DIFF(PP)

60

(0 V) 50

40

30

20

10

0

œV

/2

DIFF(PP)

t_{F .}

t_R.

V_CMis removed when signals are viewed differentially

Figure 6-11. DMD Low-Speed Differential Timing Parameters

6.16 V-by-One Interface General Timing Requirements

PARAMETER⁽¹⁾

MIN

MAX

UNIT

40 (1 lane)

20 (1 lane with Pixel

Repeat) ⁽²⁾

600 (8

lanes)

f_clock

Source clock frequency

MHz

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UNIT

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PARAMETER⁽¹⁾

MIN

MAX

43

8 lanes

4 lanes

2 lanes

1 lane

75

85

f_link-ck

Link clock frequency per lane ⁽³⁾

MHz

43 (21.5 with Pixel

Repeat)

3-Byte Mode

4-Byte Mode

5-Byte Mode

2

2.15

2.55

3.0

f_link

Link transfer rate ⁽³⁾

Unit interval

Gbps

3-Byte Mode

4-Byte Mode

5-Byte Mode

392

294

500

ps

t_RBIT

t_A

Jitter Margin

0.25

0.05

0.5

UI

t_B

Rise / Fall Time

t_EYE

Differential Data Eye

Allowable intra-pair skew

Allowable Inter-pair Skew

Allowable Inter-pair frequency offset

Total jitter

UI

t_{skew_intra}

t_{skew_inter}

fo_{skew_inter}

T_j

0.3

5-

5

UI

–300

300

0.5

0.2

0.1

ppm

UI

-

R_j

Random jitter

10^12 UI

UI

D_j_ISI

S_j

Deterministic jitter (ISI)

Sinusoidal jitter

UI

(1) V-by-One high-speed technology supports 1, 2, 4 or 8 lane operation, in addition to 3-Byte, 4-Byte, and 5-Byte transfer modes

(2) Pixel repeat is a method used to support slower clock rate sources, whereby, the source come at twice the original clock rate, with

each data pixel being repeated once, and blanking being doubled as well. This method must operate external to DLPC7540. Once

received, the DLPC7540 discards each duplicate data pixel and blanking clock. Pixel repeat is supported only during 1- lane operation.

(3) For V-by-One high-speed technology, both link clock rate and link transfer rate limits must be met for any source.

V_ID(max)

V_ID(min)

V_DIFF

0 V

œV_ID(min)

œV_ID(max)

t_A

t_B

t_A

t_EYE

0

1 UI

Figure 6-12. V-by-One Timing

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6.17 FPD-Link Interface General Timing Requirements

PARAMETER

MIN

MAX

UNIT

ƒ_clock

Clock frequency, FPDA_CLK_P/N, FPDB_CLK_P/N

Clock period, FPDA_CLK_P/N, FPDB_CLK_P/N

Unit Interval (Figure 6-13)

20.0 (1

port)

10 (1 port

with pixel

repeat) ⁽¹⁾

330

(165 per

port)

MHz

t_clock

3.03

(6.06 per

port)

50 (1 port)

100 (1

ns

port with

pixel

repeat) ⁽¹⁾

t_RBIT

0.865 (per 7.143 (1

ns

port)

t_{skew_ports}

t_A

Clock to clock skew margin between ports on same Controller, and between

ports on different Controllers

1

clocks

Jitter Margin and Skew Margin between clock and data

(on the same port). See Figure 6-14

ƒ_clock≤ 90 MHz

ƒ_clock> 90 MHz

ƒ_clock≤ 90 MHz

ƒ_clock> 90 MHz

ƒ_clock≤ 90 MHz

ƒ_clock> 90 MHz

0.25

0.23

333

UI

ps

UI

t_B

Rise/Fall Time. See Figure 6-14

200

t_EYE

Differential Data Eye (Figure 6-14)

0.50

0.54

(1) Pixel repeat is a method used to support slower clock rate sources, whereby, the source come at twice the "original" clock rate, with

each data pixel being repeated once, and blanking being doubled. Both the pixel doubling and double blanking must be done external

to DLPC7540. The DLPC7540 discards each duplicate data pixel and blanking clock. The device supports pixel repeat only when

using 1 port.

T

Ideal

T/7

Reference

Position

Reference

Clock

t_skew

Data

D0(1)

UI

D0(0)

UI

D0(6)

D0(5)

UI

D0(4)

UI

D0(3)

UI

D0(2)

UI

UI Definition

UI

Figure 6-13. FPD-Link Data Skew

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V_ID(max)

V_ID(min)

0 V

V_DIFF

œV_ID(min)

œV_ID(max)

t_A

t_B

t_A

t_EYE

0

1 UI

Figure 6-14. FPD-Link Timing

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6.18 Source Frame Timing Requirements

See Figure 6-15

PARAMETER ⁽¹⁾

MIN

MAX

UNIT

50% reference

points

t_{p_vsw}

t_{p_vbp}

t_{p_vƒp}

t_{p_tvb}

t_{p_hsw}

t_{p_hbp}

t_{p_hfp}

t_{p_thb}

VSYNC Active Pulse Width

Vertical back porch (VBP) ⁽²⁾

Vertical front porch (VFP) ⁽²⁾

Total vertical blanking (TVB) ⁽²⁾

HSYNC Active Pulse Width

Horizontal back porch (HBP) ⁽⁵⁾

Horizontal front porch (HFP) ⁽⁵⁾

Total horizontal blanking (THB) ⁽⁵⁾

1

127

lines

50% reference

points

2 ⁽³⁾

lines

50% reference

points

MAX[ (TVB_MIN- 65 ), 1] ⁽³⁾

50% reference

points

See ⁽⁴⁾

16

lines

50% reference

points

PCLKs

50% reference

points

5 (Digital Video Sources)

65 (Analog Video Sources)

50% reference

points

2

50% reference

points

20 (Digital Video Sources)

80 (Analog Video Sources) ⁽⁶⁾

f_line

Horizontal line rate

37.354

640

K Hz

APPL

Active Pixels per Line

4096

Pixels

2400 (Low latency)

2160 (Normal)

ALPF

Active Lines per Frame

480

Lines

(1) The requirements in the table apply to all external sources

(2) Vertical Blanking Parameter Definitions:

a. Vertical Back Porch: Time from the leading edge of VSYNC to the leading edge of HSYNC for the first active line, and includes the

VSYNC pulse width t_{p_vsw}

.

b. Vertical Front Porch: Time from the leading edge of HSYNC following the last active line in a frame to the leading edge of VSYNC

c. Total Vertical Blanking: The sum of VBP + VFP = TVB.

(3) The vertical blanking required (per TVB) can be allocated as desired as long as the VFP and VBP minimum values are met.

(4) The minimum TVB can be calculated using the following:

TVBmin = 11 + ROUNDUP(LLS_VFP_MIN × (Source_ALPF/VPS_ALPF)), where:

a. LLS_VFP_MIN (Normal Mode) = 22

b. Source_ALPF = Active Lines Per Frame of the incoming source

c. VPS_ALPF = 1080 (for 1920x1080 Native products and 3840x2160 4-way XPR products)

d. Less TVBmin blanking can be required depending on the video processing being done. The configurations that drive the worst

case minimum value are those configurations that combine the maximum (or near maximum) capabilities of functions such as

scaling, warping, and keystone correction.

e. This is applicable to all sources (Section 7.4). Other sources require directed testing in the end application.

f.

The minimum recommended TVB with CVT 1.2 sources is 23.

(5) Horizontal Blanking Parameter Definitions:

a. Horizontal Back Porch: Time from the leading edge of HSYNC to the rising edge of DATEN, and includes the HSYNC pulse width

t_{p_hsw}

.

b. Horizontal Front Porch: Time from the falling edge of DATEN to the leading edge of HSYNC.

c. Total Horizontal Blanking: The sum of HBP + HFP = THB.

(6) The horizontal blanking required (per THB) can be allocated as desired as long as the HFP and HBP minimum values are met.

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1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

PDATA(23/15:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

Figure 6-15. Source Frame Timing

6.19 Synchronous Serial Port Interface Timing Requirements

For SSP0, SSP1 and SSP2⁽¹⁾⁽²⁾

PARAMETER

MIN

MAX

UNIT

SSP Master

f_clock

t_clock

t_w(L)

t_w(H)

t_delay

t_su

Clock frequency, SSPx_CLK

Clock Period, SSPx_CLK

50% to 50% reference points

0.38

25.6

12.0

-2.5

15.0

0

39.0

MHz

ns

ps

3632

Pulse duration low, SSPx_CLK

Pulse duration high, SSPx_CLK

Output Delay – SSPx_TXD (MOSI)

Setup time – SSPx_RXD (MISO)

hold time – SSPx_RXD (MISO)

Transition time (t_rand t_f- SSPx_RXD

Clock Jitter, SSPx_CLK

2.5

50% to 50% reference points

20% to 80% reference points

t_h

t_t

1.5

300

500

t_clkjit

t_delay∆

SSP Slave

t_delay

t_su

Clock output delay ∆ { | t_w(H)- t_w(L)| }

Output Delay – SSPx_TXD (MOSI)

Setup time – SSPx_RXD (MISO)

hold time – SSPx_RXD (MISO)

0

2.5

15

ns

50% to 50% reference points

t_h

(1) The DLPC7540 SPI interfaces support SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock phases) as shown in

Table 6-2 and Figure 6-16. As such, each SPI interface configuration must be setup to match the SPI mode being used.

(2) In most SPI applications, one clock edge is used by both master and slave devices for transmitting data while the other edge is use

by both for sampling received data. This is referred to as Standard SPI Protocol. To maximize the SPI_CLK frequency potential, SPI

masters can alternatively be designed to sample the data in (MISO) bit on the same clock edge used to transmit the next data out

(MOSI) bit. This is referred to as Enhanced SPI Protocol. The DLPC7540 SPI master implementation supports both protocols (part

of SPI interface configuration), however, to be able to use the "Enhanced SPI Protocol", the slave device must meet the requirement

shown in Figure 6-17.

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Table 6-2. SPI Clocking Modes

SPI Clocking Mode

SPI Clock Polarity

SPI Clock Phase

0

1

2

3

0

1

0

1

0

1

CSZ

CLK

(CPOL=0)

(CPOL=1)

(CPHA=0)

MSB

LSB

TXD/RXD

(CPHA=1)

LSB

MSB

Figure 6-16. Timing Diagram for SPI Clocking Modes

SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data held until end of last clock cycle

œ Supports Enhanced SPI Protocol

Controller MISO Sampling Edges

SPI_CSZ

SPI_CLK

SPI_MISO

MSb

LSb

œ Data not held until end of last clock cycle

œ Only supports Standard SPI Protocol

Controller MISO Sampling Edges

Figure 6-17. Requirement for Enhanced SPI Protocol

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t_clock

t_t

t_w(H)

t_w(L)

80%

SSPx_CLK

(Controller output)

50%

20%

t_delay(max)

t_delay(min)

Valid

SSPx_TXD

(Controller output)

Valid

t_su

t_h

SSPx_RXD

(Controller input)

Valid

SSPx_RXD

(Controller input)

Figure 6-18. Timing Diagram for SSP Master (Modes 0/3)

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6.20 Master and Slave I²C Interface Timing Requirements

For IIC0, IIC1 and IIC2

PARAMETER⁽¹⁾

MIN

MAX

UNIT

kHz

pF

f_clock

Clock frequency, IICx_SCL ⁽²⁾

(50% reference points)

Full speed

400

100

200

Standard mode

C_L

Capacitive Load (for each bus line)

(1) Meets all I²C timing per the I²C Bus Specification (except for capacitive loading as specified). For reference see Version 2.1 of the

Phillips-NXP specification.

(2) By definition, I²C transactions operate at the speed of the slowest device on the bus. Full Speed operation requires all other I²C

devices on the bus support Full Speed operation. The length of the line (due to its capacitance), as well as the value of the I²C pullup

resistors can reduce the obtainable clock rate.

6.21 Programmable Output Clock Timing Requirements

PARAMETER

f_clock

MIN

0.19

MAX

48.75

UNIT

MHz

ns

Clock frequency, OCLKA ⁽¹⁾

Clock period, OCLKA

t_clock

20.52

5263.15

t_w(H)

Pulse duration high, OCLKA

(50% reference points)

(t_clock/2) - 2

ns

t_w(L)

Pulse duration low, OCLKA

(50% reference points)

(t_clock/2) - 2

ns

ps

t_cclkjit

Jitter, OCLKA

200

f_clock

t_clock

t_w(H)

Clock frequency, OCLKB ⁽¹⁾

Clock period, OCLKB

0.19

20.52

48.75

MHz

ns

5263.15

Pulse duration high, OCLKB

(50% reference points)

(t_clock/2) - 2

ns

t_w(L)

Pulse duration low, OCLKB

(50% reference points)

(t_clock/2) - 2

ns

ps

t_cclkjit

Jitter, OCLKB

200

f_clock

t_clock

t_w(H)

Clock frequency, OCLKC ⁽¹⁾

Clock period, OCLKC

0.19

20.52

48.75

MHz

ns

5263.15

Pulse duration high, OCLKC

(50% reference points)

(t_clock/2) - 2

ns

t_w(L)

Pulse duration low, OCLKC

(50% reference points)

(t_clock/2) - 2

ns

ps

t_cclkjit

Jitter, OCLKC

200

f_clock

t_clock

t_w(H)

Clock frequency, OCLKD ⁽¹⁾

Clock period, OCLKD

0.19

20.52

48.75

MHz

ns

5263.15

Pulse duration high, OCLKD

(50% reference points)

(t_clock/2) - 2

ns

t_w(L)

Pulse duration low, OCLKD

(50% reference points)

(t_clock/2) - 2

ns

ps

t_cclkjit

Jitter, OCLKD

200

(1)

a. OCLKA is a dedicated pin, while OCLKB thru OCLKD are available via GPIO as alternate functions.

b. The frequency of OCLKA thru OCLKD is programmable, with each having a power-up default frequency of 0.77 MHz. This default

frequency is not that meaningful for OCLKB thru OCLKD since they must be configured to their alternate GPIO function before

they can be used as a clock output.

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6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)

See Figure 6-19

PARAMETER

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_clock

t_w(H)

t_w(L)

t_s

Clock frequency, TCK

20

Clock period, TCK

50

23

Pulse duration low, TCK

50% reference points

20% to 80% reference points

60pF load

ns

Pulse duration high, TCK

27

ns

Setup time – TDI valid before TCK↑

Hold time – TDI valid after TCK↑

Setup time – TMS1 valid before TCK↑

Hold time – TMS1 valid after TCK↑

Transition time (t_rand t_f

10

ns

t_h

ns

t_s

ns

t_h

ns

t_t

3

ns

t_delay

Output delay, TCK↓ to TDO1

0

15

ns

t_clock

t_t

t_w(H)

t_w(L)

80%

TCK

(Controller input)

50%

20%

t_su

t_h

TDI / TMS1

(Controller input)

50%

Valid

t_delay

TDO1

(Controller output)

50%

Valid

Figure 6-19. Timing Diagram for JTAG Boundary Scan

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6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)

See Figure 6-20

PARAMETER

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_clock

t_w(H)

t_w(L)

t_s

Clock frequency, TCK

8.33

Clock period, TCK

120

50

15

Pulse duration low, TCK

50% reference points

20% to 80% reference points

ns

Pulse duration high, TCK

ns

Setup time – TDI valid before TCK↑

Hold time – TDI valid after TCK↑

Setup time – TMS2 valid before TCK↑

Hold time – TMS2 valid after TCK↑

Transition time (t_rand t_f

ns

t_h

ns

t_s

ns

t_h

ns

t_t

5

ns

t_delay

Output delay, TCK↓ to TDO2

0

15

ps

t_clock

t_t

t_w(H)

t_w(L)

80%

TCK

(Controller input)

50%

20%

t_su

t_h

TDI / TMS2

(Controller input)

Valid

50%

t_delay

TDO2

(Controller output)

50%

Valid

Figure 6-20. Timing Diagram for JTAG ARM Multi-Ice

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6.24 Multi-Trace ETM Interface Timing Requirements

See Figure 6-21

PARAMETER⁽¹⁾

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_clock

t_w(H)

t_w(L)

Clock frequency, ETM_TRACECLK

Clock period, ETM_TRACECLK

Pulse duration low, ETM_TRACECLK

41.56

24.1

11.2

3.0

50% reference points

ns

Pulse duration high, ETM_TRACECLK 50% reference points

ns

t_delay

Output delay, ETM_TRACECLK↑ to

"ETM_OUTPUTS" ⁽²⁾

9.0

ps

t_delay

Output delay, ETM_TRACECLK↓ to

"ETM_OUTPUTS" ⁽²⁾

3.0

ps

(1) The trace interface is a source synchronous DDR interface. TRACE_CLK has a programmable delay to provide for centering its edges

in the center of the trace data to optimize performance.

(2) "ETM_OUTPUTS" are: TSTPT_(7:0) and ETM_TRACECTL

t_clock

t_t

t_w(H)

t_w(L)

80%

20%

TRACECLK

(Internal / Undelayed)

50%

t_delay

^9Ça_hÜÇtÜÇ{_

(Controller outputs)

TRACECLK

(External / Delayed)

Figure 6-21. Timing Diagram for Multi-Trace ETM

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7 Detailed Description

7.1 Overview

The DLPC7540 is DLP Products high resolution DMD controller. When coupled with the DLP471TE DMD or

the DLP650TE DMD and DLPA100 power and motor controller, it enables low cost, high brightness 4K UHD

displays. The DLPC7540 supports 4K UHD video up to 60Hz, as well as 1080p video up to 240Hz and 3D at

120Hz. Input formats include RBG, YCbCr and ICtCp (HDR10). Advanced video and color processing includes

HDR10, improved linear light space processing, DynamicBlack, frame rate conversion, and a full parametric

surface warping engine. It accepts 10-bit VbyOne, FPD-link. The DLPA100 has full illumination controls for LED,

laser phosphor, RGB laser and hybrid illumination. Also, includes the memory bus for Flash storage. Control

interfaces include SPI, I2C, UART, JTAG and USB2.0 OTG.

7.2 Functional Block Diagram

DLPC7540 Controller

VbyOne

RX

Vby One

DMD Data 1

DLP Image

Processing

and

Video Processing

Warp Engine

Frame Processing

DMD Data 2

HSG

Contrast

Scaling

1D, 2D, Keystone

Non-planar Surfaces

Camera assisted

FPD-Link 1

FPD-Link 2

FRC

3D

Splash Screen

FPDLink

RX (2x)

Formatting

Noise Reduction

EOTF

DMD Control

I/F

Micro-controller + Memory Controller + DMD Control

Figure 7-1. Functional Block Diagram

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7.3 Feature Description

7.3.1 Input Sources

Table 7-1. Supported Input Source Parameters ⁽¹⁾

Source Resolution: 2D

Source Resolution: 3D (per Eye) ^{(2) (3)}

Bits/Pixel Accepted Bits/Pixel Processed

(Max) (Max)

INTERFACE

Min

Max

FPD-Link

10

See ⁽⁴⁾

3840 × 2160

3840 × 2160 (FS)

3840 × 2160 (VP)

1024x1200(HPH)

V-by-One

12

See ⁽⁵⁾

3840 × 2160 (FS)

3840 × 2160 (VP)

1024x1200(HPH)

(1) The user must ensure that the resolution desired for a specific interface (e.g. FPD-Link) is within the bandwidth limits for that interface.

Some resolutions at standard vertical rates (e.g. 60 Hz) may not be viable for all interfaces.

(2) FS = Frame Sequential (Full Resolution), VP = Vertically Packed (Full Resolution), HPH = Horizontally Packed (Half Resolution).

(3) Using the Low Latency configuration, only frame sequential 3D sources are supported, which can be supported in only one of two

ways (since the Warp block is disabled when using the Low latency configuration). These are:

•

For low frame rate 3D sources (e.g. 48 Hz, 60 Hz per eye), the sequence must be used to increase the display rate up to a

appropriate value (e.g. 144 Hz, 120 Hz per eye).

•

For high frame rate 3D sources (e.g. 120 Hz per eye), the source is treated like a 2D source and just passed through, since the

source is providing the appropriate display rate.

(4) The minimum clock rate for the FPD-Link interface limits the smallest resolution that can be supported by this interface.

(5) The minimum clock rate and link rate for the V-by-One interface, as well as Byte Mode, limits the smallest resolution that can be

supported by this interface. This interface supports 3-Byte, 4-Byte, and 5-Byte modes.

7.3.2 Processing Delays

The DLPC7540 introduces a variable number of field/frame delays dependent on the source type and selected

processing steps performed on the source. For optimum audio/video synchronization this delay must be

matched in the audio path. The following tables define the various video delay scenarios to aid in audio

matching.

Because the input and output rates are different when frame rate conversion (FRC) is employed, the delay

through the FRC is variable.

7.3.3 FPD-Link Interface

The DLPC7540 supports two FPD-Link 5 lane ports which can be configured for single port use (Port A or Port

B), or for dual port use (Port A and Port B). The third FPD port (Port C) is reserved for parallel port use only. FPD

ports A and B support a limited set of remapping options within each port, but there is no remapping between

ports. When utilizing this feature, each unique lane pair can only be mapped to one unique destination lane

pair, and Intra-lane remapping (i.e. swapping P with N) is not supported. In addition, the A and B ports can be

swapped. Lane and port remapping (specified in flash) can help with board layout as needed. The typical lane

mapping is shown in Figure 7-2. An example of an alternate lane mapping is shown in Figure 7-3. The specific

intra port remapping options available are shown in Table 7-2.

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Controller

Internal

Intermediate

Data Path

Controller

Internal

Final

Controller

FPD Diff

Input

Controller

Internal

Lane Mux

Host

Actual

Data

Data Path

Host FPD

Diff Output

Port A

Even Data Path

FPDA_DATAA_P

FPDA_DATAA_N

FPDA_DATAB_P

FPDA_DATAB_N

FPDA_DATAC_P

FPDA_DATAC_N

FPDA_DATAD_P

FPDA_DATAD_N

FPDA_DATAE_P

FPDA_DATAE_N

FPD_EVEN_DAT_A_P

FPD_EVEN_DAT_A_N

FPD_EVEN_DAT_B_P

FPD_EVEN_DAT_B_N

FPD_EVEN_DAT_C_P

FPD_EVEN_DAT_C_N

FPD_EVEN_DAT_D_P

FPD_EVEN_DAT_D_N

FPD_EVEN_DAT_E_P

FPD_EVEN_DAT_E_N

RA

RB

RC

RD

RE

RA

RB

RC

RD

RE

FPDA_PA

FPDA_PB

FPDA_PC

FPDA_PD

FPDA_PE

FPD_E_PA

FPD_E_PB

FPD_E_PC

FPD_E_PD

FPD_E_PE

FPDA_CLK_P

FPDA_CLK_N

FPD_EVEN_CLK_P

FPD_EVEN_CLK_N

CKA

Port B

Odd Data Path

FPD_ODD_DAT_A_P

FPD_ODD_DAT_A_N

FPD_ODD_DAT_B_P

FPD_ODD_DAT_B_N

FPD_ODD_DAT_C_P

FPD_ODD_DAT_C_N

FPD_ODD_DAT_D_P

FPD_ODD_DAT_D_N

FPD_ODD_DAT_E_P

FPD_ODD_DAT_E_N

FPDB_DATAA_P

FPDB_DATAA_N

FPDB_DATAB_P

FPDB_DATAB_N

FPDB_DATAC_P

FPDB_DATAC_N

FPDB_DATAD_P

FPDB_DATAD_N

FPDB_DATAE_P

FPDB_DATAE_N

RA

RB

RC

RD

RE

RA

RB

RC

RD

RE

FPDB_PA

FPDB_PB

FPDB_PC

FPDB_PD

FPDB_PE

FPD_O_PA

FPD_O_PB

FPD_O_PC

FPD_O_PD

FPD_O_PE

FPDB_CLK_P

FPDB_CLK_N

FPD_ODD_CLK_P

FPD_ODD_CLK_N

CKB

LANE MUX

PORT MUX

Controller

Figure 7-2. Example of Typical FPD-Link Port Lane Mapping

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Internal

Final

Data Path

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Controller

Internal

Intermediate

Data Path

Controller

FPD Diff

Input

Controller

Internal

Lane Mux

Host

Actual

Data

Host FPD

Diff Output

Port A

Even Data Path

FPDA_DATAA_P

FPDA_DATAA_N

FPDA_DATAB_P

FPDA_DATAB_N

FPDA_DATAC_P

FPDA_DATAC_N

FPDA_DATAD_P

FPDA_DATAD_N

FPDA_DATAE_P

FPDA_DATAE_N

FPD_ODD_DAT_D_P

FPD_ODD_DAT_D_N

FPD_ODD_DAT_E_P

FPD_ODD_DAT_E_N

FPD_ODD_DAT_A_P

FPD_ODD_DAT_A_N

FPD_ODD_DAT_B_P

FPD_ODD_DAT_B_N

FPD_ODD_DAT_C_P

FPD_ODD_DAT_C_N

RD

RA

RB

RC

RD

RE

FPDA_PA

FPDA_PB

FPDA_PC

FPDA_PD

FPDA_PE

FPD_E_PA

RE

RA

RB

RC

FPD_E_PB

FPD_E_PC

FPD_E_PD

FPD_E_PE

FPDA_CLK_P

FPDA_CLK_N

FPD_ODD_CLK_P

FPD_ODD_CLK_N

CKA

Port B

Odd Data Path

FPD_EVEN_DAT_E_P

FPD_EVEN_DAT_E_N

FPD_EVEN_DAT_A_P

FPD_EVEN_DAT_A_N

FPD_EVEN_DAT_B_P

FPD_EVEN_DAT_B_N

FPD_EVEN_DAT_C_P

FPD_EVEN_DAT_C_N

FPD_EVEN_DAT_D_P

FPD_EVEN_DAT_D_N

FPDB_DATAA_P

FPDB_DATAA_N

FPDB_DATAB_P

FPDB_DATAB_N

FPDB_DATAC_P

FPDB_DATAC_N

FPDB_DATAD_P

FPDB_DATAD_N

FPDB_DATAE_P

FPDB_DATAE_N

RE

RA

RB

RC

RD

RA

RB

RC

RD

RE

FPDB_PA

FPDB_PB

FPDB_PC

FPDB_PD

FPDB_PE

FPD_O_PA

FPD_O_PB

FPD_O_PC

FPD_O_PD

FPD_O_PE

FPDB_CLK_P

FPDB_CLK_N

FPD_EVEN_CLK_P

FPD_EVEN_CLK_N

CKB

LANE MUX

PORT MUX

Controller

Figure 7-3. Example of Alternate FPD-Link Port Lane Mapping

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Table 7-2. FPD-Link Intra Port Data Mapping Options

Mapping Options for Ports A & B

Input Data Port

Internal Final Data Path

0

1

2

3

4

FPDx_DATAA_P/N

FPD_x_PA

FPDx_DATAB_P/N

FPDx_DATAC_P/N

FPDx_DATAD_P/N

FPDx_DATAE_P/N

FPD_x_PA

4

0

1

2

3

FPDx_DATAA_P/N

FPDx_DATAB_P/N

FPDx_DATAC_P/N

FPDx_DATAD_P/N

FPDx_DATAE_P/N

FPD_x_PB

3

4

0

1

2

FPDx_DATAA_P/N

FPDx_DATAB_P/N

FPDx_DATAC_P/N

FPDx_DATAD_P/N

FPDx_DATAE_P/N

FPD_x_PC

2

3

4

0

1

FPDx_DATAA_P/N

FPDx_DATAB_P/N

FPDx_DATAC_P/N

FPDx_DATAD_P/N

FPDx_DATAE_P/N

FPD_x_PD

1

2

3

4

0

FPDx_DATAA_P/N

FPDx_DATAB_P/N

FPDx_DATAC_P/N

FPDx_DATAD_P/N

FPDx_DATAE_P/N

FPD_x_PE

Independent from the remapping of the physical FPD interface, the DLPC7540 supports a number of data

mappings onto the actual physical interface. There are three different 30-bit data mappings, and two different

24-bit data mappings supported. FPD sources must match at least one of these mappings These are shown in

Table 7-3, Table 7-4, Table 7-5, Table 7-6, and Table 7-7.

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Table 7-3. FPD-Link Data Mapping onto Physical Interface (30-bit Mode 0)

Bit Mapping - 30-bit Mode 0 ⁽¹⁾

(30-bits per pixel)

Mapper Input

PA-6

RGB/YCbCr 4:4:4

YCbCr 4:2:2

Y[4]

YCbCr 4:2:0

Y00[4]

Mapper Output

G/Y[4]

R/Cr[9]

R/Cr[8]

R/Cr[7]

R/Cr[6]

R/Cr[5]

R/Cr[4]

A(4)

B(9)

B(8)

B(7)

B(6)

B(5)

B(4)

PA-5

PA-4

PA-3

PA-2

PA-1

PA-0

Cb/Cr[9]

Cb/Cr[8]

Cb/Cr[7]

Cb/Cr[6]

Cb/Cr[5]

Cb/Cr[4]

Cb/C00r[9]

Cb/Cr00[8]

Cb/Cr00[7]

Cb/Cr00[6]

Cb/Cr00[5]

Cb/Cr00[4]

PB-6

PB-5

PB-4

PB-3

PB-2

PB-1

PB-0

B/Cb[5]

B/Cb[4]

G/Y[9]

G/Y[8]

G/Y[7]

G/Y[6]

G/Y[5]

Unused

Y[9]

Y01[5]

Y01[4]

Y00[9]

Y00[8]

Y00[7]

Y00[6]

Y00[5]

C(5)

C(4)

A(9)

A(8)

A(7)

A(6)

A(5)

Y[8]

Y[7]

Y[6]

Y[5]

PC-6

PC-5

PC-4

PC-3

PC-2

PC-1

PC-0

Data En

VSYNC

HSYNC

B/Cb[9]

B/Cb[8]

B/Cb[7]

B/Cb[6]

Data En

VSYNC

HSYNC

Unused

Data En

VSYNC

HSYNC

Y01[9]

Y01[8]

Y01[7]

Y01[6]

Data En

VSYNC

HSYNC

C(9)

C(8)

C(7)

C(6)

PD-6

PD-5

PD-4

PD-3

PD-2

PD-1

PD-0

3D_L/R_Ref

B/Cb[3]

B/Cb[2]

G/Y[3]

3D_L/R_Ref

Unused

Y[3]

3D_L/R_Ref

Y01[3]

3D_Ref

C(3)

C(2)

A(3)

Y01[2]

Y00[3]

G/Y[2]

Y[2]

Y00[2]

A(2)

R/Cr[3]

R/Cr[2]

Cb/Cr[3]

Cb/Cr[2]

Cb/Cr00[3]

Cb/Cr00[2]

B(3)

B(2)

PE-6

PE-5

PE-4

PE-3

PE-2

PE-1

PE-0

Field

Unused

Y[1]

Field

Y01[1]

Field

C(1)

C(0)

A(1)

A(0)

B(1)

B(0)

B/Cb[1]

B/Cb[0]

G/Y[1]

G/Y[0]

R/Cr[1]

R/Cr[0]

Y01[0]

Y00[1]

Y[0]

Y00[0]

Cb/Cr[1]

Cb/Cr[0]

Cb/Cr00[1]

Cb/Cr00[0]

(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.

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Table 7-4. FPD-Link Data Mapping onto Physical Interface (30-bit Mode 1)

Bit Mapping - 30-bit Mode 1 ⁽¹⁾

(30-bits per pixel)

Mapper Input

PA-6

RGB/YCbCr 4:4:4

YCbCr 4:2:2

Y[2]

YCbCr 4:2:0

Y00[2]

Mapper Output

G/Y[2]

R/Cr[7]

R/Cr[6]

R/Cr(5]

R/Cr[4]

R/Cr[3]

R/Cr[2]

A(2)

B(7)

B(6)

B(5)

B(4)

B(3)

B(2)

PA-5

PA-4

PA-3

PA-2

PA-1

PA-0

Cb/Cr[7]

Cb/Cr[6]

Cb/Cr[5]

Cb/Cr[4]

Cb/Cr[3]

Cb/Cr[2]

Cb/C00r[7]

Cb/Cr00[6]

Cb/Cr00[5]

Cb/Cr00[4]

Cb/Cr00[3]

Cb/Cr00[2]

PB-6

PB-5

PB-4

PB-3

PB-2

PB-1

PB-0

B/Cb[3]

B/Cb[2]

G/Y[7]

G/Y[6]

G/Y[5]

G/Y[4]

G/Y[3]

Unused

Y[7]

Y01[3]

Y01[2]

Y00[7]

Y00[6]

Y00[5]

Y00[4]

Y00[3]

C(3)

C(2)

A(7)

A(6)

A(5)

A(4)

A(3)

Y[6]

Y[5]

Y[4]

Y[3]

PC-6

PC-5

PC-4

PC-3

PC-2

PC-1

PC-0

Data En

VSYNC

HSYNC

B/Cb[7]

B/Cb[6]

B/Cb[5]

B/Cb[4]

Data En

VSYNC

HSYNC

Unused

Data En

VSYNC

HSYNC

Y01[7]

Y01[6]

Y01[5]

Y01[4]

Data En

VSYNC

HSYNC

C(7)

C(6)

C(5)

C(4)

PD-6

PD-5

PD-4

PD-3

PD-2

PD-1

PD-0

3D_L/R_Ref

B/Cb[9]

B/Cb[8]

G/Y[9]

3D_L/R_Ref

Unused

Y[9]

3D_L/R_Ref

Y01[9]

3D_Ref

C(9)

C(8)

A(9)

Y01[8]

Y00[9]

G/Y[8]

Y[8]

Y00[8]

A(8)

R/Cr[9]

R/Cr[8]

Cb/Cr[9]

Cb/Cr[8]

Cb/Cr00[9]

Cb/Cr00[8]

B(9)

B(8)

PE-6

PE-5

PE-4

PE-3

PE-2

PE-1

PE-0

Field

Unused

Y[1]

Field

Y01[1]

Field

C(1)

C(0)

A(1)

A(0)

B(1)

B(0)

B/Cb[1]

B/Cb[0]

G/Y[1]

G/Y[0]

R/Cr[1]

R/Cr[0]

Y01[0]

Y00[1]

Y[0]

Y00[0]

Cb/Cr[1]

Cb/Cr[0]

Cb/Cr00[1]

Cb/Cr00[0]

(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.

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Table 7-5. FPD-Link Data Mapping onto Physical Interface (30-bit Mode 2)

Bit Mapping - 30-bit Mode 2 ⁽¹⁾

(30-bits per pixel)

Mapper Input

PA-6

RGB/YCbCr 4:4:4

YCbCr 4:2:2

Y[0]

YCbCr 4:2:0

Y00[0]

Mapper Output

G/Y[0]

R/Cr[5]

R/Cr[4]

R/Cr(3]

R/Cr[2]

R/Cr[1]

R/Cr[0]

A(0)

B(5)

B(4)

B(3)

B(2)

B(1)

B(0)

PA-5

PA-4

PA-3

PA-2

PA-1

PA-0

Cb/Cr[5]

Cb/Cr[4]

Cb/Cr[3]

Cb/Cr[2]

Cb/Cr[1]

Cb/Cr[0]

Cb/C00r[5]

Cb/Cr00[4]

Cb/Cr00[3]

Cb/Cr00[2]

Cb/Cr00[1]

Cb/Cr00[0]

PB-6

PB-5

PB-4

PB-3

PB-2

PB-1

PB-0

B/Cb[1]

B/Cb[0]

G/Y[5]

G/Y[4]

G/Y[3]

G/Y[2]

G/Y[1]

Unused

Y[5]

Y01[1]

Y01[0]

Y00[5]

Y00[4]

Y00[3]

Y00[2]

Y00[1]

C(1)

C(0)

A(5)

A(4)

A(3)

A(2)

A(1)

Y[4]

Y[3]

Y[2]

Y[1]

PC-6

PC-5

PC-4

PC-3

PC-2

PC-1

PC-0

Data En

VSYNC

HSYNC

B/Cb[5]

B/Cb[4]

B/Cb[3]

B/Cb[2]

Data En

VSYNC

HSYNC

Unused

Data En

VSYNC

HSYNC

Y01[5]

Y01[4]

Y01[3]

Y01[2]

Data En

VSYNC

HSYNC

C(5)

C(4)

C(3)

C(2)

PD-6

PD-5

PD-4

PD-3

PD-2

PD-1

PD-0

3D_L/R_Ref

B/Cb[7]

B/Cb[6]

G/Y[7]

3D_L/R_Ref

Unused

Y[7]

3D_L/R_Ref

Y01[7]

3D_Ref

C(7)

C(6)

A(7)

Y01[6]

Y00[7]

G/Y[6]

Y[6]

Y00[6]

A(6)

R/Cr[7]

R/Cr[6]

Cb/Cr[7]

Cb/Cr[6]

Cb/Cr00[7]

Cb/Cr00[6]

B(7)

B(6)

PE-6

PE-5

PE-4

PE-3

PE-2

PE-1

PE-0

Field

Unused

Y[9]

Field

Y01[9]

Field

C(9)

C(8)

A(9)

A(8)

B(9)

B(8)

B/Cb[9]

B/Cb[8]

G/Y[9]

G/Y[8]

R/Cr[9]

R/Cr[8]

Y01[8]

Y00[9]

Y[8]

Y00[8]

Cb/Cr[9]

Cb/Cr[8]

Cb/Cr00[9]

Cb/Cr00[8]

(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.

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Table 7-6. FPD-Link Data Mapping onto Physical Interface (24-bit Mode 0) ⁽¹⁾

Bit Mapping - 24-bit Mode 0 ⁽²⁾

(24-bits per pixel)

Mapper Input

PA-6

RGB/YCbCr 4:4:4

YCbCr 4:2:2

Y[0]

YCbCr 4:2:0

Y00[0]

Mapper Output

G/Y[0]

R/Cr[5]

R/Cr[4]

R/Cr(3]

R/Cr[2]

R/Cr[1]

R/Cr[0]

A(2)

B(7)

B(6)

B(5)

B(4)

B(3)

B(2)

PA-5

PA-4

PA-3

PA-2

PA-1

PA-0

Cb/Cr[5]

Cb/Cr[4]

Cb/Cr[3]

Cb/Cr[2]

Cb/Cr[1]

Cb/Cr[0]

Cb/C00r[5]

Cb/Cr00[4]

Cb/Cr00[3]

Cb/Cr00[2]

Cb/Cr00[1]

Cb/Cr00[0]

PB-6

PB-5

PB-4

PB-3

PB-2

PB-1

PB-0

B/Cb[1]

B/Cb[0]

G/Y[5]

G/Y[4]

G/Y[3]

G/Y[2]

G/Y[1]

Unused

Y[5]

Y01[1]

Y01[0]

Y00[5]

Y00[4]

Y00[3]

Y00[2]

Y00[1]

C(3)

C(2)

A(7)

A(6)

A(5)

A(4)

A(3)

Y[4]

Y[3]

Y[2]

Y[1]

PC-6

PC-5

PC-4

PC-3

PC-2

PC-1

PC-0

Data En

VSYNC

HSYNC

B/Cb[5]

B/Cb[4]

B/Cb[3]

B/Cb[2]

Data En

VSYNC

HSYNC

Unused

Data En

VSYNC

HSYNC

Y01[5]

Y01[4]

Y01[3]

Y01[2]

Data En

VSYNC

HSYNC

C(7)

C(6)

C(5)

C(4)

PD-6

PD-5

PD-4

PD-3

PD-2

PD-1

PD-0

3D_L/R_Ref or Field

B/Cb[7]

3D_L/R_Ref or Field

Unused

3D_L/R_Ref or Field

Y01[7]

3D_Ref or Field

C(9)

C(8)

A(9)

A(8)

B(9)

B(8)

B/Cb[6]

Unused

Y01[6]

G/Y[7]

Y[7]

Y00[7]

G/Y[6]

Y[6]

Y00[6]

R/Cr[7]

Cb/Cr[7]

Cb/Cr[6]

Cb/Cr00[7]

Cb/Cr00[6]

R/Cr[6]

PE-6

PE-5

PE-4

PE-3

PE-2

PE-1

PE-0

Unused

(1) To support 24 bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to

value '0'.

(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.

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Table 7-7. FPD-Link Data Mapping onto Physical Interface (24-bit Mode 1) ⁽¹⁾

Bit Mapping - 24-bit Mode 1 ⁽²⁾

(24-bits per pixel)

Mapper Input

PA-6

RGB/YCbCr 4:4:4

YCbCr 4:2:2

Y[2]

YCbCr 4:2:0

Y00{2}

Mapper Output

G/Y[2]

R/Cr[7]

R/Cr[6]

R/Cr(5]

R/Cr[4]

R/Cr[3]

R/Cr[2]

A(4)

B(9)

B(8)

B(7)

B(6)

B(5)

B(4)

PA-5

PA-4

PA-3

PA-2

PA-1

PA-0

Cb/Cr[7]

Cb/Cr[6]

Cb/Cr[5]

Cb/Cr[4]

Cb/Cr[3]

Cb/Cr[2]

Cb/C00r[7]

Cb/Cr00[6]

Cb/Cr00[5]

Cb/Cr00[4]

Cb/Cr00[3]

Cb/Cr00[2]

PB-6

PB-5

PB-4

PB-3

PB-2

PB-1

PB-0

B/Cb[3]

B/Cb[2]

G/Y[7]

G/Y[6]

G/Y[5]

G/Y[4]

G/Y[3]

Unused

Y[7]

Y01[3]

Y01[2]

Y00[7]

Y00[6]

Y00[5]

Y00[4]

Y00[3]

C(5)

C(4)

A(9)

A(8)

A(7)

A(6)

A(5)

Y[6]

Y[5]

Y[4]

Y[3]

PC-6

PC-5

PC-4

PC-3

PC-2

PC-1

PC-0

Data En

VSYNC

HSYNC

B/Cb[7]

B/Cb[6]

B/Cb[5]

B/Cb[4]

Data En

VSYNC

HSYNC

Unused

Data En

VSYNC

HSYNC

Y01[7]

Y01[6]

Y01[5]

Y01[4]

Data En

VSYNC

HSYNC

C(9)

C(8)

C(7)

C(6)

PD-6

PD-5

PD-4

PD-3

PD-2

PD-1

PD-0

3D_L/R_Ref or Field

B/Cb[1]

3D_L/R_Ref or Field

Unused

3D_L/R_Ref or Field

Y01[1]

3D_Ref or Field

C(3)

C(2)

A(3)

A(2)

B(3)

B(2)

B/Cb[0]

Unused

Y01[0]

G/Y[1]

Y[1]

Y00[1]

G/Y[0]

Y[0]

Y00[0]

R/Cr[1]

Cb/Cr[1]

Cb/Cr[0]

Cb/Cr00[1]

Cb/Cr00[0]

R/Cr[0]

PE-6

PE-5

PE-4

PE-3

PE-2

PE-1

PE-0

Unused

(1) To support 24 bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to

value '0'.

(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.

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7.3.4 V-by-One interface

The DLPC7540 Controller supports a single 8 lane V-by-One port which can be configured for 1, 2, 4 or 8 lane

use. This interface supports limited lane remapping which is shown in . Intra-lane remapping (i.e. swapping P

with N) is not supported.

Independent from the remapping of the physical V-by-One interface, the DLPC7540 supports a number of data

mappings onto the actual physical interface as specified by the standard. V-by-One sources must match at least

one of these mappings These are shown in Table 7-8, Table 7-9, Table 7-10, Table 7-11, Table 7-12, Table 7-13,

Table 7-14, Table 7-15, Table 7-16, and Table 7-17.

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Table 7-8. V-by-One Data Mapping for 36bpp/30bpp RGB/YCbCr 4:4:4

V-by-One Data Map Mode 0

V-by-One Input Data Bit

D[0]

36bpp RGB/YCbCr 4:4:4 ⁽¹⁾

R/Cr[4]

30bpp RGB/YCbCr 4:4:4

R/Cr[2]

R/Cr[3]

R/Cr[4]

R/Cr(5]

R/Cr[6]

R/Cr[7]

R/Cr[8]

R/Cr[9]

G/Y[2]

Mapper Output

B(2)

D[1]

R/Cr[5]

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

D[2]

R/Cr[6]

D[3]

R/Cr[7]

D[4]

R/Cr[8]

D[5]

R/Cr[9]

D[6]

R/Cr[10]

R/Cr[11]

G/Y[4]

D[7]

D[8]

D[9]

G/Y[5]

G/Y[3]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

D[26]

D[27]

D[28]

D[29]

D[30]

D[31]

G/Y[6]

G/Y[4]

G/Y[7]

G/Y[5]

G/Y[8]

G/Y[6]

G/Y[9]

G/Y[7]

G/Y[10]

G/Y[11]

B/Cb[4]

B/Cb[5]

B/Cb[6]

B/Cb[7]

B/Cb[8]

B/Cb[9]

B/Cb[10]

B/Cb[11]

G/Y[8]

G/Y[9]

B/Cb[2]

B/Cb[3]

B/Cb[4]

B/Cb[5]

B/Cb[6]

B/Cb[7]

B/Cb[8]

B/Cb[9]

B/Cb[2]

B/Cb[3]

G/Y[2]

G/Y[3]

R/Cr[2]

R/Cr[3]

B/Cb[1]

B/Cb[0]

G/Y[1]

G/Y[0]

R/Cr[1]

R/Cr[0]

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

(1) For 36-bit inputs, the 12-bits per color truncates to 10-bits per color with the two least significant-bits per color being discarded.

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Table 7-9. V-by-One Data Mapping for 27bpp RGB/YCbCr 4:4:4

V-by-One Data Map Mode 1

V-by-One Input Data Bit

27bpp RGB/YCbCr 4:4:4 ⁽¹⁾

R/Cr[1]

Mapper Output

D[0]

D[1]

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

R/Cr[2]

D[2]

R/Cr[3]

D[3]

R/Cr[4]

D[4]

R/Cr[5]

D[5]

R/Cr[6]

D[6]

R/Cr[7]

D[7]

R/Cr[8]

D[8]

G/Y[1]

D[9]

G/Y[2]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

'0'

G/Y[3]

G/Y[4]

G/Y[5]

G/Y[6]

G/Y[7]

G/Y[8]

B/Cb[1]

B/Cb[2]

B/Cb[3]

B/Cb[4]

B/Cb[5]

B/Cb[6]

B/Cb[7]

B/Cb[8]

-

B/Cb[0]

-

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

D[27]

'0'

D[29]

'0'

G/Y[0]

-

D[31]

R/Cr[0]

(1) For 27-bit inputs, the 9-bits for each color shifts up one bit, and the least significant bit of each color is set to '0'.

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Table 7-10. V-by-One Data Mapping for 24bpp RGB/YCbCr 4:4:4

V-by-One Data Map Mode 2

V-by-One Input Data Bit

24bpp RGB/YCbCr 4:4:4 ⁽¹⁾

R/Cr[0]

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

'0'

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

R/Cr[1]

R/Cr[2]

R/Cr[3]

R/Cr[4]

R/Cr[5]

R/Cr[6]

R/Cr[7]

G/Y[0]

G/Y[1]

G/Y[2]

G/Y[3]

G/Y[4]

G/Y[5]

G/Y[6]

G/Y[7]

B/Cb[0]

B/Cb[1]

B/Cb[2]

B/Cb[3]

B/Cb[4]

B/Cb[5]

B/Cb[6]

B/Cb[7]

-

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

'0'

(1) For 24-bit inputs, the 8-bits for each color shifts up two bits, and the two least significant bits of each color are set to '0'.

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Table 7-11. V-by-One Data Mapping for 32bpp/24bpp/20bpp YCbCr 4:2:2 ⁽¹⁾

V-by-One Data Map Mode 3

V-by-One Input Data Bit

32bpp YCbCr 4:2:2 ⁽²⁾

24bpp YCbCr 4:2:2 ⁽³⁾

20bpp YCbCr 4:2:2

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

'0'

CbCr[8]

CbCr[4]

CbCr[2]

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

CbCr[9]

CbCr[5]

CbCr[3]

CbCr[10]

CbCr[6]

CbCr[4]

CbCr[11]

CbCr[7]

CbCr[5]

CbCr[12]

CbCr[8]

CbCr[6]

CbCr[13]

CbCr[8]

CbCr[7]

CbCr[14]

CbCr[10]

CbCr[8]

CbCr[15]

CbCr[11]

CbCr[9]

Y[8]

Y[4]

Y[2]

Y[9]

Y[5]

Y[3]

Y[10]

Y[6]

Y[4]

Y[11]

Y[7]

Y[5]

Y[12]

Y[8]

Y[6]

Y[13]

Y[9]

Y[7]

Y[14]

Y[10]

Y[8]

Y[15]

Y[11]

Y[9]

-

'0'

D[24]

D[25]

'0'

-

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

'0'

-

D[28]

D[29]

D[30]

D[31]

Y[6]

Y[2]

Y[7]

Y[3]

CbCr[6]

CbCr[7]

CbCr[2]

CbCr[3]

CbCr[2]

CbCr[3]

(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".

(2) For 32-bit inputs, the 16-bits per color truncates to 10-bit per color, with the six least significant-bits per color discarded.

(3) For 24-bit inputs, the 12-bits per color truncates to 10-bit per color, with the two least significant-bits per color discarded.

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Table 7-12. V-by-One Data Mapping for 18bpp YCbCr 4:2:2⁽¹⁾

V-by-One Data Map Mode 4

V-by-One Input Data Bit

18bpp YCbCr 4:2:2 ⁽²⁾

CbCr[1]

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

'0'

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

CbCr[2]

CbCr[3]

CbCr[4]

CbCr[5]

CbCr[6]

CbCr[7]

CbCr[8]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

-

'0'

D[24]

D[25]

'0'

-

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

'0'

-

'0'

-

Y[0]

-

D[29]

'0'

D[31]

CbCr[0]

(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".

(2) For 18-bit inputs, the 9-bits for each color shifts up one bit, and the least significant bits of each color is set to '0'.

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Table 7-13. V-by-One Data Mapping for 16bpp YCbCr 4:2:2⁽¹⁾

V-by-One Data Map Mode 5

V-by-One Input Data Bit

16bpp YCbCr 4:2:2 ⁽²⁾

CbCr[0]

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

'0'

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

CbCr[1]

CbCr[2]

CbCr[3]

CbCr[4]

CbCr[5]

CbCr[6]

CbCr[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

-

'0'

D[24]

D[25]

'0'

-

C[0]

C[1]

A[0]

A[1]

B[0]

B[1]

'0'

(1) For all YCbCr 4:2:2 formats, data channel C is forced to "0".

(2) For 16-bit inputs, the 8-bits for each color shifts up one bit, and the least significant bit of each color is set to '0'.

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Table 7-14. V-by-One Data Mapping Example for 12bpp/10bpp YCbCr 4:2:0⁽¹⁾

V-by-One Data Map Mode 6

V-by-One Input Data 12bpp YCbCr 4:2:0

Bit

12bpp YCbCr 4:2:0 10bpp YCbCr 4:2:0

Odd Line ⁽²⁾

Even Line

10bpp YCbCr 4:2:0 Mapper Output

Odd Line

Even Line⁽²⁾

D[0]

D[1]

Y01[4]

Y01[4] Y01[2]

Y11[2]

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

Y01[5]

Y01[6]

Y01[5]

Y01[6]

Y01[3]

Y01[4]

Y01[5]

Y01[6]

Y01[7]

Y01[8]

Y01[9]

Y00[2]

Y00[3]

Y00[4]

Y00[5]

Y00[6]

Y00[7]

Y00[8]

Y00[9]

Cb00[2]

Cb00[3]

Cb00[4]

Cb00[5]

Cb00[6]

Cb00[7]

Cb00[8]

Cb00[9]

Y11[3]

Y11[4]

Y11[5]

Y11[6]

Y11[7]

Y11[8]

Y11[9]

Y10[2]

Y10[3]

Y10[4]

Y10[5]

Y10[6]

Y10[7]

Y10[8]

Y10[9]

Cr00[2]

Cr00[3]

Cr00[4]

Cr00[5]

Cr00[6]

Cr00[7]

Cr00[8]

Cr00[9]

D[2]

D[3]

Y01[7]

D[4]

Y01[8]

D[5]

Y01[9]

D[6]

Y01[10]

Y01[11]

Y00[4]

Y01[10]

Y01[11]

Y00[4]

D[7]

D[8]

D[9]

Y00[5]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

D[26]

D[27]

D[28]

D[29]

D[30]

D[31]

Y00[6]

Y00[7]

Y00[8]

Y00[9]

Y00[10]

Y00[11]

Cb00[4]

Cb00[5]

Cb00[6]

Cb00[7]

Cb00[8]

Cb00[9]

Cb00[10]

Cb00[11]

Y00[10]

Y00[11]

Cr00[4]

Cr00[5]

Cr00[6]

Cr00[7]

Cr00[8]

Cr00[9]

Cr00[10]

Cr00[11]

Cb00[2]

Cb00[3]

Y00[2]

Y00[3]

Y01[2]

Y01[3]

Cr00[2]

Cr00[3]

Y10[2]

Y10[3]

Y11[2]

Y11[3]

Cb00[0]

Cb00[1]

Y00[0]

Y00[1]

Y01[0]

Y01[1]

Cr00[0]

Cr00[1]

Y10[0]

Y10[1]

Y11[0]

Y11[1]

B[0]

B[1]

A[0]

A[1]

C[0]

C[1]

(1) For all YCbCr 4:2:0 inputs, two consecutive pixel Luma values are brought in on each clock. Even lines carry the Cb values, and odd

lines carry the Cr values.

(2) For 12bpp YCbCr 4:2:0 inputs, the 12-bits per color truncates to 10-bits per color with the two least significant-bits per color discarded.

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Table 7-15. V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0⁽¹⁾

V-by-One Data Map Mode 7

V-by-One Input Data Bit

8bpp YCbCr 4:2:0

Even Line ⁽²⁾

8bpp YCbCr 4:2:0

Odd Line ⁽²⁾

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

'0'

Y01[0]

Y11[0]

Y11[1]

Y11[2]

Y11[3]

Y11[4]

Y11[5]

Y11[6]

Y11[7]

Y10[0]

Y10[1]

Y10[2]

Y10[3]

Y10[4]

Y10[5]

Y10[6]

Y10[7]

Cr00[0]

Cr00[1]

Cr00[2]

Cr00[3]

Cr00[4]

Cr00[5]

Cr00[6]

Cr00[7]

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

Y01[1]

Y01[2]

Y01[3]

Y01[4]

Y01[5]

Y01[6]

Y01[7]

Y00[0]

Y00[1]

Y00[2]

Y00[3]

Y00[4]

Y00[5]

Y00[6]

Y00[7]

Cb00[0]

Cb00[1]

Cb00[2]

Cb00[3]

Cb00[4]

Cb00[5]

Cb00[6]

Cb00[7]

-

B[0]

B[1]

A[0]

A[1]

C[0]

C[1]

'0'

(1) For all YCbCr 4:2:0 inputs, two consecutive pixel Luma values are brought in on each clock. Even lines carry the Cb values, and odd

lines carry the Cr values.

(2) For 8bpp YCbCr 4:2:0 inputs, the 8-bits for each color shifts up two bits, and the two least significant bits of each color are set to '0'.

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Table 7-16. V-by-One Data Mapping Example for 10bpp YCbCr 4:2:0 ⁽¹⁾

V-by-One Data Map Mode 8

V-by-One Input Data Bit

10bpp YCbCr 4:2:0

Even Line

10bpp YCbCr 4:2:0

Odd Line

Mapper Output

D[0]

D[1]

Y00[2]

Y003]

Y10[2]

Y10[3]

Y10[4]

Y10[5]

Y10[6]

Y10[7]

Y10[8]

Y10[9]

Cr00[2]

Cr00[3]

Cr00[4]

Cr00[5]

Cr00[6]

Cr00[7]

Cr00[8]

Cr00[9]

Y11[2]

Y11[3]

Y11[4]

Y11[5]

Y11[6]

Y11[7]

Y11[8]

Y11[9]

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

D[2]

Y00[4]

Y00[5]

Y00[6]

Y00[7]

Y00[8]

Y00[9]

Cb00[2]

Cb00[3]

Cb00[4]

Cb00[5]

Cb00[6]

Cb00[7]

Cb00[8]

Cb00[9]

Y01[2]

Y01[3]

Y01[4]

Y01[5]

Y01[6]

Y01[7]

Y01[8]

Y01[9]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

D[26]

D[27]

D[28]

D[29]

D[30]

D[31]

Y01[0]

Y01[1]

Cb00[0]

Cb00[1]

Y00[0]

Y00[1]

Y11[0]

Y11[1]

Cr00[0]

Cr00[1]

Y10[0]

Y10[1]

C[0]

C[1]

B[0]

B[1]

A[0]

A[1]

(1) For all YCbCr 4:2:0 inputs, two consecutive pixel Luma values are brought in on each clock. Even lines carry Cb values, and odd lines

carry the Cr values.

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Table 7-17. V-by-One Data Mapping Example for 8bpp YCbCr 4:2:0 ⁽¹⁾

V-by-One Data Map Mode 9

V-by-One Input Data Bit

8bpp YCbCr 4:2:0

Even Line ⁽²⁾

8bpp YCbCr 4:2:0

Odd Line ⁽²⁾

Mapper Output

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

D[12]

D[13]

D[14]

D[15]

D[16]

D[17]

D[18]

D[19]

D[20]

D[21]

D[22]

D[23]

D[24]

D[25]

'0'

Y00[0]

Y10[0]

Y10[1]

Y10[2]

Y10[3]

Y10[4]

Y10[5]

Y10[6]

Y10[7]

Cr00[0]

Cr00[1]

Cr00[2]

Cr00[3]

Cr00[4]

Cr00[5]

Cr00[6]

Cr00[7]

Y11[0]

Y11[1]

Y11[2]

Y11[3]

Y11[4]

Y11[5]

Y11[6]

Y11[7]

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

Y00[1]

Y00[2]

Y003]

Y00[4]

Y00[5]

Y00[6]

Y00[7]

Cb00[0]

Cb00[1]

Cb00[2]

Cb00[3]

Cb00[4]

Cb00[5]

Cb00[6]

Cb00[7]

Y01[0]

Y01[1]

Y01[2]

Y01[3]

Y01[4]

Y01[5]

Y01[6]

Y01[7]

-

C[0]

C[1]

B[0]

B[1]

A[0]

A[1]

'0'

(1) For all YCbCr 4:2:0 inputs, two consecutive pixel Luma values are brought in on each clock. Even lines carry the Cb values, and odd

lines carry the Cr values.

(2) For 8bpp YCbCr 4:2:0 inputs, the 8-bits for each color shifts up two bits, and the two least significant bits of each color are set to '0'.

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7.3.5 DMD (HSSI) Interface

The DLPC7540 Controller DMD interface supports two High Speed Serial Interface (HSSI) output-only interfaces

for data transmission, a single low speed LVDS output-only interface for command write transactions, as well

as a low speed single-ended input interface used for command read transactions. Each HSSI port supports full

data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique

data lane pair can only be mapped to one unique destination data lane pair, and Intra-lane remapping (i.e.

swapping P with N) is not supported. In addition, the two HSSI ports can also be swapped. Lane and port

remapping (specified in flash) can help with board layout as needed. The number of HSSI ports and number of

HSSI lanes/per HSSI port required are based on DMD type and DMD display resolution. Table 7-18 shows some

remapping examples. When both ports are used, they do not need to have the same pin mapping.

Table 7-18. Controller to DMD Pin Mapping Examples

DLPC7540 Controller PINS - REMAPPING EXAMPLES TO DMD PINS

SWAP HSSI0 PORT

WITH HSSI1 PORT AND

MIXED REMAPPING

DMD PINS

FLIP HSSI0 180

No FLIP HSSI1

SWAP HSSI0 PORT

WITH HSSI1 PORT

BASELINE

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

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7.3.6 Program Memory Flash Interface

The DLPC7540 provides three external program memory chip selects for devices to access the program

memory interface. These are detailed in Table 7-19.

Table 7-19. Program Memory Interface Chip Selects

CHIP SELECT

NAME

MAXIMUM SIZE

SUPPORTED ⁽¹⁾

CHIP SELECT USE

DATA BUS WIDTH

ACCESS TIME

PM_CSZ_0

PM_CSZ_1

PM_CSZ_2

Boot FLASH only - Required ⁽²⁾

(or additional FLASH) - Optional

Additional Peripheral Device - Optional

16 bits

< = 120ns

256Mb

(1) Using GPIO_47 as additional address bit

(2) Boot FLASH type supported is Standard NOR parallel FLASH, single or multi-bank.

FLASH access timing is software programmable with up to 31 wait states. Additional information about read and

write wait state timing is provided in Table 7-20 and Figure 7-4.

Table 7-20. Program Memory Wait State Timing

PARAMETER

EQUATION ⁽¹⁾

T_WSR: Wait State Resolution

6ns

(2) (3)

Read Wait States

ROUNDUP(MAX(T_ACC, T_CE,T_OE)/T_WSR-N)

(Number of Read Wait States for each CSz read access)

(2)

Write Wait States for T_CSand T_AS

(Time from CS/Address activation to WRZ assertion)

ROUNDUP(MAX(T_CS+5ns, T_AS+5ns)/T_WSR-N

ROUNDUP(MAX(T_WP+5ns, T_DS+5ns)/T_WSR-N

ROUNDUP(MAX(T_CH+5ns, T_DH+5ns)/T_WSR-N

)

Write Wait States for T_WPand T_DS

(Time from WRZ assertion to WEZ de-assertion)

)

Write Wait States for T_CHand T_DH

)

(Time from CS/Address activation to WRZ assertion)

(1)

a. T_ACC: Read Access Time (ADDR to DATA valid) – (address valid to DATA valid)

b. T_CE: Read Access Time (CSZ to DATA valid) – (chip select active to DATA valid)

c. T_OE: Read Access Time (OEZ to DATA valid) – (output enable active to DATA valid)

d. T_CS: CSZ Setup Time (Writes) – (chip select active before negedge(WEZ)

e. T_CS: Address Setup Time (Writes) – (address valid before negedge(WEZ)

f.

T_AS: Address Setup Time (Writes) – (address valid before negedge(WEZ)

g. T_WP: Write Pulse Width (Writes) – (WEZ active low time)

h. T_DS: Data Setup Time (Writes) – (DATA valid before posedge(WEZ)

i.

j.

T_CH: CSZ Hold Time (Writes) – (CSZ held active after posedge(WEZ)

T_DH: Data Hold Time (Writes) – (DATA held valid after posedge(WEZ)

(2) Requires a minimum of at least 1 wait state

(3) Assumes a maximum single direction trace length of 90 mm (3.5 inches)

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At least one turnaround cycle guaranteed

(to prevent data bus contention)

32-bit write

WRITE WS

READ WS

T_H

T_WP

T_S

HW

T_RD

T_WC

T_RC

T_WRC

CSZ

A_R0

A_R1

A_W0

WD_15:0

A_W1

WD_31:16

ADDR

DATA

T_DH

RD_15:0

RD_31:16

T_DS

T_AH

T_DF

T_ACC, T_CE, T_OE

WEZ

T_WPH

T_OEH

T_AS, T_CS

OEZ

T_CH

T_WP

UBZ (for SRAM)

LBZ (for SRAM)

Figure 7-4. Program Memory Interface Timing Diagram

7.3.7 GPIO Supported Functionality

The DLPC7540 provides 88 general purpose I/O that are available to support a variety of functions for many

different product configurations. In general, most of these I/O pins support only one specific function based on a

specific product configuration, although that function can be different for a different product configuration. Most

of these I/O can also be made available for TI test and debug use. Each of the following GPIO tables provide

product specific details on the allocated use of each of the GPIO for a specific supported product configuration.

7.3.8 Debug Support

The DLPC7540 contains a test point output port, TSTPT_(7:0), which provides the Host with the ability to provide

for Controller debug support. For initial debug operation, the four signals (TSTPT(3:0)) are sampled as inputs

approximately 1.5 µs after PWRGOOD goes high (or after a system reset). Once their input state has been

sampled and captured, this information is used to setup the initial test mode output state of the TSTPT_(7:0)

bus. Table 7-21 defines the test mode selection for a few programmable output states for TSTPT_(7:0). Use the

default state of 0000 (defined by the required external pulldown resistors) for normal operation (that is, no debug

required).

To allow TI to make use of this debug capability, providing for the option of a jumper to an external pullup is

recommended for TSTPT(3:0), as well as providing access to allow observation of the TSTPT bus outputs.

Table 7-21. Examples of Test Mode Selection Outputs Defined by TSTPT(3:0)⁽¹⁾

TSTPT(3:0) CAPTURED VALUES

TSTPT_(7:0)

OUTPUT

0000 (DEFAULT)

(NO SWITCHING

ACTIVITY)

0101

1000

CLOCK DEBUG SYSTEM CALIBRATION

TSTPT(0)

TSTPT(1)

0

HIGH

Vertical Sync

166.25 MHz

Delayed CW Index

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Table 7-21. Examples of Test Mode Selection Outputs Defined by TSTPT(3:0)⁽¹⁾

(continued)

TSTPT(3:0) CAPTURED VALUES

TSTPT_(7:0)

OUTPUT

0000 (DEFAULT)

(NO SWITCHING

ACTIVITY)

0101

1000

CLOCK DEBUG SYSTEM CALIBRATION

TSTPT(2)

TSTPT(3)

TSTPT(4)

TSTPT(5)

TSTPT(6)

TSTPT(7)

0

83.13 MHz

41.56 MHz

10.39 MHz

25.16 MHz

133.00 MHz

HIGH

Sequence Index

CW Spoke Test Point

CW Revolution Test Point

Reset Sequence Aux Bit 0

Reset Sequence Aux Bit 1

Reset Sequence Aux Bit 2

(1) These are only the default output selections. Software can reprogram the selection at any time.

7.4 Device Operational Modes

The DLPC7540 has two operational modes which are enabled via software command via the Host control

interface. These modes are Standby and Active.

7.4.1 Standby Mode

The system is powered up and active, however, most blocks within the Controller have been shut down to

conserve power. Only the µProcessor and its peripherals are active (supporting a dormant projector waiting to be

woken up). In this mode the DMD is parked and no image can be displayed.

7.4.2 Active Mode

The system is powered up and fully operational, capable of projecting internal or external source images.

7.4.2.1 Normal Configuration

This configuration enables the full functionality of the DLPC7540.

7.4.2.2 Low Latency Configuration

This configuration disables some of the capabilities of the DLPC7540 to reduce the overall system latency for

certain applications which are sensitive to system latency. The key function that is disabled for this configuration

is the Warping block, which removes a full frame of latency from the processing path.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The DLPC7540 is the next generation high resolution display controller. It is part of the DLP471TE, DLP471NE,

DLP650TE or DLP651NE chipsets. The controller integrates all system image processing and DMD control

and data formatting onto a single integrated circuit (IC). It supports laser-phosphor, RGB-laser, LED and

hybrid illumination systems. Standard image processing algorithms such as DynamicBlack or BrilliantColor^™

are included. The DLPC7540 also includes a full featured image warping engine which can warp images on to

arbitrary surfaces, as well as support image blending, and projector stacking. The warp engine gives true 3D

keystone correction. Applications of interest include 4K UHD Enterprise Projectors, Laser TV, Smart Projectors,

and Digital Signage.

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8.2 Typical Application

The DLPC7540 controller is ideal for applications requiring high-performance, high-resolution displays. When

the DLPC7540 display controller is combined with the DLP471TE, DLP471NE, DLP650TE or DLP651NE

DMD, a power management and motor driver device (DLPA100), and other electrical, optical and mechanical

components the chipset enables bright, affordable, full 4K UHD display solutions. A typical 4K UHD system

application using the DLPC7540 controller and DLP471TE, DLP471NE, DLP650TE or DLP651NE DMD is

shown in the figure below Figure 8-1

Flash (2)

PWM Driver

ADDR

(24) (18)

DATA

RGB_EN

RGB_PWM

(3)

SYSPWR (14.5V-20 V)

(3)

PROJ_ON

I²C

I²C_BUSY

Vx1

V

_BIAS,V_OFFSET,V_RESET

(3)

TPS65145

Voltage

Regulator

3.3 V

Front End

Device

SPI (4)

3D L/R

DLP471TE

DLPC7540

Controller

2-Port HSSI

LS Interface

Vx1:

3840 × 2160

@ 60Hz

EEPROM

I²C

.47 4K UHD DMD

1.8 V

1.21 V

1.8 V

3.3 V

TPS56121

Voltage

Regulator

1.15 V

12 V

USB Mux

OTG

GPIO

TI DLP chipset

USB 2.0

Actuator

Driver

4-Position

Actuator

Third party component

USB Camera

Figure 8-1. Typical 4K UHD LED System

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12V

1.21V

1.8V

3.3V

5V

Flash (2)

DLPA1000

Voltage

Controller

DLPA1000

Voltage

Controller

1.8V

3.3V

5V

ADDR

DATA

(24) (18)

Wheel Motor #2

Wheel Motor #1

CTRL Signals

SYSPWR (14.5V-20 V)

PROJ_ON

V

_BIAS,V_OFFSET,V_RESET

TPS65145

Voltage

Regulator

I²C

I²C_BUSY

Vx1

(3)

3.3 V

Front End

Device

SPI (4)

3D L/R

DLP471TE

DLPC7540

Controller

2-Port HSSI

LS Interface

Vx1:

3840 × 2160

@ 60Hz

EEPROM

I²C

.47 4K UHD DMD

1.8 V

CW_INDEX1

1.21 V

1.8 V

3.3 V

TPS56121

Voltage

Regulator

1.15 V

12 V

USB Mux

OTG

GPIO

TI DLP chipset

Third party component

USB 2.0

Actuator

Driver

4-Position

Actuator

USB Camera

Figure 8-2. Typical 4K UHD LPCW System

8.2.1 Design Requirements

The display controller is the digital interface between the DMD and the rest of the system. The display controller

takes digital V-by-One, FPD-Link input from front end receiver and drives the DMD over a high speed interface.

The display controller also generates the necessary signals (data, protocols, timings) required to display images

on the DMD. Reliable operation of the DMD is only ensured when the DMD and the controller are used together

in a system. In addition, other devices might be needed. Typically, a Flash part is needed to store the software

and firmware and power supply management part required to power the DMD and the controller.

8.2.2 Detailed Design Procedure

For connecting the DLPC7540 controller and the DLP471TE, DLP471NE, DLP650TE or DLP651NE DMD

together, see the reference design schematic. It is essential to follow these layout guidelines for high-speed

interfaces, V-by-One and the DMD HSSI in order to design a reliable projector. To complete the DLP system,

an optical module or light engine is required that contains the DLP471TE, DLP471NE, DLP650TE or DLP651NE

DMD, associated illumination sources, optical elements, and necessary mechanical components.

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9 Power Supply Recommendations

9.1 Power Supply Management

The DLPA100 manages power for the DLPC7540 and DMD. See Section 6.13 for all power sequencing and

timing requirements.

9.2 Hot Plug Usage

While the V-by-One, FPD-Link, and USB interfaces support hot plug usage (i.e. these interfaces can be

connected and disconnected while the DLPC7540 is powered), the controller itself (and any DMD connected

to the system) do not support Hot Plug use. As such, power down the system prior to removing the controller or

DMD from any system.

9.3 Power Supplies for Unused Input Source Interfaces

While certain product configurations cannot offer or make use of all of the available input source interfaces (e.g.

V-by-One, FPD-Link), the power supplies that are associated with these unused input source interfaces must still

be provided as if the interface was actually being used. The only concession is that the ferrite based isolation

filters for these supplies can be simplified down to simple de-coupling caps.

9.4 Power Supplies

9.4.1 1.15-V Power Supplies

The DLPC7540 can support a low cost power delivery system with a single 1.15-V power source derived from

a switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g.

0.1 µF) filtering for the core 1.15-V power rail (VDD115). Ensure that the the high-frequency capacitors are

evenly distributed amongst the power balls and that they are placed as close to the power balls as possible.

Additional filtering must be provided for each of the uniquely defined 1.15-V power pins (e.g. VDD115_PLLMA,

VAD115VX1). Filtering for the unique power pins is discussed further in Section 10.1 of this document.

9.4.2 1.21V Power Supply

The DLPC7540 can support a low cost power delivery system with a single 1.21V power source derived from a

switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1

µF) filtering for the 1.21-V power rail (VDD121_SCS). Place the high-frequency filtering capacitors as close as

possible to the VDD121_SCS power balls.

9.4.3 1.8-V Power Supplies

The DLPC7540 can support a low cost power delivery system with a single 1.8-V power source derived from

a switching regulator. To enable this approach, appropriate filtering must be provided for each of the uniquely

defined 1.8-V power pins (e.g. VDD18_PLLMA, VAD18_VX1). See Section 10.1 for more information.

9.4.4 3.3-V Power Supplies

The DLPC7540 can support a low cost power delivery system with a single 3.3-V power source derived from a

switching regulator. To enable this approach, provide typical bulk (e.g. 10 µF, 22 µF) and high frequency (e.g. 0.1

µF) filtering for the main 3.3-V I/O power rail (VDD33). Ensure that the the high-frequency capacitors are evenly

distributed amongst the power balls and that they are placed as close to the power balls as possible. Additional

filtering must be provided for each of the uniquely defined 3.3-V power pins (e.g. VAD33_USB, VDD33_FPD).

This is discussed further in Section 10.1 of the document.

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10 Layout

10.1 Layout Guidelines

10.1.1 General Layout Guidelines

In order to meet the thermal loads associated with the DLPC7540, TI recommends the following enhanced PCB

design parameters.

•

A minimum of 4 power and ground planes

– Power layers: 1-oz. copper; Ground layers: 2-oz. copper

•

Copper coverage: 90%

– Top and bottom signal layers: minimum 0.5-oz copper

– Internal signal layers: 1-oz copper

•

Thermal copper ground planes beneath the thermal ball array of package containing a via farm with the

following attributes

– Thermal via quantity to ground plane = 64 (as 8x8 array)

– Thermal via size = 0.229mm - 0.25 mm (9mils - 10 mils)

– Thermal via plating thickness = 0.025 mm (1 mil) wall thickness

For signal integrity reasons, FR370HR or equivalent high performance epoxy laminate and repreg is also

recommended.

10.1.2 Power Supply Layout Guidelines

The following filtering circuits are recommended for the power supply inputs listed below.

•

VAD115_VX1

VAD18_VX1

VAD115_FPD

VDD33_FPD

VAD33_USB

VDD18_SCS

Since the PBC layout is critical to the performance of the interfaces associated with these power supplies, it is

vital that these power supplies be treated like an analog signal. Specifically:

•

Place high-frequency components (such as ferrites and capacitors) as close to the power ball(s) as possible.

Choose high-frequency ceramic capacitors (such as those with a valua of 0.1 µF, 0.01 µF, and 100 nF) that

have low ESR and ESL values. Design the leads as short as possible, and as such, it is recommended that

these capacitors be placed under the package on the opposite side of the board..

•

For each power pin, a single trace (as wide as possible) must be used from the controller to the capacitor and

then through the series ferrite to the power source.

For each power pin, add a 100-nF decoupling capacitor placed near the escape via. Add this decoupling

capacitance to the capacitance recommended for filters. These are minimum recommendations, so different

layouts could require additional capacitance.

•

See Table 10-1 for the recommended series ferrite component for these supplies.

Controller

1.15 V

FB

VAD115_VX1

100 mF

10 mF

200 mF 100 mF

22 mF

Figure 10-1. VAD115_VX1 (V-by-One) Recommended Filter

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Controller

1.8 V

FB

VAD18_VX1

100 mF

10 mF

200 mF 100 mF

22 mF

Figure 10-2. VAD18_VX1 (V-by-One) Recommended Filter

Controller

1.15 V

FB

VDD115_FPD

100 mF

10 mF

200 mF 100 mF

22 mF

Figure 10-3. VAD115_FPD (FPD-Link) Recommended Filter

Controller

3.3 V

FB

VDD33_FPD

100 mF

10 mF

200 mF 100 mF

22 mF

Figure 10-4. VDD33_FPD (FPD-Link) Recommended Filter

Controller

3.3 V

FB

10 mF

VAD33_USB

100 mF

0.1 mF 0.01 mF

10 mF

Figure 10-5. VAD33_USB (USB) Recommended Filter

Controller

1.18 V

FB

VDD18_SCS

100 mF

10 mF

200 mF 100 mF

22 mF

Figure 10-6. VDD18_SCS (SCS DRAM) Recommended Filter

10.1.3 Layout Guidelines for Internal Controller PLL Power

The following guidelines are recommended to achieve the desired Controller performance relative to the internal

PLLs. The DLPC7540 contains multiple internal PLLs which have dedicated 1.15-V supply pins and 1.8-V supply

pins which are listed below:

•

VDD115_PLLMA

VDD115_PLLMB

VAD115_PLLS

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•

VAD115_HSSI0_PLL

VAD115_HSSI1_PLL

and

•

VAD18_PLLMA

VAD18_PLLMB

It is important that each of these 1.15-V and 1.8-V supply pins have individual high frequency filtering in the form

of a ferrite bead and a 0.1-µF ceramic capacitor. Ensure that the impedance of the ferrite bead is much greater

than that of the capacitor at frequencies above 10 MHz. Locate these components very close to the individual

PLL power supply balls. Recommended values, topology, and layout examples are shown in Table 10-1, Figure

10-7 and Figure 10-8, and Figure 10-9 respectively.

Table 10-1. Recommended PLL and Crystal Power Supply Filter Components

COMPONENT

PARAMETER

RECOMMENDED VALUE UNIT

Shunt capacitor

Capacitance

0.1

µF

Ω

Impedance at 100 MHz

DC Resistance

> 100

< 0.40

Series ferrite

Ω

Controller

1.15 V

FB

VDD115_PLLMA

0.1 mF

FB

VDD115_PLLMB

VAD115_PLLS

0.1 mF

FB

0.1 mF

FB

VAD115_HSSI0_PLL

VAD115_HSSI1_PLL

0.1 mF

FB

0.1 mF

Figure 10-7. 1.15-V PLL Power Supply Filter Topology

Controller

1.8 V

FB

VAD18_PLLMA

VAD115_PLLMB

0.1 mF

Figure 10-8. 1.8-V PLL Power Supply Filter Topology

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Signal Via

PCB Pad

ASIC Pad

Via to Common Analog /

Digital Board Power Plane

Via to Common Analog /

Digital Board Ground Plane

F

A

B

C

D

E

30

GND

REF

CLKB_O

REF

CLKB_I

Crystal

Circuit

VAD115

_PLLS

16

15

14

FB

1.15 V

GND

VDD115

_PLLMB

VSS

FB

GND

VAD18

_PLLMB

FB

1.8 V

Local Decoupling

for PLL Supplies

(view from top of

board)

Figure 10-9. PLL Power Supply Filter Layout Examples

Since the PCB layout is critical to PLL performance, it is vital that the PLL power is treated like an analog signal.

Additional design guidelines are as follows:

•

Place all filter components as close to possible to each of the PLL supply package pins.

Keep the leads of the high-frequency capacitors as short as possible, and as such, it is recommended that

these capacitors be placed under the package on the opposite side of the board.

Use a surface mount capacitor that is of high quality, low ESR, and monolithic.

For each PLL power pin, a single trace (as wide as possible) must be used from the DLPC7540 to the

capacitor and then through the series ferrite to the power source.

•

10.1.4 Layout Guideline for DLPC7540 Reference Clock

The DLPC7540 requires two external reference clocks to feed its internal PLLs. A crystal or oscillator can supply

these references. The recommended crystal configurations and reference clock frequencies are listed in Table

10-2, with additional required discrete components shown in Figure 10-10 and defined in Table 10-2.

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PLL_REFCLK_I

PLL_REFCLK_O

R_FB

R_S

Crystal

C_L1

C_L2

C_L= Crystal load capacitance

R_FB= Feedback Resistor

Figure 10-10. Discrete Components Required for Crystal

10.1.4.1 Recommended Crystal Oscillator Configuration

Table 10-2. Recommended Crystal Configurations

PARAMETER

CRYSTAL A

CRYSTAL B

UNIT

Crystal circuit configuration

Crystal type

Parallel resonant

Fundamental (first harmonic)

40

Parallel resonant

Fundamental (first harmonic)

38

Crystal nominal frequency

Crystal frequency tolerance ⁽¹⁾

Crystal equivalent series resistance (ESR)

Crystal load capacitance

Crystal Shunt Load capacitance

Temperature range

MHz

PPM

Ω

±100 (200 p-p max)

60 (Max)

±100 (200 p-p max)

60 (Max)

20 (Max)

pF

7 (Max)

pF

-40°C to +85°C

100 (Nominal)

-40°C to +85°C

100 (Nominal)

°C

Drive level

µW

R_FBfeedback resistor (nominal)

C_L1external crystal load capacitor

C_L2external crystal load capacitor

1Meg (Nominal)

See equation in ⁽²⁾

See equation in ⁽³⁾

1Meg (Nominal)

Ω

See equation in ⁽²⁾

See equation in ^{(3) (3)}

pF

A ground isolation ring around the

crystal is recommended

A ground isolation ring around the

crystal is recommended

PCB layout

(1) Crystal frequency tolerance to include accuracy, temperature, aging, and trim sensitivity. These are typically specified separately and

the sum of all required to meet this requirement.

(2) CL1 = 2 × (CL – Cstray_pll_refclk_i), where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin

associated with the Controller pin REFCLKx_I. See Table 10-3.

(3) CL2 = 2 × (CL – Cstray_pll_refclk_o), where: Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin

associated with the Controller pin REFCLKx_O. See Table 10-3.

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Table 10-3. Crystal Pin Capacitance

PARAMETER

MIN

NOM

MAX

Units

Cstray_pll_refclkA Sum of package and PCB stray capacitance at

4.5

pF

_i

Cstray_pll_refclkA Sum of package and PCB stray capacitance at

_o REFCLKA_O

Cstray_pll_refclkB Sum of package and PCB stray capacitance at

_i REFCLKB_I

Cstray_pll_refclkB Sum of package and PCB stray capacitance at

_o REFCLKB_O

REFCLKA_I

pF

The crystal circuits in the DLPC7540 have dedicated power (VAD33_OSCA and VAD33_OSCB) pins, with the

recommended filtering for each shown in Figure 10-11, and recommended values shown in Table 10-1

Controller

FB

VAD33_OSCA

VAD33_OSCB

3.3V

0.1 …F

GND

FB

0.1 …F

GND

Figure 10-11. Crystal Power Supply Filtering

Table 10-4. DLPC7540 Recommended Crystal Parts

FREQUENCY

TOLERANCE,

FREQUENCY

STABILITY,

LOAD

CAPACITANC

E

NOMINAL

FREQUENCY

OPERATING

TEMPERATURE Level

Drive

MANUFACTURER PART NUMBER

ESR

AGING/YEAR

Freq Tolerance:

±20 ppm

TXC

7M38070001 ⁽¹⁾

7M40070041 ⁽²⁾

38 MHz

40 MHz

Freq Stability:

±20 ppm

30Ω max

12 pF

–40°C to +85°C

100µW

Aging/Year: ±3 ppm

Freq Tolerance:

±20 ppm

Freq Stability:

±20 ppm

30Ω max

100µW

Aging/Year: ±3 ppm

(1) This device requires an R_Sresistor with value = 0.

(2) This device requires an R_Sresistor with value = 0.

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10.1.5 V-by-One Interface Layout Considerations

The DLPC7540 V-by-One SERDES differential interface waveform quality and timing is dependent on the total

length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and

how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention

to many factors.

DLPC7540 I/O timing parameters, V-by-One transmitter timing parameters, as well as Thine specific timing

requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted and met

through controlled PCB routing. PCB related requirements for V-by-One are provided in Table 10-5 as a starting

point for the customer.

Table 10-5. V-by-One Interface PBC Related Requirements ⁽¹⁾

PARAMETER

MIN

TYP

MAX

UNIT

Intra-lane cross-talk

(between VX1_DATAx_P and VX1_DATAx_N)

< 1.5

mVpp

Inter-lane cross-talk

(between data lane pairs)

< 1.5

Cross-talk between data lanes and other signals

Intra-lane skew

< 1.5

< 40

< 800

110

mVpp

ps

Inter-lane skew

ps

Differential Impedance

90

100

Ω

(1) If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical

to achieve the target 100 Ω impedance (e.g. to reduce transmission line losses).

Additional V-by-One layout guidelines:

•

Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the

number of necessary vias to two.

•

Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration.

Ground guard traces are also recommended.

•

Do not route the differential signal pairs over the slit of power or ground planes.

Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew

requirements.

•

Ensure that the bend angles associated with the differential signal pairs are between 135^oand 225^o(See

Figure 10-12).

Differential Pair

Shield

135^o< Angle < 225^o

Shield

Figure 10-12. V-by-One Routing Example

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10.1.6 FPD-Link Interface Layout Considerations

The DLPC7540 FPD-Link differential interface waveform quality and timing is dependent on the total length of

the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well

matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many

factors.

DLPC7540 I/O timing parameters as well as the FPD-Link transmitter timing parameters can be found in their

corresponding data sheets. PCB routing mismatch can be budgeted and met through controlled PCB routing.

PCB related requirements for FPD-Link are provided in Table 10-6 as a starting point for the customer.

Table 10-6. FPD-Link Interface PBC Related Requirements

PARAMETER

MIN

TYP

MAX

UNIT

Intra-lane Cross-talk

(between FPDz_DATAx_P and FPDz_DATAx_N)

< 2.0

mVpp

Inter-lane Cross-talk

(between data lane pairs)

< 2.0

Cross-talk between data lanes and other signals

Intra-lane skew

< 2.0

< 40

± 40

110

mVpp

ps

Inter-lane skew

ps

Differential Impedance

90

100

Ω

Additional FPD-Link layout guidelines:

•

Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the

number of necessary vias to two.

•

Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration.

Ground guard traces are also recommended.

•

Do not route the differential signal pairs over the slit of power or ground planes.

Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew

requirements.

•

Ensure that the bend angles associated with the differential signal pairs are between 135^oand 225^o(See

Figure 10-13).

Differential Pair

Shield

135^o< Angle < 225^o

Shield

Figure 10-13. FPD-Link Routing Example

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10.1.7 USB Interface Layout Considerations

The DLPC7540 USB differential interface waveform quality and timing is dependent on the total length of the

interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well

matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many

factors.

DLPC7540 I/O timing parameters, USB transmitter and receiver timing parameters, as well as USB specific

timing requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted

and met through controlled PCB routing. PCB related requirements for USB are provided in Table 10-7 as a

starting point for the customer.

Table 10-7. USB Interface PBC Related Requirements ⁽¹⁾⁽²⁾

PARAMETER

MIN

TYP

MAX

< 1.5

< 20

UNIT

mVpp

Cross-talk between data lane (USB_DAT_P, USB_DAT_N) and other signals

Intra-lane skew (USB_DAT_P, USB_DAT_N)

Differential Impedance (USB_DAT_P, USB_DAT_N)

Single Mode impedance (USB_DAT_P, USB_DAT_N)

Common Mode Impedance (USB_DAT_P, USB_DAT_N)

Parasitic resistance (USB_DAT_P, USB_DAT_N)

Total capacitance (USB_DAT_P, USB_DAT_N)

Differences of trace capacitance between USB_DAT_P, USB_DAT_N

TXRTUNE resistor

ps

Ω

76.5

21

90

45

30

103.5

Ω

39

≤ 0.5

< 4

Ω

pF

Ω

< 1

172.26

174

175.74

(1) If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical

to achieve the target 100 Ω impedance (e.g. to reduce transmission line losses).

(2) One pcb layout example for the differential pair is shown in Figure 10-14

Additional layout guidelines for USB_DAT_P/USB_DAT_N:

•

Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the

number of necessary vias to two.

•

Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration.

Ground guard traces are also recommended.

•

Do not route the differential signal pairs over the slit of power or ground planes.

Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew

requirements.

•

Ensure that the bend angles associated with the differential signal pair are between 135^oand 225^o. (See

Figure 10-15).

•

Minimize the length where the differential signal pair are parallel to clocks or digital signals.

Do not route the differential signal pair under an IC that uses a quartz crystal, oscillator, clock synchronization

circuit, magnetic device, or clock.

Ground

guard trace

Ground

guard trace

3 × 0.35 mm

USB_DAT_P

0.35 mm

0.25 mm

0.35 mm

3 × 0.35 mm

USB_DAT_N

0.04 mm

FR4 Dielectric

Ground Layer

0.02 mm

Figure 10-14. USB Layout Example

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Differential Pair

Shield

135^o< Angle < 225^o

Shield

Figure 10-15. USB Routing Example

Additional USB layout guidelines for TXRTUNE

•

Use the shortest possible connection lengths for the resistor between TXRTUNE and ground.

Use ground layer and ground guard traces to shield the wires and resistor.

10.1.8 DMD Interface Layout Considerations

The DLPC7540 controller HSSI differential interface waveform quality and timing is dependent on the total length

of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well

matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many

factors.

DLPC7540 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding

data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB

design recommendations are provided in Table 10-8 , Figure 10-16,and the paragraph below as a starting point

for the customer.

Table 10-8. PCB Recommendations for DMD Interface ⁽¹⁾⁽²⁾

PARAMETER

MIN

MAX

UNIT

T_W

Trace Width

5.7

mils

T_S

Intra-lane Trace Spacing

Inter-lane trace spacing ⁽³⁾

5.3

T_SPP

48.3

(1) Recommendations to achieve the desired nominal differential impedance as specified by R_DIFFin Section 6.7.

(2) These parameters show recommendations based on the micro-strip design shown in Figure 10-16. This design minimizes signal loss

to support longer trace lengths at the expense of electromagnetic interference (EMI). The designer has the option to use of a stripline

design for shorter trace lengths and to target minimizing EMI at the expense of signal loss.

(3) A reduced inter-lane spacing can be used to escape the Controller ball field, however, widen this spacing to at least the stated

minimum after escape.

Tw

Ts

Tw

Ts

Tw

Tspp

Signal Traces

Differential Pair #1

Differential Pair #2

Ground Plane

Figure 10-16. DMD Differential Layout Recommendations

Additional DMD interface layout guidelines:

•

Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the

number of necessary vias to two. If two are required, place one at each end of the line (one at the controller

and one at the DMD).

•

Route the differential signal pairs over a single ground or power plane using a Micro-strip line configuration.

Do not route the differential signal pairs over the slit of power or ground planes.

Ensure the bend angles associated with the differential signal pairs are between 135^oand 225^o.

Route the single-ended signal in a way that to minimizes the number of vias required. Limit the number of

necessary vias to two. If two are required, place one at each end of the line (one at the controller and one at

the DMD).

•

Avoid stubs.

No external termination resistors are required on the DMD_HSSI or DMD_LS differential signals.

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•

Include a series termination resistor (with a value of 30.1 Ω, for example) to the DMD_LS0_RDATA and

DMD_LS1_RDATA single-ended signal paths. Place the resistor as close as possible to the corresponding

DMD pin.

The DMD_DEN_ARSTZ does not typically require a series resistor, however, for a long trace, one might be

needed to reduce undershoot or overshoot.

10.1.9 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potential damage to unused video source inputs and unused GPIO, the instructions specifically noted in

the associated Section 5 must be followed. For those unused inputs without specific instructions, TI recommends

that these input pins be tied through a pullup resistor to its associated power supply or a pulldown to ground.

Unused output-only pins can remain open. Never tie unused output-only pins directly to power or ground.

For controller inputs with an internal pullup or pulldown resistor, it is unnecessary to add an external pullup

or pulldown unless specifically recommended. Internal pullup and pulldown resistors are weak and cannot be

expected to drive the external line. When external pullup or pulldown resistors are needed for pins that have

built-in weak pullups or pulldowns, use the value specified in Table 5-14.

There are also power supply considerations that must be followed for any unused video sources. These are

detailed in Section 9.3.

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10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 10-9. Max Pin-to-Pin PCB Interconnect Recommendations - DMD

Controller INTERFACE

SIGNAL INTERCONNECT TOPOLOGY ^{(1) (2) (3)}

UNIT

SINGLE BOARD SIGNAL ROUTING MULTI-BOARD SIGNAL ROUTING

DMD

LENGTH

Controller PCB: 2 (50.8)

DMD PCB: 4 (101.6)

Flex: 10 (254)

DMD_HSSI0_CLK_P

DMD_HSSI0_CLK_N

10 (254)

inch (mm)

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

Controller PCB: 2 (50.8)

DMD PCB: 4 (101.6)

Flex: 10 (254)

10 (254)

inch (mm)

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

Controller PCB: 2 (50.8)

DMD PCB: 4 (101.6)

Flex: 10 (254)

DMD_HSSI1_CLK_P

DMD_HSSI1_CLK_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

Controller PCB: 2 (50.8)

DMD PCB: 4 (101.6)

Flex: 10 (254)

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

DMD_LS0_CLK_P

DMD_LS0_CLK_N

18

(457.2)

18

(457.2)

inch

(mm)

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

18

(457.2)

18

(457.2)

inch

(mm)

DMD_LS1_CLK_P

DMD_LS1_CLK_N

18

(457.2)

18

(457.2)

inch

(mm)

DMD_LS1_WDATA_P

DMD_LS1_WDATA_N

18

(457.2)

18

(457.2)

inch

(mm)

18

(457.2)

18

(457.2)

inch

(mm)

DMD_LS0_RDATA

DMD_LS1_RDATA

18

(457.2)

18

(457.2)

inch

(mm)

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Table 10-9. Max Pin-to-Pin PCB Interconnect Recommendations - DMD (continued)

Controller INTERFACE

SIGNAL INTERCONNECT TOPOLOGY ^{(1) (2) (3)}

SINGLE BOARD SIGNAL ROUTING MULTI-BOARD SIGNAL ROUTING

DMD

LENGTH

inch

(mm)

DMD_DEN_ARSTZ

N/A

(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing lengths shown are the combination that was analyzed by TI.

(3) Due to board variations, create a SPICE simulation for all board designs with the Controller IBIS models to ensure signal routing

lengths do not exceed signal requirements.

Table 10-10. High Speed PCB Signal Routing Matching Requirements

SIGNAL GROUP LENGTH MATCHING ^{(1) (2)}

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH ⁽³⁾

UNIT

DMD_HSSI0_D0_P

DMD_HSSI0_D0_N

DMD_HSSI0_D1_P

DMD_HSSI0_D1_N

DMD_HSSI0_D2_P

DMD_HSSI0_D2_N

DMD_HSSI0_D3_P

DMD_HSSI0_D3_N

DMD_HSSI0_CLK_P

DMD_HSSI0_CLK_N

±1.0

(±25.4)

inch

(mm)

DMD ⁽⁴⁾

DMD_HSSI0_D4_P

DMD_HSSI0_D4_N

DMD_HSSI0_D5_P

DMD_HSSI0_D5_N

DMD_HSSI0_D6_P

DMD_HSSI0_D6_N

DMD_HSSI0_D7_P

DMD_HSSI0_D7_N

±0.01

(±0.254)

inch

(mm)

DMD ⁽⁵⁾

DMD_HSSI0_x_P

DMD_HSSI0_x_N

DMD_HSSI1_D0_P

DMD_HSSI1_D0_N

DMD_HSSI1_D1_P

DMD_HSSI1_D1_N

DMD_HSSI1_D2_P

DMD_HSSI1_D2_N

DMD_HSSI1_D3_P

DMD_HSSI1_D3_N

DMD_HSSI1_CLK_P

DMD_HSSI1_CLK_N

±1.0

(±25.4)

inch

(mm)

DMD ⁽⁴⁾

DMD_HSSI1_D4_P

DMD_HSSI1_D4_N

DMD_HSSI1_D5_P

DMD_HSSI1_D5_N

DMD_HSSI1_D6_P

DMD_HSSI1_D6_N

DMD_HSSI1_D7_P

DMD_HSSI1_D7_N

±0.01

(±0.254)

inch

(mm)

DMD ⁽⁵⁾

DMD ⁽⁶⁾

DMD ⁽⁴⁾

DMD_HSSI1_x_P

DMD_HSSI0_CLK_P

DMD_HSSI0_CLK_N

DMD_HSSI1_x_N

DMD_HSSI1_CLK_P

DMD_HSSI1_CLK_N

±0.05

(±1.27)

inch

(mm)

±0.05

(±1.27)

inch

(mm)

DMD_LS0_WDATA_P

DMD_LS0_WDATA_N

DMD_LS0_CLK_P

DMD_LS0_CLK_N

±1.0

(±25.4)

inch

(mm)

94

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Table 10-10. High Speed PCB Signal Routing Matching Requirements (continued)

SIGNAL GROUP LENGTH MATCHING ^{(1) (2)}

INTERFACE

DMD ⁽⁵⁾

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH ⁽³⁾

UNIT

±0.025

(±0.635)

inch

DMD_LS0_x_P

DMD_LS0_x_N

(mm)

DMD_LS1_WDATA_P

DMD_LS1_WDATA_N

DMD_LS1_CLK_P

DMD_LS1_CLK_N

±1.0

(±25.4)

inch

(mm)

DMD ⁽⁴⁾

DMD ⁽⁵⁾

DMD

±0.025

(±0.635)

inch

(mm)

DMD_LS1_x_P

DMD_LS1_x_N

DMD_LS0_RDATA

DMD_LS1_RDATA

inch

(mm)

N/A

N/A ⁽⁷⁾

inch

(mm)

DMD

DMD_DEN_ARSTZ

N/A

(1) These routing requirements are specific to the PCB routing. Internal package routing mismatches in the DLPC7540 and DLP471TE,

DLP471NE, DLP650TE or DLP651NE have already been accounted for in these requirements.

(2) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.

(3) This requirement must be maintained from the Controller to the DMD, even if the signals traverse multiple boards.

(4) This is an inter-pair specification (that is, differential pair to differential pair within the group).

(5) This is an intra-pair specification (that is, length mismatch between P and N for the same pair). This is applicable to both clock and

data.

(6) This is a channel to channel skew specification.

(7) The low speed read control interface from the DMD is single ended, and makes use of the differential write clock. As such, a routing

mismatch between these is not applicable.

10.2 Thermal Considerations

The underlying thermal requirement for the DLPC7540 is that the maximum operating junction temperature (T_J)

not be exceeded (defined in the Section 6.3). This temperature is dependent on operating ambient temperature,

heatsink, airflow, PCB design (including the component layout density and the amount of copper used), power

dissipation of the DLPC7540, and power dissipation of surrounding components. The DLPC7540’s package is

designed to extract heat via the package heat slug to the heatsink, via the thermal balls, and through the power

and ground planes of the PCB. Thus, heatsink, copper content, and airflow over the PCB are important factors.

The recommended maximum operating ambient temperature (T_A) is provided primarily as a design target and is

based on maximum DLPC7540 power dissipation and R_θJAat 0 m/s,1 m/s, and 2 m/s of forced airflow, where

R_θJAis the thermal resistance of the package as measured using the test board described in Section 10.1.1.

This test PCB is not necessarily representative of the customers PCB and thus the reported thermal resistance

can differ from the actual product application. Although the actual thermal resistance can be different, it is the

best information available during the design phase to estimate thermal performance. TI highly recommends that

once the host PCB is designed and built that the thermal performance be measured and validated.

To do this, measure the top center case temperature under the worse case product scenario (max power

dissipation, max voltage, max ambient temperature) and validate that the maximum recommended case

temperature (T_C) is not exceeded. This specification is based on the measured φ_JTfor the DLPC7540 package

and provides a relatively accurate correlation to junction temperature. Take care when measuring this case

temperature to prevent accidental cooling of the package surface. TI recommends a small (approximately 40

gauge) thermocouple. Ensure that the bead and thermocouple wire contact the top of the package. Cover the

bead and thermocouple wire with a minimal amount of thermally conductive epoxy. Route the wires closely along

the package and the board surface to avoid cooling the bead through the wires.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

11.1.2.1 Device Markings

DLP®

XDLPC7540ZDC

XXXXXXXX-XXXXXX

TEXAS INSTRUMENTS

1

2

3

CCCCCC YYWW

4

LLLLL

TTTT

G1

Terminal A1 corner

Marking Definitions:

Line 1:

TI Part Number: Engineering

Samples

X = Engineering Samples

DLPC7540 = Device ID

blank or A, B, C ... = Part Revision

ZDC = Package designator

TI Part Number: Production

Vendor Information

DLPC7540 = Device ID

blank or A, B, C ... = Part Revision

ZDC = Package designator

Line 2:

Line 3:

XXXXXXX-XXXXXX

Vendor Country Year and Week

code

CCCCCC = Country

YY = Year

WW = Week

May also include 3 character Site Code after WW

ZZZ=Site Code

Vendor Lot and Trace Code

LLLLL = Lot code

TTTT = Trace code (may be blank)

Line 4:

11.1.2.2 Package Data

Table 11-1. Package Information

PARAMETER

Number of balls (signal/thermal)

Ball pitch

VALUE

UNITS

612 / 64

1.00

mm

mm³

g

UBM (under bump metallurgy)

BPD (ball pad diameter)

Body dimension

0.48 (See Figure 11-1)

0.58 (See Figure 11-1)

See Mechanical Drawing

350 - 2000 (J-STD-20D)

5.64

Mold compound dimensions

Package volume class

Approximate weight

Substrate circuit

Pb-free

Package balls

Pb-free

96

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Table 11-1. Package Information (continued)

PARAMETER

VALUE

UNITS

Solder paste

Solder profile

Pb-free

T_C=250°C, T_P= 253°C (J-STD-20D)

MSL Level 3 (J-STD-20D)

SAC305

Moisture sensitivity level

Solder ball composition

WIrebond

Cu

a) Hot air reflow (including the combination of long and/or medium

infrared ray reflow)

Mounting technique

b) Long or medium infrared ray reflow

Package side

Ball pad

UBM.

Solder mask

BPD.

Figure 11-1. Package Ball Parameters

11.2 Trademarks

BrilliantColor^™is a trademark of Texas Instruments Inc.

V-by-One^®and DLP^®are registered trademarks of THine Electronics, Inc.

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11.4.1 Video Timing Parameter Definitions

Active Lines Per Frame Defines the number of lines in a frame containing displayable data: ALPF is a subset

(ALPF)

Active Pixels Per Line Defines the number of pixel clocks in a line containing displayable data: APPL is a

(APPL) subset of the TPPL.

Horizontal Back Porch Number of blank pixel clocks after horizontal sync but before the first active pixel.

of the TLPF.

(HBP) Blanking

Note: HBP times are reference to the leading (active) edge of the respective sync

signal.

Horizontal Front Porch Number of blank pixel clocks after the last active pixel but before Horizontal Sync.

(HFP) Blanking

Horizontal Sync (HS)

Timing reference point that defines the start of each horizontal interval (line). The

absolute reference point is defined by the active edge of the HS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all horizontal blanking parameters are measured.

Total Lines Per Frame Defines the vertical period (or frame time) in lines: TLPF = Total number of lines per

(TLPF) frame (active and inactive).

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Total Pixel Per Line

(TPPL)

Defines the horizontal line period in pixel clocks: TPPL = Total number of pixel clocks

per line (active and inactive).

Vertical Sync (VS)

Timing reference point that defines the start of the vertical interval (frame). The

absolute reference point is defined by the active edge of the VS signal. The active

edge (either rising or falling edge as defined by the source) is the reference from

which all vertical blanking parameters are measured.

Vertical Back Porch

(VBP) Blanking

Number of blank lines after vertical sync but before the first active line.

Number of blank lines after the last active line but before vertical sync.

TPPL

Vertical Front Porch

(VFP) Blanking

Vertical Back Porch (VBP)

APPL

Horizontal

Back

Porch

Horizontal

Front

Porch

TLPF

ALPF

(HBP)

(HFP)

Vertical Front Porch (VFP)

98

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

ZDC0676A

PBGA - 2.4 mm max height

SCALE 0.500

PLASTIC BALL GRID ARRAY

31.1

30.9

B

A

BALL A1 CORNER

31.1

30.9

(

29)

4X (45 X 0.2)

C

(

23)

HEAT SLUG

(1.17)

0.35 C

2.40 MAX

0.6

SEATING PLANE

BALL TYP

TYP

0.2 C

0.4

29 TYP

SYMM

(1) TYP

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

(1) TYP

W

V

U

SYMM

676X

T

29

TYP

R

P

N

M

L

K

J

0.7

0.5

H

G

F

0.25

0.1

C A B

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29

1

TYP

2

4

6

8

10 20

12 14 16 18

22 24 26 28 30

1

TYP

4224809/A 02/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZDC0676A

PBGA - 2.4 mm max height

PLASTIC BALL GRID ARRAY

(1) TYP

SYMM

676X ( 0.5)

1

21

22 23

2 3

4

5

6

8

10 11 12 13 14 15 16 17 18 19

20

24

25

26 27 28

29 30

7

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

SYMM

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:4X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.5)

METAL

EXPOSED

(

0.5)

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4224809/A 02/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).

www.ti.com

EXAMPLE STENCIL DESIGN

ZDC0676A

PBGA - 2.4 mm max height

PLASTIC BALL GRID ARRAY

(1) TYP

676X ( 0.5)

1

21

22 23

2 3

4

5

6

8

10 11 12 13 14 15 16 17 18 19

20

24

25

26 27 28

29 30

7

9

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE: 4X

4224809/A 02/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DLPC7540
厂家：	TEXAS INSTRUMENTS
描述：	DLP® display controller for 4K UHD and 1080p DMD
文件：	总105页 (文件大小：2538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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