DRV603PWR [TI]
DirectPathâ¢, 3-VRMS Line Driver With Adjustable Gain; DirectPathâ ?? ¢ ， 3 - VRMS线路驱动器，具有可调增益
| 型号： | DRV603PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DirectPathâ¢, 3-VRMS Line Driver With Adjustable Gain |
| 文件： | 总21页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV603
www.ti.com
SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
DirectPath™, 3-VRMS Line Driver With Adjustable Gain
Check for Samples: DRV603
1
FEATURES
DESCRIPTION
234
•
DirectPath™
The DRV603PW is a 3-VRMS pop-free stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single-supply
electronics where size and cost are critical design
parameters.
–
–
–
Eliminates Pop/Clicks
Eliminates Output DC-Blocking Capacitors
Provides Flat Frequency Response 20
Hz–20 kHz
•
Low Noise and THD
Designed
using
TI’s
patented
DirectPath™
–
–
–
SNR > 109 dB
technology, The DRV603 is capable of driving 3 Vrms
into a 2.5-kΩ load with 5-V supply voltage. The
device has differential inputs and uses external
gain-setting resistors to support a gain range of ±1
V/V to ±10 V/V, and line outputs that have ±8 kV IEC
ESD protection. The DRV603 (occasionally referred
to as the ‘603) has built-in shutdown control for
pop-free on/off control. The DRV603 has an external
and internal undervoltage detector that mutes the
output.
Typical Vn < 7 μVms
THD+N < 0.002%
•
Output Voltage Into 2.5-kΩ Load
–
–
2 Vrms With 3.3-V Supply Voltage
3 Vrms With 5-V Supply Voltage
•
•
Differential Input
External Undervoltage Mute
Using the DRV603 in audio products can reduce
component count considerably compared to
traditional methods of generating a 3-Vrms output. The
DRV603 does not require a power supply greater
than 5 V to generate its 8.5-Vpp output, nor does it
APPLICATIONS
•
•
•
•
PDP / LCD TV
Blu-ray Disc™, DVD Players
Home Theater in a Box
Set-Top Boxes
require
a split-rail power supply. The DRV603
integrates its own charge pump to generate a
negative supply rail that provides a clean, pop-free
ground biased 3-Vrms output.
-
The DRV603 is available in a 14-pin TSSOP.
RIGHT
DAC
+
If the low noise and trimmed dc-offset and external
undervoltage mute function are not beneficial in the
application, TI recommends the footprint compatible
DRV602.
DRV603
+
-
LEFT
DAC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
DirectPath is a trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DRV603
SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PACKAGE
DRV603PW
DRV603PWR
TRANSPORT MEDIA, QUANTITY
RAIL, 90
Tape and reel, 2000
–40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range
VALUE
–0.3 to 5.5
UNIT
V
Supply voltage, VDD to GND
Input voltage
VI
VSS – 0.3 to VDD + 0.3
> 600
V
RL
Minimum load impedance
EN to GND
Ω
–0.3 to VDD +0.3
–40 to 150
V
TJ
Maximum operating junction temperature range
Storage temperature range
°C
°C
kV
Tstg
ESD
–40 to 150
Electrostatic discharge, IEC ESD
OUTL, OUTR
±8
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
POWER RATING(1)
POWER RATING(1)
PACKAGE
R
θJC (°C/W)
RθJA (°C/W)
AT TA ≤ 25°C
AT TA ≤ 70°C
TSSOP-14 (PW)
35
115(2)
870 mW
348 mW
(1) Power rating is determined with a junction temperature of 125°C. This is the point where performance starts to degrade and long-term
reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C
for best performance and reliability.
(2) These data were taken with the JEDEC high-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the RθJA is 185°C/W.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
UNIT
V
VDD
VIH
VIL
TA
Supply voltage
DC supply voltage
3
3.3
60
40
5.5
High-level input voltage
Low-level input voltage
Operating free-air temperature
EN
EN
% of VDD
% of VDD
°C
0
70
2
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ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 3 V to 5 V, input grounded, unity gain
VDD = 3 V to 5 V
MIN TYP
MAX UNIT
|VOS
|
Output offset voltage
1
mV
dB
V
PSRR Power-supply rejection ratio
88
VOH
VOL
High-level output voltage
Low-level output voltage
High-level input current (EN)
Low-level input current (EN)
VDD = 3.3 V, RL = 2.5 kΩ
3.1
VDD = 3.3 V, RL = 2.5 kΩ
–3.05
V
|IIH
|
VDD = 5 V, VI = VDD
1
1
µA
µA
|IIL|
VDD = 5 V, VI = 0 V
VDD = 3.3 V, no load, EN = VDD
VDD = 5 V, no load, EN = VDD
Shutdown mode, VDD = 3 V to 5 V
11
IDD
Supply current
12.5
mA
1
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
THD = 1%, VDD = 3.3 V, f = 1 kHz
THD = 1%, VDD = 5 V, f = 1 kHz
MIN
2.05
3.01
3.1
TYP MAX
UNIT
VO
Output voltage (outputs in phase)
Vrms
THD = 1%, VDD = 5 V, f = 1 kHz, RL = 100 kΩ
THD+N
Total harmonic distortion plus noise VO = 2 Vrms, f = 1 kHz
0.001%
Crosstalk
VO = 2 Vrms, f = 1 kHz
VDD = 3.3 V
–100
20
dB
mA
IO
Maximum output current
Input resistor range
Feedback resistor range
Slew rate
RIN
Rfb
1
10
47
kΩ
4.7
20 100
kΩ
4.5
220
6
V/μs
pF
Maximum capacitive load
Noise output voltage
VN
BW = 20 Hz to 22 kHz, A-weighted
μVrms
VO = 3 Vrms, THD+N = 0.1%, BW = 22 kHz,
A-weighted
SNR
Signal-to-noise ratio
112
dB
GBW
AVO
Vuvp
Unity-gain bandwidth
8
150
MHz
dB
V
Open-loop voltage gain
External undervoltage detection
1.25
External undervoltage detection
hysteresis current
IHys
fcp
5
μA
Charge pump frequency
225
450 675
kHz
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PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
+INR
-INR
+IN
-INL
OUTR
SGND
EN
OUTL
UVP
PGND
PVDD
CP
External
Under
Voltage
Detector
PVSS
CN
Charge Pump
8
PIN FUNCTIONS
PIN
I/O(1)
DESCRIPTION
NAME
+INR
NO.
1
I
I
Right-channel OPAMP positive input
Right-channel OPAMP negative input
Right-channel OPAMP output
Signal ground
–INR
OUTR
SGND
EN
2
3
O
P
I
4
5
Enable input, active-high
Supply voltage
PVSS
CN
6
P
I/O
I/O
P
P
I
7
Charge-pump flying capacitor negative terminal
Charge-pump flying capacitor positive terminal
Positive supply
CP
8
PVDD
PGND
UVP
9
10
11
12
13
14
Power ground
Undervoltage protection input
Left-channel OPAMP output
OUTL
–INL
+INL
O
I
Left-channel OPAMP negative input
Left-channel OPAMP positive input
I
(1) I = input, O = output, P = power
4
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
FUNCTIONAL BLOCK DIAGRAM
+INL
-INL
+INR
-INR
Line
Driver
Line
Driver
OUTL
SGND
EN
OUTR
UVP
Click&Pop
Suppression
Short Circuit
Protection
PGND
PVDD
CP
PVSS
CN
Bias
Circuitry
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TYPICAL CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
vs
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VDD = 3.3 V, RL = 100 kΩ, f = 1 kHz
VDD = 5 V, RL = 100 kΩ, f = 1 kHz
10
1
10
1
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
100m 200m 300m 500m 800m
2
3
4
5
100m 200m
500m 800m
V - Output Voltage - V
O
2
3
4
5
V
- Output Voltage - V
O
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
vs
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VDD = 3.3 V, RL = 2.5 kΩ, f = 1 kHz
VDD = 5 V, RL = 600 Ω, f = 1 kHz
10
1
10
1
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
100m 200m
500m 800m
2
3
4
5
100m 200m
500m 800m
V - Output Voltage - V
O
2
3
4
5
V
- Output Voltage - V
O
Figure 3.
Figure 4.
6
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION+NOISE
TOTAL HARMONIC DISTORTION+NOISE
vs
vs
FREQUENCY
FREQUENCY
VDD = 3.3 V, RL = 2.5 kΩ, VO = 2 Vrms
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
10
1
10
1
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
Figure 5.
Figure 6.
PHASE
GAIN
vs
vs
FREQUENCY
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
VDD = 5 V, RL = 100 kΩ, VO = 2 Vrms
+10
+9
+150
+100
+8
+7
+6
+5
+4
+3
+2
+50
+0
-50
-100
-150
+1
0
20 50 100
500 1k 2k 5k 10k
f - Frequency - Hz
50k
200k
200k
20 50 100
500 1k 2k 5k 10k
f - Frequency - Hz
50k
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.3 V , TA = 25°C, RL = 2.5 kΩ, C(PUMP) = C(VSS) = 1 µF , CIN = 10 µF, RIN = 10 kΩ, Rfb = 20 kΩ (unless otherwise noted)
FFT
vs
QUIESCENT CURRENT
vs
FREQUENCY
VDD = 5 V, RL = 100 kΩ, VO = 3 Vrms (-60 dB)
SUPPLY VOLTAGE
+0
-20
-40
-60
No Load,
V = 0 V
14m
12m
10m
8m
I
-80
-100
-120
6m
4m
2m
0
-140
+5
+4
+2 +3
- Supply Voltage - V
-0
+1
V
0
5k
10k
f - Frequency - Hz
15k
20k
DD
Figure 9.
Figure 10.
8
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
APPLICATION INFORMATION
LINE DRIVER AMPLIFIERS
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 11
illustrates the conventional line-driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click
and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can
reduce the fidelity of the audio output signal.
9-12 V
Conventional Solution
VDD
VDD/2
+
Mute Circuit
Co
+
+
-
Output
OPAMP
GND
Enable
5V
DirectPath
VDD
DRV603 Solution
Mute Circuit
+
-
Output
GND
DRV603
VSS
Enable
Figure 11. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
Combining this with the built-in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc
blocking capacitors.
The bottom block diagram and waveform of Figure 11 illustrate the ground-referenced line-driver architecture.
This is the architecture of the DRV603.
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CHARGE PUMP FLYING CAPACITOR AND PVSS CAPACITOR
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are
smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications.
DECOUPLING CAPACITORS
The DRV603 is a DirectPath™ line-driver amplifier that requires adequate power supply decoupling to ensure
that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this
decoupling capacitor close to the DRV603 is important for the performance of the amplifier. For filtering
lower-frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also
help, but it is not required in most applications because of the high PSRR of this device.
GAIN-SETTING RESISTOR RANGES
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
DRV603 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR
VALUE, RIN
FEEDBACK RESISTOR
VALUE, Rfb
DIFFERENTIAL INPUT
GAIN
NONINVERTING INPUT
GAIN
INVERTING INPUT GAIN
22 kΩ
15 kΩ
33 kΩ
10 kΩ
22 kΩ
30 kΩ
68 kΩ
100 kΩ
1 V/V
1.5 V/V
2.1 V/V
10 V/V
–1 V/V
–1.5 V/V
–2.1 V/V
–10 V/V
2 V/V
2.5 V/V
3.1 V/V
11 V/V
C
R
R
IN
C
IN
IN
IN
-IN
-IN
R
R
FB
FB
Differential
Input
-
-
Inverting
+
+
+IN
R
R
C
FB
IN
IN
R
Cx
IN
R
FB
-
Non
Inverting
+
+IN
Rx
C
IN
Figure 12. Differential, Inverting and Non-Inverting Gain Configurations
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INPUT-BLOCKING CAPACITORS
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV603. These capacitors block the dc portion of the audio source and allow the DRV603 inputs to be properly
biased to provide maximum performance.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1. Then the frequency and/or capacitance can be determined when one of the
two values is given.
1
1
fc
+
C
+
or
IN
IN
2p R
C
2p fc
R
IN IN
IN IN
(1)
USING THE DRV603 AS A SECOND-ORDER FILTER
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the DRV603, as it can be used like a standard OPAMP. Several filter topologies can be implemented, both
single-ended and differential. In Figure 13 , a multi-feedback (MFB) with differential input and single-ended input
is shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc-gain to 1, helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at:
http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Differential Input
Inverting Input
R2
C1
R2
C1
C3
C3
R1
R3
R1
R3
-IN
-IN
-
DRV603
-
DRV603
C2
C2
+
+
+IN
R3
R1
C3
C1
R2
Figure 13. Second-Order Active Low-Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling capacitor. Using 5.6 kΩ for the resistors, C1 = 220 pF, and C2 = 470 pF, a DNR of
112 dB can be achieved with a 10-μF input ac-coupling capacitor.
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POP-FREE POWER UP
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power-supply ramp up and ramp
down. The SD pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the
SD pin high to achieve pop-less power up. Figure 14 illustrates the preferred sequence.
Supply
Enable
Supply Ramp
Time for ac-coupling
capacitors to charge
Figure 14. Power-Up Sequence
VSUP_MO
EXTERNAL UNDERVOLTAGE DETECTION
External undervoltage detection can be used to
mute/shut down the DRV603 before an input device
R11
can generate a pop.
R13
UVP pin 11
The shutdown threshold at the UVP pin is 1.25 V.
The user selects a resistor divider to obtain the
shutdown threshold and hysteresis for the specific
application. The thresholds can be determined as
R12
Cy
follows:
VUVP = 1.25 V × (R11 + R12) / R12
Hysteresis = 5 μA × R13 × (R11 + R12) / R12
with the condition R13 >> R11//R12.
For example, to obtain VUVP = 5 V and 1-V
hysteresis, R11 = 3 kΩ, R12 = 1 kΩ and R13 = 50
kΩ.
CAPACITIVE LOAD
The DRV603 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ω or larger.
LAYOUT RECOMMENDATIONS
A proposed layout for the DRV603 can be seen in the DRV603EVM User's Guide (SLOU248), and the Gerber
files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/drv603evm.html. To access this
information, open the DRV603 product folder and look in the Tools and Software folder.
GAIN-SETTING RESISTORS
The gain-setting resistors, RIN and Rfb, must be placed close to the input pins to minimize capacitive loading on
these input pins and to ensure maximum stability of the DRV603. For the recommended PCB layout, see the
DRV603EVM user's guide (SLOU248).
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SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009
APPLICATION CIRCUIT
LEFT
OUTPUT
R12
System Supply
5 V Supply
Linear Low Drop
Regulator
R11
R2
10mF
+
R1
R1
R3
R3
LEFT
INPUT
C3
C3
C1
1mF
C2
-
R2
C1
1mF
R2
C2
C1
+
R1
R1
R3
R3
RIGHT
INPUT
C3
C3
-
C1
1mF
RIGHT
OUTPUT
R2
R1 = 5.6 kΩ, R2 = 5.6 kΩ, R3 = 5.6 kΩ, C1 = 220 pF, C2 = 470 pF
Differential-input, single-ended output, second-order filter
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REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision A (February 2009) to Revision B
Page
•
•
Changed Crosstalk spec from –80dB to –100dB ................................................................................................................. 3
Added missing voltage value (1.25V) to External Undervoltage Detection threshold equation. ........................................ 12
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Changes from Revision B (October 2009) to Revision C
Page
•
•
•
•
Changed maximum operating junction temperature ............................................................................................................. 2
In Dissipation Ratings section, changed θJx to RθJx in three places and 185°C to 185°C/W ............................................... 2
Corrected reference to Figure 11 .......................................................................................................................................... 9
Added cross-reference to Figure 13 ................................................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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18-Nov-2009
PACKAGING INFORMATION
Orderable Device
DRV603PW
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
14
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DRV603PWR
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV603PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV603PWR
2000
Pack Materials-Page 2
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