DRV604PWPR [TI]
DirectPath™ 2Vrms Line Driver and HP Amp With Adjustable Gain; 的DirectPath ™ 2Vrms的线路驱动器和耳机放大器增益可调
| 型号： | DRV604PWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DirectPath™ 2Vrms Line Driver and HP Amp With Adjustable Gain |
| 文件： | 总21页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV604
www.ti.com
SLOS659 –JANUARY 2010
DirectPath™ 2Vrms Line Driver and HP Amp With Adjustable Gain
Check for Samples: DRV604
1
FEATURES
APPLICATIONS
•
•
•
•
LCD and PDP TV
23
•
DirectPath™
Blu-ray Disc™, DVD Players
Mini/Micro Combo Systems
Soundcards
–
–
Eliminates Pop/Clicks
Eliminate Output DC-Blocking Capacitors
•
3.0V to 3.7V Supply Voltage
Low Noise and THD
•
DESCRIPTION
–
–
–
SNR > 109dB
The DRV604 is a 2Vrms Pop-Free stereo line driver
with stereo headphone output designed to allow the
removal of the output DC-blocking capacitors for
reduced component count and cost. The device is
ideal for single supply electronics where size and cost
are critical design parameters.
Typical Vn < 7µVrms 20–20kHz
THD+N < 0.002% at 10kΩ
•
•
Output Voltage into 5kΩ Load
2Vrms at 3.3V Supply Voltage
Stereo DirectPath™ Headphone:
–
Designed
using
TI’s
patented
DirectPath™
–
–
40mW into 32Ω at 3.3V Supply Voltage
16Ω to ∞ Ω Stable Load Range
technology, The DRV604 is capable of driving 2 Vrms
into a 5kΩ load. The headphone output can generate
a clean 40mW into 32Ω load from a 3.3V supply.. The
device has differential inputs and uses external gain
setting resistors that supports a gain range of -1V/V
to -10V/V. Headphone and line outputs have ±8kV
IEC ESD protection enabling a simple ESD protection
circuit. The DRV604 has built-in enable control for
pop-free on/off control. DRV604 can monitor an
external supply voltage using its built in comparator
enabling it to shut down during a brown out condition
before up stream audio DAC’s can produce click and
pop artifacts.
•
•
•
•
•
Differential Input
Power Sense UVP for Brown Out Protection
Short Circuit and Thermal Protection
±8kV IEC ESD Protection
Footprint Compatible with DRV602 and
DRV603
•
Supports Dual Line Driver Configuration
-
Using the DRV604 in audio products can reduce
component count considerably compared to
traditional methods of generating headphone output
and 2Vrms output. The DRV604 does not require a
power supply greater than 3.3V to generate its
5.6Vpp output, nor does it require a split rail power
supply. The DRV604 integrates its own charge pump
to generate a negative supply rail that provides a
clean, pop-free ground biased 2Vrms output.
DAC
+
RIGHT
Line Driver
LEFT
-
DAC
+
DRV604
SOC
-
The DRV604 is available in a 28-pin HTSSOP. For a
stereo line driver with no HP amp see DRV603.
DAC
Headphone
+
-
DAC
+
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
DirectPath, FilterPro are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
DRV604
SLOS659 –JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
PIN ASSIGNMENT
The DRV604 is available in the thermally enhanced package: 28-Pin HTSSOP package (PWP).
1
2
+LD_L
-LD_L
28
27
26
+LD_R
-LD_R
3
OUT_LDL
AGND
OUT_LDR
4
Ex_UVP 25
5
EN_LD
24
PGND
6
PVSS_LD
CN_LD
PVDD_LD 23
CP_LD 22
CP_HP 21
20
7
8
CN_HP
9
PVSS_HP PVDD_ HP
10
11
19
18
EN_HP
AGND
PGND
NC
12 OUT_HPL
13 -HP_L
OUT_HPR 17
-HP_R
+HP_R
16
15
+HP_L
14
PIN FUNCTIONS
PIN
FUNCTION(1)
DESCRIPTION
NAME
PWP NO.
+LD_L
1
2
I
I
Positive input, Line driver Left
Negative input, Line driver Left
Output, Line driver Left
–LD_L
OUT_LDL
AGND
3
O
P
I
4
Analog Ground
EN_LD
PVSS_LD
CN_LD
CN_HP
PVSS_HP
EN_HP
AGND
5
Enable for Line driver, active high
6
O
I/O
I/O
O
I
Charge Pump Negative Supply Voltage Output for Line Driver
Charge Pump Flying Capacitor Negative connection, Line Driver
Charge Pump Flying Capacitor Negative connection, Headphone
Headphone, Charge Pump Negative Supply Voltage Output
Enable for Headphone, active high
7
8
9
10
11
12
13
14
15
P
O
I
Analog Ground
OUT_HPL
–HP_L
Output, Headphone Left
Negative input, Headphone Left
+HP_L
I
Positive input, Headphone Left
+HP_R
I
Positive input, Headphone Right
(1) I = input, O = output, P = power
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PIN FUNCTIONS (continued)
PIN
FUNCTION(1)
DESCRIPTION
NAME
PWP NO.
16
–HP_R
OUT_HPR
NC
I
Negative input, Headphone Right
Output, Headphone Right
No connect
17
O
18
PGND
19
P
P
I/O
I/O
P
P
I
Charge Pump Power Ground, Headphone
PVDD_HP
CP_HP
CP_LD
PVDD_LD
PGND
20
Headphone Supply Voltage, connect to positive supply, internally connected to pin 23
Charge Pump Flying Capacitor Positive connection, Headphone
Charge Pump Flying Capacitor Positive connection, Line Driver
Line Driver Supply Voltage, connect to positive supply, internally connected to pin 20
Charge Pump Power Ground, Line Driver
21
22
23
24
Ex_UVP
OUT_LDR
–LD_R
25
External Under Voltage Protection
26
O
I
Output, Line Driver Right
27
Negative input, Line driver Right
+LD_R
28
I
Positive input, Line driver Right
SYSTEM BLOCK DIAGRAM
Short-Circuit
Protection
OpAmp
LD
OpAmp
LD
Click & Pop
Suppression
Enable
Control LD
Charge
Pump LD
Internal
UVP
Thermal
Protection
External
UVP
Enable
Control HP
Charge
Pump HP
Click & Pop
Suppression
OpAmp
HP
OpAmp
HP
Short-Circuit
Protection
ORDERING INFORMATION(1)
TA
PACKAGE
DESCRIPTION
–40°C–85°C
DRV604PWP
28-Pin
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI Web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
DRV604PWP
–0.3 to 4.5
UNIT
V
PVDD to GND
Input voltage, VI
PVSS–0.3 to PVDD+0.3
1000
V
Minimum load impedance – line outputs
Minimum load impedance – headphone outputs
EN_LD to GND
Ω
8
Ω
–0.3 to PVDD+0.3
–0.3 to PVDD+0.3
–40 to 150
V
EN_HP to GND
V
Maximum operating junction temperature range, TJ
Storage temperature
°C
°C
–40 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS(1)
PACKAGE
RqJP(°C/W)
RqJA(°C/W)
RyJT(°C/W)
DRV604PWP
0.72
28
0.45
(1) PowerPAD soldered to TI recommended board.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
UNIT
V
PVDD
RL (HP)
RL (LD)
VIL
Power supply
DC supply voltage
3.0
32
5
3.3
32
10
40
60
25
3.7
Ω
Load impedance
Low level input voltage
kΩ
EN_LD, EN_HP
38
57
–40
43 %PVDD
66 %PVDD
VIH
High level input voltage EN_LD, EN_HP
Free-air temperature
TA
85
°C
4
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ELECTRICAL CHARACTERISTICS
PVDD_LD = PVDD_HP = 3.3 V, RLD = 5 kΩ, RHP = 32 Ω, RFB = 20 kΩ, RIN = 10 kΩ, TA = 25°C, Charge pump: CCP_LD
=
CCP_HP = 1.0 µF (unless otherwise noted)
DRV604
PARAMETER
TEST CONDITIONS
PVDD = 3.3 V
UNIT
MIN
TYP
MAX
|Vos
|
Output offset voltage
1
mV
dB
V
PSRR
VOH
Power supply rejection ratio
High level output voltage
Low level output voltage
PVDD, undervoltage detection
70
80
PVDD = 3.3 V
3.1
VOL
PVDD = 3.3 V
–3.05
2.8
V
Vuvp_on
Internal under-voltage detection.
V
PVDD, undervoltage detection,
hysteresis
Vuvp_hysteresis
200
1.25
5
mV
V
Vuvp
IHys
Fcp
External undervoltage detection
External undervoltage detection
hysteresis current
µA
Charge pump switching frequency
High level input current
260
15
700
1
kHz
µA
|IIH
|
PVDD = 3.3 V, VIH = PVDD, EN_HP, EN_LD
PVDD = 3.3 V, VIL = 0 V, EN_HP, EN_LD
PVDD, EN_LD, EN_HP = 3.3 V
|IIL|
low level input current
1
µA
Supply current, no load
25
12
13
35
Supply current, line driver, no load
Supply current, headphone, no load
PVDD, EN_LD = 3.3 V, EN_HP = GND
PVDD, EN_LD = GND, EN_HP = 3.3 V
I(PVDD)
mA
PVDD = 3.3 V, EN_LD, EN_HP = GND,
Ex_UVP = GND
Supply current, disabled
2.5
5
Tsd
Thermal shutdown
150
15
°C
°C
Thermal shutdown hysteresis
ELECTRICAL CHARACTERISTICS, LINE DRIVER
PVDD_LD = PVDD_HP = 3.3 V, Rload = 5 kΩ, RFB = 20 kΩ, RIN = 10 kΩ, TA = 25°C, Charge pump: CCP_LD = CCP_HP = 1.0 µF
(unless otherwise noted)
DRV604
UNIT
PARAMETER
Output voltage, outputs in phase
Total harmonic distortion plus noise
Signal-to-noise ratio
TEST CONDITIONS
1% THD+N, f = 1 kHz, 10 kΩ load
f = 1 kHz, 10 kΩ load, VO = 2 Vrms
A-weighted, AES17 filter, 2 Vrms ref
A-weighted, AES17 filter, 2 Vrms ref
A-weighted, AES17 filter
MIN
TYP
2.1
MAX
VO
Vrms
THD+N
SNR
DNR
Vn
0.001%
109
109
7
dB
dB
Dynamic range
Noise voltage
uV
Slew rate
4.5
V/µS
MHz
dB
GBW
Unity gain bandwidth
8
Crosstalk – Line L-R & R-L
Positive common-mode input voltage
Negative common-mode input voltage
Current limit
10 kΩ load, VO = 2 Vrms
-100
+2.0
-3.0
60
Vincm_pos
Vincm_neg
Ilimit
V
V
PVDD = 3.3 V
mA
pF
Maximum capacitive load
220
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ELECTRICAL CHARACTERISTICS, HEADPHONE
PVDD_LD = PVDD_HP = 3.3 V, RHP = 32 Ω, TA = 25°C, Charge pump: CCP_LD = CCP_HP = 1.0 µF (unless otherwise noted)
TAS5630
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
40
MAX
PO
VO
Output power, outputs in phase
Output voltage, outputs in phase
THD+N = 1%, f = 1 kHz, 32 Ω load
THD+N = 1%, f = 1 kHz, 32 Ω load
f = 1 kHz, 32 Ω load, PO = 40 mW
f = 1 kHz, 5 kΩ load, VO = 2 Vrms
mW
1.45
Vrms
0.02%
0.001%
THD+N
Total harmonic distortion plus noise
A-weighted, AES17 filter, 1.45 Vrms ref
(66 mW into 32 Ω)
106
109
106
SNR
Signal-to-noise ratio
dB
dB
A-weighted, AES17 filter, 2 Vrms ref 5 kΩ load
A-weighted, AES17 filter, 1.45 Vrms ref
(66 mW into 32 Ω)
DNR
Vn
Dynamic range
A-weighted, AES17 filter, 2 Vrms ref 5 kΩ load
109
7
Noise voltage
A-weighted, AES17 filter
µV
V/µS
MHz
dB
Slew rate
4.5
8
GBW
Unity gain bandwidth
Channel to channel
Positive common-mode input voltage
Crosstalk
Vincm_pos
f = 1 kHz, Rload = 32 Ω, PO = 40 mW
75
2.0
V
Negative common-mode input
voltage
Vincm_neg
Ilimit
–3.0
V
Output current limit
190
220
mA
pF
Maximum capacitive load
6
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TYPICAL CHARACTERISTICS, LINE DRIVER
THD+N vs OUTPUT VOLTAGE
THD+N vs OUTPUT VOLTAGE, LINEAR SCALE
10
1
10
V = 3.3 V,
I
V = 3.3 V,
I
Load = 5 kW,
Linear Scale = 1 kHz,
Outputs in Phase = 1 kHz
Load = 5 kW to 100 kW,
Output in Phase = 1 kHz
1
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
1
1.5
2
- Output Voltage - V
2.5
3
40m
100m
200m
500m
1
2
4
V
O
V
- Output Voltage - V
O
Figure 1.
THD+N vs FREQUENCY
Figure 2.
CHANNEL SEPARATION
0
10
1
V = 3.3 V,
V = 3.3 V,
I
I
Load = 5 kW,
2 Vrms
Load = 5 kW,
2 Vrms
-20
-40
-60
0.1
0.01
R to L
-80
L to R
-100
0.001
-120
0.0001
20
50
100
200
500
1k
2k
5k
20k
20
50
100
200
500
1k
2k
5k
20k
f - Frequency - Hz
f - Frequency - Hz
Figure 3.
HP TO LD CROSSTALK
Figure 4.
AC PSRR, Ksvr
0
0
V = 3.3 V,
I
Line Load = 5 kW,
32 W HP Load, 40 mW
200 mV Vpp supply ripple = 70 mV Vrms
-20
-40
-20
-40
-60
V = 3.3 V,
I
200 mV Vpp Ripple on PSU,
Line Load = 5 kW, 32 W HP Load
-60
Amplifier output - relative to 70 mV
HP to line right
HP to line left
-80
-80
-100
-100
20
50
100
200
500
1k
2k
5k
20k
20
50
100
200
500
1k
2k
5k
20k
f - Frequency - Hz
f - Frequency - Hz
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS, HEADPHONE
THD+N vs OUTPUT POWER
THD+N vs OUTPUT POWER, LINEAR SCALE
10
1
10
3.3 V, 32W, 1 kHz
3.3 V, 32W, 1 kHz
In phase
In phase
Out of phase
1
Out of phase
0.1
0.01
0.1
0.01
0.001
0.001
50
100
150
100u
500u
2m
5m 10m
50m 200m
P
- Output Power - mW
P
- Output Power - W
O
O
Figure 7.
CHANNEL SEPARATION
Figure 8.
LD TO HP CROSSTALK
0
-20
-40
-60
-80
0
3.3 V, LD 2 Vrms into 5 kW,
32 W HP Load No Signal
40 mW into 32W
-20
-40
-60
-80
-100
-120
-100
20
50
100
200
500
1k
2k
5k
20k
20
50
100
200
500
1k
2k
5k
20k
f - Frequency - Hz
f - Frequency - Hz
Figure 9.
START
Figure 10.
STOP
Figure 11.
Figure 12.
8
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APPLICATION INFORMATION
LINE DRIVER AMPLIFIERS
Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in
Figure 13 illustrates the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power
up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits
consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal.
Conventional Solution
9-12 V
VDD
+
Mute Circuit
Co
+
+
Output
VDD/2
OPAMP
-
GND
MUTE
DRV604 Solution
3.3 V
DirectPath
VDD
+
-
Mute Circuit
Output
GND
DRV604
VSS
MUTE
Figure 13. Conventional and DirectPath HP and Line Driver
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail,
combining this with the build in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc
blocking capacitors.
The bottom block diagram and waveform of Figure 13 illustrate the ground-referenced headphone and line driver
architecture. This is the architecture of the DRV604.
COMPONENT SELECTION
Charge Pump
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that are
smaller than 1µF can not be recommended for the HP section as it will limit the negative voltage swing in low
impedance loads.
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Decoupling Capacitors
The DRV604 is a DirectPath™ amplifier that requires adequate power supply decoupling to ensure that the noise
and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor,
typically 1µF, placed as close as possible to the device PVDD leads works best. Placing this decoupling
capacitor close to the DRV604 is important for the performance of the amplifier. For filtering lower frequency
noise signals, a 10µF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
Gain Setting Resistors Ranges
The gain setting resistors, Rin and Rfb, must be chosen so that noise, stability and input capacitor size of the
DRV604 is kept within acceptable limits. Voltage gain is defined as Rfb divided by Rin. Selecting values that are
too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise
of the amplifier. Table 1 lists the recommended resistor values for different gain settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR
VALUE, Rin
FEEDBACK RESISTOR
VALUE, Rfb
DIFFERENTIAL
INPUT GAIN
INVERTING INPUT
GAIN
NON INVERTING
INPUT GAIN
10 kΩ
10 kΩ
10 kΩ
4.7 kΩ
10 kΩ
15 kΩ
20 kΩ
47 kΩ
1.0 V/V
1.5 V/V
2.0 V/V
10.0 V/V
–1.0 V/V
–1.5 V/V
–2.0 V/V
–10.0 V/V
2.0 V/V
2.5 V/V
3.0 V/V
11.0 V/V
Cin
Cin
Rin
Rin
- In
- In
Rfb
Rfb
-
-
Differential
Input
Inverting
+
+
+ In
Rin
Rfb
Cin
Cx
Rin
Rfb
-
Non
Inverting
+
+ In
Rx
Cin
Figure 14. Differential, Inverting and Non-inverting Gain Configuration
Internal and External Under Voltage Detection and RESET Output
The DRV604 contains an internal precision band gap reference voltage and 2 comparators, one is used to
monitor the supply voltages, PVDD_LD and PVDD_HP, and the other to monitor an external user selectable
voltage on pin 25. The internal PVDD monitor is set at 2.8 V with 200 mV hysteresis.
The external under voltage detection can be used to shutdown the DRV604 before an input device can make a
pop. The shutdown threshold at the Ex_UVP pin is 1.25 V. A resistor divider is used to obtain the shutdown
threshold and hysteresis desired for the application.
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Comparator
Ex_UVP
25
1.25 V
Bandgap
AMP Enable
PVDD_LD
23
PVDD_HP 20
Comparator
Internal PVDD
The selected thresholds can be determined as follows:
R11 + R12
(
)
VUVP = 1.25 V ´
R12
(1)
(2)
R11
R12
æ
ö
V
= 5 μA × R13 ×
+1
Hysteresis
ç
÷
è
ø
With the condition R13 >> R11||R12
For example, to obtain VUVP = 4.5 V and 400 mV hysteresis, use R11 = 10 kΩ, R12 = 3 kΩ and R13 = 22kΩ.
To filter supply spikes and noise a capacitor across R12 can be added.
External
Sense
DRV604
Voltage
5mA
R11
R12
Comparator
Ex_UVP
25
R13
1.25 V
Bandgap
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV604. These capacitors block the DC portion of the audio source and allow the DRV604 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the
DC-offset voltage at the output.
These capacitors form a high-pass filter with the input resistor, Rin. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1, then the frequency and/or capacitance can be determined when one of the
two values are given.
1
1
fcin
=
Cin =
2p ´ Rin ´ Cin
2p ´ fcin ´ Rin
(3)
11
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Using the DRV604 as a 2nd order filter
Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible
with the DRV604 as it can be used like a standard OPAMP. Several filter topologies can be implemented both
single ended and differential. In the figure below a Multi Feed Back (MFB), with differential input and single
ended input is shown.
An AC-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from
the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at:
http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Differential Input
Inverting Input
R2
C1
R2
C1
C3
C3
R1
R3
R1
R3
- In
- In
-
-
C2
C2
DRV604
DRV604
+
+
+ In
R1
R3
C3
C1
R2
Figure 15. 2nd Order Active Low Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling cap. C2 can be split in two with the midpoint connected to GND, this can increase
the common-mode attenuation.
Pop-Free Power Up
Pop-free power up is ensured by keeping the EN_LD and EN_HP and/or Ex_UVP low during power supply ramp
up and down. The pins should be kept low until the input AC-coupling capacitors are fully charged before
asserting the EN_xx pins high, this way proper pre-charge of the ac-coupling is performed and pop-less
power-up is achieved. Figure 16 illustrates the preferred sequence.
Supply
EN_xx
Supply Ramp
Time for ac-coupling
capacitors to charge
Figure 16. Power-Up/Down Sequence
12
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Product Folder Link(s) :DRV604
DRV604
www.ti.com
SLOS659 –JANUARY 2010
Dual Stereo Line Driver
The DRV604 Headphone stereo amplifier can also be used as Line Driver and has the same high output voltage
capability as the Line amp when driving 5kΩ load impedances. This makes the DRV604 ideal for applications like
dual SCART outputs on LCD TV, or for multiple line outputs like in DVD or Blue-Ray players where 2x DRV604
can give a very space effective solution for a 8ch line output.
Capacitive Load
The DRV604 has the ability to drive a high capacitive load up to 220pF directly, higher capacitive loads can be
accepted by adding an output series resistor of 47Ω or larger for the line driver output.
Layout Recommendations
A proposed layout for the DRV604 can be seen in the DRV604EVM user's guide, SLOU288, and the Gerber files
can be downloaded on www.ti.com, open the DRV604 product folder and look in the Tools and Software folder.
The gain setting resistors, Rin and Rfb, must be placed close to the input pins to minimize the capacitive loading
on these input pins and to ensure maximum stability of the DRV604.
Ground traces are recommended to be routed as a star ground to minimize hum interference.
PVDD, PVSS decoupling capacitors and the charge pump capacitors should be connected with short traces.
Footprint Compatible with the DRV603
The DRV604 stereo line driver section is pin compatible with the DRV603. A single PCB layout can therefore be
used with stuffing options for different output configurations.
1
1
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DRV604
SLOS659 –JANUARY 2010
www.ti.com
APPLICATION CIRCUIT
C11
C1
C14
LD_L_IN
LD_L_IN
1
1
2
2
1
2
10uF
10uF
1uF
R11
U1
R14
10.0k
C12
C15
10.0k
1
1
2
2
1
28
2
2
1
1
+LD_L
+LD_R
-LD_R
330pF
R13
330pF
R16
GND
GND
2
3
27
26
-LD_L
R12
33.0k
33.0k
C13
C16
33.0k
R15
33.0k
22pF
22pF
LD_L_OUT
LD_L_OUT
VSUP
OUT_LDL
AGND
OUT_LDR
Ex_UVP
R3
4
5
25
24
1
2
R1
22k
GND
10k
EN_LD
EN_LD
PGND
C5
1uF GND 470pF
C9
R2
C3
3.90k
1
2
6
7
23
22
PVSS_LD
PVDD_LD
CP_LD
1uF
GND
GND
CN_LD
CN_HP
+3.3V
8
9
21
20
R4
CP_HP
PVDD_HP
PGND
2
1
C4
1R
1
2
C7
10uF
C8
PVSS_HP
EN_HP
1uF
1uF
C6
1uF
GND
EN_HP
10
11
19
18
GND
GND
GND
NC
AGND
GND
HP_L_OUT
HP_R_OUT
12
17
OUT_HPL
OUT_HPR
-HP_R
30.0k
R22
C23
C26
22pF
R25
22pF
2
R26
30.0k
1
13
14
16
15
2
1
1
2
-HP_L
33.0k
R23
33.0k
C25
2
1
+HP_R
+HP_L
R21
10.0k
C22
330pF
330pF
R24
10.0k
GND
GND
PDRV604
C2
C21
C24
HP_L_IN
HP_R_IN
1
2
1
2
2
1
10uF
10uF
2.2uF
Single-Ended Input and Output with 3.3x Gain in the Line Section, 3x Gain in the Headphone Section.
AC-Coupling Input with a High Pass Pole of 1.6Hz, 2nd Order Low Pass Filter at 50kHz.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2010
PACKAGING INFORMATION
Orderable Device
DRV604PWP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
50 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
DRV604PWPR
HTSSOP
PWP
28
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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to Customer on an annual basis.
Addendum-Page 1
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