DRV8316 [TI]
DRV8316 Three-Phase Integrated FET Motor Driver;型号: | DRV8316 |
厂家: | TEXAS INSTRUMENTS |
描述: | DRV8316 Three-Phase Integrated FET Motor Driver |
文件: | 总83页 (文件大小:2077K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DRV8316
SLVSF16 – JANUARY 2021
DRV8316 Three-Phase Integrated FET Motor Driver
1 Features
3 Description
•
•
•
•
•
•
Three-phase PWM motor driver
– 3-Phase Brushless-DC motors
4.5-V to 35-V operating voltage
– 40-V Absolute maximum voltage
High output current capability
– 8-A Peak current drive
Low on-state resistance
– 95-mΩ RDS(ON) (HS + LS) at TA = 25°C
Low power sleep mode
– 1.5-µA at VVM = 24-V, TA = 25°C
Multiple control interface options
– 6x PWM control interface
The DRV8316 provides three half-H-bridge integrated
MOSFET drivers for driving a three-phase Brushless-
DC (BLDC) motor for 12-V/24-V DC rails or battery
powered applications. These applications include
field-oriented control (FOC), sinusoidal current
control, and trapezoidal current control of BLDC
motors. The device integrates three current-sense
amplifiers (CSA) with built-in current sense for
sensing the three phase currents of BLDC motors.
Each output driver channel consists of N-channel
power MOSFETs configured in
a
half-bridge
configuration. Various PWM control modes are
supported for simple interfacing to control circuits that
can be powered by the 30-mA, 3.3-V internal
regulator (AVDD). The DRV8316R/T also supports a
buck regulator which in conjunction can support 200-
mA with programmable regulated supply. The device
supports 200-kHz maximum PWM frequency.
– 3x PWM control interface
Supports 200-kHz PWM frequency
Cycle by cycle current limit
•
•
•
Built-in integrated current sense
– No external resistor required
SPI and Hardware device variants
– 5-MHz, 16-Bit SPI communication
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Built-in 3.3-V, 30-mA LDO regulator
Built-in 3.3-V/5-V, 200-mA buck regulator
Delay compensation to reduce duty cycle distortion
Integrated protection features
– VM undervoltage lockout (UVLO)
– Charge pump undervoltage (CPUV)
– Overcurrent protection (OCP)
– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indication pin (nFAULT)
Internal protection functions are provided for
undervoltage lockout (UVLO), Overvoltage protection
(OVP), charge pump undervoltage (CPUV),
overcurrent protection (OCP), over-temperature
warning (OTW) and over-temperature shutdown
(OTSD). Fault conditions are indicated by the nFAULT
pin.
•
•
•
•
•
•
Device Information (1)
PART NUMBER
DRV8316R
PACKAGE
VQFN (40)
VQFN (40)
BODY SIZE (NOM)
7.00 mm x 5.00 mm
7.00 mm x 5.00 mm
DRV8316T (2)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
(2) Device available for preview only.
•
•
•
•
•
•
CPAP machines
Printers
Camera gimbals
HVAC motors
Office automation machines
Factory automation and robotics
4.5 V to 35 V
DRV8316T/R
OUTA
nSLEEP
Three Phase PWM
Motor Driver
PWM (6x/3x)
M
HW / SPI
Buck Regulator (R)
3x Shunt Amplifier
Built-In Protection
OUTB
CSA Output
nFAULT
OUTC
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table ..............................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 6
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings ....................................... 8
7.2 ESD Ratings .............................................................. 8
7.3 Recommended Operating Conditions ........................8
7.4 Thermal Information ...................................................9
7.5 Electrical Characteristics ............................................9
7.6 SPI Timing Requirements ........................................ 16
7.7 SPI Slave Mode Timings...........................................16
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................54
8.5 SPI Communication.................................................. 55
8.6 Register Map.............................................................56
9 Application and Implementation..................................69
9.1 Application Information............................................. 69
9.2 Typical Applications.................................................. 70
10 Power Supply Recommendations..............................75
10.1 Bulk Capacitance....................................................75
11 Layout...........................................................................76
11.1 Layout Guidelines................................................... 76
11.2 Layout Example...................................................... 77
11.3 Thermal Considerations..........................................78
12 Device and Documentation Support..........................79
12.1 Support Resources................................................. 79
12.2 Trademarks.............................................................79
12.3 Electrostatic Discharge Caution..............................79
12.4 Glossary..................................................................79
13 Mechanical, Packaging, and Orderable
Information.................................................................... 79
4 Revision History
DATE
REVISION
NOTES
January 2021
*
Initial release.
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
5 Device Comparison Table
DEVICE
PACKAGES
40-pin VQFN (7x5 mm)
INTERFACE
SPI
BUCK REGULATOR
DRV8316R
Yes
DRV8316T(1)
Hardware
(1) Device available for preview only.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
6 Pin Configuration and Functions
1
2
32
31
30
29
28
27
26
25
24
23
22
21
INLC
NC
AGND
FB_BK
GND_BK
SW_BK
CPL
INHC
3
INLB
4
INHB
INLA
5
6
INHA
DRV8316R
(PowerPAD)
CPH
7
AGND
AVDD
NC
CP
8
VM
9
VM
10
11
12
nSLEEP
nFAULT
DRVOFF
VM
PGND
Figure 6-1. DRV8316R 40-Pin VQFN With Exposed Thermal Pad Top View
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
NC
AGND
FB_BK
GND_BK
SW_BK
CPL
32
31
30
29
28
27
26
25
24
23
22
21
INLC
1
2
INHC
3
INLB
4
INHB
INLA
5
6
INHA
DRV8316T
(PowerPAD)
CPH
7
AGND
AVDD
VSEL_BK
nSLEEP
nFAULT
DRVOFF
CP
8
VM
9
VM
10
11
12
VM
PGND
Figure 6-2. DRV8316T 40-Pin VQFN With Exposed Thermal Pad Top View
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Pin Functions
PIN
40-pin Package
TYPE
DESCRIPTION
NAME
DRV8316R
DRV8316T
AGND
2, 26
2, 26
PWR
Device analog ground. Connect to system ground.
3.3 internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic
capacitor between the AVDD1 and AGND pins. This regulator can source up
to 30 mA externally.
AVDD
25
25
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor
between the CP and VM pins.
CP
8
7
6
8
7
6
PWR
PWR
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated
ceramic capacitor between the CPH and CPL pins.
CPH
CPL
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated
ceramic capacitor between the CPH and CPL pins.
DRVOFF
FB_BK
21
3
21
3
I
Disables all six MOSFETs.
PWR
Feedback for buck regulator. Connect output of buck regulator to this pin.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor
(Hardware devices).
GAIN
—
4
36
4
I
PWR
I
GND_BK
INHA
Buck regulator ground. Connect to system ground.
High-side driver control input for OUTA. This pin controls the output of the
high-side MOSFET.
27
27
High-side driver control input for OUTB. This pin controls the output of the
high-side MOSFET.
INHB
INHC
INLA
INLB
INLC
29
31
28
30
32
29
31
28
30
32
I
I
I
I
I
High-side driver control input for OUTC. This pin controls the output of the
high-side MOSFET.
Low-side driver control input for OUTA. This pin controls the output of the low-
side MOSFET.
Low-side driver control input for OUTB. This pin controls the output of the low-
side MOSFET.
Low-side driver control input for OUTC. This pin controls the output of the low-
side MOSFET.
PWM input mode setting. This pin is a 2 level input pin set by an external
resistor (Hardware devices).
MODE
NC
—
1, 24
22
33
1
I
—
O
No Connect.
Fault indication pin. Pulled logic-low with fault condition; open-drain output
requires an external pullup.
nFAULT
22
Serial chip select. A logic low on this pin enables serial interface
communication (SPI devices).
nSCS
nSLEEP
OCP
36
23
—
—
23
35
I
I
I
Driver nSLEEP. When this pin is logic low the device goes to a low-power
sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions.
OCP level setting. This pin is a 2 level input pin set by an external resistor
(Hardware devices).
OUTA
OUTB
OUTC
PGND
13, 14
16, 17
13, 14
16, 17
O
O
Half bridge output A
Half bridge output B
19, 20
19, 20
O
Half bridge output C
12, 15, 18
12, 15, 18
PWR
Device power ground. Connect to system ground.
Serial clock input. Serial data is shifted out and captured on the corresponding
rising and falling edge on this pin.(SPI devices).
SCLK
35
—
I
Serial data input. Data is captured on the falling edge of the SCLK pin (SPI
devices).
SDI
34
33
—
40
—
—
34
40
I
SDO
SLEW
SOA
O
I
Serial data output. Data is shifted out on the rising edge of the SCLK pin.
Slew rate control setting. This pin is a 4 level input pin set by an external
resistor (Hardware devices).
O
Current sense amplifier output.
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
PIN
NAME
SOB
40-pin Package
TYPE
DESCRIPTION
DRV8316R
DRV8316T
39
38
5
39
38
5
O
O
Current sense amplifier output.
Current sense amplifier output.
SOC
SW_BK
PWR
Buck switch node. Connect this pin to an inductor or resistor.
Current sense amplifier power supply input and reference. Connect a X5R or
X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
VREF/ILIM
VM
37
9, 10, 11
—
37
9, 10, 11
24
PWR/I
PWR
I
Power supply. Connect to motor supply voltage; bypass to GND with two 0.1-
µF capacitors (for each pin) plus one bulk capacitor rated for VM
Buck output voltage setting. This pin is a 4 level input pin set by an external
resistor (Hardware devices).
VSEL_BK
Thermal
pad
PWR
Must be connected to ground
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Power supply pin voltage (VM)
–0.3
40
4
V
V/µs
V
Power supply voltage ramp (VM)
Voltage difference between ground pins (GND_BK, PGND, AGND)
Charge pump voltage (CPH, CP)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
0.3
VM + 6
VM + 0.3
5.75
V
Charge pump negative switching pin voltage (CPL)
Switching regulator pin voltage (FB_BK)
Switching node pin voltage (SW_BK)
Analog regulators pin voltage (AVDD)
Logic pin input voltage (DRVOFF, INHx, INLx, nSCS, nSLEEP, SCLK, SDI)
Logic pin output voltage (nFAULT, SDO)
Output pin voltage (OUTA, OUTB, OUTC)
Ambient temperature, TA
V
V
VM + 0.3
5.75
V
V
5.75
V
5.75
V
VM + 1
125
V
–40
–40
–65
°C
°C
°C
Junction temperature, TJ
150
Storage tempertaure, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VVM
fPWM
IOUT
Power supply voltage
VVM
4.5
24
35
200
8
V
kHz
A
Output PWM frequency
Peak output winding current
OUTA, OUTB, OUTC
OUTA, OUTB, OUTC
(1)
DRVOFF, INHx, INLx, nSCS, nSLEEP,
SCLK, SDI
VIN
Logic input voltage
–0.1
5.5
V
VOD
Open drain pullup voltage
Push-pull voltage
nFAULT, SDO
SDO
–0.1
2.2
5.5
5.5
V
V
VSDO
IOD
VVREF
TA
Open drain output current
Voltage reference pin voltage
Operating ambient temperature
Operating Junction temperature
nFAULT, SDO
VREF
5
mA
V
2.8
–40
–40
AVDD
125
150
°C
°C
TJ
(1) Power dissipation and thermal limits must be observed
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
7.4 Thermal Information
DRV8316T, DRV8316R
THERMAL METRIC(1)
VQFN (RGF)
40 Pins
25.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.2
7.3
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
7.2
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES
VVM > 6 V, nSLEEP = 0, TA = 25 °C
nSLEEP = 0
0.6
0.5
1.5
2.5
2.5
5
µA
µA
IVMQ
VM sleep mode current
nSLEEP = 1, INHx = INLx = 0, SPI =
'OFF', BUCK_DIS = 1;
2
2
3
3
4
4
mA
mA
VM standby mode current
(Buck regulator disabled)
IVMS
VVM > 6 V, nSLEEP = 1, INHx = INLx =
0, SPI = 'OFF', TA = 25 °C, BUCK_DIS =
1;
VVM > 6 V, nSLEEP = 1, INHx = INLx =
0, SPI = 'OFF', IBK = 0, TA = 25
°C, BUCK_DIS = 0;
3
4
5
5
mA
mA
VM standby mode current
(Buck regulator enabled)
IVMS
nSLEEP = 1, INHx = INLx = 0, SPI =
'OFF', IBK = 0, BUCK_DIS = 0;
3
10
13
10
13
4
11.5
17
VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz,
TA = 25 °C, BUCK_DIS = 1
13 mA
21 mA
13 mA
21 mA
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz,
TA = 25 °C, BUCK_DIS = 1
VM operating mode current
(Buck regulator disabled)
IVM
nSLEEP =1, fPWM = 25 kHz, BUCK_DIS
= 1
11.5
17
nSLEEP =1, fPWM = 200 kHz,
BUCK_DIS = 1
VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz,
TA = 25 °C, BUCK_DIS =
0; BUCK_PS_DIS = 0
6
mA
mA
VM operating mode current
(Buck regulator enabled)
IVM
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz,
TA = 25 °C, BUCK_DIS =
13
0; BUCK_PS_DIS = 0
0 mA ≤ IAVDD ≤ 30 mA; BUCK_PS_DIS =
0
VAVDD
Analog regulator voltage
3.135
3.3
3.465
V
IAVDD
VVCP
fCP
External analog regulator load
Charge pump regulator voltage
Charge pump switching frequency
30 mA
VCP with respect to VM
4.7
V
400
kHz
VVM > VUVLO, nSLEEP = 1 to outputs
ready and nFAULT released
tWAKE
Wakeup time
1
ms
tSLEEP
tRST
Sleep Pulse time
Reset Pulse time
nSLEEP = 0 period to enter sleep mode
nSLEEP = 0 period to reset faults
120
20
µs
µs
40
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
DRV8316
www.ti.com
MAX UNIT
SLVSF16 – JANUARY 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
BUCK REGULATOR
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 00b
3.1
4.6
3.7
5.2
3.3
5.0
4.0
5.7
3.5
5.4
4.3
6.2
V
V
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 01b
Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(SPI Device)
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 10b
VBK
VBK
VBK
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 11b
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 200 mA
VBK–
IBK*(RLBK
+2)
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 00b
3.1
4.6
3.7
5.2
3.3
5.0
4.0
5.7
3.5
5.4
4.3
6.2
V
V
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 01b
Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(SPI Device)
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 10b
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 11b
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 50 mA
VBK–
IBK*(RLBK
+2)
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 00b
3.1
4.6
3.7
5.2
3.3
5.0
4.0
5.7
3.5
5.4
4.3
6.2
V
V
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 01b
Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(SPI Device)
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 10b
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 11b
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 40 mA
VBK–
IBK*(RBK
+2)
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
VSEL_BK pin tied to AGND
3.1
4.6
3.3
5.0
3.5
5.4
VVM > 6 V, 0 mA ≤ IBK ≤ 200
mA, VSEL_BK pin to Hi-Z
VVM > 6 V, 0 mA ≤ IBK ≤ 200
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(HW Device)
3.7
5.2
4.0
5.7
4.3
6.2
VBK
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA,
VSEL_BK pin to AGND
VBK
–
VVM < 6.0 V, 0 mA ≤ IBK ≤ 200 mA
IBK*(RLBK
+2)
V
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
VSEL_BK pin tied to AGND
3.1
3.3
3.5
5.4
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50
mA, VSEL_BK pin to Hi-Z
4.6
3.7
5.2
5.0
4.0
5.7
VVM > 6 V, 0 mA ≤ IBK ≤ 50
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(HW Device)
4.3
6.2
V
V
V
VBK
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA,
VSEL_BK pin to AGND
VBK
–
VVM < 6.0 V, 0 mA ≤ IBK ≤ 50 mA
IBK*(RLBK
+2)
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
VSEL_BK pin tied to AGND
3.1
4.6
3.3
5.0
3.5
5.4
V
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40
mA, VSEL_BK pin to Hi-Z
VVM > 6 V, 0 mA ≤ IBK ≤ 40
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(HW Device)
3.7
5.2
4.0
5.7
4.3
6.2
V
V
V
VBK
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA,
VSEL_BK pin to AGND
VBK
–
VVM < 6.0 V, 0 mA ≤ IBK ≤ 40 mA
IBK*(RBK
+2)
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck
regulator with inductor, LBK = 47 uH, CBK
= 22 µF
–100
–100
–100
100 mV
100 mV
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
regulator with inductor, LBK = 22 uH, CBK
= 22 µF
VBK_RIP
Buck regulator ripple voltage
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
regulator with resistor; RBK = 22 Ω, CBK
= 22 µF
100 mV
200 mA
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 1b
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
200 –
IAVDD
mA
LBK = 22 uH, CBK
22 µF, BUCK_PS_DIS = 1b
=
50 mA
IBK
External buck regulator load
LBK = 22 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
50 –
IAVDD
mA
RBK = 22 Ω, CBK
22 µF, BUCK_PS_DIS = 1b
=
40 mA
RBK = 22 Ω, CBK = 22 µF,
BUCK_PS_DIS = 0b
40 –
IAVDD
mA
Regulation Mode
Linear Mode
TBD
0
535 kHz
535 kHz
fSW_BK
Buck regulator switching frequency
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
DRV8316
www.ti.com
MAX UNIT
SLVSF16 – JANUARY 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
VBK rising, BUCK_SEL = 00b
VBK falling, BUCK_SEL = 00b
VBK rising, BUCK_SEL = 01b
VBK falling, BUCK_SEL = 01b
VBK rising, BUCK_SEL = 10b
VBK falling, BUCK_SEL = 10b
VBK rising, BUCK_SEL = 11b
VBK falling, BUCK_SEL = 11b
VBK rising, VSEL_BK pin tied to AGND
VBK falling, VSEL_BK pin tied to AGND
MIN
2.7
2.5
4.3
4.1
2.7
2.5
4.3
4.1
2.7
2.5
TYP
2.8
2.6
4.4
4.2
2.8
2.6
4.4
4.2
2.8
2.6
2.9
2.7
4.5
4.3
2.9
2.7
4.5
4.3
2.9
2.7
V
V
V
V
V
V
V
V
V
V
Buck regulator undervoltage lockout
(SPI Device)
VBK_UV
VBK rising, VSEL_BK pin to 47 kΩ +/- 5%
tied to AVDD
4.3
4.1
4.4
4.2
4.5
4.3
V
V
VBK falling, VSEL_BK pin to 47 kΩ +/-
5% tied to AVDD
Buck regulator undervoltage lockout
(HW Device)
VBK_UV
VBK rising, VSEL_BK pin to Hi-Z
2.7
2.5
4.3
4.1
2.8
2.6
4.4
4.2
2.9
2.7
4.5
4.3
V
V
V
V
VBK falling, VSEL_BK pin to Hi-Z
VBK rising, VSEL_BK pin tied to AVDD
VBK falling, VSEL_BK pin tied to AVDD
Buck regulator undervoltage lockout
hysteresis
VBK_UV_HYS
Rising to falling threshold
200
mV
BUCK_CL = 0b
BUCK_CL = 1b
600
150
mA
mA
Buck regulator Current limit threshold
(SPI Device)
IBK_CL
Buck regulator Current limit threshold
(HW Device)
IBK_CL
600
mA
Buck regulator Overcurrent protection
trip point
IBK_OCP
2
3
1
4
A
tBK_RETRY
Overcurrent protection retry time
ms
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP, SCLK, SDI)
VIL
Input logic low voltage
0
1.5
1.6
180
95
0.6
5.5
5.5
V
V
V
Other Pins
VIH
Input logic high voltage
nSLEEP
Other PIns
300
250
420 mV
420 mV
VHYS
IIL
Input logic hysteresis
Input logic low current
Input logic high current
nSLEEP
VPIN (Pin Voltage) = 0 V
nSLEEP, VPIN (Pin Voltage) = 5 V
Other pins, VPIN (Pin Voltage) = 5 V
nSLEEP
–1
1
30
µA
µA
µA
kΩ
kΩ
pF
15
IIH
30
75
150
70
200
100
30
300
130
RPD
CID
Input pulldown resistance
Input capacitance
Other pins
LOGIC-LEVEL INPUTS (nSCS)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Input pullup resistance
Input capacitance
0
1.5
0.6
5.5
V
V
VIH
VHYS
IIL
180
300
420 mV
VPIN (Pin Voltage) = 0 V
VPIN (Pin Voltage) = 5 V
75
25
µA
µA
kΩ
pF
IIH
–1
80
RPU
CID
100
30
130
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FOUR-LEVEL INPUTS (GAIN, MODE, SLEW, VSEL_BK)
0.2*AVD
VL1
VL2
VL3
VL4
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 4 voltage
Tied to AGND
0
V
V
V
V
D
0.27*AV
DD
0.545*AV
DD
Hi-Z
0.5*AVDD
0.606*AV 0.757*AVD 0.909*AV
47 kΩ +/- 5% tied to AVDD
Tied to AVDD
DD
D
DD
0.94*AV
DD
AVDD
RPU
RPD
Input pullup resistance
To AVDD
To AGND
70
70
100
100
130
130
kΩ
kΩ
Input pulldown resistance
FOUR-LEVEL INPUTS ( OCP/SR)
0.09*AV
DD
VL1
VL2
VL3
VL4
Input mode 1 voltage
Input mode 2 voltage
Input mode 3 voltage
Input mode 3 voltage
Tied to AGND
22 kΩ ± 5% to AGND
Hi-Z
0
V
V
V
V
0.12*AV
DD
0.2*AVD
D
0.15*AVDD
0.5*AVDD
0.45*AV
DD
0.55*AV
DD
0.94*AV
DD
Tied to AVDD
AVDD
RPU
RPD
Input pullup resistance
To AVDD
To AGND
100
100
kΩ
kΩ
Input pulldown resistance
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
IOH
Output logic low voltage
Output logic high current
Output capacitance
IOD = 5 mA
VOD = 5 V
0.4
1
V
–1
µA
pF
COD
30
PUSH-PULL OUTPUTS (SDO)
VOL
VOH
IOL
Output logic low voltage
IOP = 5 mA
IOP = 5 mA
VOP = 0 V
VOP = 5 V
0
2.2
–1
0.4
5.5
1
V
Output logic high voltage
V
Output logic low leakage current
Output logic high leakage current
Output capacitance
µA
µA
pF
IOH
–1
1
COD
30
DRIVER OUTPUTS
VVM > 6 V, IOUT = 1 A, TA = 25°C
VVM < 6 V, IOUT = 1 A, TA = 25°C
VVM > 6 V, IOUT = 1 A, TJ = 150 °C
VVM < 6 V, IOUT = 1 A, TJ = 150 °C
95
100
130
130
mΩ
mΩ
mΩ
mΩ
Total MOSFET on resistance (High-side
+ Low-side)
RDS(ON)
VVM = 24 V, SLEW = 00b or SLEW pin
tied to AGND
25
50
V/us
V/us
V/us
V/us
VVM = 24 V, SLEW = 01b or SLEW pin to
Hi-Z
Phase pin slew rate switching low to high
(Rising from 20 % to 80 %)
SR
VVM = 24 V, SLEW = 10b or SLEW pin to
47 kΩ +/- 5% to AVDD
125
200
VVM = 24 V, SLEW = 11b or SLEW pin
tied to AVDD
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVM = 24 V, SLEW = 00b or SLEW pin
tied to AGND
25
V/us
VVM = 24 V, SLEW = 01b or SLEW pin to
Hi-Z
50
125
200
V/us
V/us
V/us
Phase pin slew rate switching high to low
(Falling from 80 % to 20 %
SR
VVM = 24 V, SLEW = 10b or SLEW pin to
47 kΩ +/- 5% to AVDD
VVM = 24 V, SLEW = 11b or SLEW pin
tied to AVDD
Leakage current on OUTx
Leakage current on OUTx
VOUTx = VVM, nSLEEP = 1
VOUTx = 0 V, nSLEEP = 1
5
1
mA
µA
ILEAK
VVM = 24 V, SR = 25 V/µs, HS driver ON
to LS driver OFF
2500
1200
750
3400
1550
1000
750
ns
ns
ns
ns
ns
ns
ns
VVM = 24 V, SR = 50 V/µs, HS driver ON
to LS driver OFF
Output dead time (high to low / low to
high)
tDEAD
VVM = 24 V, SR = 125 V/µs, HS driver
ON to LS driver OFF
VVM = 24 V, SR = 200 V/µs, HS driver
ON to LS driver OFF
500
VVM = 24 V, INHx = 1 to OUTx
transisition, SR = 25 V/µs
3000
1300
950
3500
1700
1100
900
VVM = 24 V, INHx = 1 to OUTx
transisition, SR = 50V/µs
Propagation delay (high-side / low-side
ON/OFF)
tPD
VVM = 24 V, INHx = 1 to OUTx
transisition, SR = 125 V/µs
VVM = 24 V, INHx = 1 to OUTx
transisition, SR = 200 V/µs
700
ns
ns
tMIN_PULSE
Minimum output pulse width
SR = 200 V/µs
600
CURRENT SENSE AMPLIFIER
CSA_GAIN = 00
0.15
0.3
0.6
1.2
0.15
0.3
0.6
1.2
V/A
V/A
V/A
V/A
V/A
V/A
V/A
V/A
%
CSA_GAIN = 01
GCSA
Current sense gain (SPI Device)
CSA_GAIN = 10
CSA_GAIN = 11
GAIN pin tied to AGND
GAIN pin to Hi-Z
GCSA
Current sense gain (HW Device)
Current sense gain error
GAIN pin to 47 kΩ ± 5% to AVDD
GAIN pin tied to AVDD
TA = 25°C, IPHASE < 4A
TA = 25°C, IPHASE > 4A
IPHASE < 4 A
–1.5
–3
1.5
3
%
GCSA_ERR
–2.5
–5
2.5
5
%
IPHASE > 4 A
%
TA = 25°C
–3
3
%
Current sense gain error matching
between phases A, B and C
IMATCH
–5
5
%
FSPOS
FSNEG
Full scale positive current measurement
Full scale negative current measurement
8
A
–8
A
VVREF
–
VLINEAR
SOX output voltage linear range
0.25
V
0.25
Phase current = 0 A, GCSA = 0.15 V/A
Phase current = 0 A, GCSA = 0.3 V/A
Phase current = 0 A, GCSA = 0.6 V/A
Phase current = 0 A, GCSA = 1.2 V/A
–50
–50
–50
–50
50 mA
50 mA
50 mA
50 mA
IOFFSET
Current sense offset low side current in
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
Step on SOX = 1.2 V, GCSA = 0.15 V/A
Step on SOX = 1.2 V, GCSA = 0.3 V/A
Step on SOX = 1.2 V, GCSA = 0.6 V/A
Step on SOX = 1.2 V, GCSA = 1.2 V/A
Phase current = 0 A
MIN
TYP
MAX UNIT
1
1
1
1
μs
μs
μs
μs
tSET
Settling time to ±1%, 30 pF
VDRIFT
IVREF
Drift offset
–80
80 µA/℃
VREF input current
VREF = 3.0 V
50
75
55
20
µA
dB
dB
dB
AVDD to SOx, DC
60
44
10
PSRR
Power Supply Rejection Ratio
AVDD to SOx, 10 kHz
AVDD to SOx, 500 kHz
Current limit corresponding to VLIM pin
voltage range
ILIMIT
0
5
A
PROTECTION CIRCUITS
VM rising
VM falling
4.3
4.1
140
3
4.4
4.2
200
5
4.5
4.3
V
V
VUVLO Supply undervoltage lockout (UVLO)
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold
350 mV
tUVLO
Supply undervoltage deglitch time
7
µs
V
Supply rising, OVP_EN = 1, OVP_SEL =
0
32.5
31.8
20
34
33
22
21
35
Supply falling, OVP_EN = 1, OVP_SEL
= 0
34.3
23
V
V
V
Supply overvoltage protection (OVP)
(SPI Device)
VOVP
Supply rising, OVP_EN = 1, OVP_SEL =
1
Supply falling, OVP_EN = 1, OVP_SEL
= 1
19
22
Rising to falling threshold, OVP_SEL = 1
Rising to falling threshold, OVP_SEL = 0
0.9
0.7
1
0.8
5
1.1
0.9
V
V
Supply overvoltage protection (OVP)
(SPI Device)
VOVP_HYS
tOVP
Supply overvoltage deglitch time
µs
V
Supply rising
2.5
2.4
100
2.85
2.65
Charge pump undervoltage lockout
(above VM)
VCPUV
Supply falling
V
VCPUV_HYS Charge pump UVLO hysteresis
Rising to falling threshold
Supply rising
mV
V
2.7
2.5
3
VAVDD_UV
Analog regulator undervoltage lockout
Supply falling
2.8
V
Analog regulator undervoltage lockout
hysteresis
VAVDD_ UV_HYS
Rising to falling threshold
200
mV
OCP_LVL = 0b
10
15
10
15
16
24
20
28
A
A
Overcurrent protection trip point (SPI
Device)
OCP_LVL = 1b
IOCP
OCP pin tied to AGND
OCP pin tied to AVDD
OCP_DEG = 00b
OCP_DEG = 01b
OCP_DEG = 10b
OCP_DEG = 11b
16
21.5
31
A
Overcurrent protection trip point (HW
Device)
24
A
0.2
0.6
1.1
1.6
µs
µs
µs
µs
Overcurrent protection deglitch time
(SPI Device)
tOCP
Overcurrent protection deglitch time
(HW Device)
0.2
µs
OCP_RETRY = 0
OCP_RETRY = 1
5
ms
ms
Overcurrent protection retry time
(SPI Device)
tRETRY
500
Overcurrent protection retry time
(HW Device)
tRETRY
5
ms
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
DRV8316
www.ti.com
MAX UNIT
SLVSF16 – JANUARY 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
135
10
TYP
145
15
TOTW
Thermal warning temperature
Thermal warning hysteresis
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature (TJ)
160
20
°C
°C
°C
°C
TOTW_HYS
TTSD
Die temperature (TJ)
Die temperature (TJ)
Die temperature (TJ)
150
10
160
15
175
20
TTSD_HYS
7.6 SPI Timing Requirements
MIN
NOM
MAX UNIT
tREADY
SPI ready after power up
nSCS minimum high time
nSCS input setup time
nSCS input hold time
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHI_nSCS
tSU_nSCS
tHD_nSCS
tSCLK
300
25
25
SCLK minimum period
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
SDO enable delay time
SDO disable delay time
100
50
tSCLKH
tSCLKL
50
tSU_SDI
tHD_SDI
tDLY_SDO
tEN_SDO
tDIS_SDO
25
25
25
50
50
7.7 SPI Slave Mode Timings
tHD_nSCS
tHI_nSCS
tSU_nSCS
tSCLK
tSCLKH
tSCLKL
X
MSB
LSB
X
tDIS_SDO
tDLY_SDO
tSU_SDI
tHD_SDI
Z
MSB
LSB
Z
tEN_SDO
Figure 7-1. SPI Slave Mode Timings
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8 Detailed Description
8.1 Overview
The DRV8316 device is an integrated 95-mΩ (combined high-side and low-side MOSFET's on-state resistance)
driver for 3-phase motor-drive applications. The device reduces system component count, cost, and complexity
by integrating three half-bridge MOSFETs, gate drivers, charge pump, current sense amplifiers, linear regulator
for the external load and buck regulator. A standard serial peripheral interface (SPI) provides a simple method
for configuring the various device settings and reading fault diagnostic information through an external controller.
Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through
fixed external resistors.
The architecture uses an internal state machine to protect against short-circuit events, and protect against dv/dt
parasitic turnon of the internal power MOSFET.
The DRV8316 device integrates three, bidirectional current-sense amplifiers for monitoring the current level
through each of the half-bridges using a built-in current sense. The gain setting of the amplifier can be adjusted
through the SPI or hardware interface.
In addition to the high level of device integration, the DRV8316 device provides a wide range of integrated
protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump
undervoltage lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck
regulator ULVO for DRV8316R/T and overtemperature shutdown (OTW and OTSD). Fault events are indicated
by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.
The DRV8316T and DRV8316R device are available in 0.5-mm pin pitch, VQFN surface-mount packages. The
VQFN package size is 7 mm × 5 mm.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.2 Functional Block Diagram
VVM
+
CVM1
CCP
VM
CVM2
CFLY
CPL
CP
CPH
To AVDD and
Buck Regulator
Replace Inductor (LBK
)
with Resistor (RBK) for
larger external load
or to reduce power
dissipation
Charge Pump
Regulators
I/O Control
Ext.
Load
Protection
AVDD
AGND
nSLEEP
VVM
CAVDD1
AVDD Linear Regulator
Overcurrent
Protection
DRVOFF
INHA
LBK
Ext.
Load
SW_BK
Thermal Warning
Thermal Shutdown
CBK
RBK
VVM
GND_BK
Buck Regulator
INLA
FB_BK
Input
Control
INHB
INLB
Predriver Stage
VCP
Power Stage
VM
INHC
HS Pre-
driver
INLC
VDD
OUTA
VLS
RnFAULT
LS Pre-
driver
Digital Control
Output
Current
Sense for
Phase - A
nFAULT
PGND
ISEN_A
Predriver Stage
VCP
Power Stage
VM
Interface
SCLK
HS Pre-
driver
SPI
OUTB
SDI
Current Limit
AVDD
VLS
SOA
SOB
LS Pre-
driver
SDO
Current
Sense for
Phase - B
AVDD
PGND
SOC
nSCS
+
-
ILIM
ISEN_B
Predriver Stage
VCP
Power Stage
VM
Current Sense Amplifiers
HS Pre-
driver
VREF/
ILIM
ISEN_A
ISEN_B
ISEN_C
AV
OUTC
SOC
SOB
SOA
VLS
AV
AV
Output Offset
Bias
LS Pre-
driver
Current
Sense for
Phase - C
PGND
ISEN_C
PGND
PGND
PGND
TPAD
Figure 8-1. DRV8316R Block Diagram
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
VVM
+
CVM1
CCP
VM
CVM2
CFLY
CPL
CP
CPH
To AVDD and
Buck Regulator
Replace Inductor (LBK
)
with Resistor (RBK) for
larger external load
or to reduce power
dissipation
Charge Pump
Regulators
I/O Control
Ext.
Load
Protection
AVDD
AGND
nSLEEP
DRVOFF
VVM
CAVDD1
AVDD Linear Regulator
Overcurrent
Protection
LBK
Ext.
Load
SW_BK
Thermal Warning
Thermal Shutdown
CBK
RBK
GND_BK
VVM
INHA
INLA
INHB
INLB
INHC
Buck Regulator
FB_BK
Predriver Stage
VCP
Power Stage
VM
HS Pre-
driver
Input
Control
OUTA
INLC
VLS
LS Pre-
driver
Digital Control
Current
Sense for
Phase - A
MODE
SLEW
PGND
ISEN_A
Predriver Stage
VCP
Power Stage
VM
OCP/SR
GAIN
HS Pre-
driver
VSEL_BK
OUTB
Current Limit
VLS
SOA
SOB
VDD
LS Pre-
driver
RnFAULT
Current
Sense for
Phase - B
Output
PGND
nFAULT
SOC
+
-
ILIM
ISEN_B
Predriver Stage
VCP
Power Stage
VM
Current Sense Amplifiers
HS Pre-
driver
VREF/
ILIM
ISEN_A
ISEN_B
ISEN_C
AV
OUTC
SOC
SOB
SOA
VLS
AV
AV
Output Offset
Bias
LS Pre-
driver
Current
Sense for
Phase - C
PGND
ISEN_C
PGND
PGND
PGND
TPAD
Figure 8-2. DRV8316T Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3 Feature Description
Table 8-1 lists the recommended values of the external components for the driver.
Table 8-1. DRV8316 External Components
COMPONENTS
CVM1
PIN 1
VM
PIN 2
PGND
RECOMMENDED
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10-µF, VM-rated capacitor
CVM2
VM
PGND
CCP
CP
VM
X5R or X7R, 16-V, 1-µF capacitor
X5R or X7R, 10-nF, VM-rated capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
X5R or X7R, buck-output rated capacitor
Output inductor
CFLY
CPH
CPL
CAVDD
CBK
AVDD
SW_BK
SW_BK
VCC
AGND
GND_BK
FB_BK
LBK
RnFAULT
RMODE
RSLEW
ROCP
nFAULT
5.1-kΩ, Pullup resistor
MODE
SLEW
OCP
AGND or AVDD
AGND or AVDD
AGND or AVDD
AGND or AVDD
AGND or AVDD
AGND
DRV8316 hardware interface
DRV8316 hardware interface
DRV8316 hardware interface
RGAIN
GAIN
DRV8316 hardware interface
RVSEL_BK
CVREF
VSEL_BK
VREF/ILIM
DRV8316 hardware interface
X5R or X7R, 0.1-µF, VREF-rated capacitor (Optional)
Note
TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into
internal test mode.
8.3.1 Output Stage
The DRV8316 device consists of an integrated 95-mΩ (combined high-side and low-side FET's on-state
resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the
proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to
providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side
MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the motor-
supply voltage.
8.3.2 Control Modes
The DRV8316 family of devices provides four different control modes to support various commutation and
control methods. Table 8-2 shows the various modes of the DRV8316 device.
Table 8-2. PWM Control Modes
MODE Pin
(Hardware
Variant)
PWM_MODE Bits
(SPI Variant)
MODE Type
MODE
Connected to
AGND
PWM_MODE =
00b
Mode 1
Mode 2
Mode 3
Mode 4
6x Mode
PWM_MODE =
01b
Hi-Z
6x Mode with Current Limit
3x Mode
Connected to
AVDD with RMODE
PWM_MODE =
10b
Connected to
AVDD
PWM_MODE = 11b
3x Mode with Current Limit
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Note
Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during
operation of the power MOSFETs. Set all INHx and INLx pins to logic low before changing the MODE
pin or PWM_MODE register.
8.3.2.1 6x PWM Mode (MODE = 00b or MODE Pin Tied to AGND)
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-3.
Table 8-3. 6x PWM Mode Truth Table
INLx
INHx
PHASEx
0
0
1
1
0
1
0
1
Hi-Z
H
L
Hi-Z
Figure 8-3 shows the application diagram of DRV8316 configured in 6x PWM mode.
VM
OUTA
nSLEEP
INHA
INLA
INHB
VM
Controller
INLB
INHC
OUTB
Gate
Drive
and
Logic
OCP
BLDC
Motor
INLC
VM
MODE
GND
OUT3
GND
Figure 8-3. 6x PWM Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.2.2 3x PWM Mode (MODE = 10b or MODE Pin is Connected to AGND with RMODE
)
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 8-4.
Table 8-4. 3x PWM Mode Truth Table
INLx
INHx
PHASEx
0
1
1
X
0
1
Hi-Z
L
H
Figure 8-4 shows the application diagram of DRV8316 configured in 3x PWM mode.
VM
OUTA
nSLEEP
INHA
INHB
INHC
VM
Controller
INLA
INLB
OUTB
Gate
Drive
and
Logic
OCP
BLDC
Motor
INLC
VM
AVDD
AVDD
OUT3
MODE
GND
Figure 8-4. 3x PWM Mode
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.2.3 Current Limit Mode (MODE = 01b / 11b or MODE Pin is Hi-Z or Connected to AVDD)
Figure 8-5 shows the application diagram of DRV8316 configured in current limit mode. A current limit
comparator is used for the current limiting which input is generated with the three current sense amplifier's
outputs.
VM
OUTA
nSLEEP
Current
Sense
ISEN_A
INHA
VM
INLA
INHB
INLB
INHC
Controller
OUTB
Gate
Drive
and
Logic
Current
Sense
OCP
BLDC
Motor
ISEN_B
INLC
VM
Hi-Z /
Connected
to AVDD
MODE
OUT3
Current
Sense
ISEN_C
GND
Current Limit
SOA
SOB
ILIM
SOC
-
+
PWM Current Limit
Figure 8-5. Current Limit Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.3 Device Interface Modes
The DRV8316 family of devices supports two different interface modes (SPI and hardware) to let the end
application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.3.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that lets an external controller send and receive data with
the DRV8316. This support lets the external controller configure device settings and read detailed fault
information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are
described as follows:
•
The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
the SDI and SDO pins.
•
•
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
•
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV8316.
For more information on the SPI, see the Section 8.5 section.
8.3.3.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are GAIN,
SLEW, MODE, and OCP.
This conversion lets the application designer configure the most common device settings by tying the pin logic
high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from
the external controller. General fault information can still be obtained through the nFAULT pin.
•
•
•
•
The GAIN pin configures the gain of the current sense amplifier.
The SLEW pin configures the slew rate of the output voltage.
The MODE pin configures the PWM control mode.
The OCP/SR pin is used to configures the OCP level and active demagnetization modes.
For more information on the hardware interface, see the Section 8.3.10 section.
AVDD
RSLEW
AVDD
SLEW
SCLK
SDI
AVDD
AVDD
MODE
SPI
Interface
AVDD
VCC
RPU
Hardware
Interface
OCP/SR
GAIN
SDO
nSCS
AVDD
AVDD
Figure 8-7. DRV8316T Hardware Interface
Figure 8-6. DRV8316R SPI Interface
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.4 AVDD Linear Voltage Regulator
A 3.3-V, linear regulator is integrated into the DRV8316 family of devices and is available for use by external
circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the DRV8316 device.
Additionally, this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting
low current (up to 30mA). The output of the AVDD regulator should be bypassed near the AVDD pin with an X5R
or X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The AVDD nominal, no-load output voltage is 3.3V.
VM
REF
+
œ
AVDD
AGND
External Load
CAVDD
Figure 8-8. AVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator.
2 = (88/ F 8#8&&) × +#8&&
(1)
For example, at a VVM of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in Equation
2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.5 Step-Down Buck Regulator )
The DRV8316R and DRV8316T have an integrated buck regulator in conjunction with analog linear regulator to
supply regulated 3.3/5V power for an external controller or system voltage rail. Additionally, the buck output can
also be configured to 4/5.7V to support extra headroom for an external LDO generating a 3.3/5V supply. The
output voltage of the buck is set by the VSEL_BK pin in the DRV8316T device (hardware variant) and
BUCK_SEL bits in the DRV8316R device (SPI variant).
The buck regulator has a very-low quiescent current during light loads to prolong battery life. The device
improves performance during line and load transients by implementing a pulse-frequency current-mode control
scheme which requires less output capacitance and simplifies frequency compensation design.
8.3.5.1 Buck Inductor Mode
The buck regulator in DRV8316 device is primarily designed to support low inductance of 47µH and 22µH
inductors. The 47µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas
the 22µH inductor limits the load current to 50 mA.
Figure 8-9 shows the connection of buck regulator in inductor mode.
VM
SW_BK
Ext. Load
VBK
Control
LBK
CBK
GND_BK
FB_BK
Figure 8-9. Buck (Inductor Mode)
8.3.5.2 Buck Resistor mode
If the external load requirement is less than 40 mA, the inductor can be replaced with a resistor. In resistor mode,
power is dissipated from the external resistor and the efficiency is lower than inductor mode.
Figure 8-10 shows the connection of buck regulator in resistor mode.
VM
SW_BK
Ext. Load
VBK
Control
RBK
CBK
GND_BK
FB_BK
Figure 8-10. Buck (Resistor Mode)
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.5.3 Buck Regulator with External LDO
The buck regulator in the DRV8316 device also supports the voltage requirement to feed to an external LDO to
generate the standard 3.3V/5V output rail. The buck output voltage is configured to 4V or 5.7V to provide an
extra headroom to support the external LDO for generating a 3.3V or 5V rail as shown in Figure 8-11. This allows
a lower-voltage LDO design to save cost and better thermal management due to low drop-out voltage.
VM
VLDO
(3.3V / 5V)
VBK
SW_BK
(4V / 5.7V)
VIN
VLDO
Ext. Load
CLDO
Control
LBK
3.3V / 5V
LDO
CBK
GND_BK
FB_BK
GND
External LDO
GND
Figure 8-11. Buck Regulator with External LDO
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.5.4 LDO Power Sequencing on Buck Regulator
The LDO of DRV8316R and DRV8316T devices has an option of accepting the power supply from buck
regulator to reduce power dissipation. The power sequencing mode in the DRV8316R and DRV8316T device
allows on-the-fly changeover of the LDO power supply from the DC mains (VM) to buck output (VBK) as shown
in Figure 8-12. This sequencing automatically happens in the hardware device when the buck voltage is set to
either 5V or 5.7V. For disabling the power sequencing in the SPI device, set the BUCK_PS_DIS bit to 1.
VM
SW_BK
Ext. Load
VBK
Control
LBK
CBK
GND_BK
FB_BK
AVDD_PS
VBK
VM
REF
+
œ
AVDD
AGND
External Load
CAVDD
Figure 8-12. LDO Power Sequencing on Buck Regulator
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.5.5 Buck Operation and Control
The buck regulator in DRV8316R and DRV8316T implements a pulse frequency modulation (PFM) architecture
with peak current mode control. The output voltage of the buck regulator is compared with the reference voltage
(VBK_REF) which is internally generated depending on the buck-output voltage setting (VSEL_BK pin or
BUCK_SEL bits) which constitutes an outer voltage control loop. Now, depending on the comparator output
going high (VBK < VBK_REF) or low (VBK > VBK_REF), the high-side power FET of the buck turns on and off
respectively. An independent current control loop monitors the current in the high-side power FET (IBK) and turns
off the high-side FET when the current becomes higher than the buck current limit (IBK_CL). This implements a
current limit control for the buck regulator. Figure 8-13 shows the architecture of the buck and various control/
protection loops to avoid unwanted scenarios.
Slew Rate
Control
SW_BK
IBK
Ext. Load
VBK
VM
LBK
PWM Control
and Driver
CBK
GND_BK
IBK
+
Current Limit
OC Protection
UV Protection
_
IBK_CL
IBK
+
_
IBK_OCP
FB_BK
VBK
+
_
VBK_UVLO
VBK
+
_
Voltage Control
VBK_REF
VSEL_BK
Buck
(HW Device)
Reference
Voltage
Generator
Buck Control
BUCK_SEL
(SPI Device)
Figure 8-13. Buck Operation and Control Loops
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.5.6 Buck Undervoltage Protection
If at any time the input supply voltage on the FB_BK pin falls lower than the VBK_UVLO threshold, all of the both
high-side and low-side MOSFETs of the buck regulator are disabled and the nFAULT pin is driven low. The
FAULT, BK_FLT and BUCK_UV bits are also latched high in the registers on SPI devices. Normal operation
starts again (buck operation and the nFAULT pin is released) when the VBK undervoltage condition clears. The
BUCK_UV bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
8.3.5.7 Buck Overcurrent Protection
The overcurrent event is sensed by monitoring the current flowing through high-side MOSFET of the buck
regulator. If the current across high-side MOSFET exceeds the IBK_OCP threshold for longer than the tOCP_DEG
deglitch time, a buck OCP event is recognized and nFAULT pin is driven low. The FAULT, BK_FLT and BK_OCP
bits are latched high in the SPI registers. Normal operation starts again automatically (buck operation and the
nFAULT pin is released) after the tRETRY time elapses. The FAULT, BK_FLT and BK_OCP bits stay latched until
the tRETRY period expires.
On hardware interface devices, the IBK_OCP threshold is set to 600-mA, whereas on SPI devices, the IBK_OCP
threshold is set through the BUCK_CL bit to either to 600-mA or 150-mA.
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.6 Charge Pump
Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM
power supply to enhance the high-side FETs fully. The DRV8316 integrates a charge-pump circuit that generates
a voltage above the VM supply for this purpose.
The charge pump requires two external capacitors for operation. See the block diagram, pin descriptions and
see section (Table 8-1 ) for details on these capacitors (value, connection, and so forth).
The charge pump shuts down when nSLEEP is low.
VM
VM
CCP
CP
CPH
VM
Charge
Pump
Control
CFLY
CPL
Figure 8-14. DRV8316 Charge Pump
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.7 Slew Rate Control
An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew rate
control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration
of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are
predominantly determined by the rate of gate charge to internal MOSFETs as shown in Figure 8-15.
VM
VCP (Internal)
Slew Rate
Control
OUTx
VCP (Internal)
Slew Rate
Control
GND
Figure 8-15. Slew Rate Circuit Implementation
The slew rate of each half-bridge can be adjusted by the SLEW pin in hardware device variant or by using the
SLEW bits in SPI device variant. Each half-bridge can be selected to either of a slew rate setting of 25-V/µs, 50-
V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise time and fall time of the voltage on OUTx pin
as shown in Figure 8-16.
VOUTx
VM
VM
80%
80%
20%
20%
0
Time
tfall
trise
Figure 8-16. Slew Rate Timings
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.8 Cross Conduction (Dead Time)
The device is fully protected for any cross conduction of MOSFETs. In half-bridge configuration, the operation of
high-side and low-side MOSFETs are ensured to avoid any shoot-through currents by inserting a dead time
(tdead). This is implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs
and ensuring that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side
MOSFET of same half-bridge as shown in Figure 8-17 and Figure 8-18.
VM
Gate
Control
+
VGS
HS
LS
œ
OUTx
Gate
Control
+
GND
VGS
œ
Figure 8-17. Cross Conduction Protection
OUTx HS
OUTx
Gate
(VGS_HS)
10%
tDEAD
OUTx
Gate
(VHS_LS)
10%
OUTx LS
Time
Figure 8-18. Dead Time
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.9 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to change in gate driver
voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator
delay.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes, a small digital delay is added as the input command propagates
through the device.
INx
OUTx High
tPD
20%
OUTx Low
OUTx
Time
Figure 8-19. Propagation Delay Timing
8.3.9.1 Driver Delay Compensation
DRV8316 monitors the prorogation delay internally and adds a variable delay on top of it to provide fixed delay
as shown in Figure 8-20 and Figure 8-21. Delay compensation feature reduces uncertainty caused in timing of
current measurement and also reduces duty cycle distortion caused due to propagation delay.
The fixed delay is summation of propagation delay (tPD) caused to internal driver delay and variable delay (tVAR
)
added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer
Table 8-5 for recommendation on configuration for DLY_TARGET for different slew rate settings.
Delay compensation is only available in SPI variant DRV8316R and can be enabled by configuring DLYCMP_EN
and DLY_TARGET. It is disabled in hardware variant DRV8316T
INLx
INHx
1V
1V
1V
1V
OUTx
OUTx
Time
Time
tVAR
tVAR
tPD
tPD
tVAR
tVAR
tPD
tPD
DLY_TARGET
DLY_TARGET
DLY_TARGET
DLY_TARGET
Figure 8-21. Delay Compensation with current
flowing into the phase
Figure 8-20. Delay Compensation with current
flowing out of phase
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Table 8-5. Delay Target Recommendation
SLEW RATE
200 V/μs
125 V/μs
50 V/μs
DLY_TARGET
DLY_TARGET = 0x5 (1.2 μs)
DLY_TARGET = 0x8 (1.8 μs)
DLY_TARGET = 0xB (2.4 μs)
DLY_TARGET = 0xF (3.2 μs)
25 V/μs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.10 Pin Diagrams
This section presents the I/O structure of all digital input and output pins.
8.3.10.1 Logic Level Input Pin (Internal Pulldown)
Figure 8-22 shows the input structure for the logic level pins, DRVOFF, INHx, INLx, nSLEEP, SCLK and SDI.
The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep
mode to reduce leakage current through internal pull-down resistors.
AVDD
STATE
VIH
CONNECTION
Tied to AVDD
Tied to GND
INPUT
Logic High
Logic Low
VIL
RPD
ESD
Figure 8-22. Logic-Level Input Pin Structure
8.3.10.2 Logic Level Input Pin (Internal Pullup)
Figure 8-23 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or
external resistor.
AVDD
AVDD
STATE
VIH
CONNECTION
Tied to AVDD
Tied to GND
INPUT
RPU
Logic High
Logic Low
VIL
ESD
Figure 8-23. Logic nSCC
8.3.10.3 Open Drain Pin
Figure 8-24 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an
external pullup resistor to function properly.
AVDD
STATE
No Fault
Fault
STATUS
Pulled-Up
RPU
OUTPUT
Inactive
Active
Pulled-Down
ESD
Figure 8-24. Open Drain
8.3.10.4 Push Pull Pin
Figure 8-25 shows the structure of push-pull pin, SDO.
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
AVDD
STATE
VOH
STATUS
Pulled-Up
OUTPUT
Logic High
Logic Low
VOL
Pulled-Down
ESD
Figure 8-25. Push Pull
8.3.10.5 Four Level Input Pin
Figure 8-26 shows the structure of the four level input pins, GAIN, MODE, SLEW, OCP/SR and VSEL_BK on
hardware interface devices. The input can be set with an external resistor.
CONTROL
AVDD
AVDD
STATE
VL1
RESISTANCE
Tied to AGND
Setting-1
Setting-2
Setting-3
Setting-4
+
RPU
œ
Hi-Z (>2000 kΩ to
AGND)
VL2
VL3
VL4
+
RPD
47 kΩ ±5%
to AVDD
œ
Tied to AVDD
+
œ
Figure 8-26. Four Level Input Pin Structure
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.11 Current Sense Amplifiers
The DRV8316 integrates three, high-performance low-side current sense amplifiers for current measurements
using built-in current sensing. Low-side current measurements are commonly used to implement overcurrent
protection, external torque control, or brushless-DC commutation with an external controller. All three amplifiers
can be used to sense the current in each of the half-bridge legs (low-side FETs). The current sense amplifiers
include features such as programmable gain and external reference is provided on a voltage reference pin
(VREF).
8.3.11.1 Current Sense Amplifier Operation
The SOx pin on the DRV8316 outputs an analog voltage proportional to current flowing in the low side FETs
multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels which can be
set by the GAIN pin (in hardware device variant) or the GAIN bits (in SPI device variant).
Figure 8-27 shows the internal architecture of the current sense amplifiers. The current sense is implemented
with the sense FET on each low-side FET of the DRV8316 device. This current information is fed to the interal
I/V converter, which generates the CSA output voltage on the SOX pin based on the voltage on VREF pin and
the Gain setting. The CSA output voltage can be calculated as :
8
4'(W
51: = @
A ± )#+0 × +176:
2
(3)
VM
VREF
OUTX
Sense
FET
GAIN
I/V Converter
PGND
SOX
Figure 8-27. Integrated Current Sense Amplifier
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Figure 8-28 and Figure 8-29 show the detail of the amplifier operational range. In bi-directional operation, the
amplifier output for 0-V input is set at VREF / 2. Any change in the differential input results in a corresponding
change in the output times the CSA_GAIN factor. The amplifier has a defined linear region in which it can
maintain operation.
SOX
VREF
V
VREF
œ 0.25 V
œIOUTx
V
SO(rangeœ)
V
SO(off)max
/ 2
V , V
OFF DRIFT
0 V
V
VREF
V
SO(off)min
V
SO(range+)
IOUTx
0.25 V
0 V
Figure 8-28. Bidirectional Current Sense Output
SOX (V)
VREF
VREF / 2
VLINEAR
IOUTx (A) (Current flowing into the FET)
Figure 8-29. Bidirectional Current Sense Regions
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.12 Active Demagnetization
DRV8316 family of devices has smart rectification features (actice demagnetization) which reduces power losses
in device by reducing diode conduction losses. When this feature is enabled device automatically turns ON FET
whenever it detects diode conduction. This feature can be configured with the OCP/SR pins in hardware
variants. In SPI device variants this can be configured through EN_ASR and EN_AAR bits. The smart
rectification is classified into two categories of automatic synchronous rectification (ASR) mode and automatic
asynchronous rectification (AAR) mode which are described in sections below.
Note
In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active
demagnetization.
The DRV8316 device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the
negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET
output with the supply voltage (VM) threshold, whereas the AD_LS compatator compares with the ground (0-V)
threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS
comparator trips. This comparator provides a reference point for the operation of active demagnetization feature.
VM
AD_HS
Comparator
+
-
Sense
FET
(To Digital)
(To Digital)
OUTX
VM
+
-
Sense
FET
AD_LS
Comparator
0V (GND)
PGND
VREF
I/V Converter
SOX
GAIN
Figure 8-30. Active Demagnetization Operation
Table 8-6 shows the configuration of ASR and AAR mode in the DRV8316 device.
Table 8-6. PWM_MODE Configuration
OCP/SR Pin (Hardware
MODE Type
Mode 1
SR Bits (SPI Variant)
EN_ASR = 0, EN_AAR = 0
EN_ASR = 0, EN_AAR = 0
OCP Setting
16 A
ASR and AAR Mode
ASR and AAR Disabled
ASR and AAR Disabled
Variant)
Connected to AGND
Connected to AGND with
RMODE1
Mode 2
24 A
Mode 3
Mode 4
Hi-Z
EN_ASR = 1, EN_AAR = 1
EN_ASR = 1, EN_AAR = 1
16 A
24 A
ASR and AAR Enabled
ASR and AAR Enabled
Connected to AVDD
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.12.1 Automatic Synchronous Rectification Mode (ASR Mode)
The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation
and ASR during PWM mode.
8.3.12.1.1 Automatic Synchronous Rectification in Commutation
Figure 8-31 shows the operation of active demagnetization during the BLDC motor commutation. As shown in
Figure 8-31 (a), the current is flowing from HA to LC in one commutation state. During the commutation
changeover as shown in Figure 8-31 (b), the HC switch is turned on, whereas the commutation current (due to
motor inductance) in OUTA flows through the body diode of LA. This incorporates a higher diode loss depending
on the commutation current. This commutation loss is reduced by turning on the LA for the commutation time as
shown in Figure 8-31 (c).
Similarly the operation of high-side FET is realized in Figure 8-31 (d), (e) and (f).
VM
VM
HB
HC
HA
HB
HC
HA
OUTA
OUTA
OUTB
OUTB
OUTC
OUTC
OUTC
OUTC
OUTC
OUTC
LA
LB
LC
LA
LB
LC
(a) Current flowing from HA to LC
VM
(d) Current flowing from HC to LA
VM
Decay Current
Decay Current
HB
HC
HB
OUTA
LB
HC
HA
HA
OUTA
OUTB
OUTB
LA
LB
LC
LA
LC
(e) Decay current with AD disabled
VM
(b) Decay current with AD disabled
VM
Decay Current
Decay Current
HB
HC
HB
OUTA
LB
HC
HA
HA
OUTA
OUTB
OUTB
LA
LB
LC
LA
LC
(c) Decay current with AD enabled
(f) Decay current with AD enabled
Figure 8-31. ASR in BLDC Motor Commutation
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Figure 8-32 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode in
BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a
single commutation cycle.
Figure 8-32 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with
margin time (tmargin) and ASR mode early stop due to active demag. comparator threshold and delays.
Current Limit
Phase ”A‘
Current
LA
HA
HA, LB
HB, LC
HB, LA
HC, LA
HC, LB
HA, LC
(a) Commutation current of Phase —A“
tmargin
tdead
HA Conducts
LA Body Diode
Conducts
HA Body Diode
Conducts
Phase ”A‘
Current
LA Conducts
tdead
HC, LA
HC, LB
HA, LC
HB, LC
(b) Zoomed waveform of Active Demagnetization
Figure 8-32. Current Waveforms for ASR in BLDC Motor Commutation
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.12.1.2 Automatic Synchronous Rectification in PWM Mode
Figure 8-33 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on the
high-side FET, whereas the low-side FET is always off. During the PWM off time, current decays from the low-
side FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET during
the low-side diode conduction.
PWM_HS
(Applied)
&t
PWM_LS
(Applied)
&t
PWM_HS
(Actual)
&t
PWM_LS
(Actual)
&t
Ia
&t
ASR Mode Disabled
ASR Mode Enabled
Figure 8-33. ASR in PWM Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.12.2 Automatic Asynchronous Rectification Mode (AAR Mode)
Figure 8-34 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a
synchronous rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower
inductance motors, the current can decay to zero and becomes negative since low side FET is in on-state. This
creates a negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the
decay is monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves
the negative current building in the BLDC motor which results in better noise performance and better thermal
management.
PWM_HS
(Applied)
&t
PWM_LS
(Applied)
&t
PWM_HS
(Actual)
&t
PWM_LS
(Actual)
&t
Ia
&t
AAR Mode Disabled
AAR Mode Enabled
Figure 8-34. AAR in PWM Mode
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.13 Cycle-by-Cycle Current Limit
The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the ILIMIT current.
This feature restricts motor current to less than the ILIMIT
.
The current-limit circuitry utilizes the current sense amplifier output of the three phases compared with the
voltage at ILIM pin. Figure 8-35 shows the implementation of current limit circuitry. As shown in this figure, the
output of current sense amplifiers is combined with star connected resistive network. This measured voltage
VMEAS is compared with the external reference voltage e VILIM pin to realize the current limit implementation. The
relation between current sensed on OUTX pin and VMEAS threshold is given as:
8
#8&&W
: ;
¤
A F k +176# + +176$ + +176% × )#+0 3o
8/'#5 = @
2
(4)
where
•
•
•
AVDD is 3.3-V LDO output
OUTX is current flowing into the low-side MOSFET
GAIN is the CSA gain setting
The ILIMIT threshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.4) V. AVDD/2 is
minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum
threshold of 8A can be configured by applying (AVDD/2 - 0.4) V on ILIM pin. The relation between current
sensed on OUTX pin and ILIMIT threshold is given as:
VM
AVDD
I/V Converter
SOA
OUTA
Sense
FET
GAIN
PGND
SOB
To PWM
VMEAS
VILIM
Controller
-
+
ILIM
SOC
Figure 8-35. Current Limit Implementation
When then the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle as
shown in Figure 8-36. The low-side FETs can operate in brake mode or high-Z mode by configuring the
ILIM_RECIR bit in the SPI device variant.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
PWM
OUTx
ILIMIT
Bridge Operating in
Brake Mode
IBRIDGE
Time
Figure 8-36. Cycle-by-Cycle Current-Limit Operation
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Figure 8-37 shows the operation of driver in brake mode, where the current recirculates through low-side FETs
while the high-side FETs are disabled.
Figure 8-38 shows the operation of driver in hi-Z mode, where the current recirculates through the body diodes
of the low-side FETs while the high-side FETs are disabled.
VM
VM
HB
HC
HA
HB
HC
HA
X
X
X
X
X
X
OUTA
OUTA
OUTB
OUTB
OUTC
OUTC
LA
LB
LC
LA
LB LC
X X X
Figure 8-37. Brake State
Figure 8-38. Coast State
Note
The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking
time to prevent false trips of the current-limit circuit.
Note
During the brake operation, a high-current can flow through the low-side FETs which can eventually
trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct
and pump brake energy to the VM supply rail.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.13.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To
overcome this problem, DRV8316 has built in internal PWM clock which is used to turn high-side FET back on
once it is disabled after exceeding ILIMIT threshold. In SPI variant DRV8316R , this internal PWM clock can be
configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant DRV8316T PWM internal
clock is set to 20 kHz. Figure 8-39 shows operation with 100 % duty cycle.
PWM
Internal
PWM
OUTx
ILIMIT
Bridge Operating in
Brake Mode
Time
Figure 8-39. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.14 Protections
The DRV8316 family of devices is protected against VM undervoltage, charge pump undervoltage, and
overcurrent events. Table 8-7 summarizes various faults details.
Table 8-7. Fault Action and Response (SPI Devices)
FAULT
CONDITION
CONFIGURATION
REPORT
H-BRIDGE
LOGIC
RECOVERY
Automatic:
VVM > VUVLO_R
CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
VM undervoltage
(NPOR)
VVM < VUVLO
—
—
Hi-Z
Disabled
Automatic:
VAVDD > VAVDD_UV_R
CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
AVDD undervoltage
(NPOR)
VAVDD < VAVDD_UV
VFB_BK < VBK_UV
VCP < VCPUV
—
—
—
nFAULT
nFAULT
nFAULT
Hi-Z
Active
Hi-Z
Disabled
Active
Automatic:
VFB_BK > VBUCK_UV_R
CLR_FLT, nSLEEP Reset Pulse
(BUCK_UV bit)
Buck undervoltage
(BUCK_UV)
Automatic:
VVCP > VCPUV
CLR_FLT, nSLEEP Reset Pulse
(VCP_UV bit)
Charge pump
undervoltage
(VCP_UV)
Active
OVP_EN = 0b
OVP_EN = 1b
None
Active
Hi-Z
Active
Active
No action (OVP Disabled)
OverVoltage
Protection
(OVP)
Automatic:
VVM < VOVP
CLR_FLT, nSLEEP Reset Pulse (OVP bit)
VVM > VOVP
FAULT
Latched:
CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
OCP_MODE = 00b
OCP_MODE = 01b
nFAULT
nFAULT
Hi-Z
Hi-Z
Active
Active
Retry:
tRETRY
Overcurrent
Protection
(OCP)
IPHASE > IOCP
Automatic:
CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
OCP_MODE = 10b
OCP_MODE = 11b
—
nFAULT
None
Active
Active
Active
Active
Active
Active
No action
Buck Overcurrent
Protection
(BUCK_OCP)
Retry:
tRETRY
IBK > IBK_OC
nFAULT
Automatic:
CLR_FLT, nSLEEP Reset Pulse
(SPI_FLT bit)
SPI_FLT_REP = 0b
nFAULT
Active
Active
SPI Error
(SPI_FLT)
SCLK fault and ADDR
fault
SPI_FLT_REP = 1b
—
None
nFAULT
None
Active
Hi-Z
Active
Active
Active
No action
OTP Error
(OTP_ERR)
Latched:
OTP reading is erroneous
TJ > TOTW
Power Cycle, nSLEEP Reset Pulse
OTW_REP = 0b
Active
No action
Thermal warning
(OTW)
Automatic:
TJ < TOTW – THYS
CLR_FLT, nSLEEP Pulse (OTW bit)
OTW_REP = 1b
—
nFAULT
nFAULT
Active
Hi-Z
Active
Active
Automatic:
TJ < TOTSD – THYS
CLR_FLT, nSLEEP Pulse (OTS bit)
Thermal shutdown
(OTSD)
TJ > TOTSD
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.3.14.1 VM Supply Undervoltage Lockout (NPOR)
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold (VM UVLO falling
threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in
Figure 8-40. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The
NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR
bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE ON
DEVICE OFF
DEVICE ON
Time
Figure 8-40. VM Supply Undervoltage Lockout
8.3.14.2 AVDD Undervoltage Lockout (AVDD_UV)
If at any time the voltage on AVDD pin falls lower than the VAVDD_UV threshold, all of the integrated FETs, driver
charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the
AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)
register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the
CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
8.3.14.3 BUCK Undervoltage Lockout (BUCK_UV)
If at any time the voltage on VFB_BK pin falls lower than the VBK_UV threshold, the integrated FETs of the buck
regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally.
The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register
is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices.
Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK
undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or
an nSLEEP pin reset pulse (tRST).
8.3.14.4 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the
charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV
bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the
nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared
through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST). The CPUV protection is always enabled in both
hardware and SPI device varaints.
8.3.14.5 Overvoltage Protections (OV)
If at any time input supply voltage on the VM pins rises higher lower than the VOVP threshold voltage, all of the
integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high
in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)
when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
reset pulse (tRST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. On hardware
interface devices, the OVP protection is always enabled and set to a 32-V threshold.
The OVP threshold is also programmable on the SPI device variant. The OVP threshold can be set to 20-V or
32-V based on the OVP_SEL bit.
VVM
VOVP (max) rising
VOVP (min) rising
VOVP (max) falling
VOVP (min) falling
DEVICE ON
DEVICE OFF
DEVICE ON
nFAULT
Time
Figure 8-41. Over Voltage Protection
8.3.14.6 Overcurrent Protection (OCP)
A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a
FET exceeds the IOCP threshold for longer than the tOCP deglitch time, an OCP event is recognized and action is
done according to the OCP_MODE bit. On hardware interface devices, the IOCP threshold is set via OCP/SR pin,
the tOCP_DEG is fixed at 0.2-µs, and the OCP_MODE bit is configured for 5-ms automatic retry. On SPI devices,
the IOCP threshold is set through the OCP_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI
register, and the OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP automatic
retry, OCP report only, and OCP disabled.
8.3.14.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,
and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver
operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Peak Current due
to deglitch time
IOCP
IOUTx
tOCP
nFAULT Released
nFAULT Pulled High
Fault Condition
nFAULT
Clear Fault
Time
Figure 8-42. Overcurrent Protection - Latched Shutdown Mode
8.3.14.6.2 OCP Automatic Retry (OCP_MODE = 01b)
After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,
and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tRETRY time elapses. After the tRETRY
time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is
issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
Peak Current due
to deglitch time
IOCP
IOUTx
tRETRY
tOCP
nFAULT Released
nFAULT Pulled High
Fault Condition
nFAULT
Time
Figure 8-43. Overcurrent Protection - Automatic Retry Mode
8.3.14.6.3 OCP Report Only (OCP_MODE = 10b)
No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the
nFAULT pin low and latching the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. The
DRV8316 continues to operate as usual. The external controller manages the overcurrent condition by acting
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
appropriately. The reporting clears (nFAULT pin is released) when the OCP condition clears and a clear faults
command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
8.3.14.6.4 OCP Disabled (OCP_MODE = 11b)
No action occurs after a OCP event in this mode.
8.3.14.7 Buck Overcurrent Protection
A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the
current across the buck regulator FET exceeds the IBK_OCP threshold for longer than the tBK_OCP deglitch time,
an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after a
buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low. The
FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tBK_RETRY time elapses. The FAULT,
BK_FLT, and BUCK_OCP bits stay latched until the tRETRY period expires.
8.3.14.8 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OT bit in the IC status (IC_STAT)
register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by
setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device
performs no additional action and continues to function. In this case, the nFAULT pin releases when the die
temperature decreases below the hysteresis point of the thermal warning (TOTW_HYS). The OTW bit remains set
until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST) and the die temperature is lower than
thermal warning trip (TOTW).
Note
Over temperature warning is not reported on nFAULT pin by default.
8.3.14.9 Thermal Shutdown (OTS)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTS), all the FETs are disabled, the
charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in the IC status
(IC_STAT) register and OTS bit in the status register is set. Normal operation starts again (driver operation and
the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays latched high
indicating that a thermal event occurred until a clear fault command is issued either through the CLR_FLT bit or
an nSLEEP reset pulse (tRST). This protection feature cannot be disabled.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.4 Device Functional Modes
8.4.1 Functional Modes
8.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the DRV8316 family of devices. When the nSLEEP pin is low, the device
goes to a low-power sleep mode. In sleep mode, all FETs are disabled, sense amplifiers are disabled, buck
regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled, and the SPI bus
is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device goes to sleep
mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The tWAKE time must
elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all MOSFETs are disabled.
Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low
as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the
tSLEEP or tWAKE time.
8.4.1.2 Operating Mode
When the nSLEEP pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge
pump, AVDD regulator, buck regulator, and SPI bus are active.
8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
In the case of device latched faults, the DRV8316 family of devices goes to a partial shutdown state to help
protect the power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT
SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP reset
pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence
should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset
pulse has no effect on any of the regulators, device settings, or other functional blocks.
8.4.2 DRVOFF functionality
When DRVOFF pin is high, all six MOSFETs are disabled. If nSLEEP is high when the DRVOFF pin is high, the
charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults such as OCP
will be inactive.
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.5 SPI Communication
8.5.1 Programming
On DRV8316 SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit
word, with a 8 bits of status information (STAT register) and 8-bit register data.
A valid frame must meet the following conditions:
•
•
•
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
•
Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
•
•
•
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
•
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit status data.
The SPI registers are reset to the default settings on power up and when the device is enters sleep mode
8.5.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
•
1 read or write bit, W (bit B15)
6 address bits, A (bits B14 through B9)
Parity bit, P (bit B8)
8 data bits, D (bits B7 through B0)
The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the
register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
nSCS
A1
S1
D1
R1
SDI
SDO
Figure 8-44.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Master Controller
Device
MCLK
MO
MI
SCLK
SDI
SPI
Communication
SDO
SPI
Communication
nSCS
CS
Figure 8-45.
Table 8-8. SDI Input Data Word Format
R/W
ADDRESS
Parity
DATA
DATA
B15
W0
B14
A5
B13
A4
B12
A3
B11
A2
B10
A1
B9
A0
B8
P
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
Table 8-9. SDO Output Data Word Format
STATUS
B15
S7
B14
S6
B13
S5
B12
S4
B11
S3
B10
S2
B9
S1
B8
S0
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
nSCS
SCLK
SDI
X
Z
MSB
MSB
LSB
LSB
X
Z
SDO
Capture
Point
Propagate
Point
Figure 8-46. SPI Slave Timing Diagram
8.6 Register Map
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.1 STATUS Registers
Table 8-10 lists the STATUS registers. All register offset addresses not listed in Table 8-10 should be considered
as reserved locations and the register contents should not be modified.
Status Configuration
Table 8-10. STATUS Registers
Address
0x0
Acronym
IC_Status_
Status__1
Status__2
Register Name
IC Status Register
Status Register 1
Status Register 2
Section
Go
0x1
Go
0x2
Go
Complex bit access types are encoded to fit into small table cells. Table 8-11 shows the codes that are used for
access types in this section.
Table 8-11. STATUS Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
R-0
R
Read
-0
Returns 0s
Reset or Default Value
- n
Value after reset or the default value
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.1.1 IC_Status_ Register (Address = 0x0) [Reset = 0x0]
IC_Status_ is shown in Table 8-12.
Return to the Summary Table.
Table 8-12. IC_Status_ Register Field Descriptions
Bit
Field
Type
Reset
Description
6
BK_FLT
R
0x0
Buck Fault Bit
0x0 = No buck regulator fault condition is detected
0x1 = Buck regulator fault condition is detected
5
4
3
2
1
0
SPI_FLT
OCP
R
R
R
R
R
R
0x0
0x0
0x0
0x0
0x0
0x0
SPI Fault Bit
0x0 = No SPI fault condition is detected
0x1 = SPI Fault condition is detected
Over Current Protection Status Bit
0x0 = No overcurrent condition is detected
0x1 = Overcurrent condition is detected
NPOR
OVP
Supply Power On Reset Bit
0x0 = Power on reset condition is detected on VM
0x1 = No power-on-reset condition is detected on VM
Supply Overvoltage Protection Status Bit
0x0 = No overvoltage condition is detected on VM
0x1 = Overvoltage condition is detected on VM
OT
Overtemperature Fault Status Bit
0x0 = No overtemperature warning / shutdown is detected
0x1 = Overtemperature warning / shutdown is detected
FAULT
Device Fault Bit
0x0 = No fault condition is detected
0x1 = Fault condition is detected
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.1.2 Status__1 Register (Address = 0x1) [Reset = 0x0]
Status__1 is shown in Table 8-13.
Return to the Summary Table.
Table 8-13. Status__1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTW
R
0x0
Overtemperature Warning Status Bit
0x0 = No overtemperature warning is detected
0x1 = Overtemperature warning is detected
6
5
4
3
2
1
0
OTS
R
R
R
R
R
R
R
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Overtemperature Shutdown Status Bit
0x0 = No overtemperature shutdown is detected
0x1 = Overtemperature shutdown is detected
OCP_HC
OCL_LC
OCP_HB
OCP_LB
OCP_HA
OCP_LA
Overcurrent Status on High-side switch of OUTC
0x0 = No overcurrent detected on high-side switch of OUTC
0x1 = Overcurrent detected on high-side switch of OUTC
Overcurrent Status on Low-side switch of OUTC
0x0 = No overcurrent detected on low-side switch of OUTC
0x1 = Overcurrent detected on low-side switch of OUTC
Overcurrent Status on High-side switch of OUTB
0x0 = No overcurrent detected on high-side switch of OUTB
0x1 = Overcurrent detected on high-side switch of OUTB
Overcurrent Status on Low-side switch of OUTB
0x0 = No overcurrent detected on low-side switch of OUTB
0x1 = Overcurrent detected on low-side switch of OUTB
Overcurrent Status on High-side switch of OUTA
0x0 = No overcurrent detected on high-side switch of OUTA
0x1 = Overcurrent detected on high-side switch of OUTA
Overcurrent Status on Low-side switch of OUTA
0x0 = No overcurrent detected on low-side switch of OUTA
0x1 = Overcurrent detected on low-side switch of OUTA
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.1.3 Status__2 Register (Address = 0x2) [Reset = 0x0]
Status__2 is shown in Table 8-14.
Return to the Summary Table.
Table 8-14. Status__2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
OTP_ERR
R
0x0
Reserved
6
R
0x0
One Time Programmabilty Error
0x0 = No OTP error is detected
0x1 = OTP Error is detected
5
4
3
2
1
0
BUCK_OCP
BUCK_UV
R
0x0
0x0
0x0
0x0
0x0
0x0
Buck Regulator Overcurrent Staus Bit
0x0 = No buck regulator overcurrent is detected
0x1 = Buck regulator overcurrent is detected
R
Buck Regulator Undervoltage Staus Bit
0x0 = No buck regulator undervoltage is detected
0x1 = Buck regulator undervoltage is detected
VCP_UV
R
Charge Pump Undervoltage Status Bit
0x0 = No charge pump undervoltage is detected
0x1 = Charge pump undervoltage is detected
SPI_PARITY
SPI_SCLK_FLT
SPI_ADDR_FLT
R-0
R
SPI Parity Error Bit
0x0 = No SPI parity error is detected
0x1 = SPI parity error is detected
SPI Clock Framing Error Bit
0x0 = No SPI clock framing error is detected
0x1 = SPI clock framing error is detected
R
SPI Address Error Bit
0x0 = No SPI address fault is detected (due to accessing non-user
register)
0x1 = SPI address fault is detected
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2 CONTROL Registers
Table 8-15 lists the CONTROL registers. All register offset addresses not listed in Table 8-15 should be
considered as reserved locations and the register contents should not be modified.
Control Configuration
Table 8-15. CONTROL Registers
Address
0x3
Acronym
Register Name
Section
Go
Control__1
Control__2
Control__3
Control__4
Control__5
Control__6
Control__10
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Control Register 5
Control Register 6
Control Register 10
0x4
Go
0x5
Go
0x6
Go
0x7
Go
0x8
Go
0xC
Go
Complex bit access types are encoded to fit into small table cells. Table 8-16 shows the codes that are used for
access types in this section.
Table 8-16. CONTROL Access Type Codes
Access Type
Read Type
R
Code
R
Description
Read
Write Type
W
W
Write
W1C
W
Write
1C
1 to clear
WAPU
W
Write
APU
Atomic write with password unlock
Reset or Default Value
- n
Value after reset or the default value
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.1 Control__1 Register (Address = 0x3) [Reset = 0x11]
Control__1 is shown in Table 8-17.
Return to the Summary Table.
Table 8-17. Control__1 Register Field Descriptions
Bit
7-3
2-0
Field
Type
Reset
Description
RESERVED
REG_LOCK
R
0x2
Reserved
R/WAPU
0x1
Register Lock Bits
0x0 = No effect unless locked or unlocked
0x1 = No effect unless locked or unlocked
0x2 = No effect unless locked or unlocked
0x3 = Write 011b to this register to unlock all registers
0x4 = No effect unless locked or unlocked
0x5 = No effect unless locked or unlocked
0x6 = Write 110b to lock the settings by ignoring further register
writes except to these bits and address 0x03h bits 2-0.
0x7 = No effect unless locked or unlocked
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.2 Control__2 Register (Address = 0x4) [Reset = 0x18]
Control__2 is shown in Table 8-18.
Return to the Summary Table.
Table 8-18. Control__2 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
SDO_MODE
R
0x0
Reserved
R/W
0x0
SDO Mode Setting
0x0 = SDO IO in Open Drain Mode
0x1 = SDO IO in Push Pull Mode
4-3
2-1
0
SLEW
R/W
R/W
W1C
0x3
0x0
0x0
Slew Rate Settings
0x0 = Slew rate is 25 V/µs
0x1 = Slew rate is 50 V/µs
0x2 = Slew rate is 150 V/µs
0x3 = Slew rate is 200 V/µs
PWM_MODE
CLR_FLT
Device Mode Selection
0x0 = 6x mode
0x1 = 6x mode with current limit
0x2 = 3x mode
0x3 = 3x mode with current limit
Clear Fault
0x0 = No clear fault command is issued
0x1 = To clear the latched fault bits. This bit automatically resets after
being written.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.3 Control__3 Register (Address = 0x5) [Reset = 0x0]
Control__3 is shown in Table 8-19.
Return to the Summary Table.
Table 8-19. Control__3 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
Reserved
Reserved
RESERVED
RESERVED
RESERVED
PWM_100_DUTY_SEL
R
0x0
6
R
0x0
5
R
0x0
4
R/W
0x0
Freqency of PWM at 100% Duty Cycle
0x0 = 20KHz
0x1 = 40KHz
3
2
1
0
OVP_SEL
OVP_EN
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
Overvoltage Level Setting
0x0 = VM overvoltage level is 32-V
0x1 = VM overvoltage level is 20-V
Overvoltage Enable Bit
0x0 = Overvoltage protection is disabled
0x1 = Overvoltage protection is enabled
SPI_FLT_REP
OTW_REP
SPI Fault Reporting Disable Bit
0x0 = SPI fault reporting on nFAULT pin is enabled
0x1 = SPI fault reporting on nFAULT pin is disabled
Overtemperature Warning Reporting Bit
0x0 = Over temperature reporting on nFAULT is disabled
0x1 = Over temperature reporting on nFAULT is enabled
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.4 Control__4 Register (Address = 0x6) [Reset = 0x1]
Control__4 is shown in Table 8-20.
Return to the Summary Table.
Table 8-20. Control__4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DRV_OFF
R/W
0x0
Driver OFF Bit
0x0 = No Action
0x1 = Enter Low Power Standby Mode
6
OCP_CBC
OCP_DEG
R/W
R/W
0x0
0x0
OCP PWM Cycle Operation Bit
0x0 = OCP clearing in PWM input cycle change is disabled
0x1 = OCP clearing in PWM input cycle change is enabled
5-4
OCP Deglitch Time Settings
0x0 = OCP deglitch time is 0.2 µs
0x1 = OCP deglitch time is 0.6 µs
0x2 = OCP deglitch time is 1.1 µs
0x3 = OCP deglitch time is 1.6 µs
3
2
OCP_RETRY
OCP_LVL
R/W
R/W
R/W
0x0
0x0
0x1
OCP Retry Time Settings
0x0 = OCP retry time is 5 ms
0x1 = OCP retry time is 500 ms
Overcurrent Level Setting
0x0 = OCP level is 16 A
0x1 = OCP level is 24 A
1-0
OCP_MODE
OCP Fault Options
0x0 = Overcurrent causes a latched fault
0x1 = Overcurrent causes an automatic retrying fault
0x2 = Overcurrent is report only but no action is taken
0x3 = Overcurrent is not reported and no action is taken
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
65
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.5 Control__5 Register (Address = 0x7) [Reset = 0x0]
Control__5 is shown in Table 8-21.
Return to the Summary Table.
Table 8-21. Control__5 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
ILIM_RECIR
R
0x0
Reserved
6
R/W
0x0
Current Limit Recirculation Settings
0x0 = Current recirculation through FETs (Brake Mode)
0x1 = Current recirculation through diodes (Coast Mode)
5
4
3
RESERVED
RESERVED
EN_AAR
R
0x0
0x0
0x0
Reserved
Reserved
R
R/W
Active Asynshronous Rectification Enable Bit
0x0 = AAR mode is disabled
0x1 = AAR mode is enabled
2
EN_ASR
R/W
R/W
0x0
0x0
Active Synchronous Rectification Enable Bit
0x0 = ASR mode is disabled
0x1 = ASR mode is enabled
1-0
CSA_GAIN
Current Sense Amplifier's Gain Settings
0x0 = CSA gain is 0.15 V/A
0x1 = CSA gain is 0.1875 V/A
0x2 = CSA gain is 0.25 V/A
0x3 = CSA gain is 0.375 V/A
Copyright © 2021 Texas Instruments Incorporated
66
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.6 Control__6 Register (Address = 0x8) [Reset = 0x0]
Control__6 is shown in Table 8-22.
Return to the Summary Table.
Table 8-22. Control__6 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
Reserved
Reserved
RESERVED
RESERVED
BUCK_PS_DIS
R
0x0
R
0x0
4
R/W
0x0
Buck Power Sequencing Disable Bit
0x0 = Buck power sequencing is enabled
0x1 = Buck power sequencing is disabled
3
BUCK_CL
R/W
R/W
0x0
0x0
Buck Current Limit Setting
0x0 = Buck regulator current limit is set to 600 mA
0x1 = Buck regulator current limit is set to 150 mA
2-1
BUCK_SEL
Buck Voltage Selection
0x0 = Buck voltage is 3.3 V
0x1 = Buck voltage is 5.0 V
0x2 = Buck voltage is 4.0 V
0x3 = Buck voltage is 5.7 V
0
BUCK_DIS
R/W
0x0
Buck Disable Bit
0x0 = Buck regulator is enabled
0x1 = Buck regulator is disabled
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
67
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
8.6.2.7 Control__10 Register (Address = 0xC) [Reset = 0x0]
Control__10 is shown in Table 8-23.
Return to the Summary Table.
Table 8-23. Control__10 Register Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
RESERVED
DLYCMP_EN
R
0x0
Reserved
R/W
0x0
Driver Delay Compensation enable
0x0 = Disable
0x1 = Enable
3-0
DLY_TARGET
R/W
0x0
Delay Target for Driver Delay Compensation
0x0 = 0 us
0x1 = 0.4 us
0x2 = 0.6 us
0x3 = 0.8 us
0x4 = 1 us
0x5 = 1.2 us
0x6 = 1.4 us
0x7 = 1.6 us
0x8 = 1.8 us
0x9 = 2 us
0xA = 2.2 us
0xB = 2.4 us
0xC = 2.6 us
0xD = 2.8 us
0xE = 3 us
0xF = 3.2 us
Copyright © 2021 Texas Instruments Incorporated
68
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The DRV8316 can be used to drive Brushless-DC motors. The following design procedure can be used to
configure the DRV8316.
VVM
+
10 nF
CPL
1 µF
VM
0.1 µF
10 µF
0.1 µF
CPH
CP
VCC
Voltage
Supervisor
VREF
AVDD
Microcontroller
CAVDD
AGND
ADC
ADC
SOC
SOB
SOA
Replace Inductor (LBK) with Resistor
(RBK) for larger external load or to
reduce power dissipation
Current
Sensing
CSA
ADC
ADC
LBK
External
Load
SW_BK
RBK
RPU1
CBK
DRV8316R
GND_BK
nFAULT
GP-I
FB_BK
nSLEEP
DRVOFF
GP-O
Driver
Control
GP-O
INHA
INLA
INHB
INLB
INHC
INLC
GP-O
GP-O
PWM
Control
Module
PWM
Control
Input
Hall
Sensors
(Optional)
OUTA
OUTB
GP-O
GP-O
GP-O
GP-O
A
B
B
SDO
GP-I
GP-O
GP-O
GP-O
nSCS
SCLK
SPI
SPI
OUTC
PGND
SDI
Hall Input
GP-I
GP-I
GP-I
Figure 9-1. Primary Application Schematics
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
69
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
9.2 Typical Applications
9.2.1 Three-Phase Brushless-DC Motor Control
In this application, the DRV8316 is used to drive a Brushless-DC motor
9.2.1.1 Detailed Design Procedure
Table 9-1lists the example input parameters for the system design.
Table 9-1. Design Parameters
DESIGN PARAMETERS
Supply voltage
REFERENCE
EXAMPLE VALUE
VVM
IRMS
IPEAK
fPWM
SR
24 V
3 A
Motor RMS current
Motor peak current
8 A
PWM Frequency
50 kHz
200 V/µs
3.3 V
Slew Rate Setting
Buck regulator output voltage
ADC reference voltage
System ambient temperature
VBK
VVREF
TA
3.0 V
–20°C to +105°C
9.2.1.1.1 Motor Voltage
Brushless-DC motors are typically rated for a certain voltage (for example 12 V and 24 V). Operating a motor at
a higher voltage corresponds to a lower drive current to obtain the same motor power. A higher operating
voltage also corresponds to a higher obtainable rpm. DRV8316 device allows for the use of higher operating
voltage because of a maximum VM rating of 40 V.
Operating at lower voltages generally allows for more accurate control of phase currents. The DRV8316
functions down to a supply of 4.5V.
9.2.1.2 Application Curves
TBD
Graph Placeholder
Graph Placeholder
C00
C00
Figure 9-2. App Curve-1
Figure 9-3. App Curve-2
Copyright © 2021 Texas Instruments Incorporated
70
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
9.2.2 Three-Phase Brushless-DC Motor Control With Current Limit
In this application, the DRV8316 is used to drive a brushless-DC motor with current limit.
9.2.2.1 Detailed Design Procedure
Table 9-1lists the example input parameters for the system design.
Table 9-2. Design Parameters
DESIGN PARAMETERS
Supply voltage
REFERENCE
VVM
EXAMPLE VALUE
24 V
5 A
Motor RMS current
Motor peak current
Motor resistance
IRMS
IPEAK
8 A
RMOTOR
LMOTOR
fPWM
Motor inductance
PWM Frequency
50 kHz
Slew Rate Setting
SR
200 V/µs
Rise and Fall Time
tRISE, tFALL
VBK
VVREF
TA
Buck regulator output voltage
ADC reference voltage
System ambient temperature
3.3 V
3.0 V
–20°C to +105°C
9.2.2.1.1 Motor Voltage
Brushless-DC motors are typically rated for a certain voltage (for example 12 V and 24 V). Operating a motor at
a higher voltage corresponds to a lower drive current to obtain the same motor power. A higher operating
voltage also corresponds to a higher obtainable rpm. DRV8316 device allows for the use of higher operating
voltage because of a maximum VM rating of 40 V.
Operating at lower voltages generally allows for more accurate control of phase currents. The DRV8316
functions down to a supply of 4.5V.
9.2.2.2 Application Curves
TBD
Graph Placeholder
Graph Placeholder
C00
C00
Figure 9-4. Device Powerup with VM
Figure 9-5. Device Powerup with nSLEEP
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
71
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
Graph Placeholder
Graph Placeholder
C00
C00
Figure 9-6. Power Management
Figure 9-7. Driver PWM Operation with Current
Feedback
Copyright © 2021 Texas Instruments Incorporated
72
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
9.2.3 Brushed-DC and Solenoid Load
9.2.3.1 Design Requirements
Table 9-3 gives design input parameters for system design.
Table 9-3. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Brushed motor rms current
IRMS, BDC
1.0 A
2.0 A
0.5 A
1.0 A
Brushed motor peak current
Solenoid rms current
IPEAK, BDC
IRMS, SOL
Solenoid peak current
IPEAK, SOL
9.2.3.1.1 Detailed Design Procedure
Table 9-4. Brushed-DC Control
Function
IN1
EN1
IN2
EN2
OUT1
OUT2
Forward
Reverse
1
0
1
1
0
1
1
1
H
L
L
H
L
Brake (low-side slow
decay)
0
1
0
1
L
High-side slow decay
Coast
1
1
0
1
1
0
H
Z
H
Z
X
X
Table 9-5. Solenoid Control (High-Side Load)
Function
IN3
EN3
OUT3
Coast / Off
On
X
0
1
0
1
1
Z
L
Brake
H
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
73
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
9.2.4 Three Solenoid Loads
9.2.4.1 Design Requirements
Table 9-6 gives design input parameters for system design.
Table 9-6. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Solenoid rms current
IRMS, SOL
1.0 A
1.5 A
Solenoid peak current
IPEAK, SOL
9.2.4.1.1 Detailed Design Procedure
Table 9-7. Solenoid Control (high-side load)
Function
IN2
EN2
OUT2
Coast / Off
On
X
0
1
0
1
1
Z
L
Brake
H
Table 9-8. Solenoid Control (low-side load)
Function
IN1
EN1
OUT1
Coast / Off
On
X
1
0
0
1
1
Z
H
L
Brake
Copyright © 2021 Texas Instruments Incorporated
74
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
10 Power Supply Recommendations
10.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The capacitance and current capability of the power supply
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed dc, brushless DC, stepper)
The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
75
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
11 Layout
11.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed
closely to device pins.
The high-current device outputs should use wide metal traces.
To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,
grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage
circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the
device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to
reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the I2 × RDS(on) heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve theremal dissipation from the die surface.
Separate the SW_BUCK and FB_BUCK traces with ground separation to reduce buck switching from coupling
as noise into the buck outer feedback loop. Widen the FB_BUCK trace as much as possible to allow for faster
load switching.
Recommended Layout Example for VQFN Package shows a layout example for the DRV8316.
Copyright © 2021 Texas Instruments Incorporated
76
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
11.2 Layout Example
Recommended Layout Example for VQFN Package
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
77
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
11.3 Thermal Considerations
The DRV8316 has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C
(minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
11.3.1 Power Dissipation
The power dissipated in the output FET resistance, or RDS(on) dominates power dissipation in the DRV8316. A
rough estimate of average power dissipation of each half-H-bridge when running a static load is:
At start-up and fault conditions, this current is much higher than normal running current; remember to take these
peak currents and their duration into consideration.
The total device dissipation is the power dissipated in each of the three half-H-bridges added together.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this
into consideration when sizing the heatsink.
Copyright © 2021 Texas Instruments Incorporated
78
Submit Document Feedback
DRV8316
SLVSF16 – JANUARY 2021
www.ti.com
12 Device and Documentation Support
12.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
79
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8316RRGFR
DRV8316TRGFR
PDRV8316RRGFR
PREVIEW
PREVIEW
ACTIVE
VQFN
VQFN
VQFN
RGF
RGF
RGF
40
40
40
3000
3000
3000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2021
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明