DRV8701_15 [TI]
DRV8701 Brushed DC Motor Full-Bridge Gate Driver;
| 型号： | DRV8701_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8701 Brushed DC Motor Full-Bridge Gate Driver 栅 |
| 文件： | 总42页 (文件大小：1761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV8701
SLVSCX5B –MARCH 2015–REVISED JULY 2015
DRV8701 Brushed DC Motor Full-Bridge Gate Driver
1 Features
2 Applications
1
•
Single H-Bridge Gate Driver
•
•
•
•
•
•
Industrial Brushed-DC Motors
Robotics
–
–
Drives Four External N-Channel MOSFETs
Supports 100% PWM Duty Cycle
Home Automation
Industrial Pumps and Valves
Power Tools
•
•
5.9-V to 45-V Operating Supply Voltage Range
Two Control Interface Options
Handheld Vacuum Cleaners
–
–
PH/EN (DRV8701E)
PWM (DRV8701P)
3 Description
The DRV8701 is a single H-bridge gate driver that
uses four external N-channel MOSFETs targeted to
drive a 12-V to 24-V bidirectional brushed DC motor.
•
Adjustable Gate Drive (5 Levels)
–
–
6-mA to 150-mA Source Current
12.5-mA to 300-mA Sink Current
•
•
•
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Current Shunt Amplifier (20 V/V)
A
PH/EN (DRV8701E) or PWM (DRV8701P)
interface allows simple interfacing to controller
circuits. An internal sense amplifier allows for
adjustable current control. The gate driver includes
circuitry to regulate the winding current using fixed
off-time PWM current chopping.
Integrated PWM Current Regulation
–
Limits Motor Inrush Current
•
•
Low-Power Sleep Mode (9 μA)
Two LDO Voltage Regulators to Power External
Components
DRV8701 drives both high- and low-side FETs with
9.5-V VGS gate drive. The gate drive current for all
external FETs is configurable with a single external
resistor on the IDRIVE pin.
–
–
AVDD: 4.8 V, up to 30-mA Output Load
DVDD: 3.3 V, up to 30-mA Output Load
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very-low quiescent
current draw. This sleep mode can be set by taking
the nSLEEP pin low.
•
•
Small Package and Footprint
–
–
24-Pin VQFN (PowerPAD™)
4.0 × 4.0 × 0.9 mm
Protection Features:
Internal
undervoltage
overcurrent
protection
functions
charge
are
pump
provided:
faults,
–
–
–
–
–
–
VM Undervoltage Lockout (UVLO)
Charge Pump Undervoltage (CPUV)
Overcurrent Protection (OCP)
Pre-Driver Fault (PDF)
lockout,
shutdown,
short-circuit
protection,
predriver faults, and overtemperature. Fault
conditions are indicated on the nFAULT pin.
Device Information(1)
Thermal Shutdown (TSD)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
Fault Condition Output (nFAULT)
DRV8701
VQFN (24)
4.00 × 4.00 x 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Gate-Drive Current
tDRIVE
Simplified System Block Diagram
IHOLD
High-side
gate drive
5.9V to 45 V
IHOLD
IHOLD
current
DRV8701
High-side
VGS
PH/EN or PWM
nSLEEP
Gate
drive
FETs
M
H-Bridge Gate
Driver
tDRIVE
VREF
Controller
IHOLD
IHOLD
Low-side
gate drive
current
sense
sense output
nFAULT
Shunt Amp
Protection
LDO
IHOLD
Low-side
VGS
3.3 & 4.8 V
30 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8701
SLVSCX5B –MARCH 2015–REVISED JULY 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Applications ............................................... 28
Power Supply Recommendations...................... 32
9.1 Bulk Capacitance Sizing ......................................... 32
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1 Documentation Support ........................................ 34
11.2 Community Resources.......................................... 34
11.3 Trademarks........................................................... 34
11.4 Electrostatic Discharge Caution............................ 34
11.5 Glossary................................................................ 34
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2015) to Revision B
Page
•
Updated test conditions for IDRIVE,SNK and corrected TYP values ........................................................................................... 8
Changes from Original (March 2015) to Revision A
Page
•
Updated device status to production data ............................................................................................................................. 1
2
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SLVSCX5B –MARCH 2015–REVISED JULY 2015
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
DRV8701E Top View
RGE Package
24-Pin VQFN
DRV8701P Top View
1
2
3
4
5
6
18
17
16
15
14
13
1
2
3
4
5
6
18
VM
VCP
SH1
GH1
GND
PH
VM
VCP
SH1
17
GH1
16
GND
GND
CPH
CPL
CPH
CPL
GND
IN1
(PPAD)
(PPAD)
15
14
13
GND
VREF
EN
GND
VREF
IN2
nSLEEP
nSLEEP
DRV8701E (PH/EN)
PIN
PIN
PIN
TYPE
DESCRIPTION
NAME
EN
PH
NO.
14
Input
Input
Bridge enable input
Bridge phase input
Logic low places the bridge in brake mode; see Table 1
Controls the direction of the H-bridge; see Table 1
15
DRV8701P (PWM)
TYPE
DESCRIPTION
NAME
NO.
15
IN1
IN2
Input
Input
Bridge PWM input
Logic controls the state of H-bridge; see Table 2
14
Common Pins
TYPE
DESCRIPTION
NAME
NO.
Connect to motor supply voltage; bypass to GND with a 0.1-µF
ceramic plus a 10-µF minimum capacitor rated for VM; additional
capacitance may be required based on drive current
VM
1
Power
Power supply
Device ground
5
GND
16
Power
Must be connected to ground
PPAD
VCP
CPH
CPL
2
3
4
Power
Power
Charge pump output
Connect a 16-V, 1-µF ceramic capacitor to VM
Connect a 0.1-µF X7R capacitor rated for VM between CPH and
CPL
Charge pump switching nodes
3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
DVDD
8
7
Power
Power
Input
Logic regulator
4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
AVDD
Analog regulator
Pull logic low to put device into a low-power sleep mode with FETs
High-Z; internal pulldown
nSLEEP
IDRIVE
13
12
Device sleep mode
Gate drive current setting pin
Resistor value or voltage forced on this pin sets the gate drive
current; see applications section for more details
Input
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Common Pins (continued)
PIN
TYPE
DESCRIPTION
NAME
VREF
NO.
Controls the current regulation; apply a voltage between 0.3 V and
AVDD
6
Input
Analog reference input
Fault indication pin
Open
Drain
Pulled logic low with fault condition; open-drain output requires an
external pullup
nFAULT
9
Open
Drain
Pulled logic low when the drive current hits the current chopping
threshold; open-drain output requires an external pullup
SNSOUT
10
Sense comparator output
Shunt amplifier output
Voltage on this pin is equal to the SP voltage times AV plus an
offset; place no more than 1 nF of capacitance on this pin
SO
SN
SP
11
20
21
Output
Input
Shunt amplifier negative input Connect to SP through current sense resistor and to GND
Connect to low-side FET source and to SN through current sense
Input
Shunt amplifier positive input
resistor
GH1
GH2
GL1
GL2
SH1
SH2
17
24
19
22
18
23
Output
Output
Input
High-side gate
Low-side gate
Phase node
Connect to high-side FET gate
Connect to low-side FET gate
Connect to high-side FET source and low-side FET drain
External Passive Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
0.1-µF ceramic capacitor rated for VM
≥10-µF capacitor rated for VM
16-V, 1-µF ceramic capacitor
0.1-µF X7R capacitor rated for VM
6.3-V, 1-µF ceramic capacitor
6.3-V, 1-µF ceramic capacitor
See Typical Applications for resistor sizing
≥10-kΩ pullup
CVM1
CVM2
CVCP
CSW
VM
GND
GND
VM
VM
VCP
CPH
CPL
CDVDD
CAVDD
DVDD
AVDD
IDRIVE
VCC(1)
VCC(1)
SP
GND
GND
GND
nFAULT
RIDRIVE
RnFAULT
RSNSOUT
RSENSE
SNSOUT
SN/GND
≥10-kΩ pullup
Optional low-side sense resistor
(1) VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The
system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD.
External FETs
Component
QHS1
Gate
GH1
GL1
GH2
GL2
Drain
VM
Source
Recommended
SH1
QLS1
SH1
VM
SP or GND
SH2
Supports up to 200-nC FETs at 40-kHz PWM; see
Detailed Design Procedure for more details
QHS2
QLS2
SH2
SP or GND
4
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SLVSCX5B –MARCH 2015–REVISED JULY 2015
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN
MAX
47
UNIT
V
Power supply voltage (VM)
–0.3
0
Power supply voltage ramp rate (VM)
2
V/µs
V
Charge pump voltage (VCP, CPH)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1.2
–2.0
–0.3
–0.5
–1
VM + 12
VM
Charge pump negative switching pin (CPL)
Internal logic regulator voltage (DVDD)
V
3.8
V
Internal analog regulator voltage (AVDD)
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT)
High-side gate pin voltage (GH1, GH2)
5.75
5.75
VM + 12
VM + 1.2
VM + 2
12
V
V
V
Continuous phase node pin voltage (SH1, SH2)
Pulsed 10 µs phase node pin voltage (SH1, SH2)
Low-side gate pin voltage (GL1, GL2)
V
V
V
Continuous shunt amplifier input pin voltage (SP, SN)
Pulsed 10-µs shunt amplifier input pin voltage (SP, SN)
Shunt amplifier output pin voltage (SO)
1
V
1
V
–0.3
0
5.75
10
V
Open-drain output current (nFAULT, SNSOUT)
Gate pin source current (GH1, GL1, GH2, GL2)
Gate pin sink current (GH1, GL1, GH2, GL2)
Shunt amplifier output pin current (SO)
mA
mA
mA
mA
°C
°C
0
250
0
500
0
5
Operating junction temperature, TJ
–40
–65
150
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM) ESD stress voltage(1)
Charged device model (CDM) ESD stress voltage(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
45
UNIT
VM
Power supply voltage range
5.9
0
V
V
VCC
VREF
ƒPWM
IAVDD
IDVDD
ISO
Logic level input voltage
5.5
Reference RMS voltage range (VREF)
Applied PWM signal (PH/EN or IN1/IN2)
AVDD external load current
0.3(1)
AVDD
100
30(2)
30(2)
5
V
kHz
mA
mA
mA
°C
DVDD external load current
Shunt amplifier output current loading (SO)
Operating ambient temperature
TA
–40
125
(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded
(2) Power dissipation and thermal limits must be observed
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6.4 Thermal Information
DRV8701
RGE (VQFN)
24 PINS
34.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
37.1
12.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
12.2
RθJC(bot)
3.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
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SLVSCX5B –MARCH 2015–REVISED JULY 2015
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VM
IVM
VM operating voltage
5.9
45
9.5
15
25
100
1
V
VM operating supply current
VM = 24 V; nSLEEP high
6
9
mA
TA = 25°C
TA = 125°C(1)
nSLEEP = 0
VM = 24 V
IVMQ
VM sleep mode supply current
μA
14
tSLEEP
tWAKE
tON
Sleep time
nSLEEP low to sleep mode
nSLEEP high to output change
VM > UVLO to output transition
External load 0 to 30 mA
μs
ms
ms
V
Wake-up time
Turn-on time
1
DVDD
AVDD
Internal logic regulator voltage
Internal logic regulator voltage
3.0
4.4
3.3
4.8
3.5
5.2
External load 0 to 30 mA
V
CHARGE PUMP (VCP, CPH, CPL)
VM = 12 V; IVCP = 0 to 12 mA
VM = 8 V; IVCP = 0 to 10 mA
VM = 5.9 V; IVCP = 0 to 8 mA
VM > 12 V
20.5
13.5
9.4
12
21.5
14.4
9.9
22.5
15
VCP
VCP operating voltage
V
10.4
IVCP
Charge pump current capacity
8 V < VM < 12 V
10
mA
5.9 V < VM < 8 V
8
(1)
fVCP
Charge pump switching frequency VM > UVLO
200
400
700
0.8
kHz
CONTROL INPUTS (PH, EN, IN1, IN2, nSLEEP)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
V
V
1.5
100
–5
mV
μA
μA
kΩ
ns
VIN = 0 V
VIN = 5 V
5
78
IIH
RPD
tPD
64
115
500
173
PH/EN, IN1/IN2 to GHx/GLx
CONTROL OUTPUTS (nFAULT, SNSOUT)
VOL
IOZ
Output logic low voltage
IO = 2 mA
VIN = 5 V
0.1
2
V
Output high impedance leakage
–2
μA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VM > 12 V; VGHS with respect to SHx
8.5
5.5
3.5
8.5
3.9
9.5
6.4
4.0
9.3
4.3
10.5
7
High-side VGS gate drive (gate-to-
source)
VGHS
VM = 8 V; VGHS with respect to SHx
VM = 5.9 V; VGHS with respect to SHx
VM > 12 V
V
V
4.5
10.5
4.9
Low-side VGS gate drive (gate-to-
source)
VGLS
tDEAD
tDRIVE
VM = 5.9 V
Observed tDEAD depends on IDRIVE
setting
Output dead time
Gate drive time
380
ns
2.5
6
μs
RIDRIVE < 1 kΩ to GND
RIDRIVE = 33 kΩ ±5% to GND
12.5
RIDRIVE = 200 kΩ ±5% to GND, or
RIDRIVE < 1 kΩ to AVDD
IDRIVE,SRC Peak source current
25
mA
RIDRIVE > 500 kΩ ±5% to GND
RIDRIVE = 68 kΩ ±5% to AVDD
100
150
(1) Specified by design and characterization data
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
12.5
25
MAX
UNIT
RIDRIVE < 1 kΩ to GND
RIDRIVE = 33 kΩ ±5% to GND
RIDRIVE = 200 kΩ ±5% to GND, or
RIDRIVE < 1 kΩ to AVDD
IDRIVE,SNK Peak sink current
50
mA
RIDRIVE > 500 ±5% kΩ to GND
RIDRIVE = 68 kΩ ±5% to AVDD
Source current after tDRIVE
Sink current after tDRIVE
GHx
200
300
6
IHOLD
FET holding current
mA
mA
kΩ
25
490
690
200
150
ISTRONG
FET hold-off strong pulldown
FET gate hold-off resistor
GLx
Pulldown GHx to SHx
Pulldown GLx to GND
ROFF
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF
VREF input voltage
For current internal chopping
50 < VSP < 200 mV; VSN = GND
10 < VSP < 50 mV; VSN = GND
VSP = VSN = GND
0.3(2)
18
AVDD
22
V
20
20
AV
Amplifier gain
V/V
16
24
VOFF
ISP
SO offset
50
250
mV
SP input current
VSP = 100 mV; VSN = GND
-40
μA
VSP = VSN = GND to
VSP = 100 mV, VSN = GND
(3)
tSET
Settling time to ±1%
1.5
1
µs
(3)
CSO
tOFF
Allowable SO pin capacitance
PWM current regulation off-time
PWM blanking time
nF
µs
µs
25
2
tBLANK
PROTECTION CIRCUITS
VM falling; UVLO report
VM rising; UVLO recovery
Rising to falling threshold
VM falling; UVLO report
CPUV report
5.4
5.6
5.8
5.9
VUVLO
VM undervoltage lockout
V
VUVLO,HYS VM undervoltage hysteresis
100
mV
μs
V
tUVLO
VM UVLO falling deglitch time
Charge pump undervoltage
10
VCPUV
VM + 2.8
Overcurrent protection trip level,
VDS of each external FET
High-side FETs: VM – SHx
Low-side FETs: SHx – SP
VDS OCP
VSP OCP
0.8
0.8
1
1
V
V
Overcurrent protection trip level,
measured by sense amplifier
VSP voltage with respect to GND
tOCP
Overcurrent deglitch time
Overcurrent retry time
4.5
3
µs
ms
°C
°C
tRETRY
(3)
TTSD
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature, TJ
150
(3)
THYS
Die temperature, TJ
20
Positive clamping voltage
Negative clamping voltage
10.5
–1
13
VGS CLAMP Gate drive clamping voltage
V
–0.7
–0.5
(2) Operational at VREF = 0 to 0.3 V, but accuracy is degraded
(3) Specified by design and characterization data
8
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6.6 Typical Characteristics
6.5
6.4
6.3
6.2
6.1
6
6.15
6.1
TA = 125°C
TA = 85°C
TA = 25°C
TAꢀ ꢀ±ꢁꢂ&
VM = 24 V
VM = 12 V
6.05
6
5.95
5.9
5.85
5.8
5.9
5.8
5.7
5.6
5.5
5.75
5.7
5.65
5.6
5.55
5.5
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
Supply Voltage VM (V)
Ambient Temperature (°C)
D001
D002
Figure 1. Supply Current over VM
Figure 2. Supply Current over Temperature
20
18
16
14
12
10
8
16
15
14
13
12
11
10
9
TA = 125°C
TA = 85°C
TA = 25°C
TAꢀ ꢀ±ꢁꢂ&
VM = 24 V
VM = 12 V
8
7
6
6
4
5
2
4
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
Supply Voltage VM (V)
Ambient Temperature (°C)
D003
D004
Figure 3. Sleep Current over VM
Figure 4. Sleep Current over Temperature
12
4.6
4.5
4.4
4.3
4.2
4.1
4
VM = 12 V
VM = 10 V
VM = 8 V
TA = 125°C
TA = 85°C
TA = 25°C
TAꢀ ꢀ±ꢁꢂ&
11
10
9
VM = 5.9 V
8
7
3.9
3.8
3.7
3.6
3.5
3.4
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Load Current (mA)
D005
D006
Figure 5. VCP over Load (TA = 25°C)
Figure 6. VCP over Load (VM = 5.9 V)
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Typical Characteristics (continued)
3.295
3.29
4.875
4.85
3.285
3.28
4.825
4.8
3.275
3.27
4.775
4.75
3.265
3.26
3.255
3.25
4.725
4.7
3.245
3.24
TA = 125°C
TA = 85°C
TA = 25°C
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
TAꢀ ꢀ±ꢁꢂ&
4.675
4.65
3.235
3.23
4.625
3.225
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
Load Current (mA)
Load Current (mA)
D008
D007
Figure 8. AVDD Regulator over Load (VM = 12 V)
Figure 7. DVDD Regulator over Load (VM = 12 V)
55
52.5
50
20.1
19.9
19.7
19.5
19.3
19.1
18.9
18.7
18.5
18.3
47.5
45
42.5
40
37.5
35
32.5
30
27.5
25
SP = 225 mV
SP = 100 mV
SP = 50 mV
SP = 10 mV
22.5
20
VM = 24 V
VM = 12 V
17.5
15
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
D009
D010
Figure 9. SO Offset over Temperature
Figure 10. Amplifier Gain over Temperature
20
19.8
19.6
19.4
19.2
19
20
19.96
19.92
19.88
19.84
19.8
TA = 125°C
TA = 85°C
TA = 25°C
TAꢀ ꢀ±ꢁꢂ&
19.76
19.72
19.68
19.64
19.6
18.8
18.6
18.4
18.2
18
19.56
19.52
19.48
19.44
19.4
MAX
MIN
19.36
5
10
15
20
25
30
35
40
45
10
30
50
70
90
110 130 150 170 190 210 225
SP (mV)
Supply Voltage VM (V)
D011
D012
Figure 11. Amplifier Gain over VM (SP = 50 mV)
Figure 12. Amplifier Gain over VM and Temperature Range
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Typical Characteristics (continued)
180
160
140
120
100
6.2
6
5.8
5.6
5.4
5.2
5
80
150/300 mA
12.5/25 mA
6/12.5 mA
100/200 mA
60
25/50 mA
40
20
0
TAꢀ ꢀ±ꢁꢂ&
TA = 85°C
TA = 25°C
TA = 125°C
4.8
-50
-25
0
25
50
75
100
125
5
10
15
20
25
30
35
40
45
Ambient Temperature (°C)
Supply Voltage VM (V)
D013
D014
Figure 13. High-Side IDRIVEP over Temperature (VM = 12 V)
Figure 14. 6-/12.5-mA High-Side IDRIVEP over VM
16
33
32
31
30
29
28
27
26
25
24
15.5
15
14.5
14
13.5
13
12.5
12
TAꢀ ꢀ±ꢁꢂ&
TA = 85°C
TAꢀ ꢀ±ꢁꢂ&
TA = 85°C
TA = 25°C
TA = 125°C
TA = 25°C
TA = 125°C
5
10
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
Supply Voltage VM (V)
Supply Voltage VM (V)
D015
D016
Figure 15. 12.5-/25-mA High-Side IDRIVEP over VM
Figure 16. 25-/50-mA High-Side IDRIVEP over VM
130
125
120
115
110
105
100
95
185
180
175
170
165
160
155
150
145
140
135
130
TAꢀ ꢀ±ꢁꢂ&
TA = 25°C
TA = 85°C
TA = 125°C
TAꢀ ꢀ±ꢁꢂ&
TA = 25°C
TA = 85°C
TA = 125°C
90
5
10
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
Supply Voltage VM (V)
Supply Voltage VM (V)
D017
D018
Figure 17. 100-/200-mA High-Side IDRIVEP over VM
Figure 18. 150-/300-mA High-Side IDRIVEP over VM
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7 Detailed Description
7.1 Overview
The DRV8701 is an H-bridge gate driver (also called a pre-driver or controller). The device integrates FET gate
drivers in order to control four external NMOS FETs. The device can be powered with a supply voltage between
5.9 and 45 V.
A simple PH/EN (DRV8701E) or PWM (DRV8701P) interface allows interfacing to the controller circuit.
A low-power sleep mode is included, which can be enabled using the nSLEEP pin.
The gate drive strength can be adjusted to optimize a system for a given FET without adding external resistors in
series with the FET gates. The IDRIVE pin allows for selection of the peak current driven into the external FET
gate. Both the high-side and low-side FETs are driven with a VGS of 9.5 V nominally when VM > 12 V. At lower
VM voltages, the VGS is reduced. The high-side gate drive voltage is generated using a doubler-architecture
charge pump that regulates to VM + 9.5 V.
This device greatly reduces the component count of discrete motor driver systems by integrating the necessary
FET drive circuitry into a single device. In addition, the DRV8701 adds protection features above traditional
discrete implementations: UVLO, OCP, pre-driver faults, and thermal shutdown.
A start-up (inrush) or running current limitation is built in using a fixed time-off current chopping scheme. The
chopping current level is set by choosing the sense resistor value and by setting a voltage on the VREF pin.
A shunt amplifier output is provided for accurate current measurements by the system controller. The SO pin
outputs a voltage that is 20 times the voltage seen across the sense resistor.
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7.2 Functional Block Diagram
VM
0.1 µF
10 µF minimum
VM
VM
VM
VCP
Power
GH1
SH1
GL1
HS
1 µF
VCP
CPH
Gate Driver
VGLS
Charge
Pump
LS
0.1 µF
CPL
VM
BDC
Logic
DVDD
AVDD
30 mA
3.3-V LDO
4.8-V LDO
VGLS LDO
1 µF
30 mA
VCP
GH2
SH2
GL2
HS
1 µF
Gate Driver
VGLS
LS
PH/IN1
EN/IN2
Control
Inputs
nSLEEP
IDRIVE
Current Regulation
SP
+
AV
RSENSE
RIDRIVE
SN
SO
-
Outputs
SNSOUT
nFAULT
VREF
PPAD GND GND
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7.3 Feature Description
7.3.1 Bridge Control
The DRV8701E is controlled using a PH/EN interface. The following logic table (Table 1) gives the full H-bridge
state when driving a single brushed DC motor. Note that Table 1 does not take into account the current control
built into the DRV8701E. Positive current is defined in the direction of xOUT1 → xOUT2.
Table 1. DRV8701E (PH/EN) Control Interface
nSLEEP
EN
X
PH
X
SH1
SH2
AVDD/DVDD
Disabled
Enabled
Description
0
1
1
1
High-Z
High-Z
Sleep mode; H-bridge disabled High-Z
Brake, low-side slow decay
0
X
L
L
L
H
L
1
0
Enabled
Reverse drive (current SH2 → SH1)
Forward drive (current SH1 → SH2)
1
1
H
Enabled
The DRV8701P is controlled using a PWM interface (IN1/IN2). The following logic table (Table 2) gives the full H-
bridge state when driving a single brushed DC motor. Note that Table 2 does not take into account the current
control built into the DRV8701P. Positive current is defined in the direction of xOUT1 → xOUT2.
Table 2. DRV8701P (PWM) Control Interface
nSLEEP
IN1
X
IN2
X
SH1
SH2
AVDD/DVDD
Disabled
Enabled
Description
Sleep mode; H-bridge disabled High-Z
Coast; H-bridge disabled High-Z
Reverse (current SH2 → SH1)
Forward (current SH1 → SH2)
Brake; low-side slow decay
0
1
1
1
1
High-Z
High-Z
0
0
High-Z
High-Z
0
1
L
H
L
H
L
L
Enabled
1
0
Enabled
1
1
Enabled
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
1
1
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
SH1
SH2
SH1
SH2
2
3
2
3
Figure 19. H-Bridge Operational States
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7.3.2 Half-Bridge Operation
The DRV8701 can be used to drive only a single half-bridge instead of a full H-bridge. To operate in this mode,
leave GH1 and GL1 disconnected. Also, connect a 1/10 W, 330-Ω 5% resistor from SH1 to GND.
GH1
PH/IN1
SH1
GL1
Gate
Drive
EN/IN2
Control
Inputs
330
nSLEEP
VM
GH2
SH2
GL2
Gate
Drive
Logic
BDC
nFAULT
SNSOUT
SP
+
AV
RSENSE
Outputs
SN
SO
-
VREF
Figure 20. Half-H Bridge Operation Mode
For the DRV8701E, this mode is controlled by tying the PH pin low. Table 3 gives the control scheme. EN = 1
enables the high-side FET, and EN = 0 enables the low-side FET. EN = 1 and PH = 1 is an invalid state.
Table 3. DRV8701E (PH/EN) Control Interface for Half-H Bridge Mode
nSLEEP
EN
X
PH
X
SH2
High-Z
L
AVDD/DVDD
Disabled
Description
Sleep mode; disabled High-Z
Brake, low-side slow decay
Drive (Current SH2 → GND)
Invalid state
0
1
1
1
0
X
Enabled
1
0
H
Enabled
1
1
For the DRV8701P, Table 4 gives the control scheme. IN1 = 1 and IN2 = 0 is an invalid state.
Table 4. DRV8701P (PWM) Control Interface for Half-H Bridge Mode
nSLEEP
IN1
X
IN2
X
SH2
High-Z
High-Z
H
AVDD/DVDD
Disabled
Description
Sleep mode; disabled High-Z
Coast; disabled High-Z
Drive (current SH2 → GND)
Invalid state
0
1
1
1
1
0
0
Enabled
0
1
Enabled
1
0
1
1
L
Enabled
Brake; low-side slow decay
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7.3.3 Current Regulation
The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation, or
current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a
rate dependent on the DC voltage and inductance of the winding. After the current hits the current chopping
threshold, the bridge enters a brake (low-side slow decay) mode until tOFF has expired.
Note that immediately after the current is enabled, the voltage on the SP pin is ignored for a period of time
(tBLANK) before enabling the current sense circuitry.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV
is the shunt amplifier gain, which is 20 V/V in the DRV8701.
The chopping current is calculated as follows:
9REF ± 9OFF
ICHOP
AV u RSENSE
(1)
Example: If a 50 mΩ sense resistor is used and VREF = 3.3 V, the full-scale chopping current will be 3.25 A. AV
is 20 V/V and VOFF is assumed to be 50 mV in this example.
For DC motors, current regulation is generally used to limit the start-up and stall current of the motor. If the
current regulation feature is not needed, it can be disabled by tying VREF directly to AVDD and tying SP and SN
to GND.
ICHOP
Drive
Brake / Slow Decay
Drive
Brake / Slow Decay
tOFF
WꢀꢀWBLANK
tOFF
WꢀꢀWBLANK
VREF
Figure 21. Sense Amplifier and Current Chopping Operation
During brake mode (slow decay), current is recirculated through the low-side FETs. Because current is not
flowing through the sense resistor, SO does not represent the motor current.
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7.3.4 Amplifier Output SO
The SO pin on the DRV8701 outputs an analog voltage equal to the voltage seen across the SP and SN pins
multiplied by AV. The factor AV is the shunt amplifier gain, which is 20 V/V in the DRV8701. SO is only valid
during forward or reverse drive. The H-bridge current is approximately equal to:
62 ± 9OFF
I
AV u RSENSE
(2)
When SP and SN are 0 V, SO outputs the amplifier offset voltage VOFF. No capacitor is required on the SO pin.
I
R
SP
Logic
+
-
VCC
+
SN
SO
-
RSENSE
AV/(AV-1) x R
SNSOUT
VREF
AV x R
Figure 22. Sense Amplifier Diagram
If the voltage across SP and SN exceeds 1 V, then the DRV8701 flags an overcurrent condition.
The SO pin can source up to 5 mA of current. If the pin is shorted to GND, or if a higher-current load is driven by
this pin, the output acts as a constant-current source. The output voltage is not representative of the H-bridge
current in this state.
This shunt amplifier feature can be disabled by tying the SP and SN pins to GND. When the amplifier is disabled,
current regulation is also disabled.
AVDD
Slope = Av
VOFF
SP - SN (V)
Figure 23. Sense Amplifier Output
7.3.4.1 SNSOUT
The SNSOUT pin of the DRV8701 indicates when the device is in current chopping mode. When the driver is in
a slow decay mode caused by internal PWM current chopping (ICHOP threshold hit), the open-drain SNSOUT
output is pulled low. If the current regulation is disabled, then the SNSOUT pin will be high-Z.
Note that if the H-bridge is put into a slow decay mode using the inputs (PH/EN or IN1/IN2), then SNSOUT is not
pulled low.
During forward or reverse drive mode, SNSOUT is high until the DRV8701 is internally forced into current
chopping. If the drive current rises above ICHOP, the driver enters a brake mode (low-side slow decay). The
SNSOUT pin will be pulled low during this current chopping brake mode. After the driver is re-enabled, the
SNSOUT pin is released high-Z and the drive mode is restarted.
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7.3.5 PWM Motor Gate Drivers
The DRV8701 contains gate drivers for a single H-bridge with external NMOS FETs. Figure 24 shows a block
diagram of the gate driver circuitry.
VM
VGHS
PH or IN1
EN or IN2
nSLEEP
GH1
SH1
ROFF
Pre-Drive
VGLS
GL1
ROFF
Logic
BDC
VM
VGHS
GH2
SH2
ROFF
Pre-Drive
VGLS
GL2
ROFF
SP
SN
RSENSE
Figure 24. PWM Motor Gate Drivers
Gate drivers inside the DRV8701 directly drive N-channel MOSFETs, which drive the motor current. The high-
side gate drive is supplied by the charge pump, while the low-side gate drive voltage is generated by an internal
regulator.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin. Peak source currents may be set
to 6, 12.5, 25, 100, or 150 mA. The peak sink current is approximately 2× the peak source current. Adjusting the
peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge.
The peak drive current is selected by setting the value of the RIDRIVE resistor on the IDRIVE pin or by forcing a
voltage onto the IDRIVE pin (see Table 6 for details).
Fast switching times can cause extra voltage noise on VM and GND. This can be especially due to a relatively
slow reverse-recovery time of the low-side body diode, where it conducts reverse-bias momentarily, being similar
to shoot-through. Slow switching times can cause excessive power dissipation since the external FETs take a
longer time to turn on and turn off.
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When changing the state of the output, the peak current (IDRIVE) is applied for a short drive period (tDRIVE) to
charge the gate capacitance. After this time, a weaker current source (IHOLD) is used to keep the gate at the
desired state. When selecting the gate drive strength for a given external FET, the selected current must be high
enough to fully charge and discharge the gate during tDRIVE, or excessive power will be dissipated in the FET.
During high-side turn-on, the low-side gate is pulled low with a strong pull-down (ISTRONG). This prevents the low-
side FET QGS from charging and keeps the FET off, even when there is fast switching at the outputs.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the high-
or low-side FET from turning on until the opposite FET has been turned off.
tDRIVE
IHOLD
High-side
gate drive
IHOLD
IHOLD
current
High-side
VGS
tDRIVE
IHOLD
IHOLD
Low-side
gate drive
current
IHOLD
Low-side
VGS
Figure 25. Gate Driver Output to Control External FETs
QGD Miller charge
When a FET gate is turned on, three different capacitances must be charged.
•
•
•
QGS – Gate-to-source charge
QGD – Gate-to-drain charge (miller charge)
Remaining QG
The FET output is slewing primarily during the QGD charge.
25
20
10
VM
D
8
VGHS
CGD
6
15
10
5
GHx
SHx
G
Pre-Drive
CGS
4
2
S
10
30
40
50
20
QGS
QGD
Remaining QG
QG gate charge (nC)
Figure 26. Example FET Gate Charging Profile
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7.3.6 IDRIVE Pin
The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen.
The FET gate ramp directly affects the H-bridge output rise and fall time.
Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left
unconnected, then the 100-mA source and 200-mA sink setting are selected.
If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the
gate driver is configured as 25-mA source and 50-mA sink.
+
4.3V
-
AVDD
190k
+
3.7V
2.5V
1.3V
0.1V
-
IDRIVE
+
Digital
Core
-
310k
+
-
+
-
Figure 27. IDRIVE Pin Internal Circuitry
Table 5. IDRIVE Pin Configuration Settings
Source Current
IDRIVE Resistance
<1 kΩ to GND
IDRIVE Voltage
Sink Current (IDRIVE,SNK
)
HS OCP Monitor
(IDRIVE,SRC
)
GND
6 mA
12.5 mA
25 mA
ON
ON
ON
ON
ON
OFF
33 kΩ ±5% to GND
200 kΩ ±5% to GND
>500 kΩ to GND, High-Z
68 kΩ ±5% to AVDD
<1 kΩ to AVDD
0.7 V ±5%
2 V ±5%
3 V ±5%
4 V ±5%
AVDD
12.5 mA
25 mA
50 mA
100 mA
150 mA
25 mA
200 mA
300 mA
50 mA
Table 6. IDRIVE Pin Resistor Settings
33 kΩ ±5% to GND
200 kΩ ±5% to GND
<1 kΩ to GND
>500 kΩ to GND, High-Z
68 kΩ ±5% to AVDD
<1 kΩ to AVDD
AVDD
AVDD
RIDRIVE
IDRIVE
IDRIVE
IDRIVE
IDRIVE
IDRIVE
«««
RIDRIVE
«««
«««
IDRIVE
IDRIVE
IDRIVE
IDRIVE
150 / 300 mA
IDRIVE
12.5 / 25 mA (33 kΩ)
25 / 50 mA (200 kΩ)
25 / 50 mA
HS OCP monitor off
6 / 12.5 mA
100 / 200 mA
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7.3.7 Dead Time
Dead time (tDEAD) is measured as the time when SHx is High-Z between turning off one of the H-bridge FETs
and turning on the other. For example, the output is High-Z between turning off the high-side FET and turning on
the low-side FET.
The DRV8701 inserts a digital dead time of approximately 150 ns. The total dead time also includes the FET
gate turn-on time.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx
and GLx pins) includes the observable dead time.
7.3.8 Propagation Delay
The propagation delay time (tDELAY) is measured as the time between an input edge to an output change. This
time is composed of two parts: an input deglitch time and output slewing delay. The input deglitcher prevents
noise on the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, first, one FET must be turned off. The FET gate is ramped down according to the IDRIVE setting, and
the observed propagation delay ends when the FET gate has fallen below the threshold voltage.
7.3.9 Overcurrent VDS Monitor
The gate driver circuit monitors the VDS voltage of each external FET when it is driving current. When the voltage
monitored is greater than the OCP threshold voltage (VDS OCP), after the OCP deglitch time (tOCP) has expired, an
OCP condition will be detected.
VM
VM
+
High-side
VDS OCP
Monitor
GH1
SH1
GL1
-
+
VM
Low-side
VDS OCP
Monitor
+
BDC
-
High-side
VDS OCP
Monitor
GH2
SH2
GL2
-
+
Low-side
VDS OCP
Monitor
SP
SN
-
RSENSE
Figure 28. Overcurrent VDS Monitors
When IDRIVE is shorted to AVDD, the VDS OCP monitor on the high-side FETs is disabled. In cases where the
VM supplied to the DRV8701 can be different from the external H-bridge supply, this setting must be used in
order to prevent false overcurrent detection. In this mode, the IDRIVE current is set to 25-mA source and 50-mA
sink.
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7.3.10 Charge Pump
A charge pump is integrated to supply a high-side NMOS gate drive voltage of VHGS. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins
CPH and CPL. When VM is below 12 V, this charge pump behaves as a doubler and generates VCP = 2 × VM –
1.5 V if unloaded. Above VM = 12 V, the charge pump regulates VCP such that VCP = VM + 9.5 V.
VM
1 µF
VCP
CPH
Charge
Pump
VM
0.1 µF
CPL
Figure 29. Charge Pump Diagram
7.3.11 LDO Voltage Regulators
Two LDO regulators are integrated into the DRV8701. They can be used to provide the supply voltage for a low-
power microcontroller or other low-current devices. For proper operation, bypass the AVDD and DVDD pins to
GND using ceramic capacitors.
The AVDD output voltage is nominally 4.8 V, and the DVDD output is nominally 3.3 V. When the AVDD or DVDD
current load exceeds 30 mA, the LDO behaves like a constant current source. The output voltage drops
significantly with currents greater than this limit.
Note that AVDD and DVDD are disabled when the device is in sleep mode (nSLEEP = 0). In addition, when an
overtemperature (TSD) or undervoltage (UVLO) fault is encountered, the AVDD regulator is shut off.
VM
+
4.8 V
AVDD
DVDD
-
30 mA
max
1 µF
1 µF
VM
+
3.3 V
-
30 mA
max
Figure 30. AVDD and DVDD LDOs
The power dissipated in the DRV8701 due to these LDOs may be approximated by:
Power = (VM – AVDD) × IAVDD + (VM – DVDD) × IDVDD
(3)
(4)
For example at VM = 24 V, drawing 10 mA out of both AVDD and DVDD results in a power dissipation of:
Power = (24 V – 4.8 V) × 10 mA + (24 V – 3.3 V) × 10 mA = 192 mW + 207 mW = 399 mW
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7.3.12 Gate Drive Clamp
A clamping structure limits the gate drive output voltage to VGS CLAMP to protect the power FETs from damage.
The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the body diodes
of the internal gate driver FET.
VGHS
VM
IREVERSE
GHx
VGS > VCLAMP
ICLAMP
SHx
Pre-Drive
VGS negative
VGLS
GLx
RSENSE
GND
Figure 31. Gate Drive Clamp Diagram
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7.3.13 Protection Circuits
The DRV8701 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, gate driver
shorts, and overtemperature events.
7.3.13.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO threshold voltage, all FETs in the H-bridge are
disabled, the charge pump is disabled, AVDD is disabled, and the nFAULT pin is driven low. Operation resumes
when VM rises above the UVLO threshold. The nFAULT pin is released after operation has resumed.
7.3.13.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge pump undervoltage threshold voltage (VCPUV), all
FETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when VCP rises above
the CPUV threshold. The nFAULT pin is released after operation has resumed.
7.3.13.3 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs (see Figure 28). If the
voltage across a driven FET exceeds the overcurrent trip threshold (VDS OCP) for longer than the OCP deglitch
time (tOCP), an OCP event is recognized. As a result, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low; the driver is re-enabled after the OCP retry period (tRETRY) has passed. nFAULT releases high-Z
again at after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present,
normal operation resumes and nFAULT remains released high-Z.
This VDS overcurrent monitor on the high-side FETs can be disabled by using a specific IDRIVE setting. This
allows the system to have a higher DRV8701 VM supply than the H-bridge supply.
In addition to this FET VDS monitor, an overcurrent condition is also detected if the voltage at SP exceeds
VSP OCP
.
7.3.13.4 Pre-Driver Fault (PDF)
The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase above
1 V (when sourcing current) or decrease below 1 V (when sinking current) after tDRIVE, a pre-driver fault is
detected. The device encounters this fault if GHx or GLx are shorted to GND, SHx, or VM. Additionally, the
device encounters the pre-driver fault if the IDRIVE setting selected is not sufficient to turn on the external FET.
As a result, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The driver is re-enabled after
the retry period (tRETRY) has passed. The nFAULT pin is released after operation has resumed.
7.3.13.5 Thermal Shutdown (TSD)
If the die temperature exceeds TTSD, all FETs in the H-bridge are disabled, the charge pump is shut down, AVDD
is disabled, and the nFAULT pin is driven low. After the die temperature has fallen below TTSD – THYS, operation
automatically resumes. The nFAULT pin is released after operation has resumed.
Table 7. Fault Response
Fault
Condition
H-Bridge
Charge Pump
AVDD
DVDD
Recovery
VM undervoltage
(UVLO)
VM ≤ VUVLO
Disabled
Disabled
Disabled
Operating
VM ≥ VUVLO
VCP undervoltage
(CPUV)
VCP < VCPUV
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Operating
VCP > VCPUV
tRETRY
External FET overload
(OCP)
VDS ≥ 1.0 V or
VSP – VSN > 1.0 V
Gate voltage
unchanged after tDRIVE
Pre-driver fault (PDF)
tRETRY
Thermal shutdown
(TSD)
TJ ≥ 150°C
TJ ≤ 130°C
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7.3.14 Reverse Supply Protection
The following circuit may be implemented to protect the system from reverse supply conditions. This circuit
requires the following additional components:
•
•
•
•
•
NMOS FET
npn BJT
Diode
10-kΩ resistor
43-kΩ resistor
VM
43 k
10 k
0.1 µF
CP2
1 µF
+
Bulk
10 µF min
0.1 µF
CP1
VCP
VM
GH1
SH1
GL1
BDC
GH2
SH2
GL2
SP
SN
RSENSE
Figure 32. Reverse Supply Protection External Circuitry
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7.4 Device Functional Modes
The DRV8701 is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the
H-bridge FETs are High-Z, and the AVDD and DVDD regulators are disabled. Note that tSLEEP must elapse after
a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8701 is brought out of sleep mode
if nSLEEP is brought high. Note that tWAKE must elapse before the outputs change state after wake-up.
While nSLEEP is brought low, all external H-bridge FETs are disabled. The high-side gate pins GHx are pulled to
the output node SHx by an internal resistor, and the low-side gate pins GLx are pulled to GND.
When VM is not applied, and during the power-on time (tON), the outputs are disabled using weak pulldown
resistors between the GHx and SHx pins and between GLx and GND.
Table 8. Functional Modes
Condition
VM < VUVLO
Charge Pump
GHx
GLx
AVDD and DVDD
Unpowered
Sleep mode
Disabled
Weak pulldown to SHx
Weak pulldown to GND
Disabled
VUVLO < VM
nSLEEP low
Disabled
Enabled
Strong pulldown to GND Strong pulldown to GND
Depends on inputs Depends on inputs
Disabled
VUVLO < VM
nSLEEP high
Operating
Operating
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7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies
The DRV8701 can operate with a different supply voltage (VM) than the system H-bridge supply (VBAT). Case 1
describes normal operation when VM and VBAT are roughly the same. Special considerations must be taken into
account for Cases 2, 3, and 4.
•
•
Case 1: VM ≈ VBAT. Recommended operation
Case 2: VM > VBAT. IDRIVE must be shorted to AVDD to disable the high-side OCP. The IDRIVE current is
fixed at 25-mA source and 50-mA sink. This case can allow the driver to better enhance the external FETs for
VBAT < 11.5 V, or operate down to a lower supply voltage below 5.9 V.
•
•
Case 3: VM > VBAT (higher than Case 2). IDRIVE must be shorted to AVDD to disable the high-side OCP.
This case can also allow the driver to better enhance the external FETs, or operate down to a lower supply
voltage below 5.9 V. The IDRIVE current is fixed at 25-mA source and 50-mA sink. Excess gate drive current
may be driven through the DRV8701 gate clamps causing additional power dissipation in the DRV8701.
Case 4: VM < VBAT. The high-side FETs may not be in saturation. There may be a significant voltage drop
across the high-side FET when driving current. This causes high power dissipation in the external FET. When
operating in Case 4, the external FET threshold voltage must be greater than 2 V. Otherwise the DRV8701
will report a pre-driver fault whenever the FET is out of saturation.
Table 9. VM Operational Range based on VBAT
VBAT Range
Case 3
Case 2
Case 1
Case 4
VM ≥ 5.9 V
VM < 0.5 × VBAT + 5.75 V
1 V ≤ VBAT < 5.9 V
5.9 V ≤ VBAT < 6.4 V
N/A
N/A
VM ≥ 0.5 × VBAT + 5.75 V
VM ≤ 45 V
VM ≥ 5.9 V
VM < VBAT
VM = VBAT
VM > VBAT
VM < 0.5 × VBAT + 5.75 V
6.4 V ≤ VBAT < 11.5 V
11.5 V ≤ VBAT < 14 V
VM > 0.6 × VBAT + 2.5 V
VM ≥ 5.9 V
VM ≤ 0.6 × VBAT + 2.5 V
VM ≤ VBAT
VM > VBAT
VM ≤ 45 V
N/A
VM > VBAT – 4 V
VM ≥ 5.9 V
VM ≤ VBAT – 4 V
14 V ≤ VBAT ≤ 45 V
VM ≤ VBAT
Figure 33. VM Operating Range Based on Motor Supply Voltage
When nSLEEP is low, VM may be reduced down to 0 V with up to 45 V present at VBAT. However, nSLEEP
should not be brought high until VM is supplied with a voltage aligning with one of the cases outlined above.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8701 is used in brushed-DC, solenoid, or relay control.
8.2 Typical Applications
8.2.1 Brushed-DC Motor Control
The following design procedure can be used to configure the DRV8701.
VM
0.1 µF 1 µF
R1
R2
VM
+
0.1 µF
Bulk
7
24
23
22
21
20
19
AVDD
DVDD
nFAULT
SNSOUT
SO
GH2
SH2
GL2
SP
8
9
1 µF
10 k
1 µF
10 k
GND
(PPAD)
10
11
12
50 m
BDC
SN
IDRIVE
GL1
33 k
VM
Figure 34. Typical Application Schematic
8.2.1.1 Design Requirements
Table 10 gives design input parameters for system design.
Table 10. Design Parameters
Design Parameter
Nominal supply voltage
Reference
Example Value
18 V
VM
VMMIN, VMMAX
QG
Supply voltage range
12 to 24 V
FET total gate charge(1)
FET gate-to-drain charge(1)
Target FET gate rise time
Motor current chopping level
14 nC (typically)
2.3 nC (typically)
100 to 300 ns
3 A
QGD
RT
ICHOP
(1) FET part number is CSD88537ND.
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External FET Selection
The DRV8701 FET support is based on the charge pump capacity and output PWM frequency. For a quick
calculation of FET driving capacity, use the following equations when drive and brake (slow decay) are the
primary modes of operation:
IVCP
QG
ꢀ
¦
PWM
where
•
fPWM is the maximum desired PWM frequency to be applied to the DRV8701 inputs or the current chopping
frequency, whichever is larger.
•
IVCP is the charge pump capacity, which depends on VM.
(5)
(6)
The internal current chopping frequency is at most:
1
¦
ꢀ
| ꢀꢁ N+]
PWM
tOFF ꢁ tBLANK
Example: If a system at VM = 7 V (IVCP = 8 mA) uses a maximum PWM frequency of 40 kHz, then the DRV8701
will support QG < 200 nC FETs.
If the application will require a forced fast decay (or alternating between drive and reverse drive), the maximum
FET driving capacity is given by:
IVCP
QG
ꢀ
ꢀ u ¦PWM
(7)
8.2.1.2.2 IDRIVE Configuration
Select IDRIVE based on the gate charge of the FETs. Configure this pin so that the FET gates are charged
completely during tDRIVE. If the designer chooses an IDRIVE that is too low for a given FET, then the FET may
not turn on completely. TI suggests to adjust these values in-system with the required external FETs and motor
to determine the best possible setting for any application.
For FETs with a known gate-to-drain charge (QGD) and desired rise time (RT), select IDRIVE based on:
QGD
IDRIVE !
RT
(8)
Example: If the gate-to-drain charge is 2.3 nC, and the desired rise time is around 100 to 300 ns,
IDRIVE1 = 2.3 nC / 100 ns = 23 mA
IDRIVE2 = 2.3 nC / 300 ns = 7.7 mA
Select IDRIVE between 7.7 and 23 mA
Select IDRIVE as 12.5-mA source (25-mA sink)
Requires a 33-kΩ resistor from the IDRIVE pin to GND
8.2.1.2.3 Current Chopping Configuration
The chopping current is set based on the sense resistor value and the analog voltage at VREF. Calculate the
current using Equation 9. The amplifier gain AV is 20 V/V and VOFF is typically 50 mV.
Example: If the desired chopping current is 3 A,
Set RSENSE = 50 mΩ
95() ± 9OFF
ICHOP
A V u RSENSE
(9)
VREF would have to be 3.05 V.
Create a resistor divider from AVDD (4.8 V) to set VREF ≈ 3 V
Set R2 = 3.3 kΩ; set R1 = 2 kΩ.
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8.2.1.3 Application Curves
Figure 35. SH1 Rise Time (12.5-mA Source, 25-mA Sink)
Figure 36. SH1 Fall Time (12.5-mA Source, 25-mA Sink)
Figure 37. Current Regulating at 3 A on Motor Startup
Figure 38. Current Profile on Motor Startup With
Regulation
Figure 39. Current Profile on Motor Startup Without Regulation
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8.2.2 Alternate Application
In this example, the DRV8701 is powered from a supply that is boosted above VBAT. This allows the system to
work at lower VBAT voltages, but requires the user to disable OCP monitoring.
VBAT
Boost
+
10 µF
0.1 µF
0.1 µF 1 µF
R1
R2
0.01 µF
+
C1
7
24
23
22
21
20
19
AVDD
DVDD
nFAULT
SNSOUT
SO
GH2
SH2
GL2
SP
8
9
1 µF
10 k
1 µF
10 k
GND
(PPAD)
10
11
12
50 m
BDC
AVDD
68 k
SN
IDRIVE
GL1
VBAT
Figure 40. DRV8701 on Boosted Supply
8.2.2.1 Design Requirements
Table 11 gives design input parameters for system design.
Table 11. Design Parameters
Design Parameter
Battery voltage
Reference
Example Value
12 V nominal
Minimum operation: 4.0 V
VBAT
VM = 7 V when VBAT < 7 V
VM = VBAT when VBAT ≥ 7 V
DRV8701 supply voltage
VM
FET total gate charge
QG
QGD
ICHOP
42 nC
11 nC
3 A
FET gate-to-drain charge
Motor current chopping level
8.2.3 Detailed Design Procedure
8.2.3.1 IDRIVE Configuration
Because the VM supply to the DRV8701 is different from the external H-bridge supply VBAT, the designer must
disable the overcurrent monitor to prevent false overcurrent detection. The designer must place a 68-kΩ resistor
between the IDRIVE pin and AVDD.
IDRIVE is fixed at 25-mA source and 50-mA sink in this mode.
So, the rise time is 11 nC / 25 mA = 440 ns.
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8.2.3.2 VM Boost Voltage
To determine an effective voltage to boost VM, first determine the minimum VBAT at which the system must
operate. Select VM such that the gate driver clamps do not turn on during normal operation.
VBAT + 11.5 V
VM <
2
(10)
Example: If VBAT minimum is 4.0 V,
VM < 7.75 V
So VM = 7 V is selected to allow for adequate margin.
9 Power Supply Recommendations
The DRV8701 is designed to operate from an input voltage supply (VM) range between 5.9 and 45 V. A 0.1-µF
ceramic capacitor rated for VM must be placed as close to the DRV8701 as possible. In addition, the designer
must include a bulk capacitor with a valued of at least 10 µF on VM.
Bypassing the external H-bridge FETs requires additional bulk capacitance.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The datasheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
±
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Figure 41. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This
capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the high-
current path through the external FETs. The connecting metal trace widths should be as wide as possible, and
numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the
bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF
rated for VM. Place this component as close to the pins as possible.
Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated
for 16 V. Place this component as close to the pins as possible.
Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as
close to the pins as possible.
If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets
to the motor.
Use separate traces to connect the SP and SN pins to the RSENSE terminals.
10.2 Layout Example
+
10 µF
minimum
GND
GND
D
D
D
D
G
S
S
S
0.1 µF
1 µF
0.1 µF
1 µF
1 µF
S
S
S
G
D
D
D
D
7
8
24
23
22
21
20
19
AVDD
GH2
DVDD
nFAULT
SNSOUT
SO
SH2
GL2
SP
9
GND
(PPAD)
10
11
12
SN
RSENSE
IDRIVE
GL1
S
S
S
G
D
D
D
D
RIDRIVE
D
D
D
D
G
S
S
S
GND
Figure 42. Layout Recommendation
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
•
PowerPAD™ Thermally Enhanced Package, SLMA002
PowerPAD™ Made Easy, SLMA004
Current Recirculation and Decay Modes, SLVA321
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2015
PACKAGING INFORMATION
Orderable Device
DRV8701ERGER
DRV8701ERGET
DRV8701PRGER
DRV8701PRGET
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGE
24
24
24
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
8701E
ACTIVE
ACTIVE
ACTIVE
RGE
RGE
RGE
250
3000
250
Green (RoHS
& no Sb/Br)
8701E
8701P
8701P
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8701ERGER
DRV8701ERGET
DRV8701PRGER
DRV8701PRGET
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8701ERGER
DRV8701ERGET
DRV8701PRGER
DRV8701PRGET
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
24
24
24
24
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
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