DRV8702QRHBTQ1 [TI]
汽车类 47V、H 桥智能栅极驱动器 | RHB | 32 | -40 to 125;
| 型号： | DRV8702QRHBTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 47V、H 桥智能栅极驱动器 | RHB | 32 | -40 to 125 栅极驱动 驱动器 |
| 文件： | 总64页 (文件大小：2107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8702-Q1, DRV8703-Q1
ZHCSG08E –OCTOBER 2016 –REVISED JANUARY 2021
DRV870x-Q1 汽车H 桥栅极驱动器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
DRV870x-Q1 器件是一款小型单通道 H 桥栅极驱动
器，它使用四个外部 N 通道 MOSFET，旨在驱动一个
双向有刷直流电机。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 功能安全型
PH/EN、独立 H 桥或 PWM 接口允许轻松连接到控制
器电路。内部传感放大器提供可调的电流控制。集成的
电荷泵可提供 100% 占空比支持，而且可用于驱动外
部反向电池开关。
– 可帮助进行DRV8702-Q1 DRV8703-Q1 功能安
全系统设计的文档
• 单通道H 桥栅极驱动器
– 驱动四个外部N 沟道MOSFET
– 支持100% 脉宽调制(PWM) 占空比
• 工作电源电压范围：5.5V 至45V
• 三个控制接口选项
独立半桥模式支持半桥共享，能够以具有成本效益的方
式顺序控制多个直流电机。这款栅极驱动器内置有相应
的电路，能够使用关断时间固定的PWM 电流斩波来调
节绕组电流。
– PH/EN、独立H 桥和PWM
• 用于配置的串行接口(DRV8703-Q1)
• 智能栅极驱动架构
DRV870x-Q1 器件采用了智能栅极驱动技术，因此无
需任何外部栅极组件（电阻器和齐纳二极管），同时可
为外部 FET 提供保护。智能栅极驱动架构可优化死区
时间以避免出现任何击穿问题，在通过可编程压摆率控
制技术降低电磁干扰(EMI) 方面带来了灵活性，而且可
防止任何栅极短路问题。此外，该架构中还包括主动和
被动下拉特性，可防止任何dv/dt 栅极导通。
– 可调压摆率控制
• 每个H 桥独立控制
• 支持1.8V、3.3V 和5V 逻辑输入
• 电流分流放大器
• 集成PWM 电流调节功能
• 低功耗睡眠模式
• 保护特性
器件信息(1)
封装尺寸（标称值）
器件型号
DRV8702-Q1
DRV8703-Q1
封装
– 电源欠压锁定(UVLO)
– 电荷泵欠压(CPUV) 锁定
– 过流保护(OCP)
VQFN (32)
5.00mm × 5.00mm
– 栅极驱动器故障(GDF)
– 热关断(TSD)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 监视器计时器(DRV8703-Q1)
– 故障调节输出(nFAULT)
5.5 to 45 V
DRV870x-Q1
2 应用
PH/EN or PWM
Gate
Drive
nSLEEP
H-Bridge Gate Driver
• 电动车窗升降器、天窗、座椅、滑动门、后备箱和
尾门
• 继电器更换
FETs
M
VREF
Sense Output
Shunt Amplifier
Current
Sense
nFAULT
Current Regulation
Protection
– 应用报告：SLVA837
– TI 设计：TIDUCQ9
• 有刷直流泵
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDR9
DRV8702-Q1, DRV8703-Q1
ZHCSG08E –OCTOBER 2016 –REVISED JANUARY 2021
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 41
7.6 Register Maps...........................................................43
8 Application and Implementation..................................49
8.1 Application Information............................................. 49
8.2 Typical Application.................................................... 49
9 Power Supply Recommendations................................54
9.1 Bulk Capacitance Sizing........................................... 54
10 Layout...........................................................................55
10.1 Layout Guidelines................................................... 55
10.2 Layout Example...................................................... 55
11 Device and Documentation Support..........................56
11.1 Documentation Support.......................................... 56
11.2 Related Links.......................................................... 56
11.3 接收文档更新通知................................................... 56
11.4 支持资源..................................................................56
11.5 Trademarks............................................................. 56
11.6 静电放电警告...........................................................56
11.7 术语表..................................................................... 56
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 5
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................8
6.5 Electrical Characteristics.............................................8
6.6 SPI Timing Requirements......................................... 13
6.7 Switching Characteristics..........................................13
6.8 Typical Characteristics..............................................15
7 Detailed Description......................................................20
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................21
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................41
Information.................................................................... 56
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (December 2018) to Revision E (January 2021)
Page
• 添加了功能安全项目符号.................................................................................................................................... 1
Changes from Revision C (August 2018) to Revision D (December 2018)
Page
• 更改了首页，删除了第二项说明......................................................................................................................... 1
• 删除了栅极驱动电流图........................................................................................................................................1
• Added SL2 pin to the continous shunt amplifier input pin voltage...................................................................... 7
• Added SL2 pin to the continous shunt amplifier input pin voltage...................................................................... 7
• Changed IN1 to IN1/PH and IN2 to IN2/EN .......................................................................................................8
• Changed MODE typical pulldown resistance .....................................................................................................8
• Added MODE typical pullup resistance.............................................................................................................. 8
• Changed Wording in VDS Configuration section .............................................................................................52
Changes from Revision B (March 2017) to Revision C (August 2018)
Page
• 更改了特性和说明部分......................................................................................................................................1
• Changed the type of the SL2 pin from O to I in the Pin Functions table.............................................................5
• Changed SPI parameter name conventions.....................................................................................................13
• Changed the VDS(OCP) from 0.86 V to 0.96 V in the OCP Threshold Voltage graph.........................................15
• Changed the I(CHOP) equation in the Current Regulation and Current Chopping Configuration sections.........25
• Changed the current equation in the Amplifier Output (SO) section.................................................................26
• Changed the description of the WD_EN bit in the IDRIVE and WD Field Descriptions table...........................43
Changes from Revision A (November 2016) to Revision B (March 2017)
Page
• Changed the maximum voltage for AVDD from 5.7 to 5.75 in the Absolute Maximum Ratings table.............. 14
• Changed maximum VSP value for GAIN_CS = 00 and GAIN_CS = 10 for the DRV8703-Q1 amplifier gain
parameter in the Electrical Characteristics table.............................................................................................. 14
• Added the R(VDRAIN) note to the External Components table........................................................................... 23
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• Changed one resistor value from 32 kΩto 65 kΩin the MODE Pin Block Diagram ......................................24
• Changed what happens when a fault condition is no longer present in the Overcurrent Protection (OCP)
section.............................................................................................................................................................. 37
• Deleted AV × from tthe I(CHOP) equation in the Current Chopping Configuration section.............................. 52
Changes from Revision * (October 2016) to Revision A (November 2016)
Page
• 已发布完整版数据表........................................................................................................................................... 1
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5 Pin Configuration and Functions
GND
IN1/PH
IN2/EN
GND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GL2
SL2
SN
SP
Thermal
Pad
IDRIVE
VDS
GL1
SH1
GH1
GND
GND
nSLEEP
Not to scale
图5-1. DRV8702-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View
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GND
IN1/PH
IN2/EN
SDO
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GL2
SL2
SN
SP
Thermal
Pad
nSCS
GL1
SH1
GH1
GND
SDI
SCLK
nSLEEP
Not to scale
图5-2. DRV8703-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View
Pin Functions
PIN
NO.
DRV8702-Q1 DRV8703-Q1
TYPE(1)
DESCRIPTION
NAME
Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to
ground with a 6.3-V, 1-µF ceramic capacitor.
AVDD
CPH
14
30
31
12
14
30
31
12
PWR
PWR
PWR
PWR
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
CPL
Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this
pin to ground with a 6.3-V, 1-µF ceramic capacitor.
DVDD
GH1
GH2
GL1
18
26
20
24
1
18
26
20
24
1
O
High-side gate. Connect this pin to the high-side FET gate.
High-side gate. Connect this pin to the high-side FET gate.
Low-side gate. Connect this pin to the low-side FET gate.
Low-side gate. Connect this pin to the low-side FET gate.
Device ground. Connect this pin to the system ground.
Device ground. Connect this pin to the system ground.
Device ground. Connect this pin to the system ground.
Device ground. Connect this pin to the system ground.
Device ground. Connect this pin to the system ground.
Device ground. Connect this pin to the system ground.
O
O
GL2
O
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
PWR
PWR
PWR
13
17
4
13
17
—
—
—
7
9
Current setting pin for the gate drive. The resistor value or voltage forced on
this pin sets the gate-drive current. For more information see the 节8.2.2.2
section.
IDRIVE
IN1/PH
5
2
I
I
—
Input control pins. The logic of this pin is dependent on the MODE pin. This pin
is connected to an internal pulldown resistor.
2
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PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8702-Q1 DRV8703-Q1
Input control pins. The logic of this pin is dependent on the MODE pin. This pin
is connected to an internal pulldown resistor.
IN2/EN
3
3
I
I
Mode control pin. Pull this pin to logic low to use H-bridge operation. Pull this
pin to logic high for independent half-bridge operation. This pin is connected to
an internal resistor divider. Operation of this pin is latched on power up or when
exiting sleep mode. This pin is connected to an internal pullup and pulldown
resistors.
MODE
11
11
NC
32
32
7
NC
I
No connect. No internal connection.
SPI clock. This pin is for the SPI clock signal. This pin is connected to an
internal pulldown resistor.
SCLK
—
SPI input. This pin is for the SPI input signal. This pin is connected to an
internal pulldown resistor.
SDI
6
4
I
—
—
SPI output. This pin is for the SPI output signal. This pin is an open-drain
output that requires an external pullup resistor.
SDO
OD
SH1
SH2
SL2
SN
19
25
23
22
19
25
23
22
I
I
I
I
High-side source. Connect this pin to the high-side FET source.
High-side source. Connect this pin to the high-side FET source
Low-side source. Connect this pin to the low-side FET source.
Shunt-amplifier negative input. Connect this pin to the current-sense resistor.
Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times
AV plus an offset. Place no more than 1 nF of capacitance on this pin.
SO
16
21
29
27
6
16
21
29
27
O
SP
I
Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
Charge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin
and the VM pin.
VCP
VDRAIN
VDS
PWR
I
I
High-side FET drain connection. This pin is common for the two H-bridges.
VDS monitor setting pin. The resistor value or voltage forced on this pin sets
the VDS monitor threshold. For more information see the 节8.2.2.3 section.
—
28
15
Power supply. Connect this pin to the motor supply voltage. Bypass this pin to
ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.
VM
28
15
PWR
I
Current set reference input. The voltage on this pin sets the driver chopping
current.
VREF
Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault
condition occurs. This pin is an open-drain output that requires an external
pullup resistor.
nWDFLT
9
OD
—
Fault indication pin. This pin is pulled logic low when a fault condition occurs.
This pin is an open-drain output that requires an external pullup resistor.
nFAULT
nSCS
10
10
5
OD
I
SPI chip select. This pin is the select and enable for SPI. This pin is active low.
—
Device sleep mode. Pull this pin to logic low to put device into a low-power
sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to an
internal pulldown resistor.
nSLEEP
8
8
I
(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–10
MAX
47
UNIT
V
Power supply voltage
VM
Charge pump voltage
VCP, CPH
CPL
VVM + 12
VVM
V
Charge pump negative switching pin
Internal logic regulator voltage
Internal analog regulator voltage
Drain pin voltage
V
DVDD
3.8
V
AVDD
5.75
47
V
VDRAIN
VM –VDRAIN
V
Voltage difference between supply and VDRAIN
10
V
IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE,
VDS, MODE, nSCS, SCLK, SDI, SDO,
nWDFLT
Control pin voltage
5.75
V
–0.3
High-side gate pin voltage
GH1, GH2
GL1, GL2
SH1, SH2
SH1, SH2
SP, SL2
SN
VVM + 12
12
V
V
–0.3
–0.3
–1.2
–2
Low-side gate pin voltage
Continuous phase-node pin voltage
Pulsed 10-µs phase-node pin voltage
VVM + 1.2
VVM + 2
1.2
V
V
V
–0.5
–0.3
–1
Continuous shunt amplifier input pin voltage
0.3
V
Pulsed 10-µs shunt amplifier input pin voltage
Shunt amplifier output pin voltage
SP, SL2
SO
1.2
V
5.75
V
–0.3
0
Shunt amplifier output pin current
SO
5
mA
Maximum current, limit current with external
series resistor
VDRAIN
2
mA
–2
Open-drain output current
Gate pin source current
nFAULT, SDO, nWDFLT
GH1, GL1, GH2, GL2
GH1, GL1, GH2, GL2
0
0
10
250
500
150
150
mA
mA
mA
°C
Gate pin sink current
0
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
Electrostatic
discharge
V(ESD)
All pins
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Corner pins (1, 8, 9, 16, 17, 24, 25,
and 32)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
5.5
MAX
UNIT
V
VVM
Power supply voltage
VM
45
5.25
3.6
VCC
Logic-level input voltage
0
V
VVREF
f(PWM)
IAVDD
IDVDD
ISO
Current Shunt Amplifier Reference Voltage
Applied PWM signal (IN1/IN2)
AVDD external load current
VREF
0.3(1)
V
IN1, IN2
100
30(2)
30(2)
5
kHz
mA
mA
mA
°C
DVDD external load current
Shunt-amplifier output-current loading
Operating ambient temperature
SO
TA
125
–40
(1) Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
(2) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV870x-Q1
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
32.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.6
6.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
6.8
ψJB
RθJC(bot)
1.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
Gate drivers functional
5.5
4.5
5.5
45
45
VVM
VM operating voltage
V
Logic functional
IVM
VM operating supply current
VM sleep mode supply current
VVM = 13.5 V; nSLEEP=1
nSLEEP = 0, VVM = 13.5 V, TA = 25°C
nSLEEP = 0, VVM = 13.5 V, TA = 125°C(1)
2-mA load
7.5
12
mA
µA
14
I(SLEEP)
25
3
2.9
4.7
4.6
3.3
3.2
5
3.5
3.5
5.3
5.3
VDVDD
Internal logic regulator voltage
Internal logic regulator voltage
V
V
30-mA load, VVM = 13.5 V
2-mA load
VAVDD
30-mA load, VVM = 13.5 V
5
CHARGE PUMP (VCP, CPH, CPL)
VVM = 13.5 V; IVCP = 0 to 12 mA
VVM = 8 V; IVCP = 0 to 10 mA
VVM = 5.5 V; IVCP = 0 to 8 mA
VVM > 13.5 V
22.5
13.7
8.9
12
23.5
14
24.5
14.8
9.5
VVCP
VCP operating voltage
V
9.1
IVCP
Charge-pump current capacity
8 V < VVM < 13.5 V
10
mA
5.5 V < VVM < 8 V
8
CONTROL INPUTS (IN1/PH, IN2/EN, nSLEEP, MODE, nSCS, SCLK, SDI)
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIL
VIH
Vhys
IIL
Input logic-low voltage
Input logic-high voltage
Input logic hysteresis
Input logic-low current
Input logic-high current
0
0.8
1.5
100
–5
5.25
V
mV
µA
µA
VIN = 0 V
VIN = 5 V
5
IIH
70
IN1/PH, IN2/EN, nSLEEP, nSCS, SCLK,
SDI
RPD
Pulldown resistance
64
100
173
kΩ
RPD
RPU
Pulldown resistance
Pullup Resistance
MODE
MODE
65
26
kΩ
kΩ
CONTROL OUTPUTS (nFAULT, WDFAULT, SDO)
VOL
IOZ
Output logic-low voltage
IO = 2 mA
0.1
2
V
Output high-impedance leakage
5V pullup voltage
-2
µA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VVM > 13.5 V; VGSH with respect to SHx
10.5
10.5
11.5
6.8
4
High-side VGS gate drive (gate-to-
source)
VGSH
VVM = 8 V; VGSH with respect to SHx
VVM = 5.5 V; VGSH with respect to SHx
VVM > 10.5 V
5.7
3.4
V
V
Low-side VGS gate drive (gate-to-
source)
VGSL
VVM < 10.5 V
V
VM –2
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
20
50
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
70
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SRC_ High-side peak source current
mA
(VVM = 5.5V)
HS)
100
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
145
190
240
20
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
90
120
170
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SNK_ High-side peak sink current
mA
(VVM = 5.5V)
HS)
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
250
330
420
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
55
75
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SRC_ Low-side peak source current
mA
(VVM = 5.5V)
LS)
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
115
145
190
20
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
85
115
160
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SNK_ Low-side peak sink current
mA
(VVM = 5.5V)
LS)
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
235
300
360
10
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
50
70
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SRC_ High-side peak source current
mA
(VVM = 13.5V)
HS)
105
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
155
210
260
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
20
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
95
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
130
185
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SNK_ High-side peak sink current
mA
(VVM = 13.5V)
HS)
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
265
350
440
10
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
45
60
90
IDRIVE = 3’b011 (DRV8703)
IDRIVE = 3’b100 (DRV8703)
IDRIVE(SRC_ Low-side peak source current
mA
(VVM = 13.5V)
LS)
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
130
180
225
20
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
R(IDRIVE) < 1kΩto GND (DRV8702-Q1) or
IDRIVE = 3’b000 (DRV8703-Q1)
R(IDRIVE) = 33 kΩto GND (DRV8702-Q1)
or IDRIVE = 3’b001 (DRV8703-Q1)
40
R(IDRIVE) = 200 kΩto GND (DRV8702-
Q1) or IDRIVE = 3’b010 (DRV8703-Q1)
95
125
180
IDRIVE = 3’b011 (DRV8703-Q1)
IDRIVE = 3’b100 (DRV8703-Q1)
IDRIVE(SNK_ Low-side peak sink current
mA
(VVM = 13.5V)
LS)
R(IDRIVE) > 2 MΩto GND (DRV8702-Q1)
or IDRIVE = 3’b101 (DRV8703-Q1)
260
350
430
R(IDRIVE) = 68 kΩto AVDD (DRV8702-
Q1) or IDRIVE = 3’b110 (DRV8703-Q1)
R(IDRIVE) = 1 kΩto AVDD (DRV8702-Q1)
or IDRIVE = 3’b111 (DRV8703-Q1)
Source current after tDRIVE
Sink current after tDRIVE
GHx
10
40
IHOLD
FET holding current
mA
mA
kΩ
750
1000
150
150
ISTRONG
FET holdoff strong pulldown
FET gate holdoff resistor
GLx
Pulldown GHx to SHx
Pulldown GLx to GND
R(OFF)
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVREF
RVREF
AV
VREF input rms voltage
For current internal chopping
0.3(2)
3.6
V
DRV8702-Q1 and DRV8703-Q1
VREF_SCL = 00 (100%)
1
MΩ
VREF input impedance
DRV8703-Q1 VREF_SCL = 2’b01, 2’
b10 or 2’b11
175
19.8
10
kΩ
Amplifier gain (DRV8702-Q1)
60 < VSP < 225 mV; VSN = GND
19.3
9.75
20.3
V/V
GAIN_CS = 00; 10 < VSP < 450 mV; VSN
= GND
10.25
GAIN_CS = 01; 60 < VSP < 225 mV; VSN
= GND
19.3
38.4
73
19.8
39.4
78
20.3
40.4
AV
Amplifier gain (DRV8703-Q1)
V/V
GAIN_CS = 10; 10 < VSP < 112 mV; VSN
GND
=
GAIN_CS = 11; 10 < VSP < 56 mV; VSN
GND
=
81
10
VIO
Input-referred offset
VSP = VSN = GND
5
10
mV
µV/°C
µA
VIO(DRIFT) Drift offset(2)
VSP = VSN = GND
ISP
SP input current
VSP = 100 mV; VSN = GND
–20
VSO
C(SO)
SO pin output voltage range
Allowable SO pin capacitance
AV × Vio
4.5
1
V
nF
PROTECTION CIRCUITS
VM falling; UVLO2 report
VM rising; UVLO2 recovery
5.25
5.4
5.45
5.65
4.5
V(UVLO2) VM undervoltage lockout
V
V(UVLO1)
Logic undervoltage lockout
V
Vhys(UVLO) VM undervoltage hysteresis
Rising to falling threshold
VCP falling; CPUV report
100
mV
VVM + 1.5
V(CP_UV)
Charge pump undervoltage
V
VVM
1.55
+
VCP rising; CPUV recovery
Vhys(CP_UV) CP undervoltage hysteresis
Rising to falling threshold
R(VDS) < 1 kΩto GND
R(VDS) = 33 kΩto GND
R(VDS) = 200 kΩto GND
R(VDS) > 2 MΩto GND
R(VDS) = 68 kΩto AVDD
R(VDS) < 1 kΩto AVDD
VDS_LEVEL = 3’b000
VDS_LEVEL = 3’b001
VDS_LEVEL = 3’b010
VDS_LEVEL = 3’b011
VDS_LEVEL = 3’b100
VDS_LEVEL = 3’b101
VDS_LEVEL = 3’b110
VDS_LEVEL = 3’b111
50
mV
0.06
0.12
0.24
0.48
0.96
Disabled
0.06
0.145
0.17
0.2
Overcurrent protection trip level, VDS
of each external FET (DRV8702-Q1)
VDS(OCP)
V
High side FETs: VDRAIN –SHx
Low side FETs: SHx –SP/SL2
Overcurrent protection trip level, VDS
of each external FET (DRV8703-Q1)
High-side FETs: VDRAIN –SHx
VDS(OCP)
V
V
0.12
0.24
0.48
0.96
Low-side FETs: SHx –SP/SL2
Overcurrent protection trip level,
VSP(OCP)
VSP with respect to GND
0.8
1
1.2
measured by sense amplifier
T(OTW)
TSD
Thermal warning temperature(1)
Thermal shutdown temperature(1)
Thermal shutdown hysteresis(1)
Die temperature TJ
Die temperature TJ
Die temperature TJ
120
150
135
145
°C
°C
°C
Thys
20
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Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
Positive clamping voltage
Negative clamping voltage
MIN
16.3
–1
TYP
MAX
UNIT
17
17.8
VC(GS)
Gate-drive clamping voltage
V
–0.7
–0.5
(1) Ensured by design and characterization data.
(2) Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
6.6 SPI Timing Requirements
MIN
100
50
NOM
MAX
UNIT
t(CLK)
Minimum SPI clock period
Clock high time
ns
ns
ns
ns
ns
ns
ns
ns
ns
t(CLKH)
t(CLKL)
t(SU_SDI)
t(HD_SDI)
Clock low time
50
SDI input data setup time
SDI input data hold time
20
30
t(HD_SDO) SDO output hold time
t(SU_SCS) SCS setup time
t(HD_SCS) SCS hold time
40
50
50
t(HI_SCS)
SCS minimum high time before SCS active low
400
6.7 Switching Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
t(SLEEP)
t(wu)
Sleep time
nSLEEP = low to sleep mode
nSLEEP = high to output change
VM > UVLO2 to output transition
100
1
µs
ms
ms
Wake-up time
Turn on time
ton
1
CHARGE PUMP (VCP, CPH, CPL)
fS(VCP) Charge-pump switching frequency
VM > UVLO2
200
400
500
700
kHz
ns
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI, PH, EN)
tpd Propagation delay IN1, IN2 to GHx or GLx
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
Observed t(DEAD) depends on
IDRIVE setting
t(DEAD)
Output dead time (DRV8702-Q1)
240
120
240
480
ns
TDEAD = 2’b00; Observed t(DEAD)
depends on IDRIVE setting
TDEAD = 2’b01; Observed t(DEAD)
depends on IDRIVE setting
t(DEAD)
Output dead time (DRV8703-Q1)
ns
µs
TDEAD = 2’b10; Observed t(DEAD)
depends on IDRIVE setting
TDEAD = 2’b11; Observed t(DEAD)
depends on IDRIVE setting
960
2.5
t(DRIVE)
Gate drive time
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
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Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSP = VSN = GND to VSP = 240 mV,
VSN = GND, AV= 10; C(SO) = 200 pF
0.5
1
VSP = VSN = GND to VSP = 120 mV,
VSN = GND, AV= 20; C(SO) = 200 pF
tS
Settling time to ±1%(1)
µs
VSP = VSN = GND to VSP = 60 mV,
VSN = GND, AV= 40; C(SO) = 200 pF
2
VSP = VSN = GND to VSP = 30 mV,
VSN = GND, AV= 80; C(SO) = 200 pF
4
toff
PWM off-time (DRV8702-Q1)
PWM off-time (DRV8703-Q1)
PWM blanking time
25
25
µs
µs
µs
TOFF = 00
TOFF = 01
TOFF = 10
TOFF = 11
50
toff
100
200
2
t(BLANK)
PROTECTION CIRCUITS
t(UVLO) VM UVLO falling deglitch time
t(OCP)
VM falling; UVLO report
10
4
µs
µs
Overcurrent deglitch time
Overcurrent retry time
3.7
2.8
4.3
3.2
t(RETRY)
3
ms
10
20
50
100
64
WD_DLY = 2’b00
WD_DLY = 2’b01
WD_DLY = 2’b10
WD_DLY = 2’b11
t(WD)
Watchdog time out (DRV8703-Q1)
Watchdog timer reset period
ms
µs
t(RESET)
SPI
t(SPI_READY) SPI read after power on
VM > VUVLO1
CL = 20 pF
5
10
30
ms
ns
SDO output data delay time, CLK
high to SDO valid
td(SDO)
ta
SCS access time, SCS low to SDO
out of high impedance
10
10
ns
ns
SCS disable time, SCS high to SDO
high impedance
tdis
(1) Ensured by design
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6.8 Typical Characteristics
8.4
8.1
7.8
7.5
7.2
6.9
6.6
6.3
8.4
8.1
7.8
7.5
7.2
6.9
6.6
6.3
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
TA = -40èC
TA = 25èC
TA = 125èC
-50
-25
0
25
50
75
100
125
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
Temperature (èC)
D002
D001
图6-2. Supply Current vs Temperature
图6-1. Supply Current vs Supply Voltage (VM)
21
21
19
17
15
13
11
9
TA = -40èC
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
TA = 25èC
19
TA = 125èC
17
15
13
11
9
7
7
5
10
15
20
Supply Voltage (V)
25
30
35
40
45
-50
-25
0
25
50
75
100
125
Temperature (èC)
D003
D004
图6-3. Sleep Current vs Supply Voltage (VM)
图6-4. Sleep Current vs Temperature
3.4
5.1
TA = -40èC
TA = 25èC
TA = 125èC
3.35
5.05
5
3.3
3.25
3.2
4.95
4.9
TA = -40èC
3.15
3.1
TA = 25èC
TA = 125èC
5
10
15
20
Supply Voltage (V)
25
30
35
40
45
5
10
15
20
Supply Voltage (V)
25
30
35
40
45
D005
D006
2-mA load
2-mA load
图6-5. DVDD Regulator
图6-6. AVDD Regulator
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3.26
3.24
3.22
3.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
3.18
3.16
3.14
3.12
3.1
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
3.08
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
5
10
15
20
25
30
Supply Voltage (V)
35
40
45
50
D007
D008
30-mA load
30-mA load
图6-7. DVDD Regulator
图6-8. AVDD Regulator
10
9.98
9.96
9.94
9.92
9.9
19.9
19.84
19.78
19.72
19.66
19.6
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D010
D009
19.8-V/V gain
10-V/V gain
图6-10. Amplifier Gain
图6-9. Amplifier Gain
40
79
78.8
78.6
78.4
78.2
78
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
39.8
39.6
39.4
39.2
39
77.8
77.6
77.4
77.2
77
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D012
D011
78-V/V gain
39.4-V/V gain
图6-12. Amplifier Gain
图6-11. Amplifier Gain
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0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.03
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D013
D014
VDS(OCP) = 0.06 V
VDS(OCP) = 0.12 V
图6-13. OCP Threshold Voltage
图6-14. OCP Threshold Voltage
0.19
0.18
0.17
0.16
0.15
0.14
0.27
0.26
0.25
0.24
0.23
0.22
0.21
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D015
D016
VDS(OCP) = 0.17 V
VDS(OCP) = 0.24 V
图6-15. OCP Threshold Voltage
图6-16. OCP Threshold Voltage
0.51
0.505
0.5
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.495
0.49
0.485
0.48
0.475
0.47
0.465
0.46
0.455
0.45
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D017
D018
VDS(OCP) = 0.48 V
VDS(OCP) = 0.96 V
图6-17. OCP Threshold Voltage
图6-18. OCP Threshold Voltage
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300
500
450
400
350
300
250
200
150
100
50
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
250
200
150
100
50
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D019
D020
VVM = 5.5 V
VVM = 5.5 V
图6-19. High-Side Source Current
图6-20. High-Side Sink Current
250
200
150
100
50
450
400
350
300
250
200
150
100
50
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D022
D021
VVM = 5.5 V
VVM = 5.5 V
图6-22. Low-Side Sink Current
图6-21. Low-Side Source Current
350
300
250
200
150
100
50
550
500
450
400
350
300
250
200
150
100
50
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D023
D024
VVM = 13.5 V
VVM = 13.5 V
图6-23. High-Side Source Current
图6-24. High-Side Sink Current
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300
550
500
450
400
350
300
250
200
150
100
50
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
250
200
150
100
50
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D025
D026
VVM = 13.5 V
VVM = 13.5 V
图6-25. Low-Side Source Current
图6-26. Low-Side Sink Current
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7 Detailed Description
7.1 Overview
DRV87002-Q1 and DRV87003-Q1 are single H-bridge drivers, also referred to as gate controllers. The drivers
control four external NMOS FETs used to drive a bi-directional brushed-DC motors. The devices can also
operate in independent half bridge mode to drive two single directional brushed-DC motors.
The devices can support supply voltages from 5.5 V to 45 V and have a low power sleep mode enabled through
the nSLEEP pin. There are three options for the interface modes including a configurable PH/EN, independent
H-bridge control, or PWM interface. This allows easy interfacing to the controller circuit.
DRV87002-Q1 and DRV87003-Q1 include Smart Gate Drive technology which offers a combination of protection
features and gate-drive configurability to improve design simplicity and bring a new level of intelligence to motor
systems. The gate-drive strength, or gate-drive current can be adjusted through the driver itself to optimize for
different FETs and applications without the need for external resistors. Smart Gate Drive significantly reduces the
component count of discrete motor-driver systems by integrating the required FET drive circuitry into a single
device. The peak current can be adjusted through the IDRIVE pin for DRV8702-Q1 and through SPI for
DRV8703-Q1. Both the high-side and low-side FETs are driven with a gate source voltage (VGS) of 10.5 V
(nominal) when the VM voltage is more than 13.5 V. At lower VM voltages, the VGS is reduced. The high-side
gate drive voltage is generated using a doubler-architecture charge pump that regulates to the VM + 10.5 V.
The inrush or start up current and running current can be limited through a built in fixed time-off current chopping
scheme. The chopping current level is set through the sense resistor by setting a voltage on the VREF pin. See
the current regulation section for more information. A shunt-amplifier is also included in the devices to provide
accurate current measurements to the system controller. The SO pin outputs a voltage that is approximately 20
times the voltage across the sense resistor on the DRV8702-Q1 device. For the DRV8703-Q1, this gain is
configurable.
The DRV870x-Q1 device also has protection features beyond traditional discrete implementations including:
undervoltage lockout (UVLO), overcurrent protection (OCP), gate driver faults, and thermal shutdown (TSD).
The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal
charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the
device.
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7.2 Functional Block Diagram
VM
0.1 …F
10 µF
(minimum)
VM
VM
VM
Gate Driver
VVCP
Power
VDRAIN
GH1
1 µF
VCP
HS
LS
CPH
Charge Pump
SH1
GL1
VGLS
0.1 µF
CPL
DVDD
3.3-V LDO
Logic
1 µF
VM
BDC
AVDD
5-V LDO
Gate Driver
VVCP
1 µF
VGLS LDO
GH2
SH2
GL2
SL2
HS
LS
VGLS
IN1/PH
IN2/EN
nSLEEP
Current Regulation
Control Inputs
SP
MODE
+
AV
R(SENSE)
IDRIVE
SN
SO
œ
RIDRIVE
VDS
RVDS
VREF
Output
nFAULT
PAD
PAD
PAD
图7-1. DRV8702-Q1 Functional Block Diagram
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VM
0.1 …F
10 µF
(minimum)
VM
VM
VM
Power
1 µF
VCP
VDRAIN
GH1
Gate Driver
VVCP
CPH
Charge Pump
HS
LS
0.1 µF
CPL
SH1
GL1
VGLS
DVDD
3.3-V LDO
1 µF
Logic
AVDD
5-V LDO
VM
BDC
Gate Driver
VVCP
1 µF
VGLS LDO
GH2
HS
LS
IN1/PH
IN2/EN
SH2
GL2
VGLS
SL2
Control Inputs
nSLEEP
Current Regulation
SP
MODE
Outputs
nFAULT
AV
R(SENSE)
+
-
SN
SO
nWDFLT
VREF
SCLK
SDI
SPI
SDO
nSCS
PAD
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PAD
PAD
图7-2. DRV8703-Q1 Functional Block Diagram
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7.3 Feature Description
表7-1 and 表7-2 list the recommended external components for the device.
表7-1. External Components
COMPONENT
C(VM1)
PIN 1
VM
PIN 2
GND
RECOMMENDED
0.1-µF ceramic capacitor rated for VM
≥10-µF electrolytic capacitor rated for VM
16-V, 1-µF ceramic capacitor
0.1-µF X7R capacitor rated for VM
6.3-V, 1-µF ceramic capacitor
6.3-V, 1-µF ceramic capacitor
For resistor sizing, see the 节8.2 section
For resistor sizing, see the 节8.2 section
≥10 kΩ
C(VM2)
VM
GND
C(VCP)
VCP
VM
C(SW)
CPH
CPL
C(DVDD)
C(AVDD)
R(IDRIVE)
R(VDS)
DVDD
AVDD
IDRIVE
VDS
GND
GND
GND
GND
(1)
R(nFAULT)
R(nWDFLT)
R(SENSE)
VCC
nFAULT
nWDFLT
SN or GND
VM
(1)
VCC
≥10 kΩ
SP
Optional low-side sense resistor
100-Ωseries resistor
(2)
R(VDRAIN)
VDRAIN
(1) The VCC pin is not a pin on the DRV870x-Q1, but a VCC supply voltage pullup is required for open-drain outputs nFAULT. These pins
can be pulled up to either AVDD or DVDD.
(2) The R(VDRAIN) resistor should be used between the VDRAIN and VM pins to minimize current to the VDRAIN pin if no external reverse
battery protection is implemented on the VDRAIN pin.
表7-2. External Gates
COMPONENT
Q(HS1)
GATE
GH1
GL1
DRAIN
SOURCE
RECOMMENDED
VM
SH1
Supports FETs up to 200 nC at 40 kHz
PWM
Q(LS1)
SH1
VM
SP or GND
SH2
Q(HS2)
GH2
GL2
For more information, see 节8
Q(LS2)
SH2
SP or GND
7.3.1 Bridge Control
The DRV870x-Q1 device is controlled using a configurable input interface. The 节 7.3.1.1 section provides the
full H-bridge state . These tables do not consider the current control built into the DRV870x-Q1 device. Positive
current is defined in the direction of SH1 → SH2. The logic operation set by the MODE pin is latched on power-
up or when exiting sleep mode.
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VM
VM
1
2
3
1
Reverse drive
Forward drive
2
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
3
SH2
SH2
SH1
SH1
2
3
2
3
图7-3. Bridge Control
7.3.1.1 Logic Tables
表7-3, 表7-4, and 表7-5 are the device logic tables. An X denotes a don’t care input or output.
表7-3. DRV870x-Q1 PH and EN Control Interface (MODE = 0)
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
Hi-Z
L
GH2
GL2
SH2
Hi-Z
L
AVDD/DVDD
Disabled
Enabled
DESCRIPTION
0
1
1
1
X
X
0
1
X
0
1
1
X
0
0
1
X
X
0
1
0
X
Sleep mode H bridge disabled Hi-Z
Brake low-side slow decay
1
1
1
L
0
H
Enabled
Reverse (Current SH2 →SH1)
Forward (Current SH1 →SH2)
0
H
1
L
Enabled
表7-4. DRV870x-Q1 Independent PWM Control Interface (MODE = 1)
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
Hi-Z
X
GH2
GL2
SH2
Hi-Z
L
AVDD/DVDD
Disabled
Enabled
DESCRIPTION
Sleep mode H bridge disabled Hi-Z
Half-bridge 2 low side on
Half-bridge 2 high side on
Half-bridge 1 low side on
Half-bridge 1 high side on
0
1
1
1
1
X
X
X
0
X
0
X
X
X
X
X
X
0
1
1
X
X
X
1
0
H
Enabled
X
X
0
1
L
X
X
X
Enabled
1
1
0
H
X
X
X
Enabled
表7-5. DRV870x-Q1 Standard PWM Control Interface (MODE = Hi-Z)
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
Hi-Z
Hi-Z
L
GH2
GL2
SH2
Hi-Z
Hi-Z
H
AVDD/DVDD
Disabled
Enabled
DESCRIPTION
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
0
0
1
0
X
X
0
1
0
0
X
Sleep mode H bridge disabled Hi-Z
Coast H bridge disabled Hi-Z
Reverse (Current SH2 →SH1)
Forward (Current SH1 →SH2)
Brake low-side slow decay
0
0
1
0
Enabled
0
H
1
L
Enabled
1
L
1
L
Enabled
7.3.2 MODE Pin
The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep
mode. 图7-4 shows an overview of the internal circuit of the MODE pin.
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DVDD
+
œ
1.35 V
Digital
Core
26 kꢀ
MODE
+
65 kꢀ
œ
0.75 V
图7-4. MODE Pin Block Diagram
表7-6 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep mode.
表7-6. MODE Pin Configuration
MODE
CONTROL INTERFACE
0
1
PH or EN
Independent half-bridge
PWM
Hi-Z
During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the
AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to
the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin
if not driven by an external microcontroller (MCU).
7.3.3 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low.
Output
nFAULT
图7-5. nFAULT Block Diagram
For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the 节8 section). For a 5-
V pullup an external 5-V supply should be used. TI does not recommended connecting the nFAULT pin to the
AVDD pin.
7.3.4 Current Regulation
The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or
current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a
rate dependent on the DC voltage and inductance of the winding. When the current hits the current chopping
threshold, the bridge enters a brake (low-side slow decay) mode until the toff time expires.
备注
Immediately after the current is enabled, the voltage on the SP pin is ignored for a period (t(BLANK)
)
before enabling the current-sense circuitry.
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The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor
connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV
is the shunt-amplifier gain, which is 19.8 V/V for the DRV8702-Q1 device or configurable to 10, 19.8, 39.4, or 78
V/V for the DRV8703-Q1 device.
Use 方程式1 to calculate the chopping current (ICHOP).
VVREF - V ì AV
AV ì R(SENSE)
IO
I(CHOP)
=
(1)
For example, if a 50-mΩ sense resistor and a VREF value of 3.3 V are selected, the full-scale chopping current
is 3.28 A. The AV is 19.8 V/V and VIO is assumed to be 50 mV in this example.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current
regulation feature is not needed, it can be disabled by tying the VREF pin directly to the AVDD pin. If the
independent PWM control-interface mode (MODE pin is 1) is selected for operation, the device does not perform
PWM current regulation or current chopping.
7.3.5 Amplifier Output (SO)
The SO pin on the DRV870x-Q1 device outputs an analog voltage equal to the voltage across the SP and SN
pins multiplied by AV. The SO voltage is only valid for forward or reverse drive. Use 方程式 2 to calculate the
approximate current for the H-bridge.
VSO - V ì AV
AV ì R(SENSE)
IO
I =
(2)
When the SP and SN voltages are 0 V, the SO pin outputs the amplifier offset voltage times the amplifier gain,
Vio × Av. When SP minus SN is greater than 0 V, the SO pin outputs the sum of the amplifier offset voltage and
the sense resist or voltage, times the amplifier gain, (Vio + Vrsense) × Av. No capacitor is required on the SO pin.
AVDD
AV
VIO × AV
SP-SN (V)
图7-6. Current Sense Amplifier Output
If the voltage across the SP and SN pins exceeds 1 V, then the DRV870x-Q1 device flags an overcurrent
condition.
The SO pin can source up to 5 mA of current. If the pin is shorted to ground, or if this pin drives a higher current
load, the output functions as a constant-current source. The output voltage is not representative of the H-bridge
current in this state.
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I(CHOP)
Drive
Brake and Slow Decay
tOFF
Drive
Brake and Slow Decay
tOFF
t(DRIVE)
t(DRIVE)
(Vio+Vrsense) x AV
(Vio+Vrsense) x AV
VVREF
图7-7. Current Sense Amplifier and Current Chopping Operation
During brake mode (slow decay), current is circulated through the low-side FETs. Because current is not flowing
through the sense resistor, the SO pin does not represent the motor current.
7.3.5.1 SO Sample and Hold Operation
The DRV8703-Q1 device allows the shunt amplifier to operate in a sample and hold configuration. To enable this
mode, set the SH_EN bit high through the SPI. In this mode, the shunt amplifier output is disabled to the
Hi-Z state whenever the driver is in a brake mode. Place an external capacitor on this pin.
I(CHOP)
Drive
Brake and Slow Decay
tOFF
Drive
Brake and Slow Decay
tOFF
t(DRIVE)
t(DRIVE)
(Vio+Vrsense) x AV
(Vio+Vrsense) x AV
VVREF
SO Output Hi-Z
SO Output Hi-Z
图7-8. Sample and Hold Operation
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7.3.6 PWM Motor Gate Drivers
The DRV870x-Q1 device has gate drivers for a single H-bridge with external NMOS FETs. 图 7-9 shows a block
diagram of the predrive circuitry.
VGHS
VM
GH1
R(OFF)
IN1/PH
SH1
Predrive
VGLS
IN2/EN
GL1
nSLEEP
BDC
R(OFF)
Logic
VGHS
VM
GH2
SH2
R(OFF)
Predrive
VGLS
GL2
R(OFF)
SP
SN
R(SENSE)
图7-9. Predrive Block Diagram
Gate drivers inside the DRV870x-Q1 device directly drive N-Channel MOSFETs, which drive the motor current.
The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate
drive.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702-Q1 device or the
IDRIVE register for the DRV8703-Q1 device. Peak source currents can be set to the values listed in the FET
gate drivers section of the 节 6.5 table. The peak sink current is approximately two times the peak source
current. Adjusting the peak current changes the output slew rate, which also depends on the FET input
capacitance and gate charge.
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Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically
because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts
reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation
because the external FETs have a longer turn on and turn off time.
When changing the state of the output, the peak current (IDRIVE) is applied for a short period (t(DRIVE)), to charge
the gate capacitance. After this time, a weak current source (IHOLD) is used to keep the gate at the desired state.
When selecting the gate drive strength for a given external FET, the selected current must be high enough to
charge fully and discharge the gate during t(DRIVE), or excessive power is dissipated in the FET.
During high-side turn on, the low-side gate is pulled low with a strong pulldown (ISTRONG). This pulldown
prevents the low-side FET QGS from charging and keeps the FET off, even when fast switching occurs at the
outputs.
The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents
the high-side or low-side FET from turning on until the opposite FET turns off.
t(DRIVE)
IHOLD
IDRIVE(SNK)
High-side
gate drive
current
ISTRONG
ISTRONG
High-side
VGS
tDRIVE
IHOLD
IHOLD
Low-side
gate drive
current
IDRIVE(SNK)
ISTRONG
Low-side
VGS
图7-10. Gate Driver Output to Control External FETs
7.3.6.1 Miller Charge (QGD
)
When a FET gate turns on, the following capacitances must be charged:
• Gate-to-source charge, QGS
• Gate-to-drain charge, QGD (Miller charge)
• Remaining QG
The FET output is slewing primarily during the QGD charge.
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24 V
25
20
10
8
D
VGHS
6
15
10
5
G
GHx
Predrive
4
SHx
2
S
10
20
30
40
50
QGS
QGD
Gate Charge (nC)
图7-11. FET Gate Charging Profile
7.3.7 IDRIVE Pin (DRV8702-Q1 Only)
The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is selected.
The ramp of the FET gate directly affects the rise and fall times of the H-bridge output.
Tying the IDRIVE pin to ground selects the lowest drive setting of 10-mA source and 20-mA sink. Leaving this
pin open selects the drive setting of 155-mA high side and 130-mA low side for source current, and 265-mA high
side, 260-mA low side for sink current, at a VM voltage of 13.5 V. For a detailed list of IDRIVE configurations,
see 表7-7.
+
œ
4.9 V
3.7 V
2.5 V
AVDD
+
190 kΩ
œ
IDRIVE
+
310 kΩ
Digital
Core
œ
+
œ
1.3 V
0.1 V
+
œ
图7-12. IDRIVE Pin Internal Circuitry
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表7-7. DRV8702-Q1 IDRIVE Settings
SOURCE CURRENT
SINK CURRENT
IDRIVE
RESISTANCE
IDRIVE
VOLTAGE
CIRCUIT
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
IDRIVE
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
GND
0.7 V ± 5%
2 V ± 5%
3 V ± 5%
4 V ± 5%
AVDD
< 1 kΩto GND
IDRIVE
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
33 kΩ± 5% to
GND
RIDRIVE
IDRIVE
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
200 kΩ± 5% to
GND
RIDRIVE
IDRIVE
High-side: 145 mA High-side: 155 mA High-side: 250 mA High-side: 265 mA
Low-side: 115 mA Low-side: 130 mA Low-side: 235 mA Low-side: 260 mA
> 2 MΩto GND,
Hi-Z
AVDD
High-side: 190 mA High-side: 210 mA High-side: 330 mA High-side: 350 mA
Low-side: 145 mA Low-side: 180 mA Low-side: 300 mA Low-side: 350 mA
68 kΩ± 5% to
IDRIVE
AVDD
AVDD
High-side: 240 mA High-side: 260 mA High-side: 420 mA High-side: 440 mA
Low-side: 190 mA Low-side: 225 mA Low-side: 360 mA
< 1 kΩto AVDD
IDRIVE
Low-side:430 mA
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7.3.8 Dead Time
The dead time (t(DEAD)) is measured as the time when the SHx pin is in the Hi-Z state between turning off one of
the H-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side
FET and turning on the low-side FET.
The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702-Q1 device has a
digital dead time of approximately 240 ns. The DRV8703-Q1 device has programmable dead-time options of
120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the
GLx pin to ground or GHx pin to SHx pin is less than the FET threshold voltage.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx
and GLx pins) includes the observable dead time.
7.3.9 Propagation Delay
The propagation delay time (tPD) is measured as the time between an input edge to an output change. This time
is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on
the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, one FET must first be turned off. The FET gate is ramped down according to the IDRIVE resistor
selection, and the observed propagation delay ends when the FET gate falls below the threshold voltage.
7.3.10 Overcurrent VDS Monitor
The gate-driver circuit monitors the VDS voltage of each external FET when it is driving current. When the
voltage monitored is greater than the OCP threshold voltage (VDS(OCP)) after the OCP deglitch time has expired,
an OCP condition is detected. The VDS(OCP) voltage can be adjusted by changing the resistor (RVDS) on the VDS
pin of the DRV8702-Q1 device. The DRV8703-Q1 device provides VDS(OCP) voltage levels by setting the VDS
register.
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VM
VDRAIN
GH1
+
High-Side
VDS OCP
Monitor 1
SH1
GL1
œ
+
Low-Side
VDS OCP
Monitor 1
BDC
+
GH2
High-Side
VDS OCP
Monitor 2
œ
SH2
GL2
œ
+
Low-Side
VDS OCP
Monitor 2
SL2
SP
œ
R(SENSE)
SN
图7-13. VDS(OCP) Block Diagram
The VDS voltage on the high-side FET is measured across the VDRAIN to SHx pins. The low-side VDS monitor
on half-bridge 1 measures the VDS voltage across the SH1 to SP pins. The low-side VDS monitor on half-bridge
2 measures the VDS voltage across the SH2 to SL2 pins. Ensure that the SP pin is always connected to the
source of the low-side FET of half-bridge 1, even when the sense amplifier is not used.
7.3.11 VDS Pin (DRV8702-Q1 Only)
The VDS pin on the DRV8702-Q1 device is used to select the VDS threshold voltage for overcurrent detection.
Tying the VDS pin to ground selects the lowest setting of 0.06 V. Leaving this pin open selects the setting of
0.48 V. Tying the VDS pin to the AVDD the pin disables the VDS monitor. For a detailed list of VDS
configurations, see 表7-8.
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+
œ
4.9 V
3.7 V
2.5 V
AVDD
+
190 kΩ
œ
VDS
+
310 kΩ
Digital
Core
œ
+
œ
1.3 V
0.1 V
+
œ
图7-14. VDS Block Diagram
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表7-8. VDS Pin Resistor Setting
OVERCURRENT
TRIP LEVEL
VDS RESISTANCE
VDS VOLTAGE
CIRCUIT
(VDS(OCP)
)
VDS
GND
0.06 V
< 1 kΩto GND
33 kΩ± 5% to GND
200 kΩ± 5% to GND
> 2 MΩto GND, Hi-Z
68 kΩ± 5% to AVDD
< 1 kΩto AVDD
VDS
0.7 V ± 5%
2 V ± 5%
3 V ± 5%
4 V ± 5%
AVDD
0.12 V
0.24 V
0.48 V
0.96 V
RIDRIVE
VDS
RIDRIVE
VDS
AVDD
VDS
AVDD
Disabled
VDS
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7.3.12 Charge Pump
A charge pump is integrated to supply the gate drive voltage of a high-side NMOS (VGSH). The charge pump
requires a capacitor between the VM and VCP pins. Additionally, a low-ESR ceramic capacitor is required
between the CPH and CPL pins. When the VM voltage is below 13.5 V, this charge pump functions as a doubler
and generates a VVCP equal to 2 × VVM – 1.5 V if unloaded. When the VM voltage is more than 13.5 V, the
charge pump regulates VVCP such that it is equal to VVM + 10.5 V.
VM
1 ꢀF
VCP
CPH
VM
Charge
Pump
0.1 ꢀF
CPL
图7-15. Charge Pump Block Diagram
7.3.13 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VC(GS) voltage to protect the power FETs from
damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the
body diodes of the internal predriver FET.
VGHS
VM
I(REVERSE)
GHx
VGS > VC
IC
SHx
Predriver
VGLS
VGS negative
GLx
R(SENSE)
PGND
图7-16. Gate Drive Clamp
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7.3.14 Protection Circuits
The DRV870x-Q1 device is protected against VM undervoltage, charge-pump undervoltage, overcurrent, gate-
driver shorts, and overtemperature events.
7.3.14.1 VM Undervoltage Lockout (UVLO2)
If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), all FETs in the
H-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of the
DRV8703-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold. The
nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703-Q1 device remains
set until cleared by writing to the CLR_FLT bit.
The SPI settings on the DRV8703-Q1 device are not reset by this fault even though the output drivers are
disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic
undervoltage threshold (VUVLO1).
7.3.14.2 Logic Undervoltage (UVLO1)
If the voltage on the VM pin falls below the logic undervoltage threshold voltage (VUVLO1), the internal logic is
reset. The operation resumes when the VM voltage rises above the UVLO1 threshold. The nFAULT pin is logic
low during this state because it is pulled low when the VM undervoltage condition occurs. Decreasing the VM
voltage below this undervoltage threshold resets the SPI settings.
7.3.14.3 VCP Undervoltage Lockout (CPUV)
If the voltage on the VCP pin falls below the threshold voltage of the charge-pump undervoltage (CPUV) lockout,
all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The DRV8703-Q1 the VCP_UVFL bit is
set. The operation resumes when the VCP voltage rises above the CPUV threshold. The nFAULT pin is released
after the operation resumes but the VCP_UVFL bit on the DRV8703-Q1 device remains set until cleared by
writing to the CLR_FLT bit.
7.3.14.4 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a
driven FET exceeds the VDS(OCP) level for longer than the OCP deglitch time, an OCP event is recognized. All
FETs in the H-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703-Q1 device is
set. The drive re-enables after the t(RETRY) time has passed. The nFAULT pin becomes high again after the retry
time.
If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes
and the nFAULT pin goes high. The OCP bit on the DRV8703-Q1 remains set until cleared by writing to the
CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP
pin exceeds VSP(OCP) and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.
7.3.14.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase or
decrease after the t(DRIVE) time, a gate driver fault is detected. This fault occurs if the GHx or GLx pins are
shorted to the GND, SHx, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not
sufficient to turn on the external FET. All FETs in the H-bridge are disabled, and the nFAULT pin is driven low.
The GDF bit of the DRV8703-Q1 device is set. The driver re-enables after the OCP retry period (t(RETRY)) has
passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703-Q1
device remains set until cleared by writing to the CLR_FLT bit.
7.3.14.6 Thermal Shutdown (TSD)
If the die temperature exceeds the TSD temperature, all FETs in the H-bridge are disabled, the charge pump
shuts down, the AVDD regulator is disabled, and the nFAULT pin is driven low. The OTSD bit of the DRV8703-
Q1 device is set as well. After the die temperature falls below TSD – Thys temperature, device operation
automatically resumes. The nFAULT pin is released after the operation resumes, but the OTSD bit on the
DRV8703-Q1 device remains set until cleared by writing to the CLR_FLT bit.
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7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
An MCU watchdog function can be enabled to ensure that the external controller that is instructing the
DRV8703-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the
WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts
to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within
the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is
enabled. When the nWDFLT pin is enabled the following occurs:
• The nWDFLT pin goes low for 64 µs.
• The nFAULT pin is asserted.
• The WD_EN bit is cleared.
• The drivers are disabled.
The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.
表7-9 lists the fault responses of the device under the fault conditions.
表7-9. Fault Response
FAULT
CONDITION
H-BRIDGE
CHARGE PUMP
AVDD
DVDD
RECOVERY
VM undervoltage
(UVLO)
V
VM ≤V(UVLOx)
V
VM ≥V(UVLOx)
Disabled
Disabled
Disabled
Operating
(5.45 V, max)
(5.65 V, max)
VCP undervoltage
(CPUV)
V
VCP ≤V(CP_UV)
V
VCP ≥V(CP_UV)
Disabled
Operating
Operating
Operating
(VVM + 1.5, typ)
(VVM + 1.5, typ)
External FET overload
(OCP)
VDS ≥VDS(OCP)
Disabled
Disabled
Disabled
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Disabled
Operating
Operating
Operating
Operating
t(RETRY)
V
SP –VSN > 1 V
Gate driver fault
(GDF)
Gate voltage unchanged after
t(DRIVE)
t(RETRY)
Watchdog fault
(WDFLT)
Watchdog timer expires
CLR_FLT bit
Thermal shutdown
(TSD)
T
J ≤TSD –Thys
(Thys is typically 20°C)
T
J ≥TSD (150°C, min)
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7.3.14.8 Reverse Supply Protection
The circuit in 图 7-17 can be implemented to help protect the system from reverse supply conditions. This circuit
requires the following additional components:
• NMOS FET
• NPN BJT
• Diode
• 10-kΩresistor
• 43-kΩresistor
VM
43 kΩ
10 kΩ
0.1 µF
1 µF
+
Bulk
10 µF (min)
0.1 µF
CP1
CP2
VCP
VM
GH1
SH1
GL1
BDC
GH2
SH2
GL2
SP
SN
R(SENSE)
图7-17. Reverse Supply Protection
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7.3.15 Hardware Interface
The DRV8702-Q1 hardware interface allows the device to be configured without a SPI, however not all of the
functionality is configurable like the DRV8703-Q1 device. The following configuration settings are fixed for the
hardware-interface device option:
• The toff value is set to 25 µs.
• Current regulation is enabled
• The VREF pin voltage is not scaled internally (100%).
• The shunt amplifier has a fixed gain of 19.8 V/V.
7.3.15.1 IDRIVE (6-level input)
The voltage or resistance on the IDRIVE pin sets the peak source and peak sink IDRIVE setting as listed in 表
7-10.
表7-10. DRV8702-Q1 IDRIVE Settings
SOURCE CURRENT
SINK CURRENT
VVM = 13.5 V
IDRIVE
RESISTANCE
IDRIVE VOLTAGE
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
GND
0.7 V ± 5%
2 V ± 5%
3 V ± 5%
4 V ± 5%
AVDD
< 1 kΩto GND
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
33 kΩ± 5% to
GND
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
200 kΩ± 5% to
GND
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
> 2 MΩto GND,
Hi-Z
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
68 kΩ± 5% to
AVDD
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side:430 mA
< 1 kΩto AVDD
7.3.15.2 VDS (6-Level Input)
This input controls the VDS monitor trip voltage as listed in 表7-11.
表7-11. DRV8702-Q1 VDS Settings
OVERCURRENT TRIP LEVEL
VDS RESISTANCE
VDS VOLTAGE
(VDS(OCP)
0.06 V
0.12 V
0.24 V
0.48 V
0.96 V
)
GND
0.7 V ± 5%
2 V ± 5%
3 V ± 5%
4 V ± 5%
AVDD
< 1 kΩto GND
33 kΩ± 5% to GND
200 kΩ± 5% to GND
> 2 MΩto GND, Hi-Z
68 kΩ± 5% to AVDD
< 1 kΩto AVDD
Disabled
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7.4 Device Functional Modes
The DRV870x-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is
disabled, the H-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
备注
The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is in sleep
mode. The DRV870x-Q1 device is brought out of sleep mode automatically if the nSLEEP pin is
brought high.
The t(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, all external H-bridge FETs are disabled. The high-side gate pins, GHx, are
pulled to the output node, SHx, by an internal resistor and the low-side gate pins, GLx, are pulled to ground.
When the VM voltage is not applied and during the power-on time (ton) the outputs are disabled using weak
pulldown resistors between the GHx and SHx pins and the GLx and GND pins.
备注
The MODE pin controls the device-logic operation for phase and enable, independent half-bridge, or
PWM input modes. This operation is latched on power up or when exiting sleep mode.
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 Serial Peripheral Interface (SPI)
The SPI (DRV8703-Q1 only) is used to set device configurations, operating parameters, and read out diagnostic
information. The DRV8703-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16-bit
word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word consists of 8-
bit register data and the first 8 bits are don’t cares.
A valid frame has to meet following conditions:
• The clock polarity (CPOL) must be set to 0.
• The clock phase (CPHA) must be set to 0.
• The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
• No SCLK signal can occur when the nSCS signal is in transition.
• The SCLK pin must be low when the nSCS pin goes high.
• The nSCS pin should be taken high for at least 500 ns between frames.
• When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high impedance state.
• Full 16 SCLK cycles must occur.
• Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
• The most-significant bit (MSB) is shifted in and out first
• For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error
occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data
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7.5.1.2 SPI Format
The SDI input-data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit 15)
• 4 address bits, A (bits 14 through 11)
• 3 don't care bits, X (10 through 8)
• 8 data bits, D (7:0)
The SDO output-data word is 16 bits long and the first 8 bits are don’t care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
表7-12. SDI Input Data Word Format
R/W
B15
W0
ADDRESS
DON'T CARE
DATA
B14
A3
B13
A2
B12
A1
B11
A0
B10
X
B9
X
B8
X
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
表7-13. SDO Output Data Word Format
DON'T CARE
DATA
B15
X
B14
X
B13
X
B12
X
B11
X
B10
X
B9
X
B8
X
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
nSCS
SCLK
SDI
X
Z
X
Z
MSB
LSB
SDO
LSB
MSB
Capture
Point
Propagate
Point
图7-18. SPI Transaction
The SCLK pin should be low at power-up of the device for reliable SPI transaction. If the SCLK pin cannot be
guaranteed to be low at power-up, TI recommends performing a dummy SPI-read transaction (of any register)
after power-up to ensure reliable subsequent transactions. Data read from this dummy read transaction should
be discarded.
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7.6 Register Maps
表7-14. DRV8703-Q1 Memory Map
Register
7
Access
Type
Address
(Hex)
6
5
4
3
2
1
0
Name
FAULT Status
VDS and GDF
Main
FAULT
WDFLT
GDF
OCP
L1_GDF
LOCK
VM_UVFL
H2_VDS
VCP_UVFL
L2_VDS
IN1/PH
OTSD
H1_VDS
IN2/EN
OTW
R
0
1
2
3
4
5
H2_GDF
L2_GDF
H1_GDF
L1_VDS
CLR_FLT
R
RESERVED
RW
RW
RW
RW
IDRIVE and WD
VDS
TDEAD
WD_EN
VDS
WD_DLY
DIS_H2_VDS
VREF_SCL
IDRIVE
SO_LIM
DIS_L2_VDS
SH_EN
DIS_H1_VDS
DIS_L1_VDS
Config
TOFF
CHOP_IDS
GAIN_CS
表7-15. Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
7.6.1 Status Registers
The status registers are used to report warning and fault conditions. Status registers are read only registers.
表 7-16 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表
7-16 should be considered as reserved locations and the register contents should not be modified.
表7-16. Status Registers Summary Table
Address
0x00h
Register Name
FAULT status
Section
Go
0x01h
VDS and GDF status
Go
7.6.2 FAULT Status Register (address = 0x00h)
FAULT status is shown in 图7-19 and described in 表7-17.
Return to Summary Table.
Read only
图7-19. FAULT Status Register
7
6
5
4
3
2
1
0
FAULT
R-0b
WDFLT
R-0b
GDF
R-0b
OCP
R-0b
VM_UVFL
R-0b
VCP_UVFL
R-0b
OTSD
R-0b
OTW
R-0b
表7-17. FAULT Status Field Descriptions
Bit
Field
Type
Default
Description
7
FAULT
R
0b
Logic OR of the FAULT status register excluding the OTW bit
Watchdog time-out fault
6
5
4
3
2
1
WDFLT
GDF
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
Indicates gate drive fault condition
OCP
Indicates VDS monitor overcurrent fault condition
Indicates VM undervoltage lockout fault condition
Indicates charge-pump undervoltage fault condition
Indicates overtemperature shutdown
VM_UVFL
VCP_UVFL
OTSD
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表7-17. FAULT Status Field Descriptions (continued)
Bit
Field
Type
Default
Description
0
OTW
R
0b
Indicates overtemperature warning
7.6.3 VDS and GDF Status Register Name (address = 0x01h)
VDS and GDF status is shown in 图7-20 and described in 表7-18.
Return to Summary Table.
Read only
图7-20. VDS and GDF Status Register
7
6
5
4
3
2
1
0
H2_GDF
R-0b
L2_GDF
R-0b
H1_GDF
R-0b
L1_GDF
R-0b
H2_VDS
R-0b
L2_VDS
R-0b
H1_VDS
R-0b
L1_VDS
R-0b
表7-18. VDS and GDF Status Field Descriptions
Bit
Field
Type
Default
Description
7
H2_GDF
R
0b
Indicates gate drive fault on the high-side FET of half-bridge 2
Indicates gate drive fault on the low-side FET of half-bridge 2
Indicates gate drive fault on the high-side FET of half-bridge 1
Indicates gate drive fault on the low-side FET of half-bridge 1
6
5
4
3
L2_GDF
H1_GDF
L1_GDF
H2_VDS
R
R
R
R
0b
0b
0b
0b
Indicates VDS monitor overcurrent fault on the high-side FET of
half-bridge 2
2
1
0
L2_VDS
H1_VDS
L1_VDS
R
R
R
0b
0b
0b
Indicates VDS monitor overcurrent fault on the low-side FET of
half-bridge 2
Indicates VDS monitor overcurrent fault on the high-side FET of
half-bridge 1
Indicates VDS monitor overcurrent fault on the low-side FET of
half-bridge 1
7.6.4 Control Registers
The control registers are used to configure the device. Control registers are read and write capable.
表 7-19 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表
7-19 should be considered as reserved locations and the register contents should not be modified.
表7-19. Status Registers Summary Table
Address
0x02h
0x03h
0x04h
0x05h
Register Name
Main control
Section
Go
IDRIVE and WD control
VDS control
Go
Go
Config control
Go
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7.6.5 Main Control Register Name (address = 0x02h)
Main control is shown in 图7-21 and described in 表7-20.
Return to Summary Table.
Read and write
图7-21. Main Control Register
7
6
5
4
3
2
1
0
RESERVED
R/W-00b
LOCK
IN1/PH
R/W-0b
IN2/EN
R/W-0b
CLR_FLT
R/W-0b
R/W-011b
表7-20. Main Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
RESERVED
R/W
00b
Reserved
5-3
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register
changes except to address 0x02h. Writing any sequence other
than 110b has no effect when unlocked.
Write 011b to this register to unlock all registers. Writing any
sequence other than 011b has no effect when locked.
2
1
0
IN1/PH
R/W
R/W
R/W
0b
0b
0b
This bit is ORed with the IN1/PH pin
This bit is ORed with the IN2/EN pin
Write a 1 to this bit to clear the fault bits
IN2/EN
CLR_FLT
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7.6.6 IDRIVE and WD Control Register Name (address = 0x03h)
IDRIVE and WD control is shown in 图7-22 and described in 表7-21.
Return to Summary Table.
Read and write
图7-22. IDRIVE and WD Register
7
6
5
4
3
2
1
0
TDEAD
WD_EN
R/W-0b
WD_DLY
R/W-00b
IDRIVE
R/W-111b
R/W-00b
表7-21. IDRIVE and WD Field Descriptions
Bit
Field
Type
Default
Description
7-6
TDEAD
R/W
00b
Dead time
00b = 120 ns
01b = 240 ns
10b = 480 ns
11b = 960 ns
5
WD_EN
R/W
R/W
0b
Enables or disables the watchdog time (disabled by default)
4-3
WD_DLY
00b
Watchdog timeout delay (if WD_EN = 1)
00b = 10 ms
01b = 20 ms
10b = 50 ms
11b = 100 ms
2-0
IDRIVE
R/W
111b
Sets the peak source current and peak sink current of the gate
drive. 表7-22 lists the bit settings.
表7-22. IDRIVE Bit Settings
Source Current
Sink Current
Bit Value
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
000b
001b
010b
011b
100b
101b
110b
111b
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
High-side: 70 mA
Low-side: 55 mA
High-side: 70 mA
Low-side: 60 mA
High-side: 120 mA
Low-side: 115 mA
High-side: 130 mA
Low-side: 125 mA
High-side: 100 mA
Low-side: 75 mA
High-side: 105 mA
Low-side: 90 mA
High-side: 170 mA
Low-side: 160 mA
High-side: 185 mA
Low-side: 180 mA
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side: 430 mA
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7.6.7 VDS Control Register Name (address = 0x04h)
VDS control is shown in 图7-23 and described in 表7-23.
Return to Summary Table.
Read and write
图7-23. VDS Control Register
7
6
5
4
3
2
1
0
SO_LIM
R/W-0b
VDS
DIS_H2_VDS
R/W-0b
DIS_L2_VDS
R/W-0b
DIS_H1_VDS
R/W-0b
DIS_L1_VDS
R/W-0b
R/W-111b
表7-23. VDS Control Field Descriptions
Bit
Field
Type
Default
Description
7
SO_LIM
R/W
0b
0b = Default operation
1b = SO output is voltage-limited to 3.6 V
6-4
VDS
R/W
111b
Sets the VDS(OCP) monitor for each FET
000b = 0.06 V
001b = 0.145 V
010b = 0.17 V
011b = 0.2 V
100b = 0.12 V
101b = 0.24 V
110b = 0.48 V
111b = 0.96 V
3
2
1
0
DIS_H2_VDS
DIS_L2_VDS
DIS_H1_VDS
DIS_L1_VDS
R/W
R/W
R/W
R/W
0b
0b
0b
0b
Disables the VDS monitor on the high-side FET of half-bridge 2
(enabled by default)
Disables the VDS monitor on the low-side FET of half-bridge 2
(enabled by default)
Disables the VDS monitor on the high-side FET of half-bridge 1
(enabled by default)
Disables the VDS monitor on the low-side FET of half-bridge 1
(enabled by default)
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7.6.8 Config Control Register Name (address = 0x05h)
Config control is shown in 图7-24 and described in 表7-24.
Return to Summary Table.
Read and write
图7-24. Config Control Register
7
6
5
4
3
2
1
0
TOFF
CHOP_IDS
R/W-0b
VREF_SCL
R/W-00b
SH_EN
R/W-0b
GAIN_CS
R/W-01b
R/W-00b
表7-24. Config Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
TOFF
R/W
00b
Off time for PWM current chopping
00b = 25 µs
01b = 50 µs
10b = 100 µs
11b = 200 µs
5
CHOP_IDS
VREF_SCL
R/W
R/W
0b
Disables current regulation (enabled by default)
4-3
00b
Scale factor for the VREF input
00b = 100%
01b = 75%
10b = 50%
11b = 25%
2
SH_EN
R/W
R/W
0b
Enables sample and hold operation of the shunt amplifier
(disabled by default)
1-0
GAIN_CS
01b
Shunt amplifier gain setting
00b = 10 V/V
01b = 19.8 V/V
10b = 39.4 V/V
11b = 78 V/V
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The DRV870x-Q1 device is used in brushed-DC, solenoid, or relay-control applications. The following typical
application can be used to configure the DRV870x-Q1 device.
8.2 Typical Application
This application features the DRV8702-Q1 device.
VM
+
VM
0.1 µF
Bulk
0.1 µF 1 µF
+
Bulk
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GL2
SL2
SN
IN1/PH
IN2/EN
GND
BDC
10 mΩ
SP
GND
(PAD)
IDRIVE
VDS
GL1
SH1
GH1
GND
200 kΩ
0 Ω
GND
nSLEEP
VM
+
Bulk
VM
R1
R2
10 kΩ
1 µF
1 µF
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图8-1. DRV8702-Q1 Typical Application Schematic
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8.2.1 Design Requirements
For this design example, use the parameters listed in 表8-1 as the input parameters.
表8-1. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Nominal supply voltage
14 V
VM
Supply voltage range
FET part number
7 V to 35 V
CSD18502Q5B
52 nC (typical)
8.4 nC (typical)
100 to 300 ns
15 A
FET total gate charge
FET gate-to-drain charge
Target FET gate rise time
Motor current chopping level
Qg
Qgd
tr
I(CHOP)
8.2.2 Detailed Design Procedure
8.2.2.1 External FET Selection
The DRV8702-Q1 FET support is based on the charge-pump capacity and PWM-output frequency. For a quick
calculation of FET driving capacity, use 方程式 3 when drive and brake (slow decay) are the primary modes of
operation.
IVCP
Qg <
f(PWM)
(3)
where
• fPWM is the maximum desired PWM frequency to be applied to the DRV8702-Q1 inputs or the current
chopping frequency, whichever is larger.
• IVCP is the charge-pump capacity, which depends on the VM voltage.
The internal current chopping frequency is at most equal to the PWM frequency as shown in 方程式4.
1
f(PWM)
<
toff + t(BLANK)
(4)
For example, if the VM voltage of a system is 7 V (IVCP = 8 mA) and uses a maximum PWM frequency of 40
kHz, then the DRV8702-Q1 device will support FETs with a Qg up to 200 nC.
If the application requires a forced fast decay (or alternating between drive and reverse drive), use 方程式 5 to
calculate the maximum FET driving capacity.
IVCP
Qg <
2 ì f(PWM)
(5)
8.2.2.2 IDRIVE Configuration
The IDRIVE current is selected based on the gate charge of the FETs. The IDRIVE pin must be configured so
that the FET gates are charged entirely during the t(DRIVE) time. If the selected IDRIVE current is too low for a
given FET, then the FET may not turn on completely. TI recommends adjusting these values in-system with the
required external FETs and motor to determine the best possible setting for any application.
For FETs with a known gate-to-drain charge (Qgd) and desired rise time (tr), the IDRIVE current can be selected
based on the 方程式6.
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Qgd
tr
IDRIVE
>
(6)
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If the gate-to-drain charge is 2.3 nC and the desired rise time is around 100 to 300 ns, use 方程式 7 to calculate
the minimum IDRIVE (IDRIVE1) and 方程式8 to calculate the maximum IDRIVE (IDRIVE2).
IDRIVE1 = 8.4 nC / 100 ns = 84 mA
IDRIVE2 = 8.4 nC / 300 ns = 28 mA
(7)
(8)
Select a value for IDRIVE between 28 and 84 mA. An IDRIVE value of approximately 50 mA for the source
(approximately 100 mA sink) was selected for this application. This value requires a 200-kΩ resistor from the
IDRIVE pin to ground.
8.2.2.3 VDS Configuration
The VDS monitor threshold voltage, VDS(OCP), is configured based on the maximum current, IVDS, and RDS(on) of
the FETs. The drain to source voltage, VDSFET, is the maximum current, IVDS, multiplied by the RDS(on) of the
FET.
The VDS pin of the DRV8702-Q1 selects the VDS monitor trip threshold, VDS(OCP). The VDS bits in the VDS
register of the DRV8703-Q1 selects the VDS(OCP) voltage. Use 方程式9 to calculate the trip current.
VDSFET
IVDS
>
RDS(on)
(9)
If the RDS(on) of the FET is 1.8 mΩ and the desired maximum current is less than 100 A, the VDSFET voltage is
equal to 180 mV as shown in 方程式10.
For this example, select a value for the VDS(OCP) that is less than 180 mV. A VDS(OCP) value of 0.12 V was
selected for this application.
To set the VDS(OCP) to 0.12 V, use the SPI (DRV8703-Q1 Only) or place a 33k resistor at the VDS pin to ground
(DRV8702-Q1 Only).
The VDS pin can configured to select other VDS(OCP) threshold voltages. See the 节 7.3.11 section for more
information on VDS operation.
VDSFET= IVDS × RDS(on) = 100 A × 1.8 mΩ= 180 mV
(10)
8.2.2.4 Current Chopping Configuration
The chopping current is set based on the sense resistor value and the analog voltage at the VREF pin. Use 方程
式 11 to calculate the current (I(CHOP)). The amplifier gain, AV, is 19.8 V/V for the DRV8702-Q1 and VIO is
typically 5 mV (input referred).
VVREF - V ì AV
AV ì R(SENSE)
IO
I(CHOP)
=
(11)
For example, if the desired chopping current is 15 A, select a value of 10 mΩ for R(SENSE). The value of VVREF
must therefore be 2.975 V. Add a resistor divider from the AVDD (5 V) pin to set the VVREF at approximately
2.975 V. Select a value of 13 kΩfor R2 and 19.1 kΩfor R1 (the VREF resistor).
If current chopping is not required, the sense resistor can be removed and the source of the low side FET can be
connected to ground.
SN and SP should be connected to the source of the low side FET and VREF should be connected to AVDD
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8.2.3 Application Curves
10-mA source
20-mA sink
10-mA source
20-mA sink
图8-2. SH1 Fall Time
图8-3. SH1 Rise Time
图8-5. Current Profile on Motor Startup Without
图8-4. Current Profile on Motor Startup With
Regulation
Regulation
图8-6. Current Regulating at 2.25 A on Motor Startup
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9 Power Supply Recommendations
The DRV8702-Q1 device is designed to operate with an input voltage supply (VM) rangefrom 5.5 V to 45 V. A
0.1-µF ceramic capacitor rated for VM must be placed as close to the DRV8702-Q1 device as possible. Also, a
bulk capacitor valued at least 10 µF must be placed on the VM pin.
Additional bulk capacitance is required to bypass the external H-bridge FETs.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Copyright © 2016, Texas Instruments Incorporated
图9-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to ground using a low-ESR ceramic bypass capacitor with a recommended
value of 0.1 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground-plane connection to the GND pin of the device. The VM pin must also be bypassed to ground
using a bulk capacitor rated for VM. This capacitor can be electrolytic and must be at least 10 µF.
A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.1 µF rated for VM is
recommended. Place this capacitor as close to the pins as possible. A low-ESR ceramic capacitor must be
placed in between the VM and VCP pins. A value of 1 µF rated for 16 V is recommended. Place this component
as close to the pins as possible.
Bypass the AVDD and DVDD pins to ground with ceramic capacitors rated for 6.3 V. Place these bypassing
capacitors as close to the pins as possible.
Use separate traces to connect the SP and SN pins to the R(SENSE) resistor.
10.2 Layout Example
Bulk
D
D
D
D
G
S
S
S
1 µF
SH2
S
D
0.1 µF
0.1 µF
RSENSE
S
S
G
D
D
D
1
2
3
4
5
6
7
8
24 GL2
GND
23
IN1/PH
IN2/EN
GND
SL2
22
SN
GND
21
SP
20
IDRIVE
VDS
GL1
(PAD)
19
SH1
S
S
S
G
D
D
D
D
GND
18
17
GH1
GND
nSLEEP
1 µF
1 µF
Bulk
SH1
D
G
D
D
D
S
S
S
图10-1. DRV8702-Q1 Layout Example
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DRV8702-Q1, DRV8703-Q1
ZHCSG08E –OCTOBER 2016 –REVISED JANUARY 2021
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Automotive Relay Replacement Application Note
• Texas Instruments, DRV8702-Q1 EVM User’s Guide
• Texas Instruments, DRV8703-Q1 EVM User’s Guide
• Texas Instruments, Small Footprint Motor Driver Sunroof Module Design Guide
• Texas Instruments, Relay Replacement for Brushed DC Motor Drive in Automotive Applications application
report
• Texas Instruments, Understanding IDRIVE and TDRIVE in TI Smart Gate Drivers
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DRV8702-Q1
DRV8703-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OUTLINE
RHB0032N
VQFN - 0.9 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.05)
SECTION A-A
TYPICAL
A
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
A
A
2X
SYMM
33
3.5
0.3
32X
0.2
24
0.1
C A B
1
0.05
C
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4222893/B 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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DRV8702-Q1, DRV8703-Q1
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EXAMPLE BOARD LAYOUT
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222893/B 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: DRV8702-Q1 DRV8703-Q1
DRV8702-Q1, DRV8703-Q1
ZHCSG08E –OCTOBER 2016 –REVISED JANUARY 2021
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EXAMPLE STENCIL DESIGN
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222893/B 02/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: DRV8702-Q1 DRV8703-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8702QRHBRQ1
DRV8702QRHBTQ1
DRV8703QRHBRQ1
DRV8703QRHBTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
32
32
32
32
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DRV8702
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
DRV8702
DRV8703
DRV8703
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8702QRHBRQ1
DRV8702QRHBTQ1
DRV8703QRHBRQ1
DRV8703QRHBTQ1
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
32
32
32
32
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8702QRHBRQ1
DRV8702QRHBTQ1
DRV8703QRHBRQ1
DRV8703QRHBTQ1
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
32
32
32
32
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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