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DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

DRV870xD-Q1 汽车半桥栅极驱动器

1 特性

通过 PWM 接口，可轻松连接到控制器电路。内部传

1

感放大器提供可调的电流控制。集成的电荷泵可提供

100% 占空比支持，而且可用于驱动外部反向电池开

关。独立半桥模式支持半桥共享，能够以具有成本效益

的方式顺序控制多个直流电机。这款栅极驱动器内置有

相应的电路，能够使用关断时间固定的 PWM 电流斩

波来调节绕组电流。

•

符合面向汽车应用的应用

–

器件温度等级 1：环境工作温度范围为 –40°C

至 +125°C

•

单通道半桥栅极驱动器

–

驱动两个外部 N 沟道 MOSFET

支持 100% 脉宽调制 (PWM) 占空比

•

工作电源电压范围：5.5V 至 45V

PWM 控制接口

DRV870xD-Q1 器件采用了智能栅极驱动技术，因此无

需任何外部栅极组件（电阻器和齐纳二极管），同时可

为外部 FET 提供保护。智能栅极驱动架构可优化死区

时间以避免出现任何击穿问题，在通过可编程压摆率控

制技术降低电磁干扰 (EMI) 方面带来了灵活性，而且

可防止任何栅极短路问题。此外，该架构中还包括主动

和被动下拉特性，可防止任何 dv/dt 栅极导通。

用于配置的串行接口 (DRV8703D-Q1)

智能栅极驱动架构

–

可调压摆率控制

•

支持 1.8V、3.3V 和 5V 逻辑输入

电流分流放大器

集成 PWM 电流调节功能

低功耗睡眠模式

器件信息⁽¹⁾

器件型号

DRV8702D-Q1

DRV8703D-Q1

封装

封装尺寸（标称值）

保护特性

–

电源欠压锁定 (UVLO)

电荷泵欠压 (CPUV) 锁定

过流保护 (OCP)

VQFN (32)

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

栅极驱动器故障 (GDF)

热关断 (TSD)

简化原理图

5.5 to 45 V

监视器计时器 (DRV8703D-Q1)

故障调节输出 (nFAULT)

DRV870xD-Q1

PWM

2 应用

Gate

nSLEEP

Half-Bridge Gate Driver

Drive

Half-

Bridge

M

•

燃油泵

VREF

Sense Output

单向刷式直流电机

继电器或螺线管

单极负载

Shunt Amplifier

Current

Sense

nFAULT

Current Regulation

Protection

3 说明

DRV870xD-Q1 器件是一款小型半桥栅极驱动器，它使

用两个外部 N 通道 MOSFET，旨在驱动单向刷式直流

电机或电磁阀负载。

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDX8

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

7.5 Programming........................................................... 39

7.6 Register Maps......................................................... 41

Application and Implementation ........................ 47

8.1 Application Information............................................ 47

8.2 Typical Application .................................................. 47

Power Supply Recommendations...................... 51

9.1 Bulk Capacitance Sizing ......................................... 51

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 SPI Timing Requirements ....................................... 11

6.7 Switching Characteristics........................................ 11

6.8 Typical Characteristics............................................ 13

Detailed Description ............................................ 18

7.1 Overview ................................................................. 18

7.2 Functional Block Diagram ....................................... 19

7.3 Feature Description................................................. 21

7.4 Device Functional Modes........................................ 39

8

9

10 Layout................................................................... 52

10.1 Layout Guidelines ................................................. 52

10.2 Layout Example .................................................... 52

11 器件和文档支持 ..................................................... 53

11.1 文档支持................................................................ 53

11.2 相关链接................................................................ 53

11.3 接收文档更新通知 ................................................. 53

11.4 社区资源................................................................ 53

11.5 商标....................................................................... 53

11.6 静电放电警告......................................................... 53

11.7 术语表 ................................................................... 53

12 机械、封装和可订购信息....................................... 54

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (August 2018) to Revision B

Page

•

已更改首页，删除第二个说明............................................................................................................................................... 1

已删除栅极驱动电流图........................................................................................................................................................... 1

Deleted MODE pulldown resistance ...................................................................................................................................... 7

Added MODE typical pulldown resistance ............................................................................................................................ 7

Added MODE typical pullup resistance ................................................................................................................................. 7

已更改 Wording in VDS Configuration section .................................................................................................................... 49

Changes from Original (March 2017) to Revision A

Page

•

已更改更改了特性和说明部分.............................................................................................................................................. 1

已删除在简化原理图中删除了 PWM 线路中的 PH/EN ......................................................................................................... 1

Changed Vvref description update ........................................................................................................................................ 6

已更改 the V_DS(OCP)from 0.86 V to 0.96 V in the OCP Threshold Voltage graph ................................................................ 15

已更改 the I_(CHOP)equation in the Current Regulation and Current Chopping Configuration sections................................. 24

已更改 the current equation in the Amplifier Output (SO) section........................................................................................ 24

已更改 the description of the WD_EN bit in the IDRIVE and WD Field Descriptions table.................................................. 44

2

DRV8702D-Q1, DRV8703D-Q1

www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

5 Pin Configuration and Functions

DRV8702D-Q1 RHB Package With Wettable Flanks

DRV8703D-Q1 RHB Package With Wettable Flanks

32-Pin VQFN

Top View

32-Pin VQFN

Top View

GND

IN1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

RSVD

SP

GND

IN1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

RSVD

SP

IN2

SN

IN2

SN

GND

SP

SDO

SP

Thermal

Pad

Thermal

Pad

IDRIVE

VDS

GL

nSCS

SDI

GL

SH

GND

GH

SCLK

nSLEEP

GH

nSLEEP

GND

Not to scale

Pin Functions

NO.

DRV8702D-Q1 DRV8703D-Q1

TYPE⁽¹⁾

DESCRIPTION

NAME

Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to

ground with a 6.3-V, 1-µF ceramic capacitor.

AVDD

CPH

14

30

31

12

14

30

31

12

PWR

Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the

supply voltage (VM) between the CPH and CPL pins.

Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the

supply voltage (VM) between the CPH and CPL pins.

CPL

Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this

pin to ground with a 6.3-V, 1-µF ceramic capacitor.

DVDD

GH

18

20

1

18

20

1

O

High-side gate. Connect this pin to the high-side FET gate.

Low-side gate. Connect this pin to the low-side FET gate.

Device ground. Connect this pin to the system ground.

GL

O

GND

PWR

13

17

25

4

13

17

25

—

7

9

Current setting pin for the gate drive. The resistor value or voltage forced on

this pin sets the gate-drive current. For more information see the IDRIVE

Configuration section.

IDRIVE

IN1

5

2

—

2

I

Input control pins. The logic of this pin is dependent on the MODE pin. This pin

is connected to an internal pulldown resistor.

(1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output

3

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Pin Functions (continued)

NO.

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8702D-Q1 DRV8703D-Q1

Input control pins. The logic of this pin is dependent on the MODE pin. This pin

is connected to an internal pulldown resistor.

IN2

3

I

Mode control pin. Pull this pin to logic high for half-bridge operation without

internal current regulation. Leave this pin as no-connect for half-bridge

operation with internal current regulation. Operation of this pin is latched on

power up or when exiting sleep mode. This pin is connected to an internal

pullup and pulldown resistor.

MODE

11

NC

32

10

32

10

NC

OD

No connect. No internal connection

Fault indication pin. This pin is pulled logic low when a fault condition occurs.

This pin is an open-drain output that requires an external pullup resistor.

nFAULT

SPI chip select. This pin is the select and enable for SPI. This pin is active low.

This pin is connected to an internal pulldown resistor.

nSCS

—

8

5

8

I

Device sleep mode. Pull this pin to logic low to put device into a low-power

sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to

an internal pulldown resistor.

nSLEEP

Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault

condition occurs. This pin is an open-drain output that requires an external

pullup resistor.

nWDFLT

—

9

OD

RSVD

26

24

26

24

RSVD

Reserved. Do not connect anything.

SPI clock. This pin is for the SPI clock signal. This pin is connected to an

internal pulldown resistor.

SCLK

SDI

—

7

6

4

I

SPI input. This pin is for the SPI input signal. This pin is connected to an

internal pulldown resistor.

SPI output. This pin is for the SPI output signal. This pin is an open-drain

output that requires an external pullup resistor.

SDO

OD

SH

SN

19

22

19

22

I

High-side source. Connect this pin to the high-side FET source.

Shunt-amplifier negative input. Connect this pin to the current-sense resistor.

Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times

A_Vplus an offset. Place no more than 1 nF of capacitance on this pin.

SO

16

O

SP

21

23

21

23

I

Shunt-amplifier positive input. Connect this pin to the current-sense resistor.

Charge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin

and the VM pin.

VCP

29

27

29

27

PWR

I

VDRAIN

High-side FET drain connection. This pin is common for the half-bridge.

VDS monitor setting pin. The resistor value or voltage forced on this pin sets

the VDS monitor threshold. For more information see the VDS Configuration

section.

VDS

6

—

I

Power supply. Connect this pin to the motor supply voltage. Bypass this pin to

ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.

VM

28

15

28

15

PWR

I

Current set reference input. The voltage on this pin sets the driver chopping

current.

VREF

4

DRV8702D-Q1, DRV8703D-Q1

www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

47

UNIT

V

Power supply voltage

VM

Charge pump voltage

VCP, CPH

CPL

V_VM+ 12

V_VM

V

Charge pump negative switching pin

Internal logic regulator voltage

Internal analog regulator voltage

Drain pin voltage

V

DVDD

AVDD

VDRAIN

3.8

V

5.7

V

47

V

Voltage difference between supply and

VDRAIN

VM – VDRAIN

–10

10

V

VIN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE,

VDS, MODE, nSCS, SCLK, SDI, SDO,

nWDFLT

Control pin voltage

–0.3

5.75

V

High-side gate pin voltage

GH

GL

SH

SP

SN

SP

SO

–0.3

–1.2

–2

V_VM+ 12

12

V

Low-side gate pin voltage

Continuous phase-node pin voltage

Pulsed 10-µs phase-node pin voltage

V_VM+ 1.2

V_VM+ 2

1.2

V

–0.5

–0.3

–1

V

Continuous shunt amplifier input pin voltage

0.3

V

Pulsed 10-µs shunt amplifier input pin voltage

Shunt amplifier output pin voltage

1.2

V

–0.3

0

5.75

V

Shunt amplifier output pin current

5

mA

Maximum current, limit current with external

series resistor

VDRAIN

–2

2

mA

Open-drain output current

Gate pin source current

nFAULT, SDO, nWDFLT

GH, GL

0

10

250

500

150

mA

°C

Gate pin sink current

GH, GL

0

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

Electrostatic

discharge

V_(ESD)

V

All pins

Charged-device model (CDM), per AEC Q100-011

CDM ESD Classification Level C4B

Corner pins (1, 8, 9, 16, 17, 24, 25,

and 32)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

6.3 Recommended Operating Conditions

MIN

5.5

MAX

45

UNIT

V

V_VM

Power supply voltage

VM

V_CC

Logic-level input voltage

0

5.25

3.6

V

V_VREF

f_(PWM)

I_AVDD

I_DVDD

I_SO

Current Shunt Amplifier Reference Voltage

Applied PWM signal (IN1/IN2)

AVDD external load current

VREF

0.3⁽¹⁾

V

IN1, IN2

100

30⁽²⁾

5

kHz

mA

°C

DVDD external load current

Shunt-amplifier output-current loading

Operating ambient temperature

SO

T_A

–40

125

(1) Operational at V_VREF= 0 to approximately 0.3 V, but accuracy is degraded.

(2) Power dissipation and thermal limits must be observed.

6.4 Thermal Information

DRV870xD-Q1

THERMAL METRIC⁽¹⁾

RHB (VQFN)

32 PINS

32.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

19.6

6.8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

6.8

R_θJC(bot)

1.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (VM, AVDD, DVDD)

Gate drivers functional

5.5

4.5

5.5

45

V_VM

VM operating voltage

V

Logic functional

I_VM

VM operating supply current

VM sleep mode supply current

V_VM= 13.5 V; nSLEEP=1

nSLEEP = 0, V_VM= 13.5 V, T_A= 25°C

nSLEEP = 0, V_VM= 13.5 V, T_A= 125°C⁽¹⁾

2-mA load

7.5

12

mA

µA

14

I_(SLEEP)

25

3

2.9

4.7

4.6

3.3

3.2

5

3.5

5.3

V_DVDD

Internal logic regulator voltage

V

30-mA load, V_VM= 13.5 V

2-mA load

V_AVDD

30-mA load, V_VM= 13.5 V

5

CHARGE PUMP (VCP, CPH, CPL)

V_VM= 13.5 V; I_VCP= 0 to 12 mA

V_VM= 8 V; I_VCP= 0 to 10 mA

V_VM= 5.5 V; I_VCP= 0 to 8 mA

V_VM> 13.5 V

22.5

13.7

8.9

12

23.5

14

24.5

14.8

9.5

V_VCP

VCP operating voltage

V

9.1

I_VCP

Charge-pump current capacity

8 V < V_VM< 13.5 V

10

mA

5.5 V < V_VM< 8 V

8

CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI)

V_IL

V_IH

Input logic-low voltage

Input logic-high voltage

0

0.8

V

1.5

5.25

(1) Ensured by design and characterization data.

6

DRV8702D-Q1, DRV8703D-Q1

www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

100

–5

TYP

MAX

UNIT

mV

µA

V_hys

I_IL

Input logic hysteresis

Input logic-low current

Input logic-high current

Pulldown resistance

Pullup resistance

V_IN= 0 V

V_IN= 5 V

5

70

I_IH

µA

R_PD

R_PU

IN1, IN2, nSLEEP, nSCS, SCLK, SDI

64

-2

100

65

173

kΩ

MODE

kΩ

26

kΩ

CONTROL OUTPUTS (nFAULT, WDFAULT, SDO)

V_OL

I_OZ

Output logic-low voltage

I_O= 2 mA

0.1

2

V

Output high-impedance leakage

5V pullup voltage

µA

FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)

V_VM> 13.5 V; V_GSHwith respect to SH

10.5

11.5

6.8

4

High-side V_GSgate drive (gate-

to-source)

V_GSH

V_VM= 8 V; V_GSHwith respect to SH

V_VM= 5.5 V; V_GSHwith respect to SH

V_VM> 10.5 V

5.7

3.4

V

Low-side V_GSgate drive (gate-to-

source)

V_GSL

V_VM< 10.5 V

V_VM– 2

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

10

20

50

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

70

High-side peak source current

(V_VM= 5.5V)

I_{DRIVE(SRC_HS)}

mA

100

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

145

190

240

20

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

40

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

90

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

120

170

High-side peak sink current

(V_VM= 5.5V)

I_{DRIVE(SNK_HS)}

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

250

330

420

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

7

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

10

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

20

40

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

55

75

Low-side peak source current

(V_VM= 5.5V)

I_{DRIVE(SRC_LS)}

I_{DRIVE(SNK_LS)}

I_{DRIVE(SRC_HS)}

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

115

145

190

20

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

40

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

85

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

115

160

Low-side peak sink current

(V_VM= 5.5V)

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

235

300

360

10

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

20

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

50

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

70

High-side peak source current

(V_VM= 13.5V)

mA

105

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

155

210

260

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

8

DRV8702D-Q1, DRV8703D-Q1

www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

20

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

40

95

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

130

185

High-side peak sink current

(V_VM= 13.5V)

I_{DRIVE(SNK_HS)}

I_{DRIVE(SRC_LS)}

I_{DRIVE(SNK_LS)}

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

265

350

440

10

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

20

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

45

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

60

90

Low-side peak source current

(V_VM= 13.5V)

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

130

180

225

20

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

R_(IDRIVE)< 1 kΩ to GND (DRV8702D) or

IDRIVE = 3’b000 (DRV8703D)

R_(IDRIVE)= 33 kΩ to GND (DRV8702D) or

IDRIVE = 3’b001 (DRV8703D)

40

R_(IDRIVE)= 200 kΩ to GND (DRV8702D)

or IDRIVE = 3’b010 (DRV8703D)

95

IDRIVE = 3’b011 (DRV8703D)

IDRIVE = 3’b100 (DRV8703D)

125

180

Low-side peak sink current

(V_VM= 13.5V)

mA

R_(IDRIVE)> 2 MΩ to GND (DRV8702D) or

IDRIVE = 3’b101 (DRV8703D)

260

350

430

R_(IDRIVE)= 68 kΩ to AVDD (DRV8702D)

or IDRIVE = 3’b110 (DRV8703D)

R_(IDRIVE)= 1 kΩ to AVDD (DRV8702D) or

IDRIVE = 3’b111 (DRV8703D)

Source current after t_DRIVE

Sink current after t_DRIVE

GH

10

40

I_HOLD

FET holding current

mA

kΩ

750

1000

150

I_STRONG

FET holdoff strong pulldown

FET gate holdoff resistor

GL

Pulldown GH to SH

Pulldown GL to GND

R_(OFF)

CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)

V_VREFVREF input rms voltage For current internal chopping

0.3⁽²⁾

3.6

V

(2) Operational at V_VREF= 0 to approximately 0.3 V, but accuracy is degraded.

9

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for T_A= 25°C and V_VM= 13.5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DRV8702D and DRV8703D VREF_SCL =

00 (100%)

1

MΩ

R_VREF

VREF input impedance

Amplifier gain (DRV8702D-Q1)

DRV8703D VREF_SCL = 2’b01, 2’b10 or

2’b11

175

19.8

10

kΩ

A_V

60 < V_SP< 225 mV; V_SN= GND

19.3

9.75

20.3

V/V

GAIN_CS = 00; 10 < V_SP< 450 mV; V_SN

= GND

10.25

GAIN_CS = 01; 60 < V_SP< 225 mV; V_SN

= GND

19.3

38.4

73

19.8

39.4

78

20.3

40.4

A_V

Amplifier gain (DRV8703D-Q1)

V/V

GAIN_CS = 10; 10 < V_SP< 112 mV; V_SN

= GND

GAIN_CS = 11; 10 < V_SP< 56 mV; V_SN

GND

=

81

10

V_IO

Input-referred offset

Drift offset⁽²⁾

V_SP= V_SN= GND

5

10

mV

µV/°C

µA

V_IO(DRIFT)

I_SP

V_SP= V_SN= GND

SP input current

V_SP= 100 mV; V_SN= GND

–20

V_SO

SO pin output voltage range

Allowable SO pin capacitance

A_V× Vio

4.5

1

V

C_(SO)

nF

PROTECTION CIRCUITS

VM falling; UVLO2 report

VM rising; UVLO2 recovery

5.25

5.4

5.45

5.65

4.5

V_(UVLO2)

VM undervoltage lockout

V

V_(UVLO1)

Logic undervoltage lockout

VM undervoltage hysteresis

V

V_hys(UVLO)

Rising to falling threshold

VCP falling; CPUV report

100

mV

V_VM

+

1.5

V_{(CP_UV)}

Charge pump undervoltage

CP undervoltage hysteresis

V

V_VM

+

VCP rising; CPUV recovery

1.55

V_{hys(CP_UV)}

Rising to falling threshold

R_(VDS)< 1 kΩ to GND

R_(VDS)= 33 kΩ to GND

R_(VDS)= 200 kΩ to GND

R_(VDS)> 2 MΩ to GND

R_(VDS)= 68 kΩ to AVDD

R_(VDS)< 1 kΩ to AVDD

VDS_LEVEL = 3’b000

VDS_LEVEL = 3’b001

VDS_LEVEL = 3’b010

VDS_LEVEL = 3’b011

VDS_LEVEL = 3’b100

VDS_LEVEL = 3’b101

VDS_LEVEL = 3’b110

VDS_LEVEL = 3’b111

50

0.06

mV

0.12

Overcurrent protection trip level,

V_DSof each external FET

(DRV8702D-Q1)

High side FETs: VDRAIN – SH

Low side FETs: SH – SP

0.24

V_DS(OCP)

V

0.48

0.96

Disabled

0.06

0.145

0.17

Overcurrent protection trip level,

V_DSof each external FET

(DRV8703D-Q1)

High-side FETs: VDRAIN – SH

Low-side FETs: SH – SP

0.2

V_DS(OCP)

V

0.12

0.24

0.48

0.96

Overcurrent protection trip level,

measured by sense amplifier

Thermal warning temperature⁽¹⁾

V_SP(OCP)

V_SPwith respect to GND

Die temperature T_J

Thermal shutdown temperature⁽¹⁾Die temperature T_J

0.8

1

1.2

T_(OTW)

T_SD

120

150

135

145

°C

T_hys

Thermal shutdown hysteresis⁽¹⁾

Die temperature T_J

20

17

Positive clamping voltage

Negative clamping voltage

16.3

–1

17.8

–0.5

V_C(GS)

Gate-drive clamping voltage

V

–0.7

10

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

6.6 SPI Timing Requirements

MIN

100

50

NOM

MAX

UNIT

ns

t_(CLK)

Minimum SPI clock period

Clock high time

t_(CLKH)

t_(CLKL)

t_{(SU_SDI)}

t_{(HD_SDI)}

ns

Clock low time

50

ns

SDI input data setup time

SDI input data hold time

20

ns

30

ns

t_{(HD_SDO)}SDO output hold time

t_{(SU_SCS)}SCS setup time

t_{(HD_SCS)}SCS hold time

40

ns

50

ns

50

ns

t_{(HI_SCS)}

SCS minimum high time before SCS active low

400

ns

6.7 Switching Characteristics

Over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (VM, AVDD, DVDD)

t_(SLEEP)

t_(wu)

Sleep time

nSLEEP = low to sleep mode

nSLEEP = high to output change

VM > UVLO2 to output transition

100

1

µs

ms

Wake-up time

Turn on time

t_on

1

CHARGE PUMP (VCP, CPH, CPL)

f_S(VCP)Charge-pump switching frequency VM > UVLO2

CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI, PH, EN)

200

400

500

700

kHz

ns

removed PH and EN pinsIN1, IN2 to

GH or GL

t_pd

Propagation delay

FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)

Observed t_(DEAD)depends on

IDRIVE setting

t_(DEAD)

Output dead time (DRV8702D-Q1)

240

120

240

480

ns

TDEAD = 2’b00; Observed t_(DEAD)

depends on IDRIVE setting

TDEAD = 2’b01; Observed t_(DEAD)

depends on IDRIVE setting

t_(DEAD)

Output dead time (DRV8703D-Q1)

Gate drive time

ns

µs

TDEAD = 2’b10; Observed t_(DEAD)

depends on IDRIVE setting

TDEAD = 2’b11; Observed t_(DEAD)

depends on IDRIVE setting

960

2.5

t_(DRIVE)

CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)

V_SP= V_SN= GND to V_SP= 240 mV,

V_SN= GND, A_V= 10; C_(SO)= 200 pF

0.5

1

V_SP= V_SN= GND to V_SP= 120 mV,

V_SN= GND, A_V= 20; C_(SO)= 200 pF

t_S

Settling time to ±1%⁽¹⁾

µs

V_SP= V_SN= GND to V_SP= 60 mV,

V_SN= GND, A_V= 40; C_(SO)= 200 pF

2

V_SP= V_SN= GND to V_SP= 30 mV,

V_SN= GND, A_V= 80; C_(SO)= 200 pF

4

t_off

PWM off-time (DRV8702D-Q1)

PWM off-time (DRV8703D-Q1)

PWM blanking time

25

µs

TOFF = 00

TOFF = 01

TOFF = 10

TOFF = 11

50

t_off

100

200

2

t_(BLANK)

(1) Ensured by design

11

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Switching Characteristics (continued)

Over recommended operating conditions unless otherwise noted

PARAMETER

PROTECTION CIRCUITS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_(UVLO)

t_(OCP)

VM UVLO falling deglitch time

Overcurrent deglitch time

Overcurrent retry time

VM falling; UVLO report

10

4

µs

3.7

2.8

4.3

3.2

t_(RETRY)

3

ms

WD_DLY = 2’b00

WD_DLY = 2’b01

WD_DLY = 2’b10

WD_DLY = 2’b11

10

20

50

100

64

Watchdog time out (DRV8703D-

Q1)

t_(WD)

ms

µs

t_(RESET)

Watchdog timer reset period

SPI

t_{(SPI_READY)}SPI read after power on

SDO output data delay time, CLK

VM > VUVLO1

C_L= 20 pF

5

10

30

ms

ns

t_d(SDO)

high to SDO valid

SCS access time, SCS low to SDO

out of high impedance

t_a

10

ns

SCS disable time, SCS high to

SDO high impedance

t_dis

t_{(HI_SCS)}

t_{(HD_SCS)}

t_{(SU_SCS)}

SCS

t_(CLK)

SCLK

SDI

t_(CLKH)

t_(CLKL)

MSB in

(must be valid)

LSB

t_{(SU_SDI)}t_{(HD_SDI)}

MSB out (is valid)

SDO

Z

LSB

Z

t_dis

t_a

t_d(SDO)

t_{(HD_SDO)}

图 1. SPI Slave Mode Timing Definition

12

DRV8702D-Q1, DRV8703D-Q1

www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

1

2

3

4

X

15

16

SCS

SCLK

SDI

LSB

MSB

SDO

Receive

Latch Points

图 2. SPI Slave Mode Timing Diagram

6.8 Typical Characteristics

8.4

8.1

7.8

7.5

7.2

6.9

6.6

6.3

8.4

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

8.1

7.8

7.5

7.2

6.9

6.6

6.3

T_A= -40èC

T_A= 25èC

T_A= 125èC

5

10

15

20

25

30

35

40

45

-50

-25

0

25

50

75

100

125

Supply Voltage (V)

Temperature (èC)

D001

D002

图 3. Supply Current vs Supply Voltage (VM)

图 4. Supply Current vs Temperature

13

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

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Typical Characteristics (接下页)

21

19

17

15

13

11

9

21

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

T_A= -40èC

T_A= 25èC

19

T_A= 125èC

17

15

13

11

9

7

5

10

15

20

25

30

35

40

45

-50

-25

0

25

50

75

100

125

Supply Voltage (V)

Temperature (èC)

D003

D004

图 5. Sleep Current vs Supply Voltage (VM)

图 6. Sleep Current vs Temperature

3.4

5.1

5.05

5

T_A= -40èC

T_A= 25èC

T_A= 125èC

3.35

3.3

3.25

3.2

4.95

4.9

T_A= -40èC

3.15

3.1

T_A= 25èC

T_A= 125èC

5

10

15

20

25

30

35

40

45

5

10

15

20

25

30

35

40

45

Supply Voltage (V)

D005

D006

2-mA load

图 7. DVDD Regulator

图 8. AVDD Regulator

3.26

3.24

3.22

3.2

5.1

5

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

3.18

3.16

3.14

3.12

3.1

T_A= -40èC

T_A= 25èC

T_A= 125èC

T_A= -40èC

T_A= 25èC

T_A= 125èC

3.08

5

10

15

20

25

30

35

40

45

5

10

15

20

25

30

35

40

45

50

Supply Voltage (V)

D007

D008

30-mA load

图 9. DVDD Regulator

图 10. AVDD Regulator

14

DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

Typical Characteristics (接下页)

10

19.9

19.84

19.78

19.72

19.66

19.6

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

9.98

9.96

9.94

9.92

9.9

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D009

D010

10-V/V gain

19.8-V/V gain

图 11. Amplifier Gain

图 12. Amplifier Gain

40

39.8

39.6

39.4

39.2

39

79

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

78.8

78.6

78.4

78.2

78

77.8

77.6

77.4

77.2

77

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D011

D012

39.4-V/V gain

78-V/V gain

图 13. Amplifier Gain

图 14. Amplifier Gain

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.18

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.1

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D013

D014

V_DS(OCP)= 0.06 V

图 15. OCP Threshold Voltage

V_DS(OCP)= 0.12 V

图 16. OCP Threshold Voltage

15

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Typical Characteristics (接下页)

0.19

0.27

0.26

0.25

0.24

0.23

0.22

0.21

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

0.18

0.17

0.16

0.15

0.14

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D015

D016

V_DS(OCP)= 0.17 V

V_DS(OCP)= 0.24 V

图 17. OCP Threshold Voltage

图 18. OCP Threshold Voltage

0.51

1

0.99

0.98

0.97

0.96

0.95

0.94

0.93

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 45 V

0.505

0.5

0.495

0.49

0.485

0.48

0.475

0.47

0.465

0.46

0.455

0.45

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D017

D018

V_DS(OCP)= 0.48 V

V_DS(OCP)= 0.96 V

图 19. OCP Threshold Voltage

图 20. OCP Threshold Voltage

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D019

D020

V_VM= 5.5 V

图 21. High-Side Source Current

图 22. High-Side Sink Current

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

Typical Characteristics (接下页)

250

450

400

350

300

250

200

150

100

50

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

200

150

100

50

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

D021

D022

V_VM= 5.5 V

图 23. Low-Side Source Current

V_VM= 5.5 V

图 24. Low-Side Sink Current

350

300

250

200

150

100

50

550

500

450

400

350

300

250

200

150

100

50

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

0

-50

0

-50

-25

0

25

50

75

100

125

-25

0

25

50

75

125

Temperature (èC)

D023

D024

V_VM= 13.5 V

图 25. High-Side Source Current

图 26. High-Side Sink Current

300

250

200

150

100

50

550

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

3'b111

3'b110

3'b101

3'b100

3'b011

3'b010

500

450

400

350

300

250

200

150

100

50

0

-50

0

-50

-25

0

25

50

75

100

125

-25

0

25

50

75

125

Temperature (èC)

D025

D026

V_VM= 13.5 V

图 27. Low-Side Source Current

图 28. Low-Side Sink Current

17

DRV8702D-Q1, DRV8703D-Q1

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7 Detailed Description

7.1 Overview

DRV87002D-Q1 and DRV87003D-Q1 are single half-bridge drivers, also referred to as gate controllers. The

drivers control two external NMOS FETs used to drive a bi-directional brushed-DC motors. The devices can also

operate in independent half bridge mode to drive two single directional brushed-DC motors.

The devices can support supply voltages from 5.5 V to 45 V and have a low power sleep mode enabled through

the nSLEEP pin. There are three options for the interface modes including a configurable PH/EN, independent

half-bridge control, or PWM interface. This allows easy interfacing to the controller circuit.

DRV87002D-Q1 and DRV87003D-Q1 include Smart Gate Drive technology which offers a combination of

protection features and gate-drive configurability to improve design simplicity and bring a new level of intelligence

to motor systems. The gate-drive strength, or gate-drive current can be adjusted through the driver itself to

optimize for different FETs and applications without the need for external resistors. Smart Gate Drive significantly

reduces the component count of discrete motor-driver systems by integrating the required FET drive circuitry into

a single device. The peak current can be adjusted through the IDRIVE pin for DRV8702D-Q1 and through SPI

for DRV8703D-Q1. Both the high-side and low-side FETs are driven with a gate source voltage (VGS) of 10.5 V

(nominal) when the VM voltage is more than 13.5 V. At lower VM voltages, the VGS is reduced. The high-side

gate drive voltage is generated using a doubler-architecture charge pump that regulates to the VM + 10.5 V.

The inrush or start up current and running current can be limited through a built in fixed time-off current chopping

scheme. The chopping current level is set through the sense resistor by setting a voltage on the VREF pin. See

the current regulation section for more information. A shunt-amplifier is also included in the devices to provide

accurate current measurements to the system controller. The SO pin outputs a voltage that is approximately 20

times the voltage across the sense resistor on the DRV8702D-Q1 device. For the DRV8703D-Q1, this gain is

configurable.

The DRV870xD-Q1 device also has protection features beyond traditional discrete implementations including:

undervoltage lockout (UVLO), overcurrent protection (OCP), gate driver faults, and thermal shutdown (TSD).

The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal

charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the

device.

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7.2 Functional Block Diagram

VM

0.1 …F

10 µF

(minimum)

VM

Power

VDRAIN

1 µF

VCP

V_VCP

GH

HS

CPH

Charge Pump

0.1 µF

CPL

DVDD

3.3-V LDO

Gate Driver

Logic

1 µF

SH

GL

AVDD

5-V LDO

1 µF

M

V_GLSLDO

V_GLS

LS

IN1

IN2

nSLEEP

Current Regulation

Control Inputs

SP

MODE

R_(SENSE)

+

A_V

IDRIVE

SN

SO

œ

R_IDRIVE

VDS

R_VDS

VREF

Output

nFAULT

GND

PAD

图 29. DRV8702D-Q1 Functional Block Diagram

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Functional Block Diagram (接下页)

VM

0.1 …F

10 µF

(minimum)

VM

Power

1 µF

VCP

VDRAIN

GH

Gate Driver

V_VCP

CPH

0.1 µF

Charge Pump

HS

CPL

DVDD

3.3-V LDO

5-V LDO

1 µF

AVDD

1 µF

Logic

SH

V_GLSLDO

V_GLS

M

IN1

IN2

GL

LS

Control Inputs

nSLEEP

Current Regulation

SP

MODE

Outputs

A_V

R_(SENSE)

+

-

nFAULT

SN

SO

nWDFLT

VREF

SCLK

SDI

SPI

SDO

nSCS

GND

PAD

图 30. DRV8703D-Q1 Functional Block Diagram

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7.3 Feature Description

表 1 and 表 2 list the recommended external components for the device.

表 1. External Components

COMPONENT

C_(VM1)

PIN 1

VM

PIN 2

GND

RECOMMENDED

0.1-µF ceramic capacitor rated for VM

≥ 10-µF electrolytic capacitor rated for VM

16-V, 1-µF ceramic capacitor

0.1-µF X7R capacitor rated for VM

6.3-V, 1-µF ceramic capacitor

For resistor sizing, see the Typical Application section

≥ 10 kΩ

C_(VM2)

VM

GND

C_(VCP)

VCP

VM

C_(SW)

CPH

CPL

C_(DVDD)

C_(AVDD)

R_(IDRIVE)

R_(VDS)

DVDD

AVDD

IDRIVE

VDS

GND

(1)

R_(nFAULT)

R_(nWDFLT)

R_(SENSE)

V_CC

nFAULT

nWDFLT

SN or GND

VM

(1)

V_CC

≥ 10 kΩ

SP

Optional low-side sense resistor

100-Ω series resistor

(2)

R_(VDRAIN)

VDRAIN

(1) The V_CCpin is not a pin on the DRV870xD-Q1, but a V_CCsupply voltage pullup is required for open-drain outputs nFAULT. These pins

can be pulled up to either AVDD or DVDD.

(2) The R_(VDRAIN)resistor should be used between the VDRAIN and VM pins to minimize current to the VDRAIN pin if no external reverse

battery protection is implemented on the VDRAIN pin.

表 2. External Gates

COMPONENT

GATE

DRAIN

SOURCE

RECOMMENDED

Supports FETs up to 200 nC at 40 kHz

PWM

Q_(HS)

GH

VM

SH

For more information, see Application

Q_(LS)

GL

SH

SP or GND

and Implementation

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7.3.1 Bridge Control

The DRV870xD-Q1 device is controlled using a configurable input interface. The Logic Tables section provides

the half-bridge operation states. These tables do not consider the current control built into the DRV870xD-Q1

device. The logic operation set by the MODE pin is latched on power-up or when exiting sleep mode. 图 31

shows the direction of the flow of current through the load when it is connected between the SH pin and GND,

and between the SH pin and VM.

VM

1

2

Drive

Slow decay (brake)

2

1

2

1

SH

图 31. Bridge Control

7.3.1.1 Logic Tables

表 3, and 表 4 are the device logic tables. An X denotes a don’t care input or output.

注

Any other input logic combinations, aside from the ones mentioned in 表 3 and 表 4, result

in an error, and the device will trigger a fault.

表 3. DRV870xD-Q1 PWM Control Interface Without Current Regulation (MODE = 1)

nSLEEP

IN1

X

IN2

X

GH

X

GL

X

SH

Hi-Z

L

AVDD/DVDD

Disabled

Description

0

1

Sleep mode ½-bridge disabled

½-bridge low side on

0

1

Enabled

1

0

1

0

H

Enabled

½-bridge high side on

表 4. DRV870xD-Q1 PWM Control Interface With Current Regulation (MODE = Hi-Z)

nSLEEP

IN1

X

IN2

X

GH

X

GL

X

SH

Hi-Z

H

AVDD/DVDD

Disabled

Enabled

Description

Sleep mode ½-bridge disabled

½-bridge is in tri-state

½-bridge high-side on

½-bridge low-side on

0

1

0

1

0

1

0

Enabled

1

0

1

L

Enabled

If MODE = Hi-Z is selected, the device performs current regulation (refer to the Current Regulation section).

Having both the input (INx) pins high puts the motor in brake mode (low-side slow decay). If MODE = 1 is

selected, current regulation is disabled and must be performed externally using a MCU. With MODE = 1, the load

current recirculation occurs through the high-side FET as shown in 图 31.

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7.3.2 MODE Pin

The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep

mode. 图 32 shows an overview of the internal circuit of the MODE pin.

DVDD

+

œ

1.35 V

0.75 V

Digital

Core

26 kꢀ

MODE

+

65 kꢀ

œ

图 32. MODE Pin Block Diagram

表 5 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep mode.

表 5. MODE Pin Configuration

MODE

1

CONTROL INTERFACE

PWM control interface without current regulation

PWM control interface with current regulation

Hi-Z

During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the

AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to

the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin

if not driven by an external microcontroller (MCU).

7.3.3 nFAULT Pin

The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is

detected, the nFAULT line is logic low.

Output

nFAULT

图 33. nFAULT Block Diagram

For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the Application and

Implementation section). For a 5-V pullup an external 5-V supply should be used. TI does not recommended

connecting the nFAULT pin to the AVDD pin.

7.3.4 Current Regulation

The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or

current chopping. When an half-bridge is enabled, current rises through the winding at a rate dependent on the

DC voltage and inductance of the winding. When the current hits the current chopping threshold, the bridge

enters a brake (low-side slow decay) mode until the t_offtime expires.

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注

Immediately after the current is enabled, the voltage on the SP pin is ignored for a period

(t_(BLANK)) before enabling the current-sense circuitry.

The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor

connected to the SP pin, multiplied by a factor of A_V, with a reference voltage from the VREF pin. The factor A_V

is the shunt-amplifier gain, which is 19.8 V/V for the DRV8702D-Q1 device or configurable to 10, 19.8, 39.4, or

78 V/V for the DRV8703D-Q1 device.

Use 公式 1 to calculate the chopping current (I_CHOP).

V_VREF- V ì A_V

A_Vì R_(SENSE)

IO

I_(CHOP)

=

(1)

For example, if a 50-mΩ sense resistor and a VREF value of 3.3 V are selected, the full-scale chopping current

is 3.28 A. The A_Vis 19.8 V/V and V_IOis assumed to be 50 mV in this example.

注

If the load is connected between the SH pin and VM and current regulation is enabled

(MODE pin is Hi-Z), the low-side FET is switched on when the current flowing through the

load exceeds the ICHOP threshold. This result in an adverse effect by driving the load at

100% duty cycle because the maximum current flows through the load as the low-side

FET remains switched on for the t_OFFduration. Texas Instruments recommends using the

PWM control interface without current regulation (MODE pin is 1) for this configuration to

drive the load.

For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current

regulation feature is not needed, it can be disabled by tying the VREF pin directly to the AVDD pin. If the PWM

control-interface mode without current regulation (MODE pin is 1) is selected for operation, the device does not

perform PWM current regulation or current chopping.

7.3.5 Amplifier Output (SO)

The SO pin on the DRV870xD-Q1 device outputs an analog voltage equal to the voltage across the SP and SN

pins multiplied by A_V. The SO voltage is only valid for when the load is connected in the way shown in 图 31. Use

公式 2 to calculate the approximate current for the half-bridge.

V_SO- V ì A_V

A_Vì R_(SENSE)

IO

I =

(2)

When the SP and SN voltages are 0 V, the SO pin outputs the amplifier offset voltage times the amplifier gain,

V_io× Av. When SP minus SN is greater than 0 V, the SO pin outputs the sum of the amplifier offset voltage and

the sense resist or voltage, times the amplifier gain, (V_io+ V_rsense) × Av. No capacitor is required on the SO pin.

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AVDD

A_V

V_IO× A_V

SP-SN (V)

图 34. Current Sense Amplifier Output

If the voltage across the SP and SN pins exceeds 1 V, then the DRV870xD-Q1 device flags an overcurrent

condition.

The SO pin can source up to 5 mA of current. If the pin is shorted to ground, or if this pin drives a higher current

load, the output functions as a constant-current source. The output voltage is not representative of the half-bridge

current in this state.

I_(CHOP)

Drive

Brake and Slow Decay

t_OFF

Drive

Brake and Slow Decay

t_OFF

t_(DRIVE)

(V_io+V_rsense) x A_V

V_VREF

图 35. Current Sense Amplifier and Current Chopping Operation

During brake mode (slow decay), current is circulated through the low-side FET. Because current is not flowing

through the sense resistor, the SO pin does not represent the motor current.

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7.3.5.1 SO Sample and Hold Operation

The DRV8703D-Q1 device allows the shunt amplifier to operate in a sample and hold configuration. To enable

this mode, set the SH_EN bit high through the SPI. In this mode, the shunt amplifier output is disabled to the

Hi-Z state whenever the driver is in a brake mode. Place an external capacitor on this pin.

I_(CHOP)

Drive

Brake and Slow Decay

t_OFF

Drive

Brake and Slow Decay

t_OFF

t_(DRIVE)

(V_io+V_rsense) x A_V

V_VREF

SO Output Hi-Z

图 36. Sample and Hold Operation

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7.3.6 PWM Motor Gate Drivers

The DRV870xD-Q1 device has gate drivers for a single half-bridge with external NMOS FETs. 图 37 shows a

block diagram of the predrive circuitry.

V_GHS

VM

GH

IN

R_(OFF)

SH

Predrive

V_GLS

Logic

nSLEEP

GL

M

R_(OFF)

SP

SN

R_(SENSE)

图 37. Predrive Block Diagram

Gate drivers inside the DRV870xD-Q1 device directly drive N-Channel MOSFETs, which drive the motor current.

The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate

drive.

The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702D-Q1 device or the

IDRIVE register for the DRV8703D-Q1 device. Peak source currents can be set to the values listed in the FET

gate drivers section of the Electrical Characteristics table. The peak sink current is approximately two times the

peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET

input capacitance and gate charge.

Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically

because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts

reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation

because the external FETs have a longer turn on and turn off time.

When changing the state of the output, the peak current (I_DRIVE) is applied for a short period (t_(DRIVE)), to charge

the gate capacitance. After this time, a weak current source (I_HOLD) is used to keep the gate at the desired state.

When selecting the gate drive strength for a given external FET, the selected current must be high enough to

charge fully and discharge the gate during t_(DRIVE), or excessive power is dissipated in the FET.

During high-side turn on, the low-side gate is pulled low with a strong pulldown (I_STRONG). This pulldown prevents

the low-side FET Q_GSfrom charging and keeps the FET off, even when fast switching occurs at the outputs.

The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and

low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents

the high-side or low-side FET from turning on until the opposite FET turns off.

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t_(DRIVE)

I_HOLD

I_DRIVE(SNK)

High-side

gate drive

current

I_STRONG

High-side

V_GS

t_DRIVE

I_HOLD

Low-side

I_DRIVE(SNK)

gate drive

current

I_STRONG

Low-side

V_GS

图 38. Gate Driver Output to Control External FETs

7.3.6.1 Miller Charge (Q_GD

)

When a FET gate turns on, the following capacitances must be charged:

•

Gate-to-source charge, Q_GS

Gate-to-drain charge, Q_GD(Miller charge)

Remaining Q_G

The FET output is slewing primarily during the Q_GDcharge.

24 V

25

20

10

8

D

V_GHS

6

15

10

5

G

GH

Predrive

4

SH

2

S

10

30

40

50

20

Q_GS

Q_GD

Gate Charge (nC)

图 39. FET Gate Charging Profile

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7.3.7 IDRIVE Pin (DRV8702D-Q1 Only)

The rise and fall times of the half-bridge output (SH pin) can be adjusted by setting the IDRIVE resistor value or

forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is selected.

The ramp of the FET gate directly affects the rise and fall times of the half-bridge output.

Tying the IDRIVE pin to ground selects the lowest drive setting of 10-mA source and 20-mA sink. Leaving this

pin open selects the drive setting of 155-mA high side and 130-mA low side for source current, and 265-mA high

side, 260-mA low side for sink current, at a VM voltage of 13.5 V. For a detailed list of IDRIVE configurations,

see 表 6.

+

œ

4.9 V

3.7 V

2.5 V

AVDD

+

190 kΩ

œ

IDRIVE

+

310 kΩ

Digital

Core

œ

+

œ

1.3 V

0.1 V

+

œ

图 40. IDRIVE Pin Internal Circuitry

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表 6. DRV8702D-Q1 IDRIVE Settings

SOURCE CURRENT

SINK CURRENT

IDRIVE

RESISTANCE

IDRIVE

VOLTAGE

CIRCUIT

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 5.5 V

V_VM= 13.5 V

IDRIVE

High-side: 10 mA

Low-side: 10 mA

High-side: 10 mA

Low-side: 10 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

< 1 kΩ to GND

GND

0.7 V ± 5%

2 V ± 5%

3 V ± 5%

4 V ± 5%

AVDD

IDRIVE

33 kΩ ± 5% to

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 40 mA

Low-side: 40 mA

High-side: 40 mA

Low-side: 40 mA

GND

R_IDRIVE

IDRIVE

200 kΩ ± 5% to

High-side: 50 mA

Low-side: 40 mA

High-side: 50 mA

Low-side: 45 mA

High-side: 90 mA

Low-side: 85 mA

High-side: 95 mA

Low-side: 95 mA

GND

R_IDRIVE

IDRIVE

> 2 MΩ to GND,

High-side: 145 mA High-side: 155 mA High-side: 250 mA High-side: 265 mA

Low-side: 115 mA Low-side: 130 mA Low-side: 235 mA Low-side: 260 mA

Hi-Z

AVDD

68 kΩ ± 5% to

High-side: 190 mA High-side: 210 mA High-side: 330 mA High-side: 350 mA

Low-side: 145 mA Low-side: 180 mA Low-side: 300 mA Low-side: 350 mA

IDRIVE

AVDD

High-side: 240 mA High-side: 260 mA High-side: 420 mA High-side: 440 mA

Low-side: 190 mA Low-side: 225 mA Low-side: 360 mA Low-side:430 mA

< 1 kΩ to AVDD

IDRIVE

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7.3.8 Dead Time

The dead time (t_(DEAD)) is measured as the time when the SH pin is in the Hi-Z state between turning off one of

the half-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side

FET and turning on the low-side FET.

The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702D-Q1 device has a

digital dead time of approximately 240 ns. The DRV8703D-Q1 device has programmable dead-time options of

120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the

GL pin to ground or GH pin to SH pin is less than the FET threshold voltage.

The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GH

and GL pins) includes the observable dead time.

7.3.9 Propagation Delay

The propagation delay time (t_PD) is measured as the time between an input edge to an output change. This time

is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on

the input pins from affecting the output state.

The gate drive slew rate also contributes to the delay time. For the output to change state during normal

operation, one FET must first be turned off. The FET gate is ramped down according to the IDRIVE resistor

selection, and the observed propagation delay ends when the FET gate falls below the threshold voltage.

7.3.10 Overcurrent VDS Monitor

The gate-driver circuit monitors the VDS voltage of each external FET when it is driving current. When the

voltage monitored is greater than the OCP threshold voltage (V_DS(OCP)) after the OCP deglitch time has expired,

an OCP condition is detected. The V_DS(OCP)voltage can be adjusted by changing the resistor (R_VDS) on the VDS

pin of the DRV8702D-Q1 device. The DRV8703D-Q1 device provides V_DS(OCP)voltage levels by setting the VDS

register.

VM

VDRAIN

+

High-Side

VDS OCP

Monitor

GH

SH

GL

œ

+

Low-Side

VDS OCP

Monitor 1

M

œ

SP

SN

R_(SENSE)

图 41. V_DS(OCP)Block Diagram

The VDS voltage on the high-side FET is measured across the VDRAIN to SH pin. The low-side VDS monitor

measures the VDS voltage across the SH to SP pins. Ensure that the SP pin is always connected to the source

of the low-side FET of half-bridge, even when the sense amplifier is not used.

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7.3.11 VDS Pin (DRV8702D-Q1 Only)

The VDS pin on the DRV8702D-Q1 device is used to select the VDS threshold voltage for overcurrent detection.

Tying the VDS pin to ground selects the lowest setting of 0.06 V. Leaving this pin open selects the setting of

0.48 V. Tying the VDS pin to the AVDD the pin disables the VDS monitor. For a detailed list of VDS

configurations, see 表 7.

+

œ

4.9 V

3.7 V

2.5 V

AVDD

+

190 kΩ

œ

VDS

+

310 kΩ

Digital

Core

œ

+

œ

1.3 V

0.1 V

+

œ

图 42. VDS Block Diagram

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表 7. VDS Pin Resistor Setting

OVERCURRENT

TRIP LEVEL

VDS RESISTANCE

VDS VOLTAGE

CIRCUIT

(V_DS(OCP)

)

VDS

< 1 kΩ to GND

33 kΩ ± 5% to GND

200 kΩ ± 5% to GND

> 2 MΩ to GND, Hi-Z

68 kΩ ± 5% to AVDD

< 1 kΩ to AVDD

GND

0.06 V

VDS

0.7 V ± 5%

2 V ± 5%

3 V ± 5%

4 V ± 5%

AVDD

0.12 V

0.24 V

0.48 V

0.96 V

R_IDRIVE

VDS

R_IDRIVE

VDS

AVDD

VDS

AVDD

VDS

Disabled

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7.3.12 Charge Pump

A charge pump is integrated to supply the gate drive voltage of a high-side NMOS (V_GSH). The charge pump

requires a capacitor between the VM and VCP pins. Additionally, a low-ESR ceramic capacitor is required

between the CPH and CPL pins. When the VM voltage is below 13.5 V, this charge pump functions as a doubler

and generates a V_VCPequal to 2 × V_VM– 1.5 V if unloaded. When the VM voltage is more than 13.5 V, the

charge pump regulates V_VCPsuch that it is equal to V_VM+ 10.5 V.

VM

1 ꢀF

VCP

CPH

VM

Charge

Pump

0.1 ꢀF

CPL

图 43. Charge Pump Block Diagram

7.3.13 Gate Drive Clamp

A clamping structure limits the gate-drive output voltage to the V_C(GS)voltage to protect the power FETs from

damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the

body diodes of the internal predriver FET.

V_GHS

VM

I_(REVERSE)

GH

V_GS> V_C

I_C

SH

Predriver

V_GLS

V_GSnegative

GL

R_(SENSE)

PGND

图 44. Gate Drive Clamp

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7.3.14 Protection Circuits

The DRV870xD-Q1 device is protected against VM undervoltage, charge-pump undervoltage, overcurrent, gate-

driver shorts, and overtemperature events.

7.3.14.1 VM Undervoltage Lockout (UVLO2)

If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (V_UVLO2), both FETs in the

half-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of

the DRV8703D-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold.

The nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703D-Q1 device

remains set until cleared by writing to the CLR_FLT bit.

The SPI settings on the DRV8703D-Q1 device are not reset by this fault even though the output drivers are

disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic

undervoltage threshold (VUVLO1).

7.3.14.2 Logic Undervoltage (UVLO1)

If the voltage on the VM pin falls below the logic undervoltage threshold voltage (V_UVLO1), the internal logic is

reset. The operation resumes when the VM voltage rises above the UVLO1 threshold. The nFAULT pin is logic

low during this state because it is pulled low when the VM undervoltage condition occurs. Decreasing the VM

voltage below this undervoltage threshold resets the SPI settings.

7.3.14.3 VCP Undervoltage Lockout (CPUV)

If the voltage on the VCP pin falls below the threshold voltage of the charge-pump undervoltage (CPUV) lockout,

both FETs in the half-bridge are disabled and the nFAULT pin is driven low. The DRV8703D-Q1 the VCP_UVFL

bit is set. The operation resumes when the VCP voltage rises above the CPUV threshold. The nFAULT pin is

released after the operation resumes but the VCP_UVFL bit on the DRV8703D-Q1 device remains set until

cleared by writing to the CLR_FLT bit.

7.3.14.4 Overcurrent Protection (OCP)

Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a

driven FET exceeds the V_DS(OCP)level for longer than the OCP deglitch time, an OCP event is recognized. Both

FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703D-Q1

device is set. The drive re-enables after the t_(RETRY)time has passed. The nFAULT pin becomes high again after

the retry time.

If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes

and the nFAULT pin goes high. The OCP bit on the DRV8703D-Q1 remains set until cleared by writing to the

CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP

pin exceeds V_SP(OCP)and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.

7.3.14.5 Gate Driver Fault (GDF)

The GH and GL pins are monitored such that if the voltage on the external FET gate does not increase or

decrease after the t_(DRIVE)time, a gate driver fault is detected. This fault occurs if the GH or GL pins are shorted

to the GND, SH, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not sufficient

to turn on the external FET. Both FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The

GDF bit of the DRV8703D-Q1 device is set. The driver re-enables after the OCP retry period (t_(RETRY)) has

passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703D-Q1

device remains set until cleared by writing to the CLR_FLT bit.

7.3.14.6 Thermal Shutdown (TSD)

If the die temperature exceeds the T_SDtemperature, both FETs in the half-bridge are disabled, the charge pump

shuts down, the AVDD regulator is disabled, and the nFAULT pin is driven low. The OTSD bit of the DRV8703D-

Q1 device is set as well. After the die temperature falls below T_SD– T_hystemperature, device operation

automatically resumes. The nFAULT pin is released after the operation resumes, but the OTSD bit on the

DRV8703D-Q1 device remains set until cleared by writing to the CLR_FLT bit.

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7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)

An MCU watchdog function can be enabled to ensure that the external controller that is instructing the

DRV8703D-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the

WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts

to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within

the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is

enabled. When the nWDFLT pin is enabled the following occurs:

•

The nWDFLT pin goes low for 64 µs.

The nFAULT pin is asserted.

The WD_EN bit is cleared.

The drivers are disabled.

The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.

表 8 lists the fault responses of the device under the fault conditions.

表 8. Fault Response

FAULT

CONDITION

HALF-BRIDGE

CHARGE PUMP

AVDD

DVDD

RECOVERY

VM undervoltage

(UVLO)

V_VM≤ V_(UVLOx)

(5.45 V, max)

V_VM≥ V_(UVLOx)

(5.65 V, max)

Disabled

Operating

VCP undervoltage

(CPUV)

V

_VCP≤ V_{(CP_UV)}

V

_VCP≥ V_{(CP_UV)}

Disabled

Operating

Disabled

Operating

Disabled

Operating

(V_VM+ 1.5, typ)

External FET overload

(OCP)

V_DS≥ V_DS(OCP)

V_SP– V_SN> 1 V

t_(RETRY)

Gate driver fault

(GDF)

Gate voltage unchanged after

t_(DRIVE)

Watchdog fault

(WDFLT)

Watchdog timer expires

CLR_FLT bit

Thermal shutdown

(TSD)

T_J≤ T_SD– T_hys

T_J≥ T_SD(150°C, min)

(T_hysis typically 20°C)

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7.3.14.8 Reverse Supply Protection

The circuit in 图 45 can be implemented to help protect the system from reverse supply conditions. This circuit

requires the following additional components:

•

NMOS FET

NPN BJT

Diode

10-kΩ resistor

43-kΩ resistor

VM

43 kΩ

10 kΩ

0.1 µF

CP2

1 µF

+

Bulk

10 µF (min)

0.1 µF

CP1

VCP

VM

GH

SH

GL

M

SP

SN

R_(SENSE)

图 45. Reverse Supply Protection

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7.3.15 Hardware Interface

The DRV8702D-Q1 hardware interface allows the device to be configured without a SPI, however not all of the

functionality is configurable like the DRV8703D-Q1 device. The following configuration settings are fixed for the

hardware-interface device option:

•

The t_offvalue is set to 25 µs.

Current regulation is enabled

The VREF pin voltage is not scaled internally (100%).

The shunt amplifier has a fixed gain of 19.8 V/V.

7.3.15.1 IDRIVE (6-level input)

The voltage or resistance on the IDRIVE pin sets the peak source and peak sink IDRIVE setting as listed in 表 9.

表 9. DRV8702D-Q1 IDRIVE Settings

SOURCE CURRENT

SINK CURRENT

V_VM= 13.5 V

IDRIVE

RESISTANCE

IDRIVE VOLTAGE

V_VM= 5.5 V

V_VM= 13.5 V

V_VM= 5.5 V

High-side: 10 mA

Low-side: 10 mA

High-side: 10 mA

Low-side: 10 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

< 1 kΩ to GND

GND

0.7 V ± 5%

2 V ± 5%

3 V ± 5%

4 V ± 5%

AVDD

33 kΩ ± 5% to

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 40 mA

Low-side: 40 mA

High-side: 40 mA

Low-side: 40 mA

GND

200 kΩ ± 5% to

High-side: 50 mA

Low-side: 40 mA

High-side: 50 mA

Low-side: 45 mA

High-side: 90 mA

Low-side: 85 mA

High-side: 95 mA

Low-side: 95 mA

GND

> 2 MΩ to GND,

High-side: 145 mA

Low-side: 115 mA

High-side: 155 mA

Low-side: 130 mA

High-side: 250 mA

Low-side: 235 mA

High-side: 265 mA

Low-side: 260 mA

Hi-Z

68 kΩ ± 5% to

High-side: 190 mA

Low-side: 145 mA

High-side: 210 mA

Low-side: 180 mA

High-side: 330 mA

Low-side: 300 mA

High-side: 350 mA

Low-side: 350 mA

AVDD

High-side: 240 mA

Low-side: 190 mA

High-side: 260 mA

Low-side: 225 mA

High-side: 420 mA

Low-side: 360 mA

High-side: 440 mA

Low-side:430 mA

< 1 kΩ to AVDD

7.3.15.2 VDS (6-Level Input)

This input controls the VDS monitor trip voltage as listed in 表 10.

表 10. DRV8702D-Q1 VDS Settings

OVERCURRENT TRIP LEVEL

VDS RESISTANCE

VDS VOLTAGE

(V_DS(OCP)

0.06 V

0.12 V

0.24 V

0.48 V

0.96 V

)

< 1 kΩ to GND

33 kΩ ± 5% to GND

200 kΩ ± 5% to GND

> 2 MΩ to GND, Hi-Z

68 kΩ ± 5% to AVDD

< 1 kΩ to AVDD

GND

0.7 V ± 5%

2 V ± 5%

3 V ± 5%

4 V ± 5%

AVDD

Disabled

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7.4 Device Functional Modes

The DRV870xD-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is

disabled, the half-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.

注

The t_(SLEEP)time must elapse after a falling edge on the nSLEEP pin before the device is

in sleep mode. The DRV870xD-Q1 device is brought out of sleep mode automatically if

the nSLEEP pin is brought high.

The t_(WAKE)time must elapse before the outputs change state after wakeup.

On the DRV8703D-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.

While the nSLEEP pin is brought low, both external half-bridge FETs are disabled. The high-side gate pin, GH,

are pulled to the output node, SH, by an internal resistor and the low-side gate pin, GL, are pulled to ground.

When the VM voltage is not applied and during the power-on time (t_on) the outputs are disabled using weak

pulldown resistors between the GH and SH pins and the GL and GND pins.

注

The MODE pin controls the device-logic operation for the PWM input mode. This operation

is latched on power up or when exiting sleep mode.

7.5 Programming

7.5.1 SPI Communication

7.5.1.1 Serial Peripheral Interface (SPI)

The SPI (DRV8703D-Q1 only) is used to set device configurations, operating parameters, and read out

diagnostic information. The DRV8703D-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists

of a 16-bit word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word

consists of 8-bit register data and the first 8 bits are don’t cares.

A valid frame has to meet following conditions:

•

The clock polarity (CPOL) must be set to 0.

The clock phase (CPHA) must be set to 0.

The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.

No SCLK signal can occur when the nSCS signal is in transition.

The SCLK pin must be low when the nSCS pin goes high.

The nSCS pin should be taken high for at least 500 ns between frames.

When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is

in the high impedance state.

•

Full 16 SCLK cycles must occur.

Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.

The most-significant bit (MSB) is shifted in and out first

For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error

occurs and the data word is ignored.

•

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 5-bit command data

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Programming (接下页)

7.5.1.2 SPI Format

The SDI input-data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit 15)

4 address bits, A (bits 14 through 11)

3 don't care bits, X (10 through 8)

8 data bits, D (7:0)

The SDO output-data word is 16 bits long and the first 8 bits are don’t care bits. The data word is the content of

the register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read.

表 11. SDI Input Data Word Format

R/W

B15

W0

ADDRESS

DON'T CARE

DATA

B4

D4

B14

A3

B13

A2

B12

A1

B11

A0

B10

X

B9

X

B8

X

B7

D7

B6

D6

B5

D5

B3

D3

B2

D2

B1

D1

B0

D0

表 12. SDO Output Data Word Format

DON'T CARE

DATA

B15

X

B14

X

B13

X

B12

X

B11

X

B10

X

B9

X

B8

X

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

nSCS

SCLK

SDI

X

Z

X

Z

MSB

LSB

SDO

LSB

MSB

Capture

Point

Propagate

Point

图 46. SPI Transaction

The SCLK pin should be low at power-up of the device for reliable SPI transaction. If the SCLK pin cannot be

guaranteed to be low at power-up, TI recommends performing a dummy SPI-read transaction (of any register)

after power-up to ensure reliable subsequent transactions. Data read from this dummy read transaction should

be discarded.

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7.6 Register Maps

DRV8703D-Q1 Memory Map

Register

7

Access

Type

Address

(Hex)

6

5

4

3

2

1

0

Name

FAULT Status

VDS and GDF

Main

FAULT

WDFLT

GDF

OCP

L_GDF

LOCK

VM_UVFL

VCP_UVFL

OTSD

H_VDS

IN2

OTW

L_VDS

R

0

1

2

3

4

5

RESERVED

H_GDF

RESERVED

R

RESERVED

TDEAD

IN1

CLR_FLT

RW

IDRIVE and WD

VDS

WD_EN

VDS

WD_DLY

IDRIVE

DIS_H_VDS

SO_LIM

RESERVED

SH_EN

DIS_L_VDS

Config

TOFF

CHOP_IDS

VREF_SCL

GAIN_CS

表 13. Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

7.6.1 Status Registers

The status registers are used to report warning and fault conditions. Status registers are read only registers.

表 14 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表 14

should be considered as reserved locations and the register contents should not be modified.

表 14. Status Registers Summary Table

Address

0x00h

Register Name

FAULT status

Section

Go

0x01h

VDS and GDF status

Go

7.6.1.1 FAULT Status Register (address = 0x00h)

FAULT status is shown in 图 47 and described in 表 15.

Return to Summary Table.

Read only

图 47. FAULT Status Register

7

6

5

4

3

2

1

0

FAULT

R-0b

WDFLT

R-0b

GDF

R-0b

OCP

R-0b

VM_UVFL

R-0b

VCP_UVFL

R-0b

OTSD

R-0b

OTW

R-0b

表 15. FAULT Status Field Descriptions

Bit

Field

Type

Default

Description

7

FAULT

R

0b

Logic OR of the FAULT status register excluding the OTW bit

Watchdog time-out fault

6

5

4

3

2

1

0

WDFLT

GDF

R

0b

Indicates gate drive fault condition

OCP

Indicates VDS monitor overcurrent fault condition

Indicates VM undervoltage lockout fault condition

Indicates charge-pump undervoltage fault condition

Indicates overtemperature shutdown

VM_UVFL

VCP_UVFL

OTSD

OTW

Indicates overtemperature warning

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7.6.1.2 VDS and GDF Status Register Name (address = 0x01h)

VDS and GDF status is shown in 图 48 and described in 表 16.

Return to Summary Table.

Read only

图 48. VDS and GDF Status Register

7

6

5

4

3

2

1

0

RESERVED

R-00b

H_GDF

R-0b

L_GDF

R-0b

RESERVED

R-00b

H_VDS

R-0b

L_VDS

R-0b

表 16. VDS and GDF Status Field Descriptions

Bit

Field

Type

Default

Description

7-6

RESERVED

R

00b

Reserved

5

4

H_GDF

R

0b

Indicates gate drive fault on the high-side FET of half-bridge

Indicates gate drive fault on the low-side FET of half-bridge

Reserved

L_GDF

0b

3-2

1

RESERVED

H_VDS

00b

0b

Indicates VDS monitor overcurrent fault on the high-side FET of

half-bridge

0

L_VDS

R

0b

Indicates VDS monitor overcurrent fault on the low-side FET of

half-bridge

7.6.2 Control Registers

The control registers are used to configure the device. Control registers are read and write capable.

表 17 lists the memory-mapped registers for the status registers. All register offset addresses not listed in 表 17

should be considered as reserved locations and the register contents should not be modified.

表 17. Status Registers Summary Table

Address

0x02h

0x03h

0x04h

0x05h

Register Name

Main control

Section

Go

IDRIVE and WD control

VDS control

Go

Config control

Go

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7.6.2.1 Main Control Register Name (address = 0x02h)

Main control is shown in 图 49 and described in 表 18.

Return to Summary Table.

Read and write

图 49. Main Control Register

7

6

5

4

3

2

1

0

RESERVED

R/W-00b

LOCK

IN1

IN2

CLR_FLT

R/W-0b

R/W-011b

R/W-0b

表 18. Main Control Field Descriptions

Bit

Field

Type

Default

Description

7-6

RESERVED

R/W

00b

Reserved

5-3

LOCK

R/W

011b

Write 110b to lock the settings by ignoring further register

changes except to address 0x02h. Writing any sequence other

than 110b has no effect when unlocked.

Write 011b to this register to unlock all registers. Writing any

sequence other than 011b has no effect when locked.

2

1

0

IN1

R/W

0b

This bit is ORed with the IN1 pin

This bit is ORed with the IN2 pin

Write a 1 to this bit to clear the fault bits

IN2

CLR_FLT

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7.6.2.2 IDRIVE and WD Control Register Name (address = 0x03h)

IDRIVE and WD control is shown in 图 50 and described in 表 19.

Return to Summary Table.

Read and write

图 50. IDRIVE and WD Register

7

6

5

4

3

2

1

0

TDEAD

WD_EN

R/W-0b

WD_DLY

R/W-00b

IDRIVE

R/W-111b

R/W-00b

表 19. IDRIVE and WD Field Descriptions

Bit

Field

Type

Default

Description

7-6

TDEAD

R/W

00b

Dead time

00b = 120 ns

01b = 240 ns

10b = 480 ns

11b = 960 ns

5

WD_EN

R/W

0b

Enables or disables the watchdog time (disabled by default)

4-3

WD_DLY

00b

Watchdog timeout delay (if WD_EN = 1)

00b = 10 ms

01b = 20 ms

10b = 50 ms

11b = 100 ms

2-0

IDRIVE

R/W

111b

Sets the peak source current and peak sink current of the gate

drive. 表 20 lists the bit settings.

表 20. IDRIVE Bit Settings

Source Current

V_VM= 13.5 V

Sink Current

Bit Value

V_VM= 5.5 V

V_VM= 13.5 V

High-side: 10 mA

Low-side: 10 mA

High-side: 10 mA

Low-side: 10 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

000b

001b

010b

011b

100b

101b

110b

111b

High-side: 20 mA

Low-side: 20 mA

High-side: 20 mA

Low-side: 20 mA

High-side: 40 mA

Low-side: 40 mA

High-side: 40 mA

Low-side: 40 mA

High-side: 50 mA

Low-side: 40 mA

High-side: 50 mA

Low-side: 45 mA

High-side: 90 mA

Low-side: 85 mA

High-side: 95 mA

Low-side: 95 mA

High-side: 70 mA

Low-side: 55 mA

High-side: 70 mA

Low-side: 60 mA

High-side: 120 mA

Low-side: 115 mA

High-side: 130 mA

Low-side: 125 mA

High-side: 100 mA

Low-side: 75 mA

High-side: 105 mA

Low-side: 90 mA

High-side: 170 mA

Low-side: 160 mA

High-side: 185 mA

Low-side: 180 mA

High-side: 145 mA

Low-side: 115 mA

High-side: 155 mA

Low-side: 130 mA

High-side: 250 mA

Low-side: 235 mA

High-side: 265 mA

Low-side: 260 mA

High-side: 190 mA

Low-side: 145 mA

High-side: 210 mA

Low-side: 180 mA

High-side: 330 mA

Low-side: 300 mA

High-side: 350 mA

Low-side: 350 mA

High-side: 240 mA

Low-side: 190 mA

High-side: 260 mA

Low-side: 225 mA

High-side: 420 mA

Low-side: 360 mA

High-side: 440 mA

Low-side: 430 mA

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7.6.2.3 VDS Control Register Name (address = 0x04h)

VDS control is shown in 图 51 and described in 表 21.

Return to Summary Table.

Read and write

图 51. VDS Control Register

7

6

5

4

3

2

1

0

SO_LIM

R/W-0b

VDS

RESERVED

R-00b

DIS_H_VDS

R/W-0b

DIS_L_VDS

R/W-0b

R/W-111b

表 21. VDS Control Field Descriptions

Bit

Field

Type

Default

Description

7

SO_LIM

R/W

0b

0b = Default operation

1b = SO output is voltage-limited to 3.6 V

6-4

VDS

R/W

111b

Sets the V_DS(OCP)monitor for each FET

000b = 0.06 V

001b = 0.145 V

010b = 0.17 V

011b = 0.2 V

100b = 0.12 V

101b = 0.24 V

110b = 0.48 V

111b = 0.96 V

3-2

1

RESERVED

R

00b

0b

Reserved

DIS_H_VDS

R/W

Disables the VDS monitor on the high-side FET of half-bridge

(enabled by default)

0

DIS_L_VDS

R/W

0b

Disables the VDS monitor on the low-side FET of half-bridge

(enabled by default)

45

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7.6.2.4 Config Control Register Name (address = 0x05h)

Config control is shown in 图 52 and described in 表 22.

Return to Summary Table.

Read and write

图 52. Config Control Register

7

6

5

4

3

2

1

0

TOFF

CHOP_IDS

R/W-0b

VREF_SCL

R/W-00b

SH_EN

R/W-0b

GAIN_CS

R/W-01b

R/W-00b

表 22. Config Control Field Descriptions

Bit

Field

Type

Default

Description

7-6

TOFF

R/W

00b

Off time for PWM current chopping

00b = 25 µs

01b = 50 µs

10b = 100 µs

11b = 200 µs

5

CHOP_IDS

VREF_SCL

R/W

0b

Disables current regulation (enabled by default)

4-3

00b

Scale factor for the VREF input

00b = 100%

01b = 75%

10b = 50%

11b = 25%

2

SH_EN

R/W

0b

Enables sample and hold operation of the shunt amplifier

(disabled by default)

1-0

GAIN_CS

01b

Shunt amplifier gain setting

00b = 10 V/V

01b = 19.8 V/V

10b = 39.4 V/V

11b = 78 V/V

46

DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV870xD-Q1 device is used in brushed-DC, solenoid, or relay-control applications. The following typical

application can be used to configure the DRV870xD-Q1 device.

8.2 Typical Application

This application features the DRV8702D-Q1 device.

VM

+

VM

0.1 µF

Bulk

0.1 µF 1 µF

+

Bulk

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

GND

IN1

RSVD

SP

IN2

SN

BDC

10 mΩ

GND

IDRIVE

VDS

SP

GND

(PAD)

GL

200 kΩ

SH

0 Ω

GND

nSLEEP

GH

GND

VM

+

Bulk

VM

R1

R2

10 kΩ

1 µF

图 53. DRV8702D-Q1 Typical Application Schematic

47

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 23 as the input parameters.

表 23. Design Parameters

DESIGN PARAMETER

Nominal supply voltage

REFERENCE

EXAMPLE VALUE

14 V

VM

Supply voltage range

FET part number

7 V to 35 V

CSD18502Q5B

52 nC (typical)

8.4 nC (typical)

100 to 300 ns

15 A

FET total gate charge

FET gate-to-drain charge

Target FET gate rise time

Motor current chopping level

Q_g

Q_gd

t_r

I_(CHOP)

8.2.2 Detailed Design Procedure

8.2.2.1 External FET Selection

The DRV8702D-Q1 FET support is based on the charge-pump capacity and PWM-output frequency. For a quick

calculation of FET driving capacity, use 公式 3 when drive and brake (slow decay) are the primary modes of

operation.

I_VCP

Q_g<

f_(PWM)

where

•

f_PWMis the maximum desired PWM frequency to be applied to the DRV8702D-Q1 inputs or the current

chopping frequency, whichever is larger.

•

I_VCPis the charge-pump capacity, which depends on the VM voltage.

(3)

(4)

The internal current chopping frequency is at most equal to the PWM frequency as shown in 公式 4.

1

f_(PWM)

<

t_off+ t_(BLANK)

For example, if the VM voltage of a system is 7 V (I_VCP= 8 mA) and uses a maximum PWM frequency of 40 kHz,

then the DRV8702D-Q1 device will support FETs with a Q_gup to 200 nC.

If the application requires a forced fast decay (or alternating between drive and reverse drive), use 公式 5 to

calculate the maximum FET driving capacity.

I_VCP

Q_g<

2 ì f_(PWM)

(5)

8.2.2.2 IDRIVE Configuration

The IDRIVE current is selected based on the gate charge of the FETs. The IDRIVE pin must be configured so

that the FET gates are charged entirely during the t_(DRIVE)time. If the selected IDRIVE current is too low for a

given FET, then the FET may not turn on completely. TI recommends adjusting these values in-system with the

required external FETs and motor to determine the best possible setting for any application.

For FETs with a known gate-to-drain charge (Q_gd) and desired rise time (t_r), the IDRIVE current can be selected

based on the 公式 6.

Q_gd

I_DRIVE

>

t_r

(6)

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DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

If the gate-to-drain charge is 2.3 nC and the desired rise time is around 100 to 300 ns, use 公式 7 to calculate

the minimum IDRIVE (I_DRIVE1) and 公式 8 to calculate the maximum IDRIVE (I_DRIVE2).

I_DRIVE1= 8.4 nC / 100 ns = 84 mA

I_DRIVE2= 8.4 nC / 300 ns = 28 mA

(7)

(8)

Select a value for IDRIVE between 28 and 84 mA. An IDRIVE value of approximately 50 mA for the source

(approximately 100 mA sink) was selected for this application. This value requires a 200-kΩ resistor from the

IDRIVE pin to ground.

8.2.2.3 VDS Configuration

The VDS monitor threshold voltage, V_DS(OCP), is configured based on the maximum current, I_VDS, and R_DS(on)of

the FETs. The drain to source voltage, V_DSFET, is the maximum current, I_VDS, multiplied by the R_DS(on)of the FET.

The VDS pin of the DRV8702D-Q1 selects the VDS monitor trip threshold, V_DS(OCP). The VDS bits in the VDS

register of the DRV8703D-Q1 selects the V_DS(OCP)voltage. Use 公式 9 to calculate the trip current.

V_DSFET

I_VDS

>

R_DS(on)

(9)

If the R_DS(on)of the FET is 1.8 mΩ and the desired maximum current is less than 100 A, the V_DSFETvoltage is

equal to 180 mV as shown in 公式 10.

For this example, select a value for the V_DS(OCP)that is less than 180 mV. A V_DS(OCP)value of 0.12 V was

selected for this application.

To set the V_DS(OCP)to 0.12 V, use the SPI (DRV8703D-Q1 Only) or place a 33k resistor at the VDS pin to ground

(DRV8702D-Q1 Only).

The VDS pin can configured to select other V_DS(OCP)threshold voltages. See the VDS Pin (DRV8702D-Q1 Only)

section for more information on VDS operation.

V_DSFET= I_VDS× R_DS(on)= 100 A × 1.8 mΩ = 180 mV

(10)

8.2.2.4 Current Chopping Configuration

The chopping current is set based on the sense resistor value and the analog voltage at the VREF pin. Use 公式

11 to calculate the current (I_(CHOP)). The amplifier gain, A_V, is 19.8 V/V for the DRV8702D-Q1 and V_IOis typically

5 mV (input referred).

V_VREF- V ì A_V

A_Vì R_(SENSE)

IO

I_(CHOP)

=

(11)

For example, if the desired chopping current is 15 A, select a value of 10 mΩ for R_(SENSE). The value of V_VREF

must therefore be 2.975 V. Add a resistor divider from the AVDD (5 V) pin to set the V_VREFat approximately

2.975 V. Select a value of 13 kΩ for R2 and 19.1 kΩ for R1 (the VREF resistor).

If current chopping is not required, the sense resistor can be removed and the source of the low side FET can be

connected to ground.

SN and SP should be connected to the source of the low side FET and VREF should be connected to AVDD

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8.2.3 Application Curves

SH

IN2

10-mA source

20-mA sink

10-mA source

20-mA sink

图 54. SH Fall Time

图 55. SH Rise Time

SH

I_LOAD

IN2

I_LOAD

IN2

图 56. Current Profile on Motor Startup With Regulation

图 57. Current Profile on Motor Startup Without Regulation

SH

I_LOAD

IN2

图 58. Current Regulating at 2.25 A on Motor Startup

50

DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

9 Power Supply Recommendations

The DRV8702D-Q1 device is designed to operate with an input voltage supply (VM) rangefrom 5.5 V to 45 V. A

0.1-µF ceramic capacitor rated for VM must be placed as close to the DRV8702D-Q1 device as possible. Also, a

bulk capacitor valued at least 10 µF must be placed on the VM pin.

Additional bulk capacitance is required to bypass the external half-bridge FETs.

9.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk

capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors including:

•

The highest current required by the motor system.

The capacitance of the power supply and the ability of the power supply to source current.

The amount of parasitic inductance between the power supply and motor system.

The acceptable voltage ripple.

The type of motor used (brushed DC, brushless DC, and stepper).

The motor braking method.

The inductance between the power supply and motor drive system limits the rate that current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage

remains stable, and high current can be quickly supplied.

The data sheet provides a recommended value, but system-level testing is required to determine the appropriate

sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor

Driver

+

œ

GND

Local

IC Bypass

Bulk Capacitor

Capacitor

图 59. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases

when the motor transfers energy to the supply.

51

DRV8702D-Q1, DRV8703D-Q1

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10 Layout

10.1 Layout Guidelines

The VM pin should be bypassed to ground using a low-ESR ceramic bypass capacitor with a recommended

value of 0.1 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick

trace or ground-plane connection to the GND pin of the device. The VM pin must also be bypassed to ground

using a bulk capacitor rated for VM. This capacitor can be electrolytic and must be at least 10 µF.

A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.1 µF rated for VM is

recommended. Place this capacitor as close to the pins as possible. A low-ESR ceramic capacitor must be

placed in between the VM and VCP pins. A value of 1 µF rated for 16 V is recommended. Place this component

as close to the pins as possible.

Bypass the AVDD and DVDD pins to ground with ceramic capacitors rated for 6.3 V. Place these bypassing

capacitors as close to the pins as possible.

Use separate traces to connect the SP and SN pins to the R_(SENSE)resistor.

10.2 Layout Example

R_SENSE

VM

1 µF

0.1 µF

S

G

D

1

2

3

4

5

6

7

8

24

GND

RSVD

23

22

21

SP

SN

SP

IN1

IN2

GND

20 GL

IDRIVE

VDS

(PPAD)

19

SH

Bulk

18

17

GH

GND

SH1

GND

nSLEEP

D

G

S

1 µF

图 60. DRV8702D-Q1 Layout Example

52

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www.ti.com.cn

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《DRV8702-Q1 EVM 用户指南》

德州仪器 (TI)，《DRV8703-Q1 EVM 用户指南》

德州仪器 (TI)，《小型电机驱动器天窗模块设计指南》

德州仪器 (TI)，《采用 TI 智能栅极驱动技术进行电机驱动保护》TI 技术手册

德州仪器 (TI)，《采用 TI 智能栅极驱动技术缩减电机驱动 BOM 和 PCB 面积》TI 技术手册

德州仪器 (TI)，《采用 TI 智能栅极驱动技术降低 EMI 辐射发射》TI 技术手册

德州仪器 (TI)，《可在汽车应用中驱动刷式直流电机的继电器替代应用应用报告

德州仪器 (TI)，《了解 TI 智能栅极驱动器中的 IDRIVE 和 TDRIVE》

11.2 相关链接

下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链

接。

表 24. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

DRV8702D-Q1

DRV8703D-Q1

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

53

DRV8702D-Q1, DRV8703D-Q1

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www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

54

DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

PACKAGE OUTLINE

RHB0032N

VQFN - 0.9 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

A

C

0.9 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

A

2X

SYMM

33

3.5

0.3

32X

0.2

24

0.1

C A B

1

0.05

C

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4222893/B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

55

DRV8702D-Q1, DRV8703D-Q1

ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

www.ti.com.cn

EXAMPLE BOARD LAYOUT

RHB0032N

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222893/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

56

DRV8702D-Q1, DRV8703D-Q1

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ZHCSG57B –MARCH 2017–REVISED DECEMBER 2018

EXAMPLE STENCIL DESIGN

RHB0032N

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222893/B 02/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

57

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8703D-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有 SPI 控制功能的汽车类 47V、半桥智能栅极驱动器栅极驱动驱动器
文件：	总62页 (文件大小：1461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8703D-Q1 [TI]

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