DRV8832-Q1 [TI]

LOW-VOLTAGE MOTOR DRIVER IC;


型号：	DRV8832-Q1
厂家：	TEXAS INSTRUMENTS
描述：	LOW-VOLTAGE MOTOR DRIVER IC 驱动
文件：	总18页 (文件大小：791K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8832-Q1

www.ti.com

SLVSBW9B –APRIL 2013–REVISED JANUARY 2014

LOW-VOLTAGE MOTOR DRIVER IC

Check for Samples: DRV8832-Q1

FEATURES

•

Qualified for Automotive Applications

•

300-nA (Typical) Sleep Mode Current

•

AEC-Q100 Qualified With the Following

Results:

Reference Voltage Output

Current Limit Circuit

–

Device Temperature Grade 1: -40°C to

125°C Ambient Operating Temperature

Range

Fault Output

Thermally Enhanced Surface Mount Packages

–

Device HBM ESD Classification Level H2

Device CDM ESD Classification Level C4B

APPLICATIONS

•

Battery-Powered:

•

H-Bridge Voltage-Controlled Motor Driver

–

Printers

Toys

–

Drives DC Motor, One Winding of a Stepper

Motor, or Other Actuators/Loads

Robotics

Cameras

Phones

Efficient PWM Voltage Control for Constant

Motor Speed With Varying Supply Voltages

Low MOSFET On-Resistance:

HS + LS 450 mΩ

•

Small Actuators, Pumps, etc.

•

1-A Maximum DC/RMS or Peak Drive Current

2.75-V to 6.8-V Operating Supply Voltage

Range

DESCRIPTION

The DRV8832-Q1 provides an integrated motor driver solution for battery-powered toys, printers, and other low-

voltage or battery-powered motion control applications. The device has one H-bridge driver, and can drive one

DC motor or one winding of a stepper motor, as well as other loads like solenoids. The output driver block

consists of N-channel and P-channel power MOSFET’s configured as an H-bridge to drive the motor winding.

Provided with sufficient PCB heatsinking, the DRV8832-Q1 can supply up to 1-A of DC/RMS or peak output

current. It operates on power supply voltages from 2.75 V to 6.8 V.

To maintain constant motor speed over varying battery voltages while maintaining long battery life, a PWM

voltage regulation method is provided. An input pin allows programming of the regulated voltage. A built-in

voltage reference output is also provided.

Internal protection functions are provided for over current protection, short circuit protection, under voltage

lockout and overtemperature protection.

The DRV8832-Q1 also provides a current limit function to regulate the motor current during conditions like motor

startup or stall, as well as a fault output pin to signal a host processor of a fault condition.

The DRV8832-Q1 is available in tiny 3-mm x 3-mm 10-pin MSOP package with PowerPAD™ (Eco-friendly:

RoHS & no Sb/Br).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DRV8832-Q1

SLVSBW9B –APRIL 2013–REVISED JANUARY 2014

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ORDERING INFORMATION⁽¹⁾

ORDERABLE PART

TOP-SIDE

MARKING

T_A

PACKAGE⁽²⁾

NUMBER

Reel of 250

Tube of 80

DRV8832QDGQRQ1

DRV8832QDGQQ1

8832Q

-40°C to 125°C

PowerPAD™ (MSOP) - DGQ

8832Q

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DEVICE INFORMATION

Functional Block Diagram

Battery

VCC

OCP

Integ.

Comp

Gate

Drive

OUT1

Ref

VREF

VSET

DCM

VCC

Logic

IN1

IN2

OCP

Gate

Drive

OUT2

Over-

Temp

Osc

FAULTn

Current

Sense

ISENSE

GND

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Table 1. TERMINAL FUNCTIONS

EXTERNAL COMPONENTS

OR CONNECTIONS

NAME

GND

VCC

I/O⁽¹⁾

DESCRIPTION

Device ground

Bypass to GND with a 0.1-μF (minimum)

ceramic capacitor.

Device and motor supply

IN1

IN2

Bridge A input 1

Logic high sets OUT1 high

Bridge A input 2

Logic high sets OUT2 high

VREF

VSET

Reference voltage output

Voltage set input

Reference voltage output

Input voltage sets output regulation voltage

Open-drain output driven low if fault condition

present

FAULTn

Fault output

OUT1

OUT2

Bridge output 1

Bridge output 2

Connect to motor winding

Connect current sense resistor to GND.

Resistor value sets current limit level.

ISENSE

Current sense resistor

(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

DGQ PACKAGE

(TOP VIEW)

OUT2

ISENSE

OUT1

IN2

IN1

VREF

VSET

GND

(PPAD)

VCC

GND

FAULTn

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

VALUE

–0.3 to 7

–0.5 to 7

UNIT

VCC

Power supply voltage range

Input pin voltage range

Peak motor drive output current⁽³⁾

Continuous motor drive output current⁽³⁾

Continuous total power dissipation

Operating virtual junction temperature range

Storage temperature range

Internally limited

See Dissipation Ratings table

T_J

–40 to 150

–60 to 150

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed.

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THERMAL INFORMATION

DRV8832-Q1

DGQ

THERMAL METRIC⁽¹⁾

UNITS

10 PINS

69.3

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

θ_JCtop

θ_JB

63.5

51.6

°C/W

ψ_JT

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

1.5

ψ_JB

23.2

θ_JCbot

9.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

2.75

NOM

MAX

6.8

UNIT

V_CC

I_OUT

Motor power supply voltage range

Continuous or peak H-bridge output current⁽¹⁾

(1) Power dissipation and thermal limits must be observed.

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SLVSBW9B –APRIL 2013–REVISED JANUARY 2014

ELECTRICAL CHARACTERISTICS

V_CC= 2.75 V to 6.8 V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

POWER SUPPLIES

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VCC

VCC operating supply current

V_CC= 5 V

1.4

0.3

I_VCCQ

VCC sleep mode supply current V_CC= 5 V, T_A= 25°C

μA

V_CCrising

V_CCfalling

2.575

2.47

2.75

VCC undervoltage lockout

voltage

V_UVLO

LOGIC-LEVEL INPUTS

V_IL

V_IH

I_IL

Input low voltage

0.25 x VCC

Input high voltage

Input low current

Input high current

0.5 x VCC

-10

V_IN= 0

μA

I_IH

V_IN= 3.3 V

LOGIC-LEVEL OUTPUTS (FAULTn)

V_OLOutput low voltage

H-BRIDGE FETS

V_CC= 5 V, I_OL= 4 mA⁽¹⁾

0.5

V_CC= 5 V, I _O= 0.8 A, T_J= 125°C

V_CC= 5 V, I _O= 0.8 A, T_J= 25°C

V_CC= 5 V, I _O= 0.8 A, T_J= 125°C

V_CC= 5 V, I _O= 0.8 A, T_J= 25°C

340

250

270

200

450

360

R_DS(ON)

HS FET on resistance

mΩ

R_DS(ON)

I_OFF

LS FET on resistance

mΩ

μA

Off-state leakage current

–20

MOTOR DRIVER

t_R

Rise time

V_CC= 3 V, load = 4 Ω

300

t_F

Fall time

f_SW

Internal PWM frequency

44.5

kHz

PROTECTION CIRCUITS

I_OCP

t_OCP

T_TSD

Overcurrent protection trip level

1.3

150

180

OCP deglitch time

μs

°C

Thermal shutdown temperature

Die temperature⁽¹⁾

160

VOLTAGE CONTROL

V_REF

Reference output voltage

1.235

1.285

±1

1.335

V_CC= 3.3 V to 6 V, V_OUT= 3 V⁽¹⁾

I_OUT= 500 mA

ΔV_LINE

Line regulation

Load regulation

V_CC= 5 V, V_OUT= 3 V

ΔV_LOAD

±1

I_OUT= 200 mA to 800 mA⁽¹⁾

CURRENT LIMIT

V_ILIMCurrent limit sense voltage

t_ILIM

160

200

275

240

Current limit fault deglitch time

Current limit set resistance

(external resistor value)

R_ISEN

(1) Not production tested.

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TYPICAL PERFORMANCE GRAPHS

EFFICIENCY

LOAD CURRENT

(V_IN= 5 V, V_OUT= 3 V)

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

0.2

0.4

0.6

0.8

LOAD - A

Figure 1.

EFFICIENCY

OUTPUT VOLTAGE

(V_IN= 5 V, I_OUT= 500 mA)

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

Linear Regulator

DRV8832-Q1

0.5

1.5

2.5

3.5

V_OUT- V

Figure 2.

4.5

5.5

FUNCTIONAL DESCRIPTION

Power Supervisor

The DRV8832 is capable of entering a low-power sleep mode by bringing both of the INx control inputs logic low.

The outputs will be disabled Hi-Z.

In order to exit the sleep mode, bring either or both of the INx inputs logic high. This will enable the H-bridges.

When exiting the sleep mode, the FAULTn pin will pulse low.

PWM Motor Driver

The DRV8832-Q1 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry.

A block diagram of the motor control circuitry is shown below.

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VCC

OCP

IN1

OUT1

Pre-

drive

IN2

PWM

DCM

OUT2

VSET

COMP

OCP

DIFF

Integrator

ISEN

ITRIP

COMP

REF

Figure 3. Motor Control Circuitry

Bridge Control

The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:

Table 2. H-Bridge Logic

IN1

IN2

OUT1

OUT2

Function

Sleep/coast

Reverse

Forward

Brake

When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state.

The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep

mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to

the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, high-

speed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as

described below.

Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832-

Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then

the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit.

Voltage Regulation

The DRV8832-Q1 provides the ability to regulate the voltage applied to the motor winding. This feature allows

constant motor speed to be maintained even when operating from a varying supply voltage such as a

discharging battery.

The DRV8832-Q1 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current

consumption and maximize battery life.

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The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC

voltage value. This voltage is divided by 4 and compared to the VSET pin voltage. If the averaged output voltage

(divided by 4) is lower than VSET, the duty cycle of the PWM output is increased; if the averaged output voltage

(divided by 4) is higher than VSET, the duty cycle is decreased.

During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on

time. This is shown in the diagram below as case 1. The current flow direction shown indicates the state when

IN1 is high and IN2 is low.

Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%

duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional

H-bridge driver.

During the PWM off time, winding current is re-circulated by enabling both of the high-side FETs in the bridge.

This is shown as case 2 below.

VCC

Shown with

IN1=1, IN2=0

OUT1

OUT2

PWM on

PWM off

Figure 4. Voltage Regulation

Reference Output

The DRV8832-Q1 includes a reference voltage output that can be used to set the motor voltage. Typically for a

constant-speed application, VSET is driven from VREF through a resistor divider to provide a voltage equal to

1/4 the desired motor drive voltage.

For example, if VREF is connected directly to VSET, the voltage will be regulated at 5.14 V. If the desired motor

voltage is 3 V, VREF should be 0.75 V. This can be obtained with a voltage divider using 53 kΩ from VREF to

VSET, and 75 kΩ from VSET to GND.

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Current Limit

A current limit circuit is provided to protect the system in the event of an overcurrent condition, such as what

would be encountered if driving a DC motor at start-up or with an abnormal mechanical load (stall condition).

The motor current is sensed by monitoring the voltage across an external sense resistor. When the voltage

exceeds a reference voltage of 200 mV for more than approximately 3 µs, the PWM duty cycle is reduced to limit

the current through the motor to this value. This current limit allows for starting the motor while controlling the

current.

If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such

as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately

275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the

FAULTn signal low. Operation of the motor driver will continue.

The current limit fault condition is self-clearing and will be released when the abnormal load (stall condition) is

removed.

The resistor used to set the current limit must be less than 1 Ω. Its value may be calculated as follows:

200 mV

R_ISENSE=

I_LIMIT

(1)

Where:

R_ISENSEis the current sense resistor value.

I_LIMITis the desired current limit (in mA).

If the current limit feature is not needed, the ISENSE pin may be directly connected to ground.

Protection Circuits

The DRV8832-Q1 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this

analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, and the

FAULTn signal will be driven low. The device will remain disabled until VCC is removed and re-applied.

Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply,

or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the

current limit function, which is typically set to engage at a lower current level; the OCP function is intended to

prevent damage to the device under abnormal (e.g., short-circuit) conditions.

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the FAULTn signal will be

driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in

the device will be disabled, the FAULTn signal will be driven low, and internal logic will be reset. Operation will

resume when VCC rises above the UVLO threshold.

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THERMAL INFORMATION

Thermal Protection

The DRV8832-Q1 has thermal shutdown (TSD) as described above. If the die temperature exceeds

approximately 160°C, the device will be disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

Power Dissipation

Power dissipation in the DRV8832-Q1 is dominated by the power dissipated in the output FET resistance, or

R_DS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.

· ·

P_TOT= 2 R_DS(ON)(I_OUT(RMS)

)

(2)

where P_TOTis the total power dissipation, R_DS(ON)is the resistance of each FET, and I_OUT(RMS)is the RMS output

current being applied to each winding. I_OUT(RMS)is equal to the approximately 0.7x the full-scale output current

setting. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current for each

winding (one high-side and one low-side).

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and

heatsinking.

Note that R_DS(ON)increases with temperature, so as the device heats, the power dissipation increases. This must

be taken into consideration when sizing the heatsink.

Heatsinking

The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad

must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,

this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs

without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area

is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and

bottom layers.

For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally

Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated.

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REVISION HISTORY

Changes from Revision A (August 2013) to Revision B

Page

•

Added Power Supervisor section .......................................................................................................................................... 6

Changed Bridge Control section ........................................................................................................................................... 7

Changed Current Limit section ............................................................................................................................................. 9

Changed Thermal Shutdown (TSD) section ......................................................................................................................... 9

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PACKAGE OPTION ADDENDUM

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31-Dec-2013

PACKAGING INFORMATION

Orderable Device

DRV8832QDGQQ1

DRV8832QDGQRQ1

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

MSOP-

PowerPAD

DGQ

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

Level-2-260C-1 YEAR

8832Q

ACTIVE

MSOP-

DGQ

2500

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

Level-2-260C-1 YEAR

-40 to 125

PowerPAD

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

31-Dec-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8832-Q1 :

Catalog: DRV8832

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DRV8832QDGQRQ1

MSOP-

Power

PAD

DGQ

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

MSOP-PowerPAD DGQ 10

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

DRV8832QDGQRQ1

2500

Pack Materials-Page 2

IMPORTANT NOTICE

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DRV8832-Q1 [TI]

相关型号：

DRV8832-Q1_15

DRV8832DGQ

DRV8832DGQR

DRV8832DRCR

DRV8832DRCT

DRV8832QDGQQ1

DRV8832QDGQRQ1

DRV8833

DRV8833C

DRV8833CPWP

DRV8833CPWPR

DRV8833CRTER