DS100BR111SQE/NOPB [TI]
具有输入均衡和输出去加重功能的 10.3Gbps 超低功耗 2 通道转接驱动器 | RTW | 24 | -40 to 85;型号: | DS100BR111SQE/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有输入均衡和输出去加重功能的 10.3Gbps 超低功耗 2 通道转接驱动器 | RTW | 24 | -40 to 85 驱动 驱动器 |
文件: | 总39页 (文件大小:1754K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 4, 2012
DS100BR111
Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input
Equalization and Output De-Emphasis
General Description
Features
The DS100BR111 is an extremely low power, high perfor-
mance dual-channel repeater for serial links with data rates
up to 10.3 Gbps. The DS100BR111 pinout is configured as
one bidirectional lane (one transmit, one receive channel).
Two channel repeaters for up to 10.3 Gbps
■
DS100BR210 : 2x unidirectional channels
DS100BR111 : 1x bidirectional lane
—
—
10G-KR bi-directional interface compatibility
■
The DS100BR111 inputs feature a powerful 4-stage continu-
ous time linear equalizer (CTLE) to provide a boost of up to
+36 dB at 5 GHz and open an input eye that is completely
closed due to inter-symbol interference (ISI) induced by the
interconnect mediums such as an FR-4 backplane or
AWG-30 cables. The transmitter features a programmable
output de-emphasis driver with up to -12 dB and allows am-
plitude voltage levels to be selected from 700 mVp-p to 1200
mVp-p to suit multiple application scenarios.
Allows for back-channel communication and training
—
Low 65mW/channel (typical) power consumption, with
option to power down unused channels
Advanced signal conditioning features
■
■
Receive equalization up to +36 dB
Transmit de-emphasis up to -12 dB
Transmit VOD control: 700 to 1200 mVp-p
< 0.3 UI of residual DJ at 10 Gbps
—
—
—
—
When configured as a 10G-KR repeater, the DS100BR111
allows the KR host and the end point to optimize the full link
by adjusting transmit and receive equalizer coefficients using
back-channel communication techniques specified by the
802.3ap standard.
Programmable via pin selection, EEPROM or SMBus
interface
■
Single supply operation selectable: 2.5V or 3.3v
■
■
Flow-thru pinout in 4mmx4mm 24-pin leadless LLP
package
The programmable settings can be applied via pin contol,
SMBus (I2C) protocol or an external EEPROM. When oper-
ating in the EEPROM mode, the configuration information is
automatically loaded on power up – This eliminates the need
for an external microprocessor or software driver.
>5kV HBM ESD rating
■
■
Industrial -40 to 85°C operating temperature range
Applications
Part of National's PowerWise family of energy efficient de-
vices, the DS100BR111 consumes just 65 mW/channel (typ-
ical), and allow the option to turn-off unused channels. This
ultra low power consumption eliminates the need for external
heat sinks and simplifies thermal management in active cable
applications.
High-speed active copper cable modules and FR-4
backplane in communication systems
■
10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with OOB
detection), InfiniBand, CPRI, RXAUI and many others.
■
Typical Application
30138890
© 2012 Texas Instruments Incorporated
301388 SNLS338D
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Block Diagram - Detail View Of Channel (1 Of 2)
30138886
Pin Diagram
30138825
DS100BR111 Pin Diagram 24 lead
Note 1: The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to
ensure optimal electrical and thermal performance.
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2
Ordering Information
NSID
Qty
Spec
Package
SQA24A
SQA24A
DS100BR111SQ
DS100BR111SQE
Tape & Reel Supplied As 1,000 Units
Tape & Reel Supplied As 250 Units
NOPB
NOPB
3
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Pin Descriptions
Pin Name
Pin Number I/O, Type
Pin Description
Differential High Speed I/O's
INA+, INA- ,
INB+, INB-,
24, 23
11, 12
I, CML
O,CML
Inverting and non-inverting CML differential inputs to the
equalizer. A on-chip 50Ω termination resistor connects INx+ to
VDD and INx- to VDD.
OUTA+, OUTA-,
OUTB+, OUTB-,
7, 8
20, 19
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
Control Pins
ENSMB
3
I, LVCMOS
Float
System Management Bus (SMBus) enable pin
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
ENSMB = 1 (SMBUS MODE)
SCL
5
I, LVCMOS
O, Open
Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled. A clock input in Slave mode.
Can also be a clock output in Master mode.
SDA
4
I, LVCMOS, ENSMB Master or Slave mode
O, Open
Drain
The SMBus bidirectional SDA pin is enabled. Data input or open
drain (pull-down only) output.
AD0-AD3
10, 9, 2, 1
I, LVCMOS, ENSMB Master or Slave mode
Float
SMBus Slave Address Inputs. In SMBus mode, these pins are
(4-Levels)
the user set SMBus slave address inputs. There are 16
addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device
SMBus address.
Note: Setting VOD_SEL = High in SMBus Mode will force the
Address = B0'h
READEN#
DONE#
17
18
I, LVCMOS
When using an External EEPROM, a transition from high to low
starts the load from the external EEPROM
IO, LVCMOS, EEPROM Download Status
Float
HIGH indicates Error / Still Loading
(4-Levels)
LOW indicates download complete. No Error.
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
I, LVCMOS, EQA/B ,0/1 control the level of equalization of each channel. The
Float
EQA/B pins are active only when ENSMB is de-asserted (LOW).
When ENSMB goes high the SMBus registers provide
independent control of each lane, and the EQB0/B1 pins are
converted to SMBUS AD2/AD3 inputs.
(4-Levels)
Table 3: Equalizer Settings
DEMA, DEMB
4, 5
IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins
Float
(4-Levels)
are only active when ENSMB is de-asserted (LOW). Each of the
4 A/B channels have the same level unless controlled by the
SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane and the DEM
pins are converted to SMBUS SCL and SDA pins.
Table 4: De-emphasis and Output Voltage Settings
TX_DIS
6
I, LVCMOS
DS100BR111
High = OUTA Enabled /OUTB Disabled
Low = OUTA/B Enabled
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4
Pin Name
Pin Number I/O, Type
Pin Description
VOD_SEL
17
I, LVCMOS, EQ Mode and VOD select.
Float
High = 10G-KR Mode (VOD = 1.1V/1.3V)
(4-Levels)
Float = (VOD = 1.0 V)
20K = (VOD = 1.2 V)
Low = (VOD = 700m V)
Note: DS100BR111 OUTA is limited to 700mV in pin mode,
see Table 4 for additional information.
Note: Setting VOD_SEL = High in SMBus Mode will force the
SMBus Address = B0'h
VDD_SEL
MODE
16
18
I, Internal
Pull-up
Enables the 3.3V to 2.5V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
I, LVCMOS
Controls Device Mode of Operation
High = Continuous Talk
Float = 10G-KR Mode, Slow OOB
20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of
inactivity. SD stays active.
Low = SAS Mode, Fast OOB
Status Output
LOS
13
14
O, Open
Drain
Indicates Loss of Signal (Default is LOS on INA). Can be
modified via SMBus registers.
LOS Threshold Input
SD_TH
I, LVCMOS, The SD_TH pin controls LOS threshold setting;
Float
Assert (mV), Deassert (mV)
(4-Levels)
20K = 160 mV, 100 mV
Float = 180 mV, 110 mV (Default)
High = 190 mV, 130 mV
Low = 210 mV, 150 mV
Note: Using values less than the default level can extend the
time required to detect LOS and are not recommended.
Power
VDD
21, 22
Power
Power supply pins
2.5V mode connect to 2.5V
3.3V mode do not connect to any supply voltage. Should be used
to attach external decoupling to device, 100 - 200 nF recom-
mended.
Note: See Applications section for additional information.
VIN
15
Power
Power
VIN = 3.3V +/-10% (input to internal LDO regulator)
Note: Must FLOAT for 2.5V operation. See Applications
section for additional information.
GND
DAP
Ground pad (DAP - die attach pad).
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not
guaranteed. Unless the "Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V
mode), or VIN (in 3.3V mode). For additional information.
Tables Table 2: 4-Level Control Pin Settings, Table 6: 4-Level Input Voltage
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
5
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MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
Package Thermal Resistance
θJC
100 V
1250 V
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
3.2°C/W
33.0°C/W
θJA, No Airflow, 4 layer JEDEC
For soldering specifications:
Supply Voltage (VDD)
Supply Voltage (VIN)
LVCMOS Input/Output Voltage
CML Input Voltage
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
See product folder at www.national.com
www.national.com/ms/MS/MS-SOLDERING.pdf
Min
Typ Max Units
2.375 2.5 2.625
CML Input Current
Supply Voltage (2.5V mode)
Supply Voltage (3.3V mode)
Ambient Temperature
V
V
°C
V
Junction Temperature
Storage Temperature
ESD Rating
3.0
-40
3.3 3.6
25 +85
3.6
-40°C to +125°C
SMBus (SDA, SCL)
HBM, STD - JESD22-A114F
> 5 kV
Symbol
Power Supply Current
IDD Supply Current
Parameter
Conditions
Min
Typ
Max
Units
TX_DIS = LOW, EQ = ON
VOD_SEL = Float ( 1000 mV)
50
12
63
Auto Low Power Mode
15
TX_DIS = LOW, MODE = 20K
VID CHA and CHB = 0.0V
VOD_SEL = Float (1000 mV)
mA
TX_DIS = HIGH (BR111)
25
35
LVCMOS DC Specifications
VIH
High Level Input
Voltage
2.0
VDD
0.7
V
VIL
Low Level Input Voltage
GND
2.0
V
V
VOH
High Level Output
Voltage
IOH = -4.0 mA
(Note 5)
VOL
IIN
Low Level Output
Voltage
IOL = 4.0 mA
0.4
+15
+15
+80
V
Input Leakage Current Vinput = 0V or VDD
VDD_SEL = Float
-15
-15
uA
Vinput = 0V or VIN
VDD_SEL = Low
IIN-P
Input Leakage Current Vinput = 0V or VDD - 0.05V
-160
uA
4-Level Input
VDD_SEL = Float
(Note 3)
Vinput = 0V or VIN - 0.05V
VDD_SEL = Low
LOS and ENABLE / DISABLE Timing
TLOS_OFF
TLOS_ON
TOFF
Input IDLE to Active
RX_LOS response time
(Note 13)
(Note 13)
0.035
0.4
uS
uS
uS
Input Active to IDLE
RX_LOS response time
TX Disable assert Time (Note 13)
TX_DIS = HIGH to
0.005
Output OFF
TON
TX Disable negateTime (Note 13)
TX_DIS = LOW to
Output ON
0.150
150
uS
nS
TLP_EXIT
Auto Low Power Exit
ALP to Normal
Operation
(Note 13)
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6
Symbol
Parameter
Conditions
Min
Typ
Max
Units
uS
TLP_ENTER
Auto Low Power Enter (Note 13)
Normal Operation to
Auto Low Power
100
800
CML RECEIVER INPUTS
VTX
Source Transmit
Launch Signal Level
RX return loss
Default power-up conditions
ENSMB = 0 or 1
190
1600
mV
dB
RLRX-IN
SDD11 @ 4.1 GHz
SDD11 @ 11.1 GHz
SCD11 @ 11.1 GHz
-12
-8
-10
HIGH SPEED TRANSMITTER OUTPUTS
VOD1
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = LOW (700 mV
setting)
500
800
950
650
1000
1150
-3
800
1100
1350
mVp-p
DE = LOW
VOD2
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
DE = LOW
VOD3
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = 20K (1200 mV
setting)
DE = LOW
VOD_DE1
VOD_DE2
VOD_DE3
De-Emphasis Levels
De-Emphasis Levels
De-Emphasis Levels
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
dB
dB
dB
DE = FLOAT
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
-6
DE = 20K
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
-9
VOD_SEL = FLOAT (1000
mV setting)
DE = HIGH
VCM-AC
VCM-DC
VIDLE
Output Common-Mode AC Common Mode Voltage
4.5
1.1
mV (RMS)
Voltage
DE = 0 dB, VOD <= 1000 mV
DC Common Mode Voltage
Output DC Common-
Mode Voltage
0
1.9
30
V
TX IDLE Output
Voltage
mV
7
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
dB
RLTX-DIFF
TX return loss
SDD22 @ 4.1 GHz
SDD22 @ 11.1 GHz
SCC22 @ 2.5 GHz
SCC22 @ 11.1 GHz
DC, IFORCE = +/- 100 uA
(Note )
-13
-9
-22
-10
2.5
delta ZM
TR/F
Transmitter
Termination Mismatch
%
Transmitter Rise and
Fall Time
Measurement points at 20% -
80%
38
ps
(Note 14)
TPD
Propagation Delay
Measured at 50% crossing
EQ = 00
230
7
ps
ps
TCCSK
TPPSK
Channel to Channel
Skew
T = 25°C, VDD = 2.5V
Part to Part Skew
T = 25°C, VDD = 2.5V
20
ps
ns
TTX-IDLE-SET-TO- Max time to transition to VIN = 1Vpp, 10 Gbps
6.5
idle after differential
signal
EQ = 00, DE = 0
IDLE
TTX-IDLE-TO-DIFF- Max time to transition to VIN = 1Vpp, 10 Gbps
3.2
3.3
ns
ns
valid differential signal EQ = 00, DE = 0
DATA
after idle
TENV_DISTORT
Active OOB timing
distortion, input active
time vs. output active
time
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8
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ps (RMS)
OUTPUT JITTER SPECIFICATIONS: (Note 4)
RJ
Random Jitter
No Media
Source Amplitude = 700 mV,
PRBS15 pattern,
0.3
DJ1
Deterministic Jitter
0.09
UI
10.3125 Gbps
VOD = Default, EQ =
minimum, DE = 0 dB
Equalization
DJE1
Residual Deterministic 8 meter 30AWG Cable on
0.27
0.17
UI
UI
Jitter
Input
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = 0F'h; See Figure 15
DJE2
Residual Deterministic
Jitter
30" 4-mil FR4 on Inputs
Source = 700 mV, PRBS15
pattern
10.3125 Gbps
EQ = 16'h; See Figure 12
De-emphasis
DJD1
Residual Deterministic 10” 4 mil stripline FR4 on
0.13
UI
Jitter
10.3125 Gbps
Outputs
Source = 700 mV, PRBS15
pattern
EQ = Min, VOD = 1200 mV,
DE = 010'b
See Figure 17
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur, including inoperability and degradation of device
reliability and/or performance. Functional operation of the device and/or non-
degradation at the Absolute Maximum Ratings or other conditions beyond
those indicated in the Recommended Operating Conditions is not implied.
The Recommended Operating Conditions indicate conditions at which the
device is functional and the device should not be operated beyond such
conditions. Absolute Maximum Numbers are guaranteed for a junction
temperature range of -40°C to +125°C. Models are validated to Maximum
Operating Voltages only.
Note 4: Typical jitter reported is determined by jitter decomposition software
on the DSA8200 Oscilloscope.
Note 5: VOH only applies to the DONE# pin; LOS, SCL, and SDA are open-
drain outputs that have no internal pull-up capability. DONE# is a full
LVCMOS output with pull-up and pull-down capability
Note 6: Force +/- 100 uA on output, measure delta V on the Output and
calculate impedance. Mismatch is the percentage difference of OUTn+ and
OUTn- impedance driving the same logic state.
Note 3: Input is held to a maximum of 50 mV below VDD or VIN to simulate
the use of a 1K resistor on the input.
9
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Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
0.8
Units
SERIAL BUS INTERFACE DC SPECIFICATIONS: (Note 7)
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
V
VIH
2.1
3.6
V
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
mA
VDD
Nominal Bus Voltage
2.375
-200
3.6
+200
10
V
ILEAK-Bus
CI
Input Leakage Per Bus Segment (Note 8)
µA
pF
Capacitance for SDA and SCL
(Note 8, Note 9, Note 12)
RTERM
External Termination Resistance Pullup VDD = 3.3V,
2000
Ω
Ω
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
(Note 8, Note 9, Note 10)
Pullup VDD = 2.5V,
1000
(Note 8, Note 9, Note 10)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
400
520
kHz
kHz
ENSMB = FLOAT (Master Mode)
(Note 7)
280
1.3
400
TBUF
Bus Free Time Between Stop and
Start Condition
µs
µs
µs
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
0.6
0.6
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
THD:DAT
TSU:DAT
TLOW
Stop Condition Setup Time
Data Hold Time
0.6
0
µs
ns
ns
µs
µs
ns
ns
Data Setup Time
100
1.3
0.6
Clock Low Period
THIGH
tF
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
(Note 11)
50
(Note 11)
300
300
tR
(Note 11)
tPOR
Time in which a device must be
operational after power-on reset
(Note 11, Note 12)
500
ms
Note 7: EEPROM interface requires 400 KHz capable EEPROM device.
Note 8: Recommended value.
Note 9: Recommended maximum capacitance load per bus segment is 400pF.
Note 10: Maximum termination voltage should be identical to the device supply voltage.
Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Note 12: Guaranteed by Design and/or characterization. Parameter not tested in production.
Note 13: Parameter not tested in production.
Note 14: Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation.
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10
Timing Diagrams
30138802
FIGURE 1. CML Output Transition Times
30138803
FIGURE 2. Propagation Delay Timing Diagram
11
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30138804
FIGURE 3. Idle Timing Diagram
30138801
FIGURE 4. SMBus Timing Parameters
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12
Functional Description
The DS100BR111 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the
details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision
4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.
The control pins have been enhanced to have 4 different levels and provide a wider range of control settings. Refer to Table 2: 4-
Level Control Pin Settings
Table 2: 4-Level Control Pin Settings
Pin Setting
Description
0
R
Tie pin to GND through a 1 KΩ resistor
Tie pin to ground through 20 KΩ resistor
Float the pin (no connection)
Float
1
Tie pin to VDD through a 1 KΩ resistor
Note: 4-Level IO pins require a 1K resistance to GND or VDD/VIN. It is possible to tie mulitple 4-level IO pins together with a single
resistor to GND or VDD/VIN. When multiple IOs are connected in parallel, the resistance to GND or VDD/VIN should be adjusted
to compensate. For 2 pins the optimal resistance is 500 Ohms, 3 pins = 330 Ohms, and 4 pins = 250 Ohms.
Note: For 2.5V mode the control pin logic 1 level is VDD (pins 21 and 22), in 3.3V mode the control pin logic 1 level is defined by
VIN (pin 15).
Table 3: Equalizer Settings
EQA1/
EQB1
EQA0/
EQB0
Level
EQ — 8 bits [7:0] dB Boost at 5 Ghz
Suggested Media
1
2
0
0
0
R
0000 0000 = 0x00
0000 0001 = 0x01
0000 0010 = 0x02
0000 0011 = 0x03
0000 0111 = 0x07
0001 0101 = 0x15
0000 1011 = 0x0B
0000 1111 = 0x0F
0101 0101 = 0x55
0001 1111 = 0x1F
2.5
6.5
9
FR4 < 5 inch trace
FR4 5 inch trace
FR4 10 inch trace
FR4 15 inch trace
FR4 20 inch trace
FR4 25 inch trace
FR4 25 inch trace
7m 30AWG Cable
FR4 30 inch trace
3
0
Float
1
4
0
11.5
14
5
R
0
6
R
R
15
7
R
Float
1
17
8
R
19
9
Float
Float
0
20
10
R
23
8m 30 AWG Cable
FR4 35 inch trace
11
12
13
14
15
16
Float
Float
0010 1111 = 0x2F
0011 1111 = 0x3F
1010 1010 = 0xAA
0111 1111 = 0x7F
1011 1111 = 0xBF
1111 1111 = 0xFF
25
27
30
31
33
34
10m 30 AWG Cable
10m - 12m, Cable
Float
1
0
1
1
1
1
R
Float
1
Note: Settings are approximate and will change based on PCB material, trace dimensions, and driver waveform characteristics.
13
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Table 4: De-emphasis and Output Voltage Settings
SMBus Register VOD
Level
Level VOD_SEL DEMA/B
SMBus Register DEM Level
VOD (mV)
DEM (dB)
1
2
0
0
000
010
011
101
000
010
011
101
000
010
011
101
000
001
001
010
000
000
000
000
011
011
011
011
101
101
101
101
100
100
110
110
700
700
0
0
0
Float
- 3.5
- 6
3
R
700
4
0
1
700
- 9
5
Float
Float
Float
Float
R
0
Float
R
1000
1000
1000
1000
1200
1200
1200
1200
1100
1100
1300
1300
0
6
- 3.5
- 6
7
8
1
- 9
9
0
- 0
10
11
12
13
14
15
16
R
Float
R
- 3.5
- 6
R
R
1
- 9
1
0
0
1
Float
R
- 1.5
- 1.5
- 3.5
1
1
1
Note: The DS100BR111 VOD for OUTPUT A is limited to 700 mV in pin mode (ENSMB=0). With ENSMB = 1 or FLOAT, the VOD
for OUTPUT A can be adjusted with SMBus register 0x23 [4:2] as shown in the SMBus Register Table.
Note: When VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR111 will support 10G-KR back-channel
communication using pin control.
Note: In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR111 AD0-AD3 pins are internally
forced to 0'h
Table 5: Signal Detect Threshold Level
SMBus REG bit
[3:2] and [1:0]
SD_TH
Assert Level (Typical)
De-assert Level (Typical)
0
10
01
00
11
210 mV
160 mV
180 mV
190 mV
150 mV
100 mV
110 mV
130 mV
20K to GND
Float (Default)
1
Note: VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps
www.ti.com
14
APPLICATIONS INFORMATION
rically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a
low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources
on the printed circuit board. See AN-1187 for additional infor-
mation on LLP packages.
4-Level Input Configuration Guidelines
The 4-level input pins utilize a resistor divider to help set the
4 valid levels. There is an internal 30K pull-up and a 60K pull-
down connected to the package pin. These resistors, together
with the external resistor connection combine to achieve the
desired voltage level. Using the 1K pull-up, 1K pull-down, no
connect, and 20K pull-down provide the optimal voltage levels
for each of the four input states.
Different transmission line topologies can be used in various
combinations to achieve the optimal system performance.
Impedance discontinuities at vias can be minimized or elimi-
nated by increasing the swell around each hole and providing
for a low inductance return current path. When the via struc-
ture is associated with thick backplane PCB, further optimiza-
tion such as back drilling is often used to reduce the
detrimental high frequency effects of stubs on the signal path.
Table 6: 4-Level Input Voltage
Level
Setting
01K to GND
20K to GND
FLOAT
3.3V Mode
0.1 V
2.5V Mode
0.08 V
0
R
F
1
0.33 * VIN
0.67 * VIN
VIN - 0.05V
0.33 * VDD
0.67 * VDD
VIN - 0.04V
Power Supply Configuration Guidelines
The DS100BR111 can be configured for 2.5V operation or
3.3V operation. The lists below outline required connections
for each supply selection.
1K to VDD/VIN
•
Typical 4-Level Input Thresholds
3.3V Mode of Operation
1. Tie VDD_SEL = 0 with 1K resistor to GND.
Level 1 - 2 = 0.2 VIN or VDD
Level 2 - 3 = 0.5 VIN or VDD
Level 3 - 4 = 0.8 VIN or VDD
—
—
—
2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling
at VIN is recommended.
In order to minimize the startup current associated with the
integrated 2.5V regulator the 1K pull-up / pull-down resistors
are recommended. If several 4 level inputs require the same
setting, it is possible to combine two or more 1K resistors into
a single lower value resistor. As an example; combining two
inputs with a single 500Ω resistor is a good way to save board
space.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pull-up resistor to VIN
5. Any 4-Level input which requires a connection to "Logic
1" should use a 1K resistor to VIN
2.5V Mode of Operation
1. VDD_SEL = Float
10G-KR Configuration Guidelines
2. VIN = Float
When configured in "KR Mode", using eith the VOD_SEL pin
setting or SMBus register control, the DS100BR111 is de-
signed to operate transparently within a KR backplance chan-
nel environment. Installing a DS100 repeater within the KR
backplane channel splits the total channel attenuation into
two parts. Ideally the repeater can be placed near the middle
of the channel maximizing the signal to noise ratio across the
bidirectional interface.
3. Feed 2.5V supply into VDD pins.
4. See information on VDD bypass below.
5. SDA and SCL pins connect pull-up resistor to VDD for
2.5V uC SMBus IO
6. SDA and SCL pins connect pull-up resistor to VDD for
3.3V uC SMBus IO
7.
Any 4-Level input which requires a connection to "Logic
1" should use a 1K resistor to VIN
In order to maximize the 10G-KR solution space, the 802.3ap
specification calls for an optimization of the transmit signal
conditioning coefficients based on feedback for the KR re-
ceiver. Setting the DS100BR111 active CTLE to compensate
for the channel loss from each of the KR transmitters will re-
duce the transmit and receive equalization settings required
on the KR physical layer devices. This central location keeps
a larger S/N raito at all points in the channel, extending the
available solution space and increasing the overall margin of
almost any channel.
Note: The DAP (bottom solder pad) is the GND connection.
Power Supply Bypass
Two approaches are recommended to ensure that the
DS100BR111 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1 μF bypass capac-
itor should be connected to each VDD pin such that the ca-
pacitor is placed as close as possible to the device. Smaller
body size capacitors can help facilitate proper component
placement.
PCB Layout Guidelines
The CML inputs and outputs have been optimized to work with
interconnects using a controlled differential impedance of 85
- 100Ω. It is preferable to route differential lines exclusively on
one layer of the board, particularly for the input traces. The
use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmet-
15
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System Management Bus (SMBus) and Configuration
Registers
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the config-
uration registers.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
The DS100BR111 has AD[3:0] inputs in SMBus mode. These
pins are the user set SMBus slave address inputs. When
pulled low the AD[3:0] = 0000'b, the device default address
byte is B0'h. Based on the SMBus 2.0 specification, this con-
figuration results in a 7-bit slave address of 1011000'b. The
LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1011
0000'b or B0'h. The device address byte can be set with the
use of the AD[3:0] inputs.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
Shown in the form of an expression:
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
Slave Address [7:4] = The DS100BR111 hardware address
(1011'b) + Address pin AD[3]
Slave Address [3:1] = Address pins AD[2:0]
Slave Address [0] = 0'b for a WRITE or 1'b for a READ
Slave Address Examples:
•
•
•
•
AD[3:0] = 0001'b, the device slave address byte is B2'h
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
Slave Address [3:1] = 001'b
—
—
—
READING A REGISTER
Slave Address [0] = 0'b for a WRITE
To read a register, the following protocol is used (see SMBus
2.0 specification).
AD[3:0] = 0010'b, the device slave address byte is B4'h
Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
Slave Address [3:1] = 010'b
—
—
—
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
Slave Address [0] = 0'b for a WRITE
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
AD[3:0] = 0100'b, the device slave address byte is B8'h
Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
Slave Address [3:1] = 100'b
—
—
—
5. The Host drives a START condition.
Slave Address [0] = 0'b for a WRITE
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
AD[3:0] = 1000'b, the device slave address byte is C0'h
Slave Address [7:4] = 1011'b + 1'b = 1100'b or C'h
Slave Address [3:1] = 000'b
—
—
—
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
Slave Address [0] = 0'b for a WRITE
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
TRANSFER OF DATA VIA THE SMBus
10. The Host drives a STOP condition.
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
There are three unique states for the SMBus:
Please see SMBus Register Map Table for more information.
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
30138805
FIGURE 5. Typical SMBus Write Operation
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16
EEPROM Modes in DS100BR111 Devices
[4:1] = Address of 4'b0001
[0] = Write Bit, 1'b0
—
—
The DS100BR111 supports reading directly from an external
EEPROM device by implementing SMBus Master mode.
When using the SMBus master mode, the DS100 will read
directly from specific location in the external EEPROM. When
designing a system for using the external EEPROM, the user
needs to follow these specific guidelines.
•
•
The device address can be set with the use of the AD[3:0]
input up to 16 different addresses. Use the example below
to set each of the SMBus addresses.
AD[3:0] = 0001'b, the device address byte is B2'h
AD[3:0] = 0010'b, the device address byte is B4'h
AD[3:0] = 0011'b, the device address byte is B6'h
AD[3:0] = 0100'b, the device address byte is B8'h
—
—
—
—
•
Set the DS100BR111 into SMBus Master Mode
Float ENSMB (PIN 3)
—
•
•
•
•
The external EEPROM device must support 400 KHz
operation
The external EEPROM device address byte must be
0xA0'h
Set the AD[3:0] inputs for SMBus address byte. When the
AD[3:0] = 0000'b, the device address byte is B0'h.
Based on the SMBus 2.0 specification, a device can have
a 7-bit slave address of 1010 000'b. The LSB is set to 0'b
(for a WRITE). The bit mapping for SMBus is listed below:
The master implementation in the DS100BR111 supports
multiple devices reading from 1 EEPROM. When tying
multiple devices to the SDA and SCL pins, use these
guidelines:
Use adjacent SMBus addresses for the 4 devices
Use a pull-up resistor on SDA; value = 4.7KΩ
Use a pull-up resistor on SCL: value = 4.7KΩ
Daisy-chain READEN# (pin 17) and DONE# (pin18)
from one device to the next device in the sequence
—
—
—
—
[7:5] = Reserved Bits from the SMBus specification
[4:1] = Usable SMBus Address Bits
[0] = Write Bit
—
—
—
1. Tie READEN# of the 1st device in the chain (U1)
to GND
2. Tie DONE# of U1 to READEN# of U2
3. Tie DONE# of U2 to READEN# of U3
4. Tie DONE# of U3 to READEN# of U4
•
The DS100BR111 devices have AD[3:0] inputs in SMBus
mode (pins 1, 2, 9, 10). These pins set SMBus slave
address. When the AD[3:0] = 0001'b, the device address
byte is B2'h.
5. Optional: Tie DONE# of U4 to a LED to show each
of the devices have been loaded successfully
[7:5] = Default to 3b'101
—
Master EEPROM Mode in the DS100BR111
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data
start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR111 address
and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM.
There are 37 bytes of data size for each DS100BR111 device.
30138815
FIGURE 6. Typical EEPROM Data Set
17
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The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS100BR111 or 40
bytes in total. The result of this calculation is placed immediately after the DS100BR111 data in the EEPROM which ends with
"5454". The CRC-8 in the DS100BR111 uses a polynomial = x8 + x2 + x + 1
In SMBus master mode the DS100BR111 reads its initial configuration from an external EEPROM upon power-up. Some of the
pins of the DS100BR111 perform the same functions in SMBus master and SMBus slave mode. Once the DS100BR111 has
finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and
can be further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and
can be omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus
master mode.
•
•
DONE#
READEN#
When the DS100BR111 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the
READEN# pin goes low. When the DS100BR111 is finished reading its configuration from the external EEPROM, it drives the
DONE# pin low. In applications where there is more than one DS100BR111 on the same SMBus, bus contention can result if more
than one DS100BR111 tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this bus
contention. The system should be designed so that the READEN# pin from one DS100BR111 in the system is driven low on power-
up. This DS100BR111 will take command of the SMBus on power-up and will read its initial configuration from the external
EEPROM. When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the
READEN# pin of another DS100BR111. When this DS100BR111 senses its READEN# pin driven low, it will take command of the
SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the
DONE# pin of each DS100BR111 to the READEN# pin of the next DS100BR111, each DS100BR111 can read its initial configu-
ration from the EEPROM without causing bus contention.
30138816
FIGURE 7. Typical multi-device EEPROM connection diagram
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18
Table 7: Multi-Device EEPROM Register Map Overview
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
0
CRC EN
Address
Map
EEPROM > Reserved
256 Bytes
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
Header
1
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3] EE Burst[2] EE Burst[1] EE Burst[0]
CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
EE AD0 [7] EE AD0 [6] EE AD0 [5] EE AD0 [4] EE AD0 [3] EE AD0 [2] EE AD0 [1] EE AD0 [0]
CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
EE AD1 [7] EE AD1 [6] EE AD1 [5] EE AD1 [4] EE AD1 [3] EE AD1 [2] EE AD1 [1] EE AD1 [0]
CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
EE AD2 [7] EE AD2 [6] EE AD2 [5] EE AD2 [4] EE AD2 [3] EE AD2 [2] EE AD2 [1] EE AD2 [0]
CRC[7] CRC[6] CRC[5] CRC[4] CRC[3] CRC[2] CRC[1] CRC[0]
EE AD3 [7] EE AD3 [6] EE AD3 [5] EE AD3 [4] EE AD3 [3] EE AD3 [2] EE AD3 [1] EE AD3 [0]
Device 0 3
Info
Device 1 5
Info
Device 2 7
Info
Device 3 9
Info
4
6
8
10
Device 0 11
Addr 3
RES
RES
RES
DRES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 0 12
Addr 4
PDWN Inp PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 0 46
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 0 47
Addr 39
Device 1 48
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 1 49
Addr 4
PDWN Inp PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 1 83
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 1 84
Addr 39
Device 2 85
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 2 86
Addr 4
PDWN Inp PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 2 120 RES
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 2 121 RES
Addr 39
Device 3 122 RES
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 3 123 RES
Addr 4
PDWN Inp PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 3 157 RES
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Device 3 158 RES
Addr 39
•
•
•
•
CRC EN = 1; Address Map = 1
EEPROM > 256 Bytes = 0
COUNT[3:0] = 0011'b
Note: Multiple DS100BR111 devices may point at the same address space if they have identical programming values.
19
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Table 8: Single EEPROM Header + Register Map with Default Value
EEPROM
Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
0
CRC EN
Address
Map
EEPROM > RES
256 Bytes
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
Description
Present
Value
0
0
0
0
0
0
0
0
Description 1 RES
RES
0
RES
0
RES
0
RES
0
RES
0
RES
0
RES
0
Value
0
2
Max
Max
Max
Max
Max
Max
Max
Max
Description
Value
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Burst size[7] Burst size[6] Burst size[5] Burst size[4] Burst size[3] Burst size[2] Burst size[1] Burst size[0]
0
0
0
0
0
0
0
0
Description 3 Reserved
Reserved
0x01 [6]
0
Reserved
0x01 [5]
0
Reserved
0x01 [4]
0
Reserved
0x01 [3]
0
Reserved
0x01 [2]
0
Reserved
0x01 [1]
0
Reserved
0x01 [0]
0
Register
Value
0x01 [7]
0
Description 4 Ovrd_LOS LOS_Value PDWN Inp PWDN Osc Reserved
eSATA
eSATA
Ovrd
Enable A
Enable B
TX_DIS
Register
Value
0x02 [5]
0
0x02 [4]
0
0x02 [3]
0
0x02 [2]
0
0x02 [0]
0
0x04 [7]
0
0x04 [6]
0
0x04 [5]
0
Description 5 TX_DIS
CHA
TX_DIS
CHB
Reserved
EQ Stage 4 EQ Stage 4 Reserved
Overide
IDLE_th
Reserved
CHB
CHA
Register
Value
0x04 [4]
0
0x04 [3]
0
0x04 [2]
0
0x04 [1]
0
0x04 [0]
0
0x06 [4]
1
0x08 [6]
0
0x08 [5]
0
Description 6 Ovrd_IDLE Reserved
Ovrd_Out
Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Register
Value
0x08 [4]
0
0x08 [3]
0
0x08 [2]
0
0x08 [1]
0
0x08 [0]
0x0B [6]
1
0x0B [5]
1
0x0B [4]
1
0
Description 7 Reserved
Reserved
0x0B [2]
0
Reserved
0x0B [1]
0
Reserved
0x0B [0]
0
Idle auto A
0x0E [5]
0
Idle sel A
0x0E [4]
0
Reserved
0x0E [3]
0
Reserved
0x0E [2]
0
Register
Value
0x0B [3]
0
Description 8 CHA EQ[7] CHA EQ[6] CHA EQ[5] CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0]
Register
Value
0x0F [7]
0
0x0F [6]
0
0x0F [5]
1
0x0F [4]
0
0x0F [3]
1
0x0F [2]
1
0x0F [1]
1
0x0F [0]
1
Description 9 A Sel scp
A Out Mode Reserved
Reserved
0x10 [4]
0
Reserved
0x10 [3]
1
Reserved
0x10 [2]
1
Reserved
0x10 [1]
0
Reserved
0x10 [0]
1
Register
Value
0x10 [7]
1
0x10 [6]
1
0x10 [5]
1
Description 1 DEMA[2]
DEMA[1]
0x11 [1]
1
DEMA[0]
0x11 [0]
0
CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0]
0
Register
Value
0x11 [2]
0
0x12 [7]
0
0x12 [3]
0
0x12 [2]
0
0x12 [1]
0
0x12 [0]
0
Description 1 Idle auto B Idle sel B
Reserved
0x15 [3]
0
Reserved
0x15 [2]
0
CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4]
1
Register
Value
0x15 [5]
0
0x15 [4]
0
0x16 [7]
0
0x16 [6]
0
0x16 [5]
1
0x16 [4]
0
Description 1 CHB EQ[3] CHB EQ[2] CHB EQ[1] CHB EQ[0] B Sel scp
B Out Mode Reserved
Reserved
0x17 [4]
0
2
Register
Value
0x16 [3]
1
0x16 [2]
1
0x16 [1]
1
0x16 [0]
1
0x17 [7]
1
0x17 [6]
1
0x17 [5]
1
Description 1 Reserved
Reserved
0x17 [2]
1
Reserved
0x17 [1]
0
Reserved
0x17 [1]
1
CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow
3
Register
Value
0x17 [3]
1
0x18 [2]
0
0x18 [1]
1
0x18 [0]
0
0x19 [7]
0
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20
1
4
Description
Register
Value
IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Reserved
Reserved
Reserved
Reserved
0x19 [3]
0
0x19 [2]
0
0x19 [1]
0
0x19 [0]
0
0
0
0
0
Description 1 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
Register
Value
0
0
1
0
1
1
1
1
Description 1 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
Register
Value
1
0
1
0
1
1
0
1
Description 1 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
Register
Value
0
1
0
0
0
0
0
0
1
8
Reserved
CHA VOD CHA VOD
CHA VOD Reserved
[0]
Reserved
Reserved
Reserved
Description
[2]
[1]
Register
Value
0x23 [4]
0
0x23 [3]
0
0x23 [2]
0
0
0
0
1
0
Description 1 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x25 [4]
0
9
Register
Value
1
1
1
1
1
0
1
Description 2 Reserved
Reserved
0x25 [2]
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
Register
Value
0x25 [3]
1
0
1
0
1
0
0
Description 2 Reserved
Reserved
Reserved
Reserved
ovrd fst idle en hi idle th A en hi idle th B en fst idle A
1
Register
Value
0x28 [6]
0
0x28 [5]
0
0x28 [4]
0
0x28 [3]
0
0
0
0
0
Description 2 en fst idle B sd mgain A sd mgain B Reserved
Reserved
Reserved
Reserved
Reserved
2
Register
Value
0x28 [2]
0
0x28 [1]
0
0x28 [0]
0
0
0
0
0
0
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
Register
Value
0
1
0
1
1
1
1
1
Description 2 Reserved
Reserved
Reserved
Reserved
CHB VOD[2] CHB VOD[1] CHB VOD[0] Reserved
4
Register
Value
0x2D [4]
0
0x2D 3]
1
0x2D [2]
1
0
1
0
1
0
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
Register
Value
1
0
0
0
0
0
0
0
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
Register
Value
0
0
0
0
0
1
0
1
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
Register
Value
1
1
1
1
0
1
0
1
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
Register
Value
1
0
1
0
1
0
0
0
Description 2 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9
Register
Value
0
0
0
0
0
0
0
0
21
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3
0
Description
Register
Value
Reserved
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
1
1
1
1
1
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Register
Value
0
1
0
1
1
0
1
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
Register
Value
1
0
0
0
0
0
0
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
Register
Value
0
0
0
0
0
1
0
1
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4
Register
Value
1
1
1
1
0
1
0
1
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
Register
Value
1
0
1
0
1
0
0
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
Register
Value
0
0
0
0
0
0
0
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
Register
Value
0
0
0
0
0
0
0
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
Register
Value
0
1
0
1
0
1
0
0
Description 3 Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9
Register
Value
0
1
0
1
0
1
0
0
www.ti.com
22
Below is an example of a 2 kbits (256 x 8-bit) EEPROM Register Dump in hex format for a multi-device DS100BR111 application.
Table 9: Multi DS100BR111 EEPROM Data
EEPROM
Address
Address
(Hex)
EEPROM
Data
Comments
0
1
2
3
4
5
6
7
8
9
00
0x43
CRC_EN = 0, Address Map = 1, Device Count = 3 (Devices 0, 1, 2, and 3)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
0x00
0x08
0x00
0x0B
0x00
0x30
0x00
0x30
0x00
0x0B
0x00
0x00
0x04
0x07
0x00
0x2F
0xED
0x40
0x02
0xFE
0xD4
0x00
0x2F
0xAD
0x40
0x02
0xFA
0xD4
0x01
0x80
0x5F
0x56
0x80
0x05
0xF5
0xA8
0x00
0x5F
0x5A
0x80
0x05
0xF5
0xA8
0x00
0x00
EEPROM Burst Size
CRC not used
Device 0 Address Location
CRC not used
Device 1 Address Location
CRC not used
Device 2 Address Location
CRC not used
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Device 3 Address Location
Begin Device 0 and Device 3 - Address Offset 3
Default EQ CHA
Default EQ CHB
Default EQ CHB
BR111 CHA VOD = 700 mV
BR111 CHB VOD = 1000 mV
23
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EEPROM
Address
Address
(Hex)
EEPROM
Data
Comments
46
2E
0x54
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
0x54
0x00
0x00
0x04
0x07
0x00
0x2F
0xED
0x40
0x02
0xFE
0xD4
0x00
0x2F
0xAD
0x40
0x02
0xFA
0xD4
0x01
0x80
0x5F
0x56
0x80
0x05
0xF5
0xA8
0x00
0x5F
0x5A
0x80
0x05
0xF5
0xA8
0x00
0x00
0x54
0x54
End Device 0 and Device 3 - Address Offset 39
Begin Device 1 and Device 2 - Address Offset 3
Default EQ CHA
Default EQ CHB
Default EQ CHB
BR111 CHA VOD = 700 mV
BR111 CHB VOD = 1000 mV
End Device 1 and Device 2 - Address Offset 39
www.ti.com
24
TABLE 1. Table 10: SMBus Register Map
EEPROM
Register
Name
Address
Bits
Field
Type Default
Description
Reg Bit
0x00
Device ID
7
Reserved
R/W
0x00
set bit to 0
6:3
2
I2C Address [3:0]
R
R
[6:3] SMBus strap observation
EEPROM reading
done
1: EEPROM Loading
0: EEPROM Done Loading
1
Reserved
Reserved
Idle Control
RWSC
RWSC
R/W
set bit to 0
set bit to 0
0
0x01
Control 1
7:6
0x00
Yes
Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
5:3
2
Reserved
R/W
R/W
Set bits to 0
LOS Select
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
1:0
7
Reserved
Reserved
Reserved
LOS override
R/W
R/W
Set bits to 00'b
Set bit to 0
0x02
Control 2
0x00
6
Set bit to 0
5
Yes
Yes
LOS pin override enable (1);
Use Normal Signal Detection (0)
4
LOS override
value
1: Normal Operation
0: Output LOS
3
PWDN Inputs
PWDN Oscillator
Reserved
Yes
Yes
1: PWDN
0: Normal Operation
2
1
0
Reserved
Yes
Yes
Set bit to 0
0x04
Control 3
7:6
eSATA Mode
Enable
R/W
0x00
[7] Channel A (1)
[6] Channel B (1)
5
4
3
TX_DIS Override
Enable
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
TX_DIS Value
Channel A
1: TX Disabled
0: TX Enabled
TX_DIS Value
Channel B
2
Reserved
Set bit to 0
1:0
EQ CONTROL
[1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
0x05
0x06
CRC 1
CRC 2
7:0
7
CRC[7:0]
R/W
0x00
0x10
Slave Mode CRC Bits
Disable EEPROM R/W
CFG
Disable Master Mode EEPROM Configuration
6:5
4
Reserved
Reserved
Set bits to 0
Set bit to 1
Yes
3
CRC Slave Mode
Disable
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED
register updates will NOT take effect until
correct CRC value is loaded
2:1
0
Reserved
Set bits to 0
CRC Enable
Slave CRC Trigger
25
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0x07
Digital Reset
and Control
R/W
0x01
7
6
Reserved
Set bit to 0
Reset Regs
Self clearing reset for registers.
Writing a [1] will return register settings to
default values.
5
Reset SMBus
Master
Self clearing reset for SMBus master state
machine
4:0
Reserved
Reserved
Set bits to '0001b
Set bit to 0
0x08
Pin Override 7
6
R/W
0x00
Override Idle
Threshold
Yes
[1]: Override by Channel - see Reg 0x13 and
0x19
[0]: SD_TH pin control
5
4
Reserved
Yes
Yes
Set bit to 0
Override IDLE
[1]: Force IDLE by Channel - see Reg 0x0E
and 0x15
[0]: Normal Operation
3
2
Reserved
Yes
Set bit to 0
[1]: Enable Output Mode control for individual
outputs. See register locations 0x10[6] and
0x17[6].
Override Out
Mode
[0]: Disable - Outputs are kept in the normal
mode of operation allowing VOD and DE ad-
justments.
1
0
Override DEM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Yes
Yes
Set bit to 0
0x0C
CH A
7
R/W
0x00
Set bit to 0
Analog
Override 1
6
Set bit to 0
5
Set bit to 0
4
Set bit to 0
3:0
7:0
Set bits to 0000'b.
Set bits to 00'h.
0x0D
0x0E
CH A
Reserved
R/W
R/W
0x00
0x00
CH A
7:6
5
Reserved
Idle Auto
Set bits to 00'b.
Idle Control
Yes
Yes
Yes
Auto IDLE value when override bit is set (reg
0x08 [4] = 1)
4
Idle Select
Force IDLE value when override bit is set (reg
0x08 [4] = 1)
3
Reserved
Set bit to 0.
Set bits to 0.
2:0
7:0
Reserved
0x0F
0x10
CH A
EQ Setting
BOOST [7:0]
R/W
R/W
0x2F
0xED
Yes
Yes
Yes
EQ Boost Default to 24 dB
See EQ Table for Information
CH A
7
6
Sel_scp
[1]: Short Circuit Protection ON
[0]: Short Circuit Protection OFF
Control 1
Output Mode
[1]: Normal operation
[0]: 10G-KR operation
5:3
2:0
Reserved
Reserved
Yes
Yes
Set bits to = 101'b
Set bits to = 101'b
www.ti.com
26
0x11
CH A
Control 2
0x82
7:5
4
Reserved
Reserved
Reserved
DEM [2:0]
R
Set bits to = 100'b
Set bit to 0
R/W
3
Set bit to 0
2:0
Yes
De-Emphasis (Default = -3.5 dB)
000'b = -0.0 dB
001'b = -1.5 dB
010'b = -3.5 dB
011'b = -6.0 dB
100'b = -8.0 dB
101'b = -9.0 dB
110'b = -10.5 dB
111'b = -12.0 dB
0x12
CH A
Idle
Threshold
7
Slow OOB
Reserved
R/W
0x00
Yes
Yes
Slow OOB Enable (1); Disable (0)
Set bits to 000'b.
6:4
3:2
IDLE thA[1:0]
Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0
IDLE thD[1:0]
Yes
De-assert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
0x13
CH B
Analog
Override 1
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
0x00
Set bit to 0
6
Set bit to 0
5
Set bit to 0
4
Set bit to 0
3:0
7:0
Set bits to 0000'b.
Set bits to 00'h.
0x14
0x15
CH B
Reserved
R/W
R/W
0x00
0x00
CH B
Idle Control
7:6
5
Reserved
Idle Auto
Set bits to 00'b
Yes
Yes
Yes
Auto IDLE value when override bit is set (reg
0x08 [4] = 1)
4
Idle Select
Force IDLE value when override bit is set (reg
0x08 [4] = 1)
3:2
1:0
7:0
Reserved
Set bits to 00'b.
Set bits to 00'b.
Reserved
0x16
0x17
CH B
EQ Setting
BOOST [7:0]
R/W
R/W
0x2F
0xED
Yes
Yes
Yes
Yes
EQ Boost Default to 24 dB
See EQ Table for Information
CH B
Control 1
7
6
Sel_scp
1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
Output Mode
[1]: Normal operation
[0]: 10G-KR operation
5:3
2:0
Reserved
Reserved
Set bits to = 101'b
Set bits to = 101'b
27
www.ti.com
0x18
CH B
Control 2
0x82
7:5
4
Reserved
Reserved
Reserved
DEM [2:0]
R
Set bits to = 100'b
Set bit to 0
R/W
3
Set bit to 0
2:0
Yes
De-Emphasis (Default = -3.5 dB)
000'b = -0.0 dB
001'b = -1.5 dB
010'b = -3.5 dB
011'b = -6.0 dB
100'b = -8.0 dB
101'b = -9.0 dB
110'b = -10.5 dB
111'b = -12.0 dB
0x19
CH B
Idle
Threshold
7
Slow OOB
Reserved
R/W
0x00
Yes
Yes
Slow OOB Enable (1); Disable (0)
Set bits to 000'b.
6:4
3:2
IDLE thA[1:0]
Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0
IDLE thD[1:0]
Yes
Yes
De-assert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
0x23
CH A VOD 7:6
Reserved
R/W
0x00
Set bits to 00'b.
Control
4:2
VOD_CH0[2:0]
DS100BR111 VOD Controls for CH A (Default
= 000'b)
000'b = 700 mV
001'b = 800 mV
010'b = 900 mV
011'b = 1000 mV
100'b = 1100 mV
101'b = 1200 mV
110'b = 1300 mV
1:0
7:5
4:2
1:0
7
Reserved
Set bits to 00'b.
Set bits to 101'b.
Set bits to 011'b.
Set bits to 01'b.
0x25
0x28
Reserved
Reserved
R/W
R/W
0xAD
0x00
Reserved
Yes
Reserved
Idle Control
Reserved
6
Override Fast Idle
Yes
Yes
5:4
en_high_idle_th
[1:0]
Enable high SD thresholds
[5]: CH A
[4]: CH B
3:2
1:0
en_fast_idle[1:0]
Reserved
Yes
Yes
Enable Fast IDLE
[3]: CH A
[2]: CH B
Set bits to 00'b.
www.ti.com
28
0x2D
CH B VOD
Control
R/W
0xAD
7:5
4:2
Reserved
Set bits to 101'b.
VOD_CH0[2:0]
Yes
VOD Controls for CH B (Default = 011'b)
000'b = 700 mV
001'b = 800 mV
010'b = 900 mV
011'b = 1000 mV
100'b = 1100 mV
101'b = 1200 mV
110'b = 1300 mV
1:0
7:5
4:0
Reserved
Set bits to = 01'b
Read bits = 011'b
BR111 = 0 0111'b
0x51
Device
Information
Version[2:0]
Device ID[4:0]
R
0x67
29
www.ti.com
Typical DC Performance
Characteristics
The following data was collected at 25°C
100
90
80
70
60
50
40
30
20
10
0
3.3V Mode
2.5V Mode
700 800 900 1000 1100 1200 1300
OUTPUT VOLTAGE (mV)
30138893
FIGURE 8. Supply Current vs. Output Voltage Setting
60
VOD = 700 mV
Temp = 25°C
56
52
2.5V Mode
48
44
40
2.0
2.2
2.4
2.6
2.8
3.0
SUPPLY VOLTAGE (V)
30138894
FIGURE 9. Supply Current vs. Supply Voltage
1500
1400
1300
1200
1100
1000
900
800
700
600
500
0
1
2
3
4
5
6
7
VOD SETTING
30138895
FIGURE 10. Output Voltage vs. Output Voltage Setting
www.ti.com
30
Typical AC Performance Characteristics
NO MEDIA:
Device
Random Jitter (Rj)
Deterministic Jitter
(Dj)
Dj Component Breakdown Total Jitter (Tj @
1E-12)
DS100BR111 @
10.3125 Gbps
280 fs
9.8 ps
DDJ = 7.6 ps
DCD = 2.1 ps
DDPWS = 5.4 ps
PJ = 0.25 ps
13.7 ps
30138863
FIGURE 11. No Media; D3186 driving device directly
31
www.ti.com
The following lab setups were used to collect typical performance data on FR4 and Cable media.
30138871
FIGURE 12. Equalization Test Setup for FR4
EQUALIZATION RESULTS:
30138842
FIGURE 13. Equalization Performance with 10" of 4 mil FR4 using EQ settting 0x01
30138857
FIGURE 14. Equalization Performance with 30" of 4 mil FR4 using EQ settting 0x16
www.ti.com
32
30138872
FIGURE 15. Equalization Test Setup for Cables
CABLE TRANSMIT and RECEIVE RESULTS:
30138861
FIGURE 16. 8M 30AWG Cable Performance with 700mV Launch VOD and Rx EQ setting 0x0F
33
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30138870
FIGURE 17. De-Emphasis Test Setup
DE-EMPHASIS RESULTS:
30138839
FIGURE 18. De-Emphasis Performance with 5" of 4 mil FR4 using DE settting 0x01
30138838
FIGURE 19. 5" of 4 mil FR4 Without De-Emphasis
www.ti.com
34
30138841
FIGURE 20. De-Emphasis Performance with 10" of 4 mil FR4 using DE settting 0x02
30138840
FIGURE 21. 10" of 4 mil FR4 Without De-Emphasis
35
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS100BR111SQ (Tape and Reel 1000 units)
Order Number DS100BR111SQE (Tape and Reel 250 units)
NS Package Number SQA24A
(See AN-1187 for PCB Design and Assembly Recommendations)
www.ti.com
36
Notes
37
www.ti.com
Notes
www.ti.com
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amplifier.ti.com
dataconverter.ti.com
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dsp.ti.com
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Interface
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interface.ti.com
logic.ti.com
www.ti.com/industrial
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www.ti.com/security
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Logic
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Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
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