DS110DF1610 [TI]
8.5Gbps 至 11.3Gbps 16 通道重定时器;型号: | DS110DF1610 |
厂家: | TEXAS INSTRUMENTS |
描述: | 8.5Gbps 至 11.3Gbps 16 通道重定时器 |
文件: | 总79页 (文件大小:861K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DS110DF1610
SNLS472A –JANUARY 2014–REVISED JUNE 2017
DS110DF1610 8.5- to 11.3-Gbps 16-Channel Retimer
1 Features
2 Description
The DS110DF1610 is a sixteen-channel multi-rate
1
•
Pin-Compatible Family
retimer with integrated signal conditioning. The device
includes a full adaptive Continuous Time Linear
Equalizer (CTLE), Decision Feedback Equalizer
(DFE), clock and data recovery (CDR), and a transmit
FIR filter to enhance the reach and robustness over
long, lossy, crosstalk impaired high speed serial links
–
–
–
DS150DF1610: 12.5 - 15G
DS125DF1610: 9.8 to 12.5G
DS110DF1610: 8.5 – 11.3G
•
•
•
4x4 Analog Cross Point Switch for Each Quad
Fully-Adaptive CTLE
to achieve BER < 1×10-15
.
Self-Tuning DFE, With Optional Continuous
Adaption
Each channel of the DS110DF1610 independently
locks to serial data at 8.5 to 11.3 Gbps and any
supported sub-multiple. A simple external oscillator
(±100ppm) that is synchronous or asynchronous with
the incoming data stream can be used as a reference
clock to speed up the lock process. Integrated 4x4
cross point switches allow for full non-blocking routing
or broadcasting within each quad of the
DS110DF1610.
•
•
•
•
On-Chip, AC-coupling on Receive Inputs
Adjustable Transmit VOD
Adjustable 3-Tap Transmit FIR Filter
Locks to Half/Quarter/Eighth Data Rates For
Legacy Support
•
On-Chip Eye Monitor (EOM), PRBS Checker,
PRBS Pattern Generator
Programmable transmit FIR filter offers control of the
pre-cursor, main tap and post-cursor for transmit
equalization. The fully adaptive receive equalization
(CTLE and DFE) enables longer distance
transmission in lossy copper interconnects and
backplanes with multiple connectors.
•
•
•
•
•
•
•
•
Supports IEEE 1149.1 and 1149.6
Programmable Output Polarity Inversion
Input Signal Detection, CDR Lock Detection
Single 2.5-V ±5% Power Supply
SMBus-Based Register Configuration
Optional EEPROM Configuration
A non-disruptive mission mode eye-monitor feature
allows link monitoring internal to the receiver. The
built-in PRBS generator and checker compliment the
internal diagnostic features to complete standalone
BERT measurements. Built-in JTAG enables
manufacturing tests.
15-mm × 15-mm, 196-Pin FCBGA Package
Operating Temp Range : –10°C to +85°C
Typical Application Diagram
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS110DF1610
FCBGA (196)
15.00 mm × 15.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS110DF1610
SNLS472A –JANUARY 2014–REVISED JUNE 2017
www.ti.com
Table of Contents
6.1 Overview ................................................................. 12
6.2 Functional Block Diagrams ..................................... 12
6.3 Feature Description................................................. 13
6.4 Device Functional Modes........................................ 21
6.5 Programming .......................................................... 22
6.6 Register Maps......................................................... 23
Application and Implementation ........................ 66
7.1 Typical Applications ................................................ 66
7.2 Initialization Setup................................................... 67
Power Supply Recommendations...................... 71
8.1 Power Supply Filtering............................................ 71
1
2
3
4
5
Features.................................................................. 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 8
5.1 Absolute Maximum Ratings (DS110DF1610) .......... 8
5.2 Recommended Operating Conditions....................... 8
5.3 Thermal Characteristics ............................................ 8
5.4 Electrical Characteristics........................................... 9
Detailed Description ............................................ 12
7
8
6
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2014) to Revision A
Page
•
Changed device status from PRODUCT PREVIEW to PRODUCTION DATA ...................................................................... 1
2
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Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: DS110DF1610
DS110DF1610
www.ti.com
SNLS472A –JANUARY 2014–REVISED JUNE 2017
4 Pin Configuration and Functions
P
TX_6B_N
GND
N
TX_6B_P
GND
M
GND
L
K
TX_4B_N
GND
J
TX_4B_P
GND
H
GND
G
F
TX_3A_N
GND
E
TX_3A_P
GND
D
GND
C
GND
B
TX_1A_N
GND
A
GND
GND
TX_1A_P
01
02
01
02
TX_5B_N
GND
TX_5B_P
GND
TX_4A_N
GND
TX_4A_P
GND
TX_2A_N
GND
TX_2A_P
GND
GND
TX_7A_N
GND
TX_7A_P
GND
TX_5A_N
GND
TX_5A_P
GND
TX_2B_N
GND
TX_2B_P
GND
TX_0B_N
GND
TX_0B_P
GND
03
04
05
06
07
08
09
10
11
12
13
14
03
04
05
06
07
08
09
10
11
12
13
14
TX_6A_N
GND
TX_6A_P
TX_3B_N
GND
TX_3B_P
TX_1B_N
ADDR1
TCK_IO
TDI_IO
N/C
TX_1B_P
GND
ALL_DON
E
READ_E
N
TX_7B_N
GND
TX_7B_P
GND
VDD
VDD
VDD
VDD
TX_0A_N
ADDR0
TMS_IO
N/C
TX_0A_P
GND
N/C
SCL_IO
N/C
VDD
GND
VDD
GND
VDD
VDD
GND
N/C
REF_CLK
_P
CLK_MO
N_P
N/C
SDA_IO
GND
VDD
GND
GND
VDD
TDO_IO
TRST_IO
N/C
REF_CLK
_N
INTERR#
_IO
RESET#_
IO
CLK_MO
N_N
EN_SMB
GND
VDD
GND
VDD
GND
VDD
GND
GND
RX_7B_N
GND
N/C
GND
N/C
GND
GND
VDD
GND
VDD
GND
VDD
N/C
GND
GND
RX_0A_P
GND
RX_7B_P
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
RX_0A_N
GND
RX_6A_N
GND
RX_6A_P
GND
GND
GND
RX_3B_N
GND
RX_3B_P
GND
GND
GND
RX_1B_N
GND
RX_1B_P
GND
RX_7A_N
GND
RX_7A_P
GND
RX_5A_N
GND
RX_5A_P
GND
RX_2B_N
GND
RX_2B_P
GND
RX_0B_N
GND
RX_0B_P
GND
RX_5B_N
GND
RX_5B_P
GND
RX_4A_N
GND
RX_4A_P
GND
RX_2A_N
GND
RX_2A_P
GND
RX_6B_N
RX_6B_P
RX_4B_N
RX_4B_P
RX_3A_N
RX_3A_P
RX_1A_N
RX_1A_P
P
N
M
L
K
J
H
G
F
E
D
C
B
A
(TOP VIEW)
Pin Descriptions
DS110DF1610,
DS125DF1610 PIN NAME
DS150DF1610 PIN
NAME
NO.
I/O TYPE
DESCRIPTION
HIGH-SPEED DIFFERENTIAL I/Os
RX_1A_P
RX_1A_N
RX_0_0P
RX_0_0N
A14
B14
I, CML
I, CML
I, CML
I, CML
I, CML
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_0B_P
Rx_0B_N
RX_0_1P
RX_0_1N
A12
B12
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_0A_P
RX_0A_N
RX_0_2P
RX_0_2N
A10
B10
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_2A_P
RX_2A_N
RX_0_3P
RX_0_3N
C13
D13
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_1B_P
RX_1B_N
RX_0_4P
RX_0_4N
C11
D11
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
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Pin Descriptions (continued)
DS110DF1610,
DS125DF1610 PIN NAME
DS150DF1610 PIN
NAME
NO.
I/O TYPE
DESCRIPTION
RX_3A_P
RX_3A_N
RX_0_5P
RX_0_5N
E14
F14
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
I, CML
O, CML
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_2B_P
RX_2B_N
RX_0_6P
RX_0_6N
E12
F12
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_4A_P
RX_4A_N
RX_0_7P
RX_0_7N
G13
H13
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_3B_P
RX_3B_N
RX_1_0P
RX_1_0N
G11
H11
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_4B_P
Rx_4B_N
RX_1_1P
RX_1_1N
J14
K14
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_5A_P
RX_5A_N
RX_1_2P
RX_1_2N
J12
K12
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_5B_P
RX_5B_N
RX_1_3P
RX_1_3N
L13
M13
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_6A_P
RX_6A_N
RX_1_4P
RX_1_4N
L11
M11
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_6B_P
RX_6B_N
RX_1_5P
RX_1_5N
N14
P14
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_7A_P
RX_7A_N
RX_1_6P
RX_1_6N
N12
P12
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
RX_7B_P
RX_7B_N
RX_1_7P
RX_1_7N
N10
P10
Inverting and non-inverting CML-
compatible, AC coupled differential
inputs. An on-chip 100 Ohm differential
termination resistor connects these
inputs.
TX_1A_P
TX_1A_N
TX_0_0P
TX_0_0N
A1
B1
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
4
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Product Folder Links: DS110DF1610
DS110DF1610
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Pin Descriptions (continued)
DS110DF1610,
DS125DF1610 PIN NAME
DS150DF1610 PIN
NAME
NO.
I/O TYPE
DESCRIPTION
TX_0B_P
TX_0B_N
TX_0_1P
TX_0_1N
A3
B3
O, CML
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_0A_P
TX_0A_N
TX_0_2P
TX_0_2N
A5
B5
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_2A_P
TX_2A_N
TX_0_3P
TX_0_3N
C2
D2
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_1B_P
TX_1B_N
TX_0_4P
TX_0_4N
C4
D4
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_3A_P
TX_3A_N
TX_0_5P
TX_0_5N
E1
F1
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_2B_P
TX_2B_N
TX_0_6P
TX_0_6N
E3
F3
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_4A_P
TX_4A_N
TX_0_7P
TX_0_7N
G2
H2
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_3B_P
TX_3B_N
TX_1_0P
TX_1_0N
G4
H4
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_4B_P
TX_4B_N
TX_1_1P
TX_1_1N
J1
K1
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_5A_P
TX_5A_N
TX_1_2P
TX_1_2N
J3
K3
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_5B_P
TX_5B_N
TX_1_3P
TX_1_3N
L2
M2
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_6A_P
TX_6A_N
TX_1_4P
TX_1_4N
L4
M4
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
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Pin Descriptions (continued)
DS110DF1610,
DS125DF1610 PIN NAME
DS150DF1610 PIN
NAME
NO.
I/O TYPE
DESCRIPTION
TX_6B_P
TX_6B_N
TX_1_5P
TX_1_5N
N1
P1
O, CML
O, CML
O, CML
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_7A_P
TX_7A_N
TX_1_6P
TX_1_6N
N3
P3
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
TX_7B_P
TX_7B_N
TX_1_7P
TX_1_7N
N5
P5
Inverting and non-inverting CML-
compatible differential outputs. Driver
presents an output impedance of 100
ohms between these outputs when
switching.
CLOCK PINS
REF_CLK_P
REF_CLK_N
P7
P8
I, LVDS/LVCMOS Inverting and non-inverting
CML-compatible differential inputs for
25 MHz, 125 MHz, or 312.5 MHz
clock.
When configured for single-ended
input operation, apply LVCMOS ref
clock to REF_CLK_P and float
REF_CLK_N. Single-ended signals
should be DC coupled.
CLK_MON_P
CLK_MON_N
A7
A8
O, LVDS
Inverting and non-inverting
CML-compatible differential outputs to
monitor system differential clock.
When daisy chaining to another retimer
the output frequency should be set to
25 MHz or 125 MHz.
SMBUS INTERFACE
SDA_IO
M7
L6
I/O, Open Drain Data Input / Open Drain Output
External pull-up resistor is required.
Pin is 3.3 V LVCMOS tolerant.
SCL_IO
I/O, Open Drain Clock input/output, Pin is 3.3 V
LVCMOS Tolerant
EEPROM configuration (SMBus
Master mode)
will be available in final silicon
JTAG INTERFACE
TMS_IO
B7
I, LVCMOS
JTAG Test Mode Select, internal pull-
up
TDO_IO
C7
C8
D6
D7
O, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
JTAG Test Data Out
TRST_IO
TCK_IO
JTAG Test Reset, internal pull-up
JTAG Test clock, internal pull-up
JTAG Test Data Input, internal pull-up
TDI_IO
OTHER PINS
RESET_IO
L8
M8
B6
I, LVCMOS
O, Open Drain
I/O, LVCMOS
Resets registers and state machines
on rising edge. Expected pulse of
10µs.
INTERR_IO
Active Low interrupt signal. Pin goes
low when an interrupt event occurs.
Interrupts must be enabled via SMBus.
ADDR0 (GPIO0)
4 level input strap pin for SMBus
address code LSB. Standard LVCMOS
output.
6
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DS110DF1610
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Pin Descriptions (continued)
DS110DF1610,
DS125DF1610 PIN NAME
DS150DF1610 PIN
NAME
NO.
I/O TYPE
DESCRIPTION
ADDR1(GPIO1)
D5
I/O, LVCMOS
4 level input strap pin for SMBus
address code MSB. Standard
LVCMOS output.
READ_EN (GPIO2)
ALL_DONE (GPIO3)
G5
L5
I/O, LVCMOS
I/O, LVCMOS
I, LVCMOS
Tie low for SMBus slave mode
operation. Pin has internal pull down.
EEPROM load status. Pin goes LOW
when EEPROM load is complete.
EN_SMB
(SCAN_MODE)
N8
Connect to GND through ≤1kΩ resistor
for SMBus slave operation.
Connect to VDD through ≤1kΩ resistor
for EEPROM configuration
POWER
VDD
E5, E7, E9, E10,
F5, F6, F8, F10,
G7, G9, H6, H8,
J5, J7, J9, J10, K5,
K6, K8, K10
Power
Power
VDD = 2.5 V +/- 5%
Ground reference
GND
A2, A4, A6, A9,
A11, A13, B2, B4,
B9, B11, B13, C1,
C3, C5, C10, C12,
C14, D1, D3, D10,
D12, D14, E2, E4,
E6, E8, E11, E13,
F2, F4, F7, F9,
F11, F13, G1, G3,
G6, G8, G10, G12,
G14, H1, H3, H5,
H7, H9, H10, H12,
H14, J2, J4, J6, J8,
J11, J13, K2, K4,
K7, K9, K11, K13,
L1, L3, L10, L12,
L14, M1, M3, M5,
M10, M12, M14,
N2, N4, N6, N9,
N11, N13, P2, P4,
P6, P9, P11, P13
N/C
B8, C6, C9, D8,
D9, L7, L9, M6,
M9, N7
No Connect, leave floating
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5 Specifications
5.1 Absolute Maximum Ratings (DS110DF1610)
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.5
–0.5
–0.5
–0.5
–30
MAX
2.75
2.75
4
UNIT
V
Supply voltage (VDD)
LVCMOS input/output voltage
Open-drain I/O supply voltage
CML input voltage
V
V
VDD + 0.5
30
V
CML input current
mA
°C
kV
kV
Storage temperature, Tstg
–40
150
Human Body Model (HBM) - JESD22-A114F
ESD Ratings
>4
Charged Device Model (CDM) - JESD22-A114F
>1
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications
5.2 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
2.375
–10
TYP
2.5
25
MAX
2.625
85
UNIT
V
Supply voltage
Ambient temperature
SMBus (SDA, SCL), INTERR_IO
°C
V
2.5
3.6
5.3 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)(1)
BOARD
θ JA (°C / W)
Ψ JT (°C / W)
Ψ JB (°C / W)
JEDEC
18.2
7.2
0.7
0.3
0.3
0.3
5.4
3.2
3.2
3.2
8x6 inches 10 layer
8x6 inches 20 layer
8x6 inches 30 layer
6.4
6.3
(1) For soldering specifications: See product folder at www.ti.com
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5.4 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
8.5
TYP
MAX
11.3
UNIT
Full Rate
Half Rate
4.25
5.65
R_baud
Input Data Rate
Gbps
Quarter Rate
Eighth Rate
2.125
1.0625
2.825
1.4125
POWER SUPPLY
CTLE only, 800mVp-p VOD, per channel,
CDR locked
210
CDR Locking with CTLE only, 800mVp-p
342.8
VOD,
per channel
CTLE and DFE, 800mVp-p VOD, per
channel,
CDR locked
235
Power Consumption per
Active Channel
W
mW
mW
CDR Locking with CTLE and DFE,
800mVp-p VOD
367.8
PRBS Checker
57
83
PRBS Generator
Power applied,
no signals present
300
WSTATIC
Static Power consumption
LVCMOS
V IH
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
1.75
GND
2
VDD
0.7
V
V
V
V
VIL
VOH
IOH = 4mA
IOL = –4mA
VOL
0.4
Vinput = VDD,
+30
Open Drain pins
Vinput = VDD,
JTAG pins, Ref_CLK pins
+25
+50
Input High Leakage
current
IIH
mA
Vinput = VDD,
CLK_MON pin
Vinput = VDD,
GPIO pins, EN_SMB pin
+75
Vinput = 0V,
Open Drain pins
–15
–45
Vinput = 0V,
JTAG pins, Ref_CLK pins
Input Low Leakage
current
IIL
mA
Vinput = 0V,
CLK_MON pin
–50
Vinput = 0V,
GPIO pins, EN_SMB pin
–120
RX INPUTS
RRD
DC Input Resistance
80
100
120
Ω
VRX-IN
Input Differential Voltage
1600
mVPP
VDD – (VRX-
IN/ 4)
Vcm-RX
Input common mode
Internal coupling cap
VRX-IN / 4
V
TX OUTPUTS
drv_sel_vod[5:0] = 31, DEM, C0 = default
drv_sel_vod[5:0] = 15, DEM, C0 = default
825
400
1000
525
1200
675
VOD
Output Differential Voltage
mVPP
mVPP
Step Size for drv_sel_vod
Control
ΔVOD
Default DEM, and FIR settings
32
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Change in Output
Differentential Voltage due
to Change in Temperature
and Voltage
ΔVODVT
<15
mVPP
Output Differential
Resistance
RRd
RRDZ
tr, tf
IOS
100
50
Ω
Ω
Output Resistance of
Shutdown Termination
Resistor
Resistor connects output pin to VDD
20% - 80% using 8T Pattern, fir_sel_edge
= default
Output Rise/Fall Time
35
ps
mA
Differential Driver Output pin short to
GND
drv_sel_vod = >4
Output Short Circuit
Current
–16
RETIMER JITTER SPECS
PRBS-7 pattern, measured to 1e-12
10.3125 Gbps data rate
8.6
(89)
ps
(mUI)
JTJ
JRJ
JDJ
Total Output Jitter
PRBS-7 pattern, measured to 1e-12
8.625 Gbps data rate
9.35
(80.6)
PRBS-7 pattern, measured to 1e-12
10.3125 Gbps data rate
400
(4.125)
fs-rms
(mUI-rms)
Output Random Jitter
Output Deterministic Jitter
PRBS-7 pattern, measured to 1e-12
8.625 Gbps data rate
439
(3.78)
PRBS-7
10.3125 Gbps data rate
3.15
(33)
ps
(mUI)
PRBS-7
3.35
8.625 Gbps data rate
(28.9)
JTRANS
JPEAK
Jitter Transfer
Jitter Peaking
–6
<0.1
6.35
8.43
dB
dB
Data Rate = 8.625 Gbps
Data Rate = 11.3 Gbps
BWPLL
PLL Bandwidth
MHz
RETIMER TIMING SPECS
Data Rate = 10.3125Gbps,
No Cross Point
480
505
<80
ps
ps
ps
Propagation Delay from
Rx inputs to Tx outputs
tD
Data Rate = 10.3125 Gbps,
Cross Point enabled
Channel To Channel
Skew
tSK
RECOMMENDED REFERENCE CLOCK SPECS
25
125
Input Reference Clock
Frequency
REFf
MHz
312.5
Reference Clock PPM
Tolerance
REFPPM
–100
100
100
PPM
mV
Reference Clock Input
High Threshold
REFTH
REFTL
Differential mode
Differential mode
Reference Clock Input
Low Threshold
–100
mV
SMBus ELECTRICAL CHARACTERISTICS
VIH
VIL
CIN
Input High Level Voltage
Input Low Level Voltage
Input Pin Capacitance
SDA and SCL
SDA and SCL
1.75
VDDIO
0.7
V
V
GND
<5
pF
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDA and SCL
VOL
Low Level Output Voltage VDDIO = 2.5V
IOL = 2mA
0.4
V
RECOMMENDED SMBus SWITCHING CHARACTERISTICS
fSCL
SCL Clock Frequency
Data Hold Time
10
15
100
400
kHz
ns
tHD:DAT
tSU:DAT
Data Setup Time
170
ns
RECOMMENDED JTAG SWITCHING CHARACTERISTICS
tTCK
TCK Clock Period
100
50
ns
ns
TDI, TMI Setup Time to
TCK
tSU
TDI, TMS Hold Time to
TCK
tHD
50
50
ns
ns
tDLY
TCK Falling Edge to TDO
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6 Detailed Description
6.1 Overview
The DS110DF1610 is a multi-rate, 16-channel retimer with integrated 4x4 cross point switches and receiver AC
coupling capacitors. There is 1 cross point switch per 4 channels (quad). Each channel in the DS110DF1610
operates independently even if the cross point switch routing is enabled. All channels include a Continuous Time
Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), Variable Gain Amplifier (VGA), Clock and Data
Recovery circuit (CDR) and a differential driver with a 3-tap transmit Finite Impulse Response (FIR) filter. Each
channel also has its own Eye Opening Monitor (EOM) and configurable Pseudo-Random Bit Sequence (PRBS)
pattern checker and pattern generator that can be used for debug purposes.
The DS110DF1610 also supports IEEE 1149.1 (DC) and IEEE1149.6 (AC) JTAG. The DS110DF1610 is
configurable through a single SMBus port. The DS110DF1610 can also act as an SMBus master to configure
itself from an EEPROM.
The sections below describe the functionality of the various circuits and features within the DS110DF1610. For
more information about how to program or operate these features please consult the DS110DF1610
Programming Guide.
6.2 Functional Block Diagrams
1 of 4 Quads - DS110DF1610
EQ
EQ
DFE
DFE
Driver
CDR
IN_0+
IN_0-
OUT_0+
OUT_0-
100ꢀ
100W
100W
CDR
Driver
IN_1+
IN_1-
OUT_1+
OUT_1-
100ꢀ
CrossPoint
EQ
CDR
CDR
Driver
DFE
DFE
IN_2+
IN_2-
OUT_2+
OUT_2-
100ꢀ
Driver
100W
EQ
IN_3+
IN_3-
OUT_3+
OUT_3-
100ꢀ
100W
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Figure 1. DS110DF1610 Simplified Cross Point Diagram
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Functional Block Diagrams (continued)
Retimer/CDR
EQ
Driver
Cross Point
VGA/DFE
FIR Filter
IN+
IN-
OUT+
OUT-
100ꢀ
100W
Eye
Opening
Monitor
PRBS
Check
Patt.
Gen
Signal
Detect
VCO
Digital Core
REFCLK_IN
SMBus
1.2V
Regulator
2V
Regulator
2.5V
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Figure 2. DS110DF1610 Simplified Data Path Diagram
6.3 Feature Description
6.3.1 Device Data Path Operation
The DS110DF1610 data path consists of several key blocks as shown in Figure 2. These key circuits are:
•
•
•
•
•
•
AC-coupled Receiver with Signal Detect
CTLE
Cross Point Switch
DFE with VGA
CDR
Differential Driver with FIR Filter
6.3.1.1 AC-Coupled Receiver With Signal Detect
The differential receiver for each DS110DF1610 channel contains on chip AC coupling capacitors. The minimum
bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.
The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high
speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to
automatically power on or off the rest of the high speed data path depending on if a signal is present. Users can
obtain manual control over the signal detect block through the SMBus channel registers. This can be useful if it is
desired manually force channels to be disabled. For information on how to manually operate the signal detect
circuit please see the DS110DF1610 Programming Guide and channel register 0x15 information.
6.3.1.2 CTLE
The CTLE in the DS110DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting
stage. The CTLE is adapted to a boost setting according to a Figure of Merit (FOM) during the lock acquisition
process. Once the CDR has locked, the CTLE boost level will be frozen until a manual re-adapt command is
issued or until the CDR re-enters the lock acquisition state.
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Feature Description (continued)
The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-
boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost
combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel
registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost
settings. Users also have the option of limiting the EQ table length to any value between a minimum value of 1
and a maximum value of 32.
CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost
combinations that sum to the same number will have approximately the same boost level, but will result in a
different shape for the EQ transfer function (boost curve). The boost levels can be set between 6 dB and 38 dB.
The CTLE bandwidth can be adjusted through SMBus control to 3 different levels:
CTLE BANDWIDTH SETTING
Full Rate
RESULTING BANDWIDTH (GHz)
9
7
5
Mid Rate
Half Rate
The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather
than a linear stage. This is useful in some applications, but it should not be typically used in combination with the
DFE.
6.3.1.3 Cross Point Switch
Each quad has a 4x4 non-blocking analog cross point switch. This allows for full switching or broadcasting of
data between any input within the quad to any output within the quad. Since the cross point switch is an analog
implementation, all of the channels are allowed to operate asynchronously. The analog implementation also
minimizes added latency through the device.
As shown in Figure 1, the cross point switch connections for each quad are located between CTLE and DFE in
each channel.
The cross point switch consists of consists of 4 sets of MUXs and buffers. In each channel there is a local buffer
and a multi-drive buffer. The local buffer transmits data from the CTLE to the DFE of the same channel. The
multi drive buffer transmits data from the CTLE to the DFE(s) of other channels within the quad. Each channel
has two MUXs:
1. Data path mux – Selects whether to get data from the local buffer or from other channel’s multi-driver buffer
2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting
should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ
becomes associated with that CDR’s register set. For example, if the cross point was configured to do point
to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the
outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible
through the register set of channel 1.
A simplified diagram of the cross point switch is shown in Figure 3.
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Local
Buffer
IN_0+
IN_0-
VGA, DFE, CDR,
Tx0 +/-
CTLE
CTLE
CTLE
CTLE
Multi-Point
Buffer
2
Local
Buffer
IN_1+
IN_1-
VGA, DFE, CDR,
Tx1 +/-
Multi-Point
Buffer
2
Local
Buffer
IN_2+
IN_2-
VGA, DFE, CDR,
Tx2 +/-
Multi-Point
Buffer
2
Local
Buffer
IN_3+
IN_3-
VGA, DFE, CDR,
Tx3 +/-
Multi-Point
Buffer
2
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Figure 3. Cross Point Switch Diagram
In a typical point-to-point switching application users must configure the following for each channel:
1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Cross point enable bit (ch reg 0x96)
5. Perform a CDR reset and reset release (ch reg 0x0A)
Note, when using the cross point switch the local and multi-drive buffer should both be enabled regardless of the
desired configuration.
The cross point switch can also be used to replicate data or perform a broadcast function. The options for this
type of configuration include:
•
•
1:2 – any channel input to any 2 channels output
1:3 – any channel input to any 3 channels output
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•
1:4 – any channel input to all 4 channels output
When the cross point switch is configured to replicate/broadcast data a master must be assigned during the
cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels
will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there
must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as
slaves. There cannot be more than one master channel in a broadcast network.
In a typical data replication/broadcast application users must configure the following for each channel:
1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Master/Slave assignment (ch reg 0x96)
5. Cross point enable bit (ch reg 0x96)
6. Perform a CDR reset and reset release (ch reg 0x0A)
6.3.1.4 DFE With VGA
A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects
of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled,
regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only
during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap
polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be
disabled.
The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity
bit.
DFE PARAMETER
Tap 1 Weight Range
Tap 2-5 Weight Range
Tap Weight Step Size
VALUE (mV)
0 – 224
0 – 112
7
A VGA is located at the input to the DFE block. The VGA has 2-bit control to allow for 4 levels of boost. The VGA
can be used to assist in the recovery of extremely small signals. Note that the VGA is integrated within the DFE,
so in order to use the VGA the DFE must be enabled.
6.3.1.5 Clock and Data Recovery
The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output
Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling
position is fixed at the 0.5UI location for each bit.
By default, the equalized data is fed into the CDR for clock and data recovery. This data is then output to FIR
filter and differential driver. Users can configure the CDR data to route the recovered clock and data to the PRBS
checker. Users also have the option of configuring the output of the CDR to send raw non-retimed data, or data
from the pattern generator.
The CDR requires the following in order to be properly configured:
•
•
Input reference clock with proper reference clock divider setting to run the PPM counter.
Expected data rates must be programmed into the CDR either through the rate/sub-rate table or entered
manually with the corrected divider settings.
6.3.1.6 Reference Clock
The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for
each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed
values in the rate/sub-rate table or the manually entered data rates.
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The reference clock can be set to any of the 3 allowable frequencies independant of the data rate of the high
speed channel. The input reference clock can be single-ended or differential for the 25 MHz or 125 MHz settings.
If the 312.5 MHz setting is used, the input signaling type should be differential. The reference clock can be output
through the CLK_MON pins for observation or daisy chaining the reference clock to the next device. If the
CLK_MON port is used for daisy chaining then the output frequency should be set to 25 MHz.
If the reference clock port is configured to operate in single-ended mode, the 2.5V LVCMOS clock signal should
be applied to the REF_CLK_P pin. In this configuration the REF_CLK_N pin should be floated (N/C). In this case
the LVCMOS clock signal should be DC coupled into the REF_CLK_P pin.
Configuring the reference clock frequency is done in share register 0x02[6:5]. Configuring the reference clock
input port for single-ended or differential mode operation is done in share register 0x0B[4]. Enabling or disabling
the CLK_MON port is done in share reg 0x0A[0]. Selecting the divided (25 MHz) or undivided (input frequency) is
done in share register 0x04[7].
Table 1. Reference Clock Configurations
DEFAULT CLK_MON
FREQUENCY
CLK_MON FREQUENCY FOR
DAISY CHAINING
INPUT FREQUENCY
INPUT CONFIGURATION
25 MHz
125 MHz
312.5 MHz
Single-ended or Differential
Single-ended or Differential
Differential
25 MHz
125 MHz
312.5 MHz
25 MHz
25 MHz
25 MHz
6.3.1.7 Differential Driver With FIR Filter
The DS110DF1610 output driver can be manually powered off through SMBus register control. The outputs of
the DS110DF1610 also have optional output termination resistors that can be enabled when the driver is
manually powered down. These termination resistors can help reduce the effects of cross talk in high speed
systems.
The DS110DF1610 uses a 3-tap FIR filter to assist with transmit equalization. The FIR filter consists of a pre
cursor tap, a main cursor tap and a post cursor tap. Each tap has a polarity bit and 64 available levels. By
default, the main cursor tap is set to a positive polarity, while the pre cursor and post cursor taps are set to a
negative polarity. Users can invert the polarity of all 3 FIR taps to invert the polarity of the output data.
6.3.1.7.1 Setting the Output VOD
Users can control the output differential voltage (VOD) of the driver by manipulating the drv_sel_vod bits, DEM
bits, and FIR main cursor tap. The table below shows various settings for VOD settings ranging from 150mVPP to
1200 mVPP. Using the FIR, DEM and drv_sel_vod bits is the recommended method for configuring the output
VOD for the best signal integrity. The user also has the option of using only the drv_sel_vod bits to configure the
output VOD, which is sometimes useful for slower datarates. If the FIR taps and DEM bits are set to 0x0, the
drv_sel_vod bits can be used to set the output VOD from 50mVPP to 1400mVPP
.
FIR
DRV_SEL_VOD
SETTING
VOD (mVPP
)
DEM SETTING
PRE
0
MAIN
56
52
49
45
54
56
52
46
42
56
46
40
POST
-4
1200
1150
1100
1050
1000
950
0
0
0
0
2
3
3
3
3
3
3
3
31
31
31
31
31
31
31
31
31
25
25
25
0
-4
0
-4
0
-4
0
-3
0
-2
900
0
-2
850
0
-1
800
0
-1
750
0
-3
700
0
-2
650
0
-1
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FIR
DRV_SEL_VOD
SETTING
VOD (mVPP
)
DEM SETTING
PRE
0
MAIN
50
POST
-2
600
550
500
450
400
350
300
250
200
150
3
3
3
3
3
3
3
3
3
3
21
19
17
15
13
12
10
8
0
50
-3
0
52
-3
0
50
-3
0
52
-3
0
51
-3
0
51
-3
0
55
-3
6
0
56
-3
4
0
57
-3
6.3.1.7.2 Output Driver Polarity Inversion
In some cases it may be necessary to invert the polarity of the data transmitted from the retimer. To invert the
polarity of the data read back the FIR polarity settings for the pre, main and post cursor and then invert these
bits.
6.3.1.7.3 Driver Output Rise/Fall Time
In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic
interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory
compliance. In others, it can reduce the crosstalk in the system.
The DS110DF1610 can be configured to operate with a nominal rise/fall time corresponding to the maximum
slew rate of the output drivers into the load capacitance. Alternatively, the DS110DF1610 can be configured to
operate with a slightly greater rise/fall time if desired. By default the DS110DF1610 is configured to use the
fastest edge rate.
6.3.2 Debug Features
6.3.2.1 Pattern Generator
Each channel in the DS110DF1610 can be configured to generate a 16-bit user defined data pattern or a pseudo
random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit
symbol for DC balancing purposes. The DS110DF1610 pattern generator supports the following PRBS
sequences:
•
•
•
•
PRBS – 7
PRBS – 9
PRBS – 15
PRBS – 31
6.3.2.2 Pattern Checker
The pattern checker can be manually set to lock for specific PRBS sequences and polarities or it can be set to
automatically detect the incoming pattern and polarity. If the pattern checker is meant to work with a user defined
pattern, then it must be programmed to search for that exact pattern.
The pattern checker consists of a 47-bit bit counter and an 11-bit error counter. In order to read out the bit and
error counters, the pattern checker must first be frozen. Continuous operation with simultaneous read out of the
bit and error counters is not possible in this implementation.
6.3.2.3 Eye Opening Monitor
The DS110DF1610’s Eye Opening Monitor (EOM) can be used for 2 functions:
1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture
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The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement
is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from
channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to
convert the contents of channel registers 0x27 and 0x28 into their appropriate units:
•
•
HEO [UI] = ch reg 0x27 ÷ 64
VEO [mV] = ch reg 0x28 x 3.125
A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a
64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical
scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal
scaling controlled by the state machine and is always directly proportional to the data rate.
When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be
discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot
from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is
incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage
position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64
matrix is read out. Figure 4 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In
this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users
can apply different algorithms to the output data to plot density or color gradients to the output data.
63
127 191
4095
63
64 128
4032
63
0
0
0
Phase Position
Figure 4. EOM Full Eye Capture Readout
To manually control the EOM vertical range, remove scaling control from the state machine then select the
desired range:
1. Channel Reg 0x2C[6] → 0
2. See table:
CH REG 0x11[7:6] VALUE
EOM VERTICAL RANGE [mV]
2’b00
2'b01
2'b10
±100
±200
±300
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CH REG 0x11[7:6] VALUE
EOM VERTICAL RANGE [mV]
2'b11
±400
The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over
equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit
error rate.
The EOM can be accessed in two ways to read out the entire eye plot:
•
•
Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in
register 0x26. In this mode, the device must be addressed each time a new byte is read.
To perform a full eye capture with the EOM, follow these steps within the desired channel register set:
REGISTER
[BITS]
STEP
VALUE
DESCRIPTION
1
2
0x67[5]
0
Disable lock EOM lock monitoring
Set the desired EOM vertical range
0x2C[6]
0x11[7:6]
0
2'b--
3
4
0x11[5]
0x24[7]
0
1
Power on the EOM
Enable fast EOM
Begin read out of the 64 x 64 array, discard first 4 words
Ch reg 0x24[0] is self clearing.
0x25 is the MSB of the 16-bit word
0x24[0]
0x25
0x26
5
1
0x26 is the LSB of the 16-bit word
0x25
0x26
6
7
Continue reading information until the 64 x 64 array is complete.
Return the EOM to its original state. Undo steps 1-4
0x67[5]
0x2C[6]
0x11[5]
1
1
1
0
0x24[7,1]
6.3.2.4 Interrupt Signals
The DS110DF1610 can be configured to report different events as interrupt signals. These interrupt signals do
not impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits
in the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that
interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once
the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The
DS110DF1610 will report the occurrence of an interrupt through the INTERR_IO pin. The INTERR_IO pin is an
open drain output that will pull the line low when an interrupt signal is triggered.
Note that all available interrupts are disabled by default. Users must activate the various interrupts before they
can be used.
The interrupts available in the DS110DF1610 are:
•
•
•
•
•
•
•
CDR loss of lock
CDR locked
Signal detect loss
Signal detected
PRBS pattern generator lock up
PRBS pattern checker bit error detected
HEO/VEO threshold violation
When an interrupt occurs, share register 0x08 and 0x09 report which channel generated the interrupt request.
Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the
appropriate interrupt status bits in the corresponding channel registers.
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6.3.3 Other Features
6.3.3.1 Lock Sequencer
A channel will temporarily consume a higher amount of power while its CDR is attempting to lock, compared to
when the CDR is locked. In order to reduce the impact of a power consumption spike when data is transmitted to
a DS110DF1610, the internal lock sequencer will limit the number of active channels that are simultaneously
allowed to attempt to lock.
The lock sequencer grants tokens to various channels that have detected a signal at the input to the CTLE. Once
a channel has achieved CDR lock, it returns its token to the lock sequencer. The lock sequencer will distribute
any available tokens on a first come first serve basis to any channel that is allowed to attempt lock and that has
detected a valid signal.
The lock sequencer is configurable in the share registers. Users can control which channels are allowed to
attempt lock when a signal is present by configuring share registers 0x0F and 0x10. Users can also limit the
number of channels that are allowed to simultaneously attempt to lock by configuring share register 0x05.
RESET_IO Pin
The RESET_IO pin in the DS110DF1610 emulates a power on reset (POR). This type of reset re-initializes the
entire device including the SMBus address strap settings and restores both share and channel register defaults.
The RESET_IO pin triggers a reset on the rising edge of the signal. It is not recommended to hold the
RESET_IO pin at a logic LOW state for an extended period of time. RESET_IO should be held at logic HIGH
during power on. After power on, the RESET_IO pin should be pulsed low for a minimum of 10 µs to perform a
reset.
6.4 Device Functional Modes
6.4.1 SMBus Slave Mode
6.4.1.1 SDA and SDC
In both SMBus master and SMBus slave mode, the DS110DF1610 is configured using the SMBus. The SMBus
consists of two lines, the SDA or serial data line and the SCL or serial clock line. In the DS110DF1610 these pins
are 3.3V tolerant. The SDA and SCL lines are both open-drain. They require a pull-up resistor to a supply
voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2KΩ to 5KΩ range will provide reliable SMBus
operation.
6.4.1.2 Address Line
In either SMBus mode the DS110DF1610 must be assigned an SMBus address. A unique address should be
assigned to each device on the SMBus.
The DS110DF1610 can be configured to respond to one of the sixteen SMBus addresses listed in the table
below. GPIO1 and GPIO0 are configured to be four level inputs immediately after the device powers on. Logic 0
can be set by tying the pin to ground through a ≤1kΩ resistor. Logic R is set by tying the pin to ground through a
20kΩ resistor. Logic F is set by floating the pin. Logic 1 is set by tying the pin to VCC = 2.5V through a ≤1kΩ
resistor.
ADDR1(GPIO1) (PIN D5)
ADDR0(GPIO0) (PIN B6)
7-BIT ADDRESS
7’h18
8-BIT WRITE ADDRESS
0
0
0
R
F
1
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40
7’h19
0
7’h1A
0
7’h1B
R
R
R
R
F
0
7’h1C
R
F
1
7’h1D
7’h1E
7’h1F
0
7’h20
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Device Functional Modes (continued)
ADDR1(GPIO1) (PIN D5)
ADDR0(GPIO0) (PIN B6)
7-BIT ADDRESS
7’h21
8-BIT WRITE ADDRESS
F
F
F
1
1
1
1
R
F
1
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
7’h22
7’h23
0
7’h24
R
F
1
7’h25
7’h26
7’h27
When an SMBus device is addressed for reading or writing a bit is appended to the address a the least
significant bit space. This bit is set to 0 for a write or to 1 for a read.
6.4.1.3 Device Configuration in SMBus Slave Mode
The configurable settings of the DS110DF1610 may be set independently for each channel at any time after
power up using the SMBus. A register write is accomplished when the controller sends a START condition on the
SMBus followed by the Write address of the DS110DF1610 to be configured. After sending the Write address of
the DS110DF1610, the controller sends the register address byte followed by the register data byte. The
DS110DF1610 acknowledges each byte written to the controller according to the data link protocol of the SMBus
Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.
There are 3 types of device registers in the DS110DF1610. These are the global registers, shared registers and
the channel registers. The global registers are programmed to access the various channel registers or the shared
registers. The shared registers control or allow observation of settings which affect the operation of all channels
of the DS110DF1610 at the greater device level.
The channel registers are used to set all the configuration settings of the DS110DF1610. They provide
independent control for each channel of the DS110DF1610 for all the settable device characteristics. Any
registers not described in the tables that follow should be treated as reserved. The user should not try to write
new values to these registers. The user-accessible registers described in the tables that follow provide a
complete capability for customizing the operation of the DS110DF1610 on a channel-by-channel basis.
6.5 Programming
6.5.1 Bit Fields in the Register Set
Many of the registers in the DS110DF1610 are divided into bit fields. This allows a single register to serve
multiple purposes, which may be unrelated. Often configuring the DS110DF1610 requires writing a bit field that
makes up only part of a register value while leaving the remainder of the register value unchanged.
The procedure for accomplishing this is to read in the current value of the register to be written, modify only the
desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to
be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the
register first. In all the register configuration procedures described in the following sections, this procedure should
be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be
changed, however, the procedure described above should be used.
6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
Global registers can be accessed from the shared register page and also the channel register pages. There are
three global registers in the DS110DF1610:
1. Register 0xFC
2. Register 0xFD
3. Register 0xFF
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Programming (continued)
Registers 0xFC and 0xFD are used to select the channel registers to be written to. To select a channel write a 1
to its corresponding bit in these global registers. Note more than one channel may be written to by setting
multiple bits in registers 0xFC and 0xFD. However, when performing an SMBus read transaction only one
channel can be selected at a time. If multiple channels are selected when attempting to perform an SMBus read,
the device will return 0x00.
GLOBAL
REGISTER
BIT
DESCRIPTION
CDR/TX PIN ASSIGNMENT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Channel 15– Quad 3 Channel 3– Cross Point Ch D
Channel 14– Quad 3 Channel 2 – Cross Point Ch C
Channel 13– Quad 3 Channel 1 – Cross Point Ch B
Channel 12– Quad 3 Channel 0 – Cross Point Ch A
Channel 11– Quad 2 Channel 3– Cross Point Ch D
Channel 10– Quad 2 Channel 2 – Cross Point Ch C
Channel 9– Quad 2 Channel 1 – Cross Point Ch B
Channel 8– Quad 2 Channel 0 – Cross Point Ch A
Channel 7– Quad 1 Channel 3– Cross Point Ch D
Channel 6– Quad 1 Channel 2 – Cross Point Ch C
Channel 5– Quad 1 Channel 1 – Cross Point Ch B
Channel 4– Quad 1 Channel 0 – Cross Point Ch A
Channel 3– Quad 0 Channel 3 – Cross Point Ch D
Channel 2– Quad 0 Channel 2 – Cross Point Ch C
Channel 1– Quad 0 Channel 1 – Cross Point Ch B
Channel 0 – Quad 0 Channel 0 – Cross Point Ch A
TX_7B
TX_7A
TX_6B
TX_6A
TX_5B
TX_5A
TX_4B
TX_4A
TX_3B
TX_3A
TX_2B
TX_2A
TX_1B
TX_1A
TX_0B
TX_0A
0xFD
0xFC
Register 0xFF is used select the shared register page or the channel register page for the channels selected in
registers 0xFC and 0xFD.
GLOBAL REGISTER
BITS
DESCRIPTION
1: Select Channel Registers
0: Select Share Registers
0xFF
0
6.6 Register Maps
6.6.1 Shared and Channel Registers
Table 2. Shared Registers
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
0
0
0
0
R
R
R
R
N
N
N
N
SMBus_Addr3
SMBus Address
Strapped 7-bit addres is 0x18 +
SMBus_Addr[3:0]
SMBus_Addr2
SMBus_Addr1
SMBus_Addr0
RESERVED
0
5
4
3:0
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Register Maps (continued)
Table 2. Shared Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
0
1
1
1
0
0
0
0
0
0
1
R
R
N
N
N
N
N
N
N
N
N
Y
Y
Version2
Version1
Version0
Device version
R
R
Device_ID4
Device_ID3
Device_ID2
Device_ID1
Device_ID0
RESERVED
REFCLK_SEL1
REFCLK_SEL0
1
R
Device ID code for
DS110DF1610
R
R
R
RW
RW
RW
Sets the REFCLK input
frequency
00: 25 MHz
01: 125 MHz
10: 312.5MHz
11: Reserved
2
3
4:0
7:0
7
0
0
0
RW
RW
N
N
N
RESERVED
RESERVED
SEL_REF_CLK_DIG_OUT_AN 1: Selects the divided clock
A
0: Selects the undivided clock
6
5
0
0
RWSC
RWSC
N
N
RST_SMB_REGS
RST_SMB_MAS
1: Resets share registers
1: Resets SMBus Master
controller
4
3
0
0
RW
RW
N
N
RESERVED
4
MR_DIS_LOCK_SEQR
1: Disables the lock sequencer
circuit
0: Normal operation, lock
sequencer is enabled
2
1
0
7
6
5
4
0
0
1
0
0
0
1
RW
RW
RW
RW
RW
RW
R
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
CRC_EN
1: Slave CRC Trigger
RESERVED
EEPROM_READ_DONE
This bit is set to 1 when read
from EEPROM is done
5
3
2
1
0
0
0
0
0
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
LIMIT_CONC_LOCKS3
LIMIT_CONC_LOCKS2
LIMIT_CONC_LOCKS1
LIMIT_CONC_LOCKS0
RESERVED
Sets max number of channels
that can lock at any given time,
defaults to 8 channels.
1
0
6
7
7:0
7:0
RESERVED
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Register Maps (continued)
Table 2. Shared Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
INT_Q1C3
INT_Q1C2
INT_Q1C1
INT_Q1C0
INT_Q0C3
INT_Q0C2
INT_Q0C1
INT_Q0C0
INT_Q3C3
INT_Q3C2
INT_Q3C1
INT_Q3C0
INT_Q2C3
INT_Q2C2
INT_Q2C1
INT_Q2C0
SEL_CLK_FROM_DIG
Interrupt from quad 1, ch 3
Interrupt from quad 1, ch 2
Interrupt from quad 1, ch 1
Interrupt from quad 1, ch 0
Interrupt from quad 0, ch 3
Interrupt from quad 0, ch 2
Interrupt from quad 0, ch 1
Interrupt from quad 0, ch 0
Interrupt from quad 3, ch 3
Interrupt from quad 3, ch 2
Interrupt from quad 3, ch 1
Interrupt from quad 3, ch 0
Interrupt from quad 2, ch 3
Interrupt from quad 2, ch 2
Interrupt from quad 2, ch 1
Interrupt from quad 2, ch 0
R
R
8
R
R
R
R
R
R
R
R
9
R
R
R
R
RW
1: selects ref clk from digital to
transmit out
0: selects ref clk from analog
loop chain to transmit out. All
channels’ analog blocks must
have ref clk loop through
enabled to transmit ref clk out of
device
6
5
0
0
RW
RW
N
N
SEL_REFCLK_TX_VCM1
SEL_REFCLK_TX_VCM0
Sets the output common-mode
voltage:
00: 800mV
01: 1000mV
10: 1200mV
11: Tracks VCC, bias at 1.2V
A
4
3
0
0
RW
RW
N
N
SEL_REFCLK_TX_VOD1
SEL_REFCLK_TX_VOD0
Sets the output differential
peak-to-peak voltage:
00: 400mV
01: 533mV
10: 667mV
11: 800mV
2
1
0
0
RW
RW
N
N
RESERVED
SEL_REFCLK_TX_SCP
1:disable
0:Ref-clk TX short-circuit
protection
0
1
RW
Y
DIS_REFCLK_OUT
1: Disable REFCLK_OUT (TRI-
STATE)
0: Enable REFCLK_OUT
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Register Maps (continued)
Table 2. Shared Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
0
RW
R
N
N
RESERVED
REFCLK_DET
This bit is set to 1 when refclk
has been detected
5
4
0
0
RW
RW
N
N
RESERVED
REFCLK_SINGLE_END
1: Reference clock input port
configured as single-ended
input
B
0: Normal operation, reference
clock input port configured as
differential input
3:0
7:3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
RESERVED
RESERVED
SAR_ADC_RST
SAR_ADC_EN
RESERVED
Resets SAR ADC
Enables SAR ADC
C
1
0
7
SAR_ADC_OUT7
SAR_ADC_OUT6
SAR_ADC_OUT5
SAR_ADC_OUT4
SAR_ADC_OUT3
SAR_ADC_OUT2
SAR_ADC_OUT1
SAR_ADC_OUT0
RESERVED
6
5
4
D
E
10-bit SAR ADC Output[7:0]
3
2
1
0
7:2
1
SAR_ADC_OUT9
SAR_ADC_OUT8
EN_CH_LOCK15
10-bit SAR ADC Output[9:8]
0
R
7
RW
1: Allows channel to lock
0: Channel not allowed to lock
6
5
4
3
2
1
0
1
1
1
1
1
1
1
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
EN_CH_LOCK14
EN_CH_LOCK13
EN_CH_LOCK12
EN_CH_LOCK11
EN_CH_LOCK10
EN_CH_LOCK9
EN_CH_LOCK8
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
F
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
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Register Maps (continued)
Table 2. Shared Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
RW
RW
RW
RW
RW
RW
RW
RW
R
EEPROM
FIELD NAME
DESCRIPTION
7
6
1
1
1
1
1
1
1
1
0
Y
Y
Y
Y
Y
Y
Y
Y
N
EN_CH_LOCK7
EN_CH_LOCK6
EN_CH_LOCK5
EN_CH_LOCK4
EN_CH_LOCK3
EN_CH_LOCK2
EN_CH_LOCK1
EN_CH_LOCK0
EEPRM_LOAD_STATUS
1: Allows channel to lock
0: Channel not allowed to lock
1: Allows channel to lock
0: Channel not allowed to lock
5
1: Allows channel to lock
0: Channel not allowed to lock
4
1: Allows channel to lock
0: Channel not allowed to lock
10
11
FC
3
1: Allows channel to lock
0: Channel not allowed to lock
2
1: Allows channel to lock
0: Channel not allowed to lock
1
1: Allows channel to lock
0: Channel not allowed to lock
0
1: Allows channel to lock
0: Channel not allowed to lock
7:6
11: Not valid
10: EEPROM load completed
successfully
01: EEPROM load failed after
64 attempts
00: EEPROM load in progress
5
4
3
2
1
0
7
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
EEPRM_ATMPT5
EEPRM_ATMPT4
EEPRM_ATMPT3
EEPRM_ATMPT2
EEPRM_ATMPT1
EEPRM_ATMPT0
Channel 7– Quad 1 Channel 3
R
Number of attempts made to
load EEPROM image
R
R
R
RW
1: Enables SMBus access
to channel 7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
Channel 6– Quad 1 Channel 2
Channel 5– Quad 1 Channel 1
Channel 4– Quad 1 Channel 0
Channel 3– Quad 0 Channel 3
Channel 2– Quad 0 Channel 2
Channel 1– Quad 0 Channel 1
Channel 0– Quad 0 Channel 0
1: Enables SMBus access
to channel 6
1: Enables SMBus access
to channel 5
1: Enables SMBus access
to channel 4
1: Enables SMBus access
to channel 3
1: Enables SMBus access
to channel 2
1: Enables SMBus access
to channel 1
1: Enables SMBus access
to channel 0
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Register Maps (continued)
Table 2. Shared Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
RW
RW
RW
RW
RW
RW
RW
RW
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
N
N
N
N
N
N
N
N
Channel 15– Quad 3 Channel 3 1: Enables SMBus access
to channel 15
Channel 14– Quad 3 Channel 2 1: Enables SMBus access
to channel 14
Channel 13– Quad 3 Channel 1 1: Enables SMBus access
to channel 13
Channel 12– Quad 3 Channel 0 1: Enables SMBus access
to channel 12
FD
Channel 11– Quad 2 Channel 3 1: Enables SMBus access
to channel 11
Channel 10– Quad 2 Channel 2 1: Enables SMBus access
to channel 10
Channel 9– Quad 2 Channel 1
1: Enables SMBus access
to channel 9
Channel 8– Quad 2 Channel 0
1: Enables SMBus access
to channel 8
7
6
0
0
0
0
0
0
1
1
0
0
R
R
N
N
N
N
N
N
N
N
N
N
VENDOR_ID7
VENDOR_ID6
VENDOR_ID5
VENDOR_ID4
VENDOR_ID3
VENDOR_ID2
VENDOR_ID1
VENDOR_ID0
RESERVED
5
R
4
R
FE
3
R
2
R
1
R
0
R
7:2
1
RW
RW
WRITE_ALL_CH
1: Write to all channels as if
they are the same, but only
allows to read back from a
single channel specified in
0xFC and 0xFD.
Note: EN_CH_SMB must be set
to 1, or else this function is
invalid.
FF
0
0
RW
N
EN_CH_SMB
1: Enables SMBus access to
the channels specified in 0xFC
and 0xFD.
0: Enables SMBus access to
the shared registers
28
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Table 3. Channel Registers, 0 to 1F
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
CLK_CORE_DIS
DESCRIPTION
7
0
RW
N
1: Disables the primary digital
clock, resets all state machines
0: Normal operation
6:4
3
0
0
RW
RW
N
N
RESERVED
RST_CORE
1: Reset core state machine
0: Normal Operation
2
1
0
0
RW
RW
N
N
RST_REGS
RST_VCO
1: Resets channel registers,
restores default values
0: Normal Operation
0
1: Resets PPM counter, EOM
counter, FLD counter, SBT counter
0: Normal Operation
0
7
0
0
RW
R
N
N
RST_REFCLK
SIG_DET
1: Reset PPM counter
0: Normal Operation
1: Signal is present on high speed
inputs
0: No signal is detected on high
speed inputs
6
5
0
0
R
R
N
N
POL_INV_DET
1: PRBS checker detected polarity
inversion 0: No pattern inversion
detected
CDR_LOCK_LOSS_INT
1: indicates loss of CDR lock after
having acquired it.
Bit clears on read.
4
3
2
1
0
0
0
0
0
0
R
R
R
R
R
N
N
N
N
N
PRBS_SEQ_DET3
PRBS_SEQ_DET2
PRBS_SEQ_DET1
PRBS_SEQ_DET0
SIG_DET_LOSS_INT
1: Indicates if the PRBS-31
sequence is locked
1
1: Indicates if the PRBS-15
sequence is locked
1: Indicates if the PRBS-9
sequence is locked
1: Indicates if the PRBS-7
sequence is locked
Loss of signal indicator.
Bit is set once signal is acquired
and then lost.
7:0
0
R
N
MULTI_PURP_STATUS
Register configured by setting
channel register 0x0C[7:4]
2
3
7
6
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
EQ_BST0[1]
EQ_BST0[0]
EQ_BST1[1]
EQ_BST1[0]
EQ_BST2[1]
EQ_BST2[0]
EQ_BST3[1]
EQ_BST3[0]
RESERVED
RESERVED
RESERVED
RESERVED
5
0
This register can be used to force
an EQ boost setting if used in
conjuntion with channel register
0x2D[3]
4
0
3
0
2
0
1
0
0
0
4
5
6
7
7:0
7:0
7:0
7:0
0x01
0x01
0x01
0x01
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Table 3. Channel Registers, 0 to 1F (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
0
1
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
CDR_CAP_DAC_RNG_P2
CDR_CAP_DAC_RNG_P1
CDR_CAP_DAC_RNG_P0
CDR_CAP_DAC_START4
CDR_CAP_DAC_START3
CDR_CAP_DAC_START2
CDR_CAP_DAC_START1
CDR_CAP_DAC_START0
DIVSEL_VCO_CAP_OV
Positive cap dac range modifier
Positive cap dac range modifier
Positive cap dac range modifier
Starting VCO Cap Dac Setting 0
Starting VCO Cap Dac Setting 0
Starting VCO Cap Dac Setting 0
Starting VCO Cap Dac Setting 0
Starting VCO Cap Dac Setting 0
8
Enable bit to override cap_cnt with
value in register 0x0B[4:0]
6
5
0
0
RW
RW
Y
Y
SET_CP_LVL_LPF_OV
BYPASS_PFD_OV
Enable bit to override lpf_dac_val
with value in register 0x1F[4:0]
Enable bit to override
sel_retimed_loopthru and
sel_raw_loopthru with values in
reg 0x1E[7:5]
4
0
RW
Y
EN_FD_PD_VCO_PDIQ_OV
Enable bit to override en_fd,
pd_pd, pd_vco, pd_pdiq with reg
0x1E[0], reg 0x1E[2], reg 0x1C[0],
reg 0x1C[1]
9
3
2
0
0
RW
RW
Y
Y
EN_PD_CP_OV
DIVSEL_OV
Enable bit to override pd_fd_cp
and pd_pd_cp with value in reg
0x1B[1:0]
Enable bit to override divsel with
value in reg 0x18[6:4]
1: Override enable
0: Normal operation
1
0
7
6
0
0
0
1
RW
RW
RW
RW
Y
Y
Y
Y
EN_FLD_OV
Enable to override pd_fld with
value in reg 0x1E[1]
PFD_LOCK_
MODE_SM
Enable fd in lock state
SBT_EN
Enable bit to override sbt_en with
value in reg 0x1D[7]
EN_IDAC_PD_CP_OV
EN_IDAC_FD_CP_OV
Enable bit to overridephase
detector charge pump settings with
reg 0x1C[7:5]
Enable bit to override frequency
detector charge pump settings with
reg 0x1C[4:2]
5
0
RW
Y
DAC_LPF_HIGH_
PHASE_OV
DAC_LPF_LOW_
PHASE_OV
Enable bit to override loop filter
comparator trip voltage with reg
0x16[7:0]
A
4
3
2
1
0
1
0
0
0
0
RW
RW
RW
RW
RW
Y
N
N
N
N
EN150_LPF_OV
CDR_RESET_OV
CDR_RESET_SM
CDR_LOCK_OV
CDR_LOCK
Enable bit to override en150_lpf
with value in reg 0x1F[6]
Enable bit to override CDR reset
with reg 0x0A[2]
1: CDR is put into reset
0: normal CDR operation
Enable CDR lock signal override
with reg 0x0A[0]
CDR lock signal override bit
30
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Table 3. Channel Registers, 0 to 1F (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
1
1
0
1
1
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
CDR_CAP_DAC_RNG_N2
CDR_CAP_DAC_RNG_N1
CDR_CAP_DAC_RNG_N0
CAP_DAC_START1[4]
CAP_DAC_START1[3]
CAP_DAC_START1[2]
CAP_DAC_START1[1]
CAP_DAC_START1[0]
STATUS_CONTROL
Negative cap dac range modifier
Negative cap dac range modifier
Negative cap dac range modifier
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
Starting VCO cap dac setting 1
5
4
B
C
D
3
2
1
0
7:4
These bits repurpose channel
register 0x02 to report different
status signals
3
1
RW
Y
SINGLE_BIT_LIMIT_CHECK_ON
1: Normal operation, device
checks for single bit transitions as
a gate to achieving CDR lock
2
1
0
0
RW
RW
N
Y
RESERVED
EN_IDAC_FD_CP3
Frequency detector charge pump
setting bit 3 (MSB)
LSB located in channel register
0x1C
0
0
RW
Y
EN_IDAC_PD_CP3
DES_PD
Phase detector charge pump
setting bit 3 (MSB)
LSB located in channel register
0x1C
7
1
RW
N
1: Deserializer is powered down
0: Deserializer is enabled
6
5
4
0
1
1
RW
RW
RW
N
Y
Y
RESERVED
DRV_SEL_VOD4
DRV_SEL_VOD3
Used in conjunction with 0x2D[2:0]
to control the VOD levels of the
high speed drivers
3
0
1
RW
RW
RW
RW
RW
RW
Y
Y
N
N
N
Y
FIR_RLOAD_MAX
FIR_SEL_NEG_GM
RESERVED
2
1:0
7:0
7:0
7:0
0
E
0x93
0x69
0x3A
RESERVED
F
RESERVED
10
RESERVED
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Table 3. Channel Registers, 0 to 1F (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
0
RW
RW
Y
Y
EOM_SEL_VRANGE1
EOM_SEL_VRANGE1
Manually set the EOM vertical
range, used with channel register
0x2C[6]
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
5
4
3
1
0
0
RW
RW
RW
Y
N
Y
EOM_PD
1: Normal operation
RESERVED
DFE_TAP2_POL
Bit forces DFE tap 2 polarity,
manual DFE operation required to
take effect
11
2
1
0
7
0
0
0
1
RW
RW
RW
RW
Y
Y
Y
Y
DFE_TAP3_POL
DFE_TAP4_POL
DFE_TAP5_POL
DFE_TAP1_POL
Bit forces DFE tap 3 polarity,
manual DFE operation required to
take effect
Bit forces DFE tap 4 polarity,
manual DFE operation required to
take effect
Bit forces DFE tap 5 polarity,
manual DFE operation required to
take effect
Bit forces DFE tap 1 polarity,
manual DFE operation required to
take effect
6
5
4
3
2
1
0
7
6
5
4
3
2
1
1
0
0
0
0
0
1
0
0
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
Y
SD_SEL_MUTEZ
DFE_SEL_NEG_GM
DFE_WT1[4]
12
DFE_WT1[3]
Bits force DFE tap 1 weight,
manual DFE operation required to
take effect
DFE_WT1[2]
DFE_WT1[1]
DFE_WT1[0]
EQ_PD_PEAKDET
EQ_PD_SD
RESERVED
EQ_EN_DC_OFF
EQ_PD_EQ
1: Normal operation
13
EQ_LIMIT_EN
1: Configures the final stage of the
equalizer to be a limiting stage.
0: Normal operation, final stage of
the equalizer is configured to be a
linear stage.
1
0
0
0
RW
RW
N
N
EQ_PD_CM
RESERVED
32
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Table 3. Channel Registers, 0 to 1F (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
EQ_SD_PRESET
DESCRIPTION
7
0
RW
Y
1: Forces signal detect HIGH, and
force enables the channel. Should
not be set if bit 6 is set.
0: Normal Operation.
6
0
RW
Y
EQ_SD_RESET
1: Forces signal detect LOW and
force disables the channel. Should
not be set if bit 7 is set.
14
0: Normal Operation.
5
4
0
0
0
0
0
0
0
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
N
Y
N
Y
Y
N
EQ_REFA_SEL1
EQ_REFA_SEL0
EQ_REFD_SEL1
EQ_REFD_SEL0
RESERVED
Controls the signal detect assert
levels.
3
Controls the signal detect de-
assert levels.
2
1:0
7
DFE_FORCE_EN
RESERVED
6
5
COMP_EN_HYST
COMP_EN
4
3
DRV_PD
1: Powers down the high speed
driver
0: Normal operation
15
2
1
0
0
1
0
RW
RW
RW
Y
Y
Y
Reserved
DRV_DEM1
DRV_DEM0
Degenerates the pre-driver
degeneration
00: 0 dB
01: 1 dB
10: 2 dB
11: 3 dB
16
17
7:0
7:0
7
0x7A
RW
RW
RW
RW
RW
RW
Y
Y
N
Y
Y
Y
RESERVED
0x25
RESERVED
0
1
0
0
RESERVED
6
PDIQ_SEL_DIV2
PDIQ_SEL_DIV1
PDIQ_SEL_DIV0
These bits will force the divider
setting if 0x09[2] is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
5
4
18
3
2
0
0
RW
RW
N
N
RESERVED
DRV_PD_R_EN
1: Enables the shut down
termination resistor to be present
when the driver is powered down
with channel register 0x15[3]
0: Normal operation, resistor is
disconnected from output for
propper driver operation
1:0
7:6
5:0
0
RW
RW
RW
N
N
Y
RESERVED
RESERVED
RESERVED
0x20
19
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Table 3. Channel Registers, 0 to 1F (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7:4
3
0xA
0
RW
RW
RW
Y
Y
Y
RESERVED
DRV_SEL_VCM1
DRV_SEL_VCM0
Controls driver output common
mode voltage.
This feature is reserved for future
use.
2
0
1A
1:0
7:2
1
0
0
1
1
1
0
0
RW
RW
RW
RW
RW
RW
RW
N
N
Y
Y
Y
Y
Y
RESERVED
RESERVED
1B
CP_EN_CP_PD
CP_EN_CP_FD
EN_IDAC_PD_CP2
EN_IDAC_PD_CP1
EN_IDAC_PD_CP0
1: Normal operation
1: Normal operation
0
7
Phase detector charge pump
setting
MSB located in channel register
0x0C[0]
6
5
Override bit required for these bits
to take effect
1C
4
3
2
1
0
0
RW
RW
RW
Y
Y
Y
EN_IDAC_FD_CP2
EN_IDAC_FD_CP1
EN_IDAC_FD_CP0
Frequency detector charge pump
setting
MSB located in channel register
0x0C[1]
Override bit required for these bits
to take effect
1:0
7
0
0
RW
RW
N
Y
RESERVED
SBT_EN
SBT enable override
0: Normal operation
1D
6:0
7
0
1
1
1
RW
RW
RW
RW
N
Y
Y
Y
RESERVED
PFD_SEL_DATA_MUX2
PFD_SEL_DATA_MUX1
PFD_SEL_DATA_MUX0
For these values to take effect,
register 0x09[5] must be set to 1.
000: Raw Data*
6
5
001: Retimed Data
100: Pattern Generator
111: Mute
All other values are reserved.
*Note in this mode the FIR filter
will not function. Data is routed
only through the pre cursor tap.
See Functional Description section
for more information.
4
3
0
1
RW
RW
N
Y
SER_EN
DFE_PD
1: Enables the serializer for pattern
generation
0: Disables the serializer
1E
This bit must be cleared for the
DFE to be functional in any adapt
mode.
0: DFE enabled
1: DFE disabled
2
0
RW
Y
PFD_PD_PD
PFD phasee detector power down
override
1
0
0
1
RW
RW
Y
Y
PFD_EN_FLD
PFD_EN_FD
PFD enable FLD override
PFD enable frequency detector
override
1F
7:0
0x55
RW
Y
RESERVED
34
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Table 4. Channel Registers, 20 to 39
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
DFE_WT5[3]
DFE_WT5[2]
DFE_WT5[1]
DFE_WT5[0]
DFE_WT4[3]
DFE_WT4[2]
DFE_WT4[1]
DFE_WT4[0]
DFE_WT3[3]
DFE_WT3[2]
DFE_WT3[1]
DFE_WT3[0]
DFE_WT2[3]
DFE_WT2[2]
DFE_WT2[1]
DFE_WT2[0]
EOM_OV
Bits force DFE tap 5 weight,
manual DFE operation
required to take effect
20
Bits force DFE tap 4 weight,
manual DFE operation
required to take effect
Bits force DFE tap 3 weight,
manual DFE operation
required to take effect
21
Bits force DFE tap 2 weight,
manual DFE operation
required to take effect
1: Override enable for EOM
manual control
0: Normal operation
22
6
0
RW
N
EOM_SEL_RATE_OV
1: Override enable for EOM
rate selection
0: Normal operation
5:0
7
0
0
RW
RW
N
N
RESERVED
EOM_GET_HEO_VEO_OV
1: Override enable for
manual control of the
HEO/VEO trigger
0: Normal operation
23
6
1
0
RW
RW
Y
N
DFE_OV
1: Normal operation, DFE
must be enabled in channel
register 0x1E[3]
5:0
RESERVED
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
FAST_EOM
DESCRIPTION
7
0
RW
N
1: Enables fast EOM mode
for fully eye capture. In this
mode the phase DAC and
voltage DAC of the EOM are
automatically incremented
through a 64 x 64 matrix.
Values for each point are
stored in channel registers
25 and 26.
6
5
4
0
0
0
RW
RW
RW
N
N
N
DFE_EQ_ERROR_NO_LOCK
DFE/CTLE SM quit due to
loss of lock
GET_HEO_VEO_ERROR_
NO_HITS
GET_HEO_VEO sees no
hits at zero crossing
24
GET_HEO_VEO_ERROR_
NO_OPENING
GET_HEO_VEO cannot see
a vertical eye opening
3
2
0
0
RW
N
N
RESERVED
DFE_ADAPT
RWSC
1: Manually start DFE
adaption, self clearing.
0: Normal operation
1
0
RW
N
EOM_GET_HEO_VEO
1: Manually triggers a
HEO/VEO measurement.
Must be enabled with
channel register 0x23[7].
0
0
RWSC
N
EOM_START
1: Starts EOM counter, self
clearing
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EOM_COUNT15
EOM_COUNT14
EOM_COUNT13
EOM_COUNT12
EOM_COUNT11
EOM_COUNT10
EOM_COUNT9
EOM_COUNT8
EOM_COUNT7
EOM_COUNT6
EOM_COUNT5
EOM_COUNT4
EOM_COUNT3
EOM_COUNT2
EOM_COUNT1
EOM_COUNT0
HEO7
25
26
27
MSBs of EOM counter
LSBs of EOM counter
HEO6
HEO5
HEO value, requires CDR to
be locked for valid
measurement
HEO4
HEO3
HEO2
HEO1
HEO0
36
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
0
0
0
0
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
N
N
N
VEO7
VEO6
R
VEO5
VEO value, requires CDR to
be locked for valid
measurement
R
VEO4
28
R
VEO3
R
VEO2
R
VEO1
R
VEO0
RW
R
RESERVED
EOM_VRANGE_SETTING1
EOM_VRANGE_SETTING0
Use these bits to read back
the EOM voltage range
setting
R
00: ±100 mV
29
01: ±200 mV
10: ±300 mV
11: ±400 mV
4:0
7
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
RESERVED
EOM_TIMER_THR7
EOM_TIMER_THR6
EOM_TIMER_THR5
EOM_TIMER_THR4
EOM_TIMER_THR3
EOM_TIMER_THR2
EOM_TIMER_THR1
EOM_TIMER_THR0
RESERVED
Controls the amount of time
the EOM samples each point
in the eye for. The total
6
5
counter bit width is 16-bits,
this register is the upper 8-
bits. The counter counts in
32-bit words, therefore, the
total number of bits counted
is 32 times this value.
4
2A
3
2
1
0
7:6
5:4
3
RESERVED
EOM_MIN_REQ_HITS3
EOM_MIN_REQ_HITS2
EOM_MIN_REQ_HITS1
EOM_MIN_REQ_HITS0
These bits set the number of
hits for a particular phase
and voltage location in the
EOM before the EOM will
indicate a hit has occured.
This filtering only affects the
HEO measurement.
2
2B
1
0
7
6
1
1
RW
RW
N
Y
RELOAD_DFE_TAPS
VEO_SCALE
1: Reload DFE taps from last
adapted value
1: Scale VEO based on EOM
vertical range
0: Manual control of vertical
range
5
4
1
1
RW
RW
Y
Y
DFE_SM_FOM1
DFE_SM_FOM0
00: not valid
01: SM uses only HEO
10: SM uses only VEO
11: SM uses both HEO and
VEO
2C
3
2
0
0
RW
RW
Y
Y
DFE_ADAPT_COUNTER3
DFE_ADAPT_COUNTER2
Counter for incrementing
taps when FoM decreases in
EQ adaption
1
0
1
0
RW
RW
Y
Y
DFE_ADAPT_COUNTER1
DFE_ADAPT_COUNTER0
Counter for incrementing
taps when FoM decreases in
DFE adaption
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
0
RW
Y
PD_SCP
1: Power down the short
circuit protection for the high
speed driver outputs
0: Normal operation, short
circuit protection is enabled
for the high speed driver
outputs
6
5
4
3
0
0
0
0
RW
RW
RW
RW
Y
Y
Y
Y
SD_EN_FAST_OOB
SD_REF_HIGH
SD_GAIN
Feature is reserved for future
use.
Feature is reserved for future
use.
2D
Feature is reserved for future
use.
EQ_BST_OV
Allow override control of the
EQ setting by writing to
channel register 0x03. Not
recommended for normal
operation.
2
1
1
1
1
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
N
Y
Y
Y
Y
DRV_SEL_VOD2
DRV_SEL_VOD1
DRV_SEL_VOD0
RESERVED
RATE1
Used in conjunction with
0x0D[5:4] to control the VOD
levels of the high speed
drivers
0
2E
7:0
7
4 bits determine standard.
0xF0: 8.625Gbps/4.3125
Gbps
0xE0: 9.95328Gbps
0xD0: 10.51875Gbps,
8.5Gbps, 4.25Gbps,
2.125Gbps
6
RATE0
5
SUBRATE1
SUBRATE0
4
0xC0: 10.3125Gbps,
1.25Gbps
0x00: 5Gbps, 2.5Gbps
3
0
RW
Y
INDEX_OV
If this bit is set to 1, reg 0x13
is to be used as a 5 bit index
to the [31:0] array of EQ
settings.
2F
2
1
0
1
1
0
RW
RW
Y
Y
N
EN_PPM_CHECK
EN_FLD_CHECK
CTLE_ADAPT
1: PPM check to be used as
a qualifier when performing
lock detect
1: False lock detector is used
as a qualifier when
performing lock detect
RWSC
Starts CTLE adaption, self
clearing
38
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
FREEZE_PPM_CNT
DESCRIPTION
7
0
0
0
RW
N
1: Freeze PPM counter to
allow safe read
asynchronously
6
5
RW
RW
Y
N
EQ_SEARCH_OV_EN
EN_PATT_INV
Enables the EQ search bit to
be force by channel register
0x13[2]
1: Enables automatic pattern
inversion of successive 16-
bit words when using the
user defined pattern
generator option.
4
3
0
0
RW
RW
N
N
RELOAD_PRBS_CHKR
PRBS_EN_DIG_CLK
Feature is reserved for future
use.
This bit enables the clock to
operate the PRBS generator
and/or the PRBS checker.
Toggling this bit is the
30
primary method to reset the
PRBS pattern generator and
PRBS checker.
2
0
RW
N
PRBS_PROGPATT_EN
1: Enable a fixed user
defined pattern. Requires
that the pattern generator be
configured properly to be
enabled
1
0
0
0
RW
RW
N
N
PRBS_PATTERN_SEL1
PRBS_PATTERN_SEL0
Selects the PRBS generator
pattern to output. Requires
that the pattern generator be
configured properly.
00: PRBS-7
01: PRBS-9
10: PRBS-15
11: PRBS-31
7
0
RW
N
PRBS_INT_EN
1: Enables interrupt for
detection of PRBS errors.
The PRBS checker must be
properly configured for this
feature to work
6
5
0
0
RW
RW
Y
N
ADAPT_MODE1
ADAPT_MODE0
00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal,
then DFE, then CTLE again
11: adapt CTLE until lock,
then DFE, then EQ until
optimal
31
4
3
0
0
RW
RW
N
N
EQ_SM_FOM1
EQ_SM_FOM0
Sets the desired FoM for EQ
adaption
00: not valid
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and
VEO
2
1
0
0
RW
RW
N
N
RESERVED
CDR_LOCK_LOSS_INT_EN
1: enables loss of CDR lock
interrupt
0
0
RW
N
SIG_DET_LOSS_INT_EN
1: enable loss of signal
detect interrupt
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
HEO_INT_THRESH3
HEO_INT_THRESH2
HEO_INT_THRESH1
HEO_INT_THRESH0
VEO_INT_THRESH3
VEO_INT_THRESH2
VEO_INT_THRESH1
VEO_INT_THRESH0
HEO_THRESH3
These bits set the threshold
for the HEO and VEO
interrupt. Each threshold bit
represents 8 counts of HEO
or VEO.
32
HEO_THRESH2
In adapt modes where the
EQ adapts until lock and
then adapts the DFE, this
register sets the minimum
HEO and VEO required
before starting DFE
HEO_THRESH1
HEO_THRESH0
33
VEO_THRESH3
VEO_THRESH2
adaption. This can be a max
of 15
VEO_THRESH1
VEO_THRESH0
PPM_ERR_RDY
1: Indicates that a PPM error
count is read to be read from
channel register 0x3B and
0x3C
6
0
RW
Y
LOW_POWER_MODE_DISABLE
By default, all blocks (except
signal detect) power down
after 100ms after signal
detect goes low.
5
4
1
1
RW
RW
Y
Y
LOCK_COUNTER1
LOCK_COUNTER0
Afteer achieving lock, the
CDR continues to monitor
the lock criteria.If the lock
criteria fail, the lock is
checked for a total of N
number of times before
declaring an out of lock
condition, where N is set by
this the value in these
registers, with a max value
of +3, for a total of 4. If
during the N lock checks,
lock is regained, then the
lock condition is left HI, and
the counter is reset back to
zero.
34
3
2
1
0
1
1
1
1
RW
RW
RW
RW
Y
Y
Y
Y
DFE_MAX_TAP2_5[3]
DFE_MAX_TAP2_5[2]
DFE_MAX_TAP2_5[1]
DFE_MAX_TAP2_5[0]
These 4 bits are used to set
the maximum value by which
DFE taps 2-5 are able to
adapt with each subsequent
adaptation. Same used for
both polarities.
40
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
0
RW
RW
Y
Y
DATA_LOCK_PPM1
DATA_LOCK_PPM0
Modifies the value of the
ppm delta tolerance from
channel register 0x64
00 - ppm_delta[7:0] =1 x
ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x
ppm_delta[7:0] +
ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x
ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x
ppm_delta[7:0] +
ppm_delta[3:1]
35
5
0
RW
N
GET_PPM_ERROR
Get ppm error from
ppm_count - clears when
done. Normally updates
continuously, but can be
manually triggered with read
value from channel register
0x3B and 0x3C
4
3
2
1
0
7
1
1
1
1
1
0
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
N
DFE_MAX_TAP1[4]
DFE_MAX_TAP1[3]
DFE_MAX_TAP1[2]
DFE_MAX_TAP1[1]
DFE_MAX_TAP1[0]
UNCORR_ERR_INT_EN
Determins max tap limit for
DFE tap 1
Feature is reserved for future
use.
6
0
RW
N
HEO_VEO_INT_EN
1: Enable HEO/VEO interrupt
capability
5
4
1
1
RW
RW
Y
Y
REF_MODE1
REF_MODE0
11: Fast_lock all cap dac ref
clock enabled
(recommended)
10: Reserved
01: Reserved
00: referenceless all cap dac,
for debug use only
36
3
0
RW
Y
EN_6466B_LOCK_GATE
1: Enables check for 64b66b
encoding as a gate to lock
0: Normal operation
2
1
0
0
0
0
RW
RW
RW
Y
N
N
CDR_CAP_DAC_RNG_OV
EN_6466B_RESTART
K28P5_6466_INT_EN
Override enable for cap dac
range
Feature is reserved for future
use.
Feature is reserved for future
use.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
CTLE_STATUS7
CTLE_STATUS6
CTLE_STATUS5
CTLE_STATUS4
CTLE_STATUS3
CTLE_STATUS2
CTLE_STATUS1
CTLE_STATUS0
Feature is reserved for future
use.
37
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Table 4. Channel Registers, 20 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
N
DFE_STATUS7
DFE_STATUS6
DFE_STATUS5
DFE_STATUS4
DFE_STATUS3
DFE_STATUS2
DFE_STATUS1
DFE_STATUS0
R
R
Feature is reserved for future
use.
38
R
R
R
R
RW
PRELOCK_COMPARATOR_
ABRT_MODE
Feature is reserved for future
use.
6
5
0
0
RW
RW
Y
Y
EOM_RATE1
EOM_RATE0
With eom_ov=1, these bits
control the Eye Monitor Rate.
11 - Use for Full Rate,
Fastest
10 - Use for 1/2 Rate
01 - Use for 1/4 Rate
00 - Use for 1/8 Rate,
Slowest
39
4
3
2
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
START_INDEX4
START_INDEX3
START_INDEX2
START_INDEX1
START_INDEX0
Start index for EQ adaptation
Table 5. Channel Registers, 3A to 59
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
R
Y
Y
Y
Y
Y
Y
Y
FIXED_EQ_BST0[1]
FIXED_EQ_BST0[0]
FIXED_EQ_BST1[1]
FIXED_EQ_BST1[0]
FIXED_EQ_BST2[1]
FIXED_EQ_BST2[0]
FIXED_EQ_BST3[1]
FIXED_EQ_BST3[0]
PPM_COUNT15
PPM_COUNT14
PPM_COUNT13
PPM_COUNT12
PPM_COUNT11
PPM_COUNT10
PPM_COUNT9
During adaptation, if the
divider setting is >2, then a
fixed EQ setting, from this
register will be used. However,
if channel register 0x6F[7] is
enabled, then an EQ
3A
adaptation will be performed
instead.
N
N
N
N
N
N
N
N
R
R
R
3B
PPM count MSB
R
R
R
R
PPM_COUNT8
42
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Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
Y
PPM_COUNT7
PPM_COUNT6
PPM_COUNT5
PPM_COUNT4
PPM_COUNT3
PPM_COUNT2
PPM_COUNT1
PPM_COUNT0
FIR_PD_pd
R
R
3C
PPM count LSB
R
R
R
R
RW
FIR_C0_SGN
FIR main cursor polarity
1: negative
6
0
RW
Y
0: positive
5
4
3
2
1
0
7
1
1
0
1
1
0
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
FIR_C0[5]
FIR_C0[4]
FIR_C0[3]
FIR_C0[2]
FIR_C0[1]
FIR_C0[0]
FIR_PD_TX
FIR_CN1_SGN
3D
FIR main cursor setting
FIR pre cursor polarity
1: negative
6
1
RW
Y
0: positive
5
4
3
2
1
0
7
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
FIR_CN1[5]
FIR_CN1[4]
FIR_CN1[3]
FIR_CN1[2]
FIR_CN1[1]
FIR_CN1[0]
FIR_SEL_I_MAX
FIR_CP1_SGN
3E
FIR pre cursor setting
FIR post cursor polarity
1: negative
6
1
RW
Y
0: positive
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FIR_CP1[5]
3F
FIR_CP1[4]
FIR_CP1[3]
FIR post cursor setting
FIR_CP1[2]
FIR_CP1[1]
FIR_CP1[0]
EQ_ARRAY_INDEX_0_BST0[1]
EQ_ARRAY_INDEX_0_BST0[0]
EQ_ARRAY_INDEX_0_BST1[1]
EQ_ARRAY_INDEX_0_BST1[0]
EQ_ARRAY_INDEX_0_BST2[1]
EQ_ARRAY_INDEX_0_BST2[0]
EQ_ARRAY_INDEX_0_BST3[1]
EQ_ARRAY_INDEX_0_BST3[0]
40
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Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_1_BST0[1]
EQ_ARRAY_INDEX_1_BST0[0]
EQ_ARRAY_INDEX_1_BST1[1]
EQ_ARRAY_INDEX_1_BST1[0]
EQ_ARRAY_INDEX_1_BST2[1]
EQ_ARRAY_INDEX_1_BST2[0]
EQ_ARRAY_INDEX_1_BST3[1]
EQ_ARRAY_INDEX_1_BST3[0]
EQ_ARRAY_INDEX_2_BST0[1]
EQ_ARRAY_INDEX_2_BST0[0]
EQ_ARRAY_INDEX_2_BST1[1]
EQ_ARRAY_INDEX_2_BST1[0]
EQ_ARRAY_INDEX_2_BST2[1]
EQ_ARRAY_INDEX_2_BST2[0]
EQ_ARRAY_INDEX_2_BST3[1]
EQ_ARRAY_INDEX_2_BST3[0]
EQ_ARRAY_INDEX_3_BST0[1]
EQ_ARRAY_INDEX_3_BST0[0]
EQ_ARRAY_INDEX_3_BST1[1]
EQ_ARRAY_INDEX_3_BST1[0]
EQ_ARRAY_INDEX_3_BST2[1]
EQ_ARRAY_INDEX_3_BST2[0]
EQ_ARRAY_INDEX_3_BST3[1]
EQ_ARRAY_INDEX_3_BST3[0]
EQ_ARRAY_INDEX_4_BST0[1]
EQ_ARRAY_INDEX_4_BST0[0]
EQ_ARRAY_INDEX_4_BST1[1]
EQ_ARRAY_INDEX_4_BST1[0]
EQ_ARRAY_INDEX_4_BST2[1]
EQ_ARRAY_INDEX_4_BST2[0]
EQ_ARRAY_INDEX_4_BST3[1]
EQ_ARRAY_INDEX_4_BST3[0]
EQ_ARRAY_INDEX_5_BST0[1]
EQ_ARRAY_INDEX_5_BST0[0]
EQ_ARRAY_INDEX_5_BST1[1]
EQ_ARRAY_INDEX_5_BST1[0]
EQ_ARRAY_INDEX_5_BST2[1]
EQ_ARRAY_INDEX_5_BST2[0]
EQ_ARRAY_INDEX_5_BST3[1]
EQ_ARRAY_INDEX_5_BST3[0]
41
42
43
44
45
44
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Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_6_BST0[1]
EQ_ARRAY_INDEX_6_BST0[0]
EQ_ARRAY_INDEX_6_BST1[1]
EQ_ARRAY_INDEX_6_BST1[0]
EQ_ARRAY_INDEX_6_BST2[1]
EQ_ARRAY_INDEX_6_BST2[0]
EQ_ARRAY_INDEX_6_BST3[1]
EQ_ARRAY_INDEX_6_BST3[0]
EQ_ARRAY_INDEX_7_BST0[1]
EQ_ARRAY_INDEX_7_BST0[0]
EQ_ARRAY_INDEX_7_BST1[1]
EQ_ARRAY_INDEX_7_BST1[0]
EQ_ARRAY_INDEX_7_BST2[1]
EQ_ARRAY_INDEX_7_BST2[0]
EQ_ARRAY_INDEX_7_BST3[1]
EQ_ARRAY_INDEX_7_BST3[0]
EQ_ARRAY_INDEX_8_BST0[1]
EQ_ARRAY_INDEX_8_BST0[0]
EQ_ARRAY_INDEX_8_BST1[1]
EQ_ARRAY_INDEX_8_BST1[0]
EQ_ARRAY_INDEX_8_BST2[1]
EQ_ARRAY_INDEX_8_BST2[0]
EQ_ARRAY_INDEX_8_BST3[1]
EQ_ARRAY_INDEX_8_BST3[0]
EQ_ARRAY_INDEX_9_BST0[1]
EQ_ARRAY_INDEX_9_BST0[0]
EQ_ARRAY_INDEX_9_BST1[1]
EQ_ARRAY_INDEX_9_BST1[0]
EQ_ARRAY_INDEX_9_BST2[1]
EQ_ARRAY_INDEX_9_BST2[0]
EQ_ARRAY_INDEX_9_BST3[1]
EQ_ARRAY_INDEX_9_BST3[0]
EQ_ARRAY_INDEX_10_BST0[1]
EQ_ARRAY_INDEX_10_BST0[0]
EQ_ARRAY_INDEX_10_BST1[1]
EQ_ARRAY_INDEX_10_BST1[0]
EQ_ARRAY_INDEX_10_BST2[1]
EQ_ARRAY_INDEX_10_BST2[0]
EQ_ARRAY_INDEX_10_BST3[1]
EQ_ARRAY_INDEX_10_BST3[0]
46
47
48
49
4A
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Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_11_BST0[1]
EQ_ARRAY_INDEX_11_BST0[0]
EQ_ARRAY_INDEX_11_BST1[1]
EQ_ARRAY_INDEX_11_BST1[0]
EQ_ARRAY_INDEX_11_BST2[1]
EQ_ARRAY_INDEX_11_BST2[0]
EQ_ARRAY_INDEX_11_BST3[1]
EQ_ARRAY_INDEX_11_BST3[0]
EQ_ARRAY_INDEX_12_BST0[1]
EQ_ARRAY_INDEX_12_BST0[0]
EQ_ARRAY_INDEX_12_BST1[1]
EQ_ARRAY_INDEX_12_BST1[0]
EQ_ARRAY_INDEX_12_BST2[1]
EQ_ARRAY_INDEX_12_BST2[0]
EQ_ARRAY_INDEX_12_BST3[1]
EQ_ARRAY_INDEX_12_BST3[0]
EQ_ARRAY_INDEX_13_BST0[1]
EQ_ARRAY_INDEX_13_BST0[0]
EQ_ARRAY_INDEX_13_BST1[1]
EQ_ARRAY_INDEX_13_BST1[0]
EQ_ARRAY_INDEX_13_BST2[1]
EQ_ARRAY_INDEX_13_BST2[0]
EQ_ARRAY_INDEX_13_BST3[1]
EQ_ARRAY_INDEX_13_BST3[0]
EQ_ARRAY_INDEX_14_BST0[1]
EQ_ARRAY_INDEX_14_BST0[0]
EQ_ARRAY_INDEX_14_BST1[1]
EQ_ARRAY_INDEX_14_BST1[0]
EQ_ARRAY_INDEX_14_BST2[1]
EQ_ARRAY_INDEX_14_BST2[0]
EQ_ARRAY_INDEX_14_BST3[1]
EQ_ARRAY_INDEX_14_BST3[0]
EQ_ARRAY_INDEX_15_BST0[1]
EQ_ARRAY_INDEX_15_BST0[0]
EQ_ARRAY_INDEX_15_BST1[1]
EQ_ARRAY_INDEX_15_BST1[0]
EQ_ARRAY_INDEX_15_BST2[1]
EQ_ARRAY_INDEX_15_BST2[0]
EQ_ARRAY_INDEX_15_BST3[1]
EQ_ARRAY_INDEX_15_BST3[0]
4B
4C
4D
4E
4F
46
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_16_BST0[1]
EQ_ARRAY_INDEX_16_BST0[0]
EQ_ARRAY_INDEX_16_BST1[1]
EQ_ARRAY_INDEX_16_BST1[0]
EQ_ARRAY_INDEX_16_BST2[1]
EQ_ARRAY_INDEX_16_BST2[0]
EQ_ARRAY_INDEX_16_BST3[1]
EQ_ARRAY_INDEX_16_BST3[0]
EQ_ARRAY_INDEX_17_BST0[1]
EQ_ARRAY_INDEX_17_BST0[0]
EQ_ARRAY_INDEX_17_BST1[1]
EQ_ARRAY_INDEX_17_BST1[0]
EQ_ARRAY_INDEX_17_BST2[1]
EQ_ARRAY_INDEX_17_BST2[0]
EQ_ARRAY_INDEX_17_BST3[1]
EQ_ARRAY_INDEX_17_BST3[0]
EQ_ARRAY_INDEX_18_BST0[1]
EQ_ARRAY_INDEX_18_BST0[0]
EQ_ARRAY_INDEX_18_BST1[1]
EQ_ARRAY_INDEX_18_BST1[0]
EQ_ARRAY_INDEX_18_BST2[1]
EQ_ARRAY_INDEX_18_BST2[0]
EQ_ARRAY_INDEX_18_BST3[1]
EQ_ARRAY_INDEX_18_BST3[0]
EQ_ARRAY_INDEX_19_BST0[1]
EQ_ARRAY_INDEX_19_BST0[0]
EQ_ARRAY_INDEX_19_BST1[1]
EQ_ARRAY_INDEX_19_BST1[0]
EQ_ARRAY_INDEX_19_BST2[1]
EQ_ARRAY_INDEX_19_BST2[0]
EQ_ARRAY_INDEX_19_BST3[1]
EQ_ARRAY_INDEX_19_BST3[0]
EQ_ARRAY_INDEX_20_BST0[1]
EQ_ARRAY_INDEX_20_BST0[0]
EQ_ARRAY_INDEX_20_BST1[1]
EQ_ARRAY_INDEX_20_BST1[0]
EQ_ARRAY_INDEX_20_BST2[1]
EQ_ARRAY_INDEX_20_BST2[0]
EQ_ARRAY_INDEX_20_BST3[1]
EQ_ARRAY_INDEX_20_BST3[0]
50
51
52
53
54
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Table 5. Channel Registers, 3A to 59 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_21_BST0[1]
EQ_ARRAY_INDEX_21_BST0[0]
EQ_ARRAY_INDEX_21_BST1[1]
EQ_ARRAY_INDEX_21_BST1[0]
EQ_ARRAY_INDEX_21_BST2[1]
EQ_ARRAY_INDEX_21_BST2[0]
EQ_ARRAY_INDEX_21_BST3[1]
EQ_ARRAY_INDEX_21_BST3[0]
EQ_ARRAY_INDEX_22_BST0[1]
EQ_ARRAY_INDEX_22_BST0[0]
EQ_ARRAY_INDEX_22_BST1[1]
EQ_ARRAY_INDEX_22_BST1[0]
EQ_ARRAY_INDEX_22_BST2[1]
EQ_ARRAY_INDEX_22_BST2[0]
EQ_ARRAY_INDEX_22_BST3[1]
EQ_ARRAY_INDEX_22_BST3[0]
EQ_ARRAY_INDEX_23_BST0[1]
EQ_ARRAY_INDEX_23_BST0[0]
EQ_ARRAY_INDEX_23_BST1[1]
EQ_ARRAY_INDEX_23_BST1[0]
EQ_ARRAY_INDEX_23_BST2[1]
EQ_ARRAY_INDEX_23_BST2[0]
EQ_ARRAY_INDEX_23_BST3[1]
EQ_ARRAY_INDEX_23_BST3[0]
EQ_ARRAY_INDEX_24_BST0[1]
EQ_ARRAY_INDEX_24_BST0[0]
EQ_ARRAY_INDEX_24_BST1[1]
EQ_ARRAY_INDEX_24_BST1[0]
EQ_ARRAY_INDEX_24_BST2[1]
EQ_ARRAY_INDEX_24_BST2[0]
EQ_ARRAY_INDEX_24_BST3[1]
EQ_ARRAY_INDEX_24_BST3[0]
EQ_ARRAY_INDEX_25_BST0[1]
EQ_ARRAY_INDEX_25_BST0[0]
EQ_ARRAY_INDEX_25_BST1[1]
EQ_ARRAY_INDEX_25_BST1[0]
EQ_ARRAY_INDEX_25_BST2[1]
EQ_ARRAY_INDEX_25_BST2[0]
EQ_ARRAY_INDEX_25_BST3[1]
EQ_ARRAY_INDEX_25_BST3[0]
55
56
57
58
59
48
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Table 6. Channel Registers, 5A to 9B
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_26_BST0[1]
EQ_ARRAY_INDEX_26_BST0[0]
EQ_ARRAY_INDEX_26_BST1[1]
EQ_ARRAY_INDEX_26_BST1[0]
EQ_ARRAY_INDEX_26_BST2[1]
EQ_ARRAY_INDEX_26_BST2[0]
EQ_ARRAY_INDEX_26_BST3[1]
EQ_ARRAY_INDEX_26_BST3[0]
EQ_ARRAY_INDEX_27_BST0[1]
EQ_ARRAY_INDEX_27_BST0[0]
EQ_ARRAY_INDEX_27_BST1[1]
EQ_ARRAY_INDEX_27_BST1[0]
EQ_ARRAY_INDEX_27_BST2[1]
EQ_ARRAY_INDEX_27_BST2[0]
EQ_ARRAY_INDEX_27_BST3[1]
EQ_ARRAY_INDEX_27_BST3[0]
EQ_ARRAY_INDEX_28_BST0[1]
EQ_ARRAY_INDEX_28_BST0[0]
EQ_ARRAY_INDEX_28_BST1[1]
EQ_ARRAY_INDEX_28_BST1[0]
EQ_ARRAY_INDEX_28_BST2[1]
EQ_ARRAY_INDEX_28_BST2[0]
EQ_ARRAY_INDEX_28_BST3[1]
EQ_ARRAY_INDEX_28_BST3[0]
EQ_ARRAY_INDEX_29_BST0[1]
EQ_ARRAY_INDEX_29_BST0[0]
EQ_ARRAY_INDEX_29_BST1[1]
EQ_ARRAY_INDEX_29_BST1[0]
EQ_ARRAY_INDEX_29_BST2[1]
EQ_ARRAY_INDEX_29_BST2[0]
EQ_ARRAY_INDEX_29_BST3[1]
EQ_ARRAY_INDEX_29_BST3[0]
EQ_ARRAY_INDEX_30_BST0[1]
EQ_ARRAY_INDEX_30_BST0[0]
EQ_ARRAY_INDEX_30_BST1[1]
EQ_ARRAY_INDEX_30_BST1[0]
EQ_ARRAY_INDEX_30_BST2[1]
EQ_ARRAY_INDEX_30_BST2[0]
EQ_ARRAY_INDEX_30_BST3[1]
EQ_ARRAY_INDEX_30_BST3[0]
5A
5B
5C
5D
5E
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_31_BST0[1]
EQ_ARRAY_INDEX_31_BST0[0]
EQ_ARRAY_INDEX_31_BST1[1]
EQ_ARRAY_INDEX_31_BST1[0]
EQ_ARRAY_INDEX_31_BST2[1]
EQ_ARRAY_INDEX_31_BST2[0]
EQ_ARRAY_INDEX_31_BST3[1]
EQ_ARRAY_INDEX_31_BST3[0]
GRP0_OV_CNT7
5F
GRP0_OV_CNT6
GRP0_OV_CNT5
GRP0_OV_CNT4
60
61
62
63
Group 0 count LSB
GRP0_OV_CNT3
GRP0_OV_CNT2
GRP0_OV_CNT1
GRP0_OV_CNT0
CNT_DLTA_OV_0
Override enable for group 0
mannual data rate selection
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
GRP0_OV_CNT14
GRP0_OV_CNT13
GRP0_OV_CNT12
GRP0_OV_CNT11
GRP0_OV_CNT10
GRP0_OV_CNT9
GRP0_OV_CNT8
GRP1_OV_CNT7
GRP1_OV_CNT6
GRP1_OV_CNT5
GRP1_OV_CNT4
GRP1_OV_CNT3
GRP1_OV_CNT2
GRP1_OV_CNT1
GRP1_OV_CNT0
CNT_DLTA_OV_1
Group 0 count MSB
Group 1 count LSB
Override enable for group 1
mannual data rate selection
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
GRP1_OV_CNT14
GRP1_OV_CNT13
GRP1_OV_CNT12
GRP1_OV_CNT11
GRP1_OV_CNT10
GRP1_OV_CNT9
GRP1_OV_CNT8
Group 1 count MSB
50
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
0
0
0
0
0
0
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
GRP0_OV_DLTA3
Sets the PPM delta tolerance
for the PPM counter lock
check for group 0. Must also
program channel register
0x67[7].
GRP0_OV_DLTA2
GRP0_OV_DLTA1
GRP0_OV_DLTA0
GRP1_OV_DLTA3
GRP1_OV_DLTA2
GRP1_OV_DLTA1
GRP1_OV_DLTA0
RESERVED
5
4
64
3
Sets the PPM delta tolerance
for the PPM counter lock
check for group 1. Must also
program channel register
0x67[6].
2
1
0
65
66
7:0
7:00
7
RESERVED
GRP0_OV_DLTA4
GRP1_OV_DLTA4
HV_LOCKMON_EN
6
5
1: Normal operation,
HEO/VEO measurements are
used for lock monitoring
67
4:1
0
0
0
RW
RW
N
N
RESERVED
LOCKMON_FRC_EN
This feature is reserved for
future use.
7:5
4
0
0
RW
RW
N
N
RESERVED
ADPT_FRC_EN
This feature is reserved for
future use.
3
2
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
SCN_OBS_CTRL3
SCN_OBS_CTRL2
SCN_OBS_CTRL1
SCN_OBS_CTRL0
RESERVED
68
This feature is reserved for
future use.
1
0
7:5
4
CTLE_ADPT_FRC_EN
This feature is reserved for
future use.
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
0
0
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HV_LCKMON_CNT_MS3
HV_LCKMON_CNT_MS2
HV_LCKMON_CNT_MS1
HV_LCKMON_CNT_MS0
VEO_LCK_THRSH3
VEO_LCK_THRSH2
VEO_LCK_THRSH1
VEO_LCK_THRSH0
HEO_LCK_THRSH3
HEO_LCK_THRSH2
HEO_LCK_THRSH1
HEO_LCK_THRSH0
69
This feature is reserved for
future use.
VEO threshold to meet before
lock is established
6A
HEO threshold to meet before
lock is established
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FOM_A7
FOM_A6
FOM_A5
FOM_A4
FOM_A3
FOM_A2
FOM_A1
FOM_A0
FOM_B7
FOM_B6
FOM_B5
FOM_B4
FOM_B3
FOM_B2
FOM_B1
FOM_B0
FOM_C7
FOM_C6
FOM_C5
FOM_C4
FOM_C3
FOM_C2
FOM_C1
FOM_C0
Alternate Figure of Merit
variable A
Max value for this register is
128, do not use the MSB
6B
HEO adjustment for Alternate
FoM, variable B
6C
VEO adjustment for alternate
FoM, variable C
6D
EN_NEW_FOM_CTLE
1: CTLE adaption state
machine will use the alternate
FoM
HEO_ALT = (HEO-B)*A*2
VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in
channel register 0x6B, 0x6C,
and 0x6D. The value of A is
equal to the register value
divided by 128
The Alternate FoM = (HEO-
B)*A*2 + (VEO-C)*(1-A)*2
6
0
RW
Y
EN_NEW_FOM_DFE
1: DFE adaption state
machine will use the alternate
FoM
6E
HEO_ALT = (HEO-B)*A*2
VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in
channel register 0x6B, 0x6C,
and 0x6D. The value of A is
equal to the register value
divided by 128
The Alternate FoM = (HEO-
B)*A*2 + (VEO-C)*(1-A)*2
5:1
0
0
0
RW
RW
N
N
RESERVED
GET_HV_ST_FRC_EN
This feature is reserved for
future use.
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
0
RW
Y
EN_LOW_DIVSEL_EQ
1: EQ adaption will be
performed for all divider
settings
0: EQ adaption will only be
performed for dividers of 1 and
2
6F
70
6:5
4:0
7:4
3
0
0
0
0
0
1
1
0
RW
RW
RW
RW
RW
RW
RW
R
Y
N
N
Y
Y
Y
Y
N
RESERVED
RESERVED
RESERVED
EQ_LB_CNT3
EQ_LB_CNT2
EQ_LB_CNT1
EQ_LB_CNT0
PRBS_INT
2
This feature is reserved for
future use.
1
0
7
1: Indicates that a PRBS
stream has been detected.
Requires the PRBS checker to
be properly configured. This
bit will stay set until it has
been cleared by being read.
This bit will clear after reading
6
5
0
R
R
N
K28P5_6466_COND_MET_INT
This feature only functions
during intial lock if the k28.5 or
64b/66b lock conditions are
enabled and met.
1: Indicates that the k28.5 or
64b/66b lock conditions were
met
71
0
N
DFE_POL_1_OBS
Primary observation point for
DFE tap 1 polarity
4
3
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
DFE_WT1_OBS4
DFE_WT1_OBS3
DFE_WT1_OBS2
DFE_WT1_OBS1
DFE_WT1_OBS0
RESERVED
Primary observation point for
DFE tap 1 weight
2
R
1
R
0
R
7:5
4
RW
R
DFE_POL_2_OBS
Primary observation point for
DFE tap 2 polarity
3
2
0
0
0
0
0
0
R
R
N
N
N
N
N
N
DFE_WT2_OBS3
DFE_WT2_OBS2
DFE_WT2_OBS1
DFE_WT2_OBS0
RESERVED
72
Primary observation point for
DFE tap 2 weight
1
R
0
R
7:5
4
RW
R
DFE_POL_3_OBS
Primary observation point for
DFE tap 3 polarity
3
2
1
0
0
0
0
0
R
R
R
R
N
N
N
N
DFE_WT3_OBS3
DFE_WT3_OBS2
DFE_WT3_OBS1
DFE_WT3_OBS0
73
Primary observation point for
DFE tap 3 weight
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7:5
4
0
0
RW
R
N
N
RESERVED
DFE_POL_4_OBS
Primary observation point for
DFE tap 4 polarity
3
2
0
0
0
0
0
0
R
R
N
N
N
N
N
N
DFE_WT4_OBS3
DFE_WT4_OBS2
DFE_WT4_OBS1
DFE_WT4_OBS0
RESERVED
74
Primary observation point for
DFE tap 4 weight
1
R
0
R
7:5
4
RW
R
DFE_POL_5_OBS
Primary observation point for
DFE tap 5 polarity
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
1
0
0
0
1
0
0
R
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
DFE_WT5_OBS3
75
R
DFE_WT5_OBS2
Primary observation point for
DFE tap 5 weight
R
DFE_WT5_OBS1
R
DFE_WT5_OBS0
RW
RW
RW
RW
RW
RW
RW
RW
RW
POST_LOCK_VEO_THR3
POST_LOCK_VEO_THR2
POST_LOCK_VEO_THR1
POST_LOCK_VEO_THR0
POST_LOCK_HEO_THR3
POST_LOCK_HEO_THR2
POST_LOCK_HEO_THR1
POST_LOCK_HEO_THR0
PRBS_GEN_POL_EN
VEO threshold after lock is
established
76
HEO threshold after lock is
established
This feature is reserved for
future use. To invert the
polarity of the PRBS data use
the normal method of inverting
of the sign bits for the FIR
taps.
6
5
4
3
2
1
0
0
0
1
1
0
1
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
CDR_CAP_DAC_START1[5]
CDR_CAP_DAC_START0[5]
POST_LOCK_SBTTHR4
POST_LOCK_SBTTHR3
POST_LOCK_SBTTHR2
POST_LOCK_SBTTHR1
POST_LOCK_SBTTHR0
This feature is reserved for
future use
77
SBT threshold after lock is
established.
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
UNCORR_ERR_INT
DESCRIPTION
7
6
5
4
3
0
0
0
0
0
R
R
R
R
R
N
N
N
N
N
This feature is reserved for
future use.
PRBS_LOCKUP_STATUS
SD_STATUS
This feature is reserved for
future use.
Primary observation point for
signal detect status
CDR_LOCK_STATUS
CDR_LOCK_INT
Primary observation point for
CDR lock status
Requires that channel register
0x79[1] be set.
1: Indicates CDR has
achieved lock, lock goes from
LOW to HIGH. This bit is
cleared after reading. This bit
will stay set until it has been
cleared by reading.
2
0
R
N
SD_INT
Requires that channel register
0x79[0] be set.
78
1: Indicates signal detect
status has changed. This will
trigger when signal detect
goes from LOW to HIGH or
HIGH to LOW. This bit is
cleared after reading. This bit
will stay set until it has been
cleared by reading.
1
0
0
0
R
R
N
N
EOM_VRANGE_LIMIT_ERROR
HEO_VEO_INT
This feature is reserved for
future use.
Requires that channel register
0x36[6] be set.
1: Indicates that HEO/VEO
dropped below the limits set in
channel register 0x76 This bit
is cleared after reading. This
bit will stay set until it has
been cleared by reading.
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
0
0
0
R
R
R
N
N
N
PWDN_SD
This feature is reserved for
future use.
PRBS_CHKR_EN
PRBS_GEN_EN
1: Enable the PRBS checker.
0: Disable the PRBS checker
1: Enable the pattern
generator
0: Disable the pattern
generator
4
3
1
0
R
R
N
Y
PRBS_LCKUP_EXIT_EN
EN_K285
This feature is reserved for
future use.
1: Enables K28.5 checking as
a requirement for lock
0: Normal operation
79
2
1
0
0
R
R
Y
N
CAL_OVERRIDE
This feature is reserved for
future use.
CDR_LOCK_INT_EN
1: Enable CDR lock interrupt,
observable in channel register
0x78[3]
0: Disable CDR lock interrupt
0
0
R
N
SD_INT_EN
1: Enable signal detect
interrupt, observable in
channel register 0x78[3]
0: Disable signal detect
interrupt
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
SEL_A7
SEL_A6
SEL_A5
SEL_A4
This feature is reserved for
future use.
7A
7B
7C
SEL_A3
SEL_A2
SEL_A1
SEL_A0
SEL_D7
SEL_D6
SEL_D5
SEL_D4
This feature is reserved for
future use.
SEL_D3
SEL_D2
SEL_D1
SEL_D0
PRBS_FIXED7
PRBS_FIXED6
PRBS_FIXED5
PRBS_FIXED4
PRBS_FIXED3
PRBS_FIXED2
PRBS_FIXED1
PRBS_FIXED0
W
W
Pattern generator user defined
pattern LSB. MSB located at
channel register 0x97.
W
W
W
W
W
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SNLS472A –JANUARY 2014–REVISED JUNE 2017
Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
CONT_ADAPT_HEO_CHNG_THRS3
CONT_ADAPT_HEO_CHNG_THRS2
CONT_ADAPT_HEO_CHNG_THRS1
CONT_ADAPT_HEO_CHNG_THRS0
CONT_ADAPT_VEO_CHNG_THRS3
CONT_ADAPT_VEO_CHNG_THRS2
CONT_ADAPT_VEO_CHNG_THRS1
CONT_ADAPT_VEO_CHNG_THRS0
CONT_ADPT_TAP_INCR3
Limit for HEO change before
triggering a DFE adaption
while continous DFE adaption
is enabled.
7D
Limit for VEO change before
triggering a DFE adaption
while continous DFE adaption
is enabled.
Limit of allowable DFE tap
weight change from the
previous base point
CONT_ADPT_TAP_INCR2
CONT_ADPT_TAP_INCR1
CONT_ADPT_TAP_INCR0
7E
CONT_ADPT_FOM_CHNG_THRS3
CONT_ADPT_FOM_CHNG_THRS2
CONT_ADPT_FOM_CHNG_THRS1
CONT_ADPT_FOM_CHNG_THRS0
EN_OBS_ALT_FOM
Limit for FoM change before
triggering a DFE adaption
while continous DFE adaption
is enabled.
1: Allows for alternate FoM
calculation to be shown in
channel registers 0x27, 0x28
and 0x29 instead of HEO and
VEO
6
5
0
1
RW
RW
N
Y
RESERVED
DIS_HV_CHK_FOR_CONT_ADAPT 1: Ignore HEO/VEO lock
condition checks during
continous adaption. Normal
operation for continous DFE
adaption
7F
4
3
1
1
RW
RW
Y
Y
EN_DFE_CONT_ADAPT
CONT_ADPT_CMP_BOTH
1: Continous DFE adaption is
enabled
0: DFE adapts only during lock
and then freezes
1: If continous DFE adaption is
enabled, a DFE adaption will
trigger if either HEO or VEO
degrades
2
1
0
1
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
R
Y
Y
Y
N
N
N
N
N
N
N
N
N
CONT_ADPT_COUNT2
CONT_ADPT_COUNT1
CONT_ADPT_COUNT0
HEO_CENTER7
HEO_CENTER6
HEO_CENTER5
HEO_CENTER4
HEO_CENTER3
HEO_CENTER2
HEO_CENTER1
HEO_CENTER0
RESERVED
Limit for number of weights
the DFE can look ahead in
continous adaption
0
7
6
R
5
R
4
R
This feature is reserved for
future use.
80
81
3
R
2
R
1
R
0
R
7:0
R
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
0
RW
N
FREEZE_PRBS_CNTR
1: Freeze the PRBS bit and
error counts to allow for read
back
0: Normal operation. Both bit
and error counters are allowed
to increment if the PRBS
checker is properly configured.
6
0
RW
N
RST_PRBS_CNTS
1: Reset PRBS bit and error
counts
0: Normal operation, counters
are released from reset
5
4
0
0
RW
RW
N
N
RESERVED
PRBS_PATT_OV
1: Override PRBS pattern auto
detection. Forces the pattern
checker to only lock onto the
pattern defined in bits 3 and 2
of this register.
0: Normal operation, pattern
checker will automatically
detect the PRBS pattern
82
3
2
0
0
RW
RW
N
N
PRBS_PATT1
PRBS_PATT0
Usage is enabled with channel
reg 0x82[4]
Select PRBS pattern to be
checked 00: PRBS-7
01: PRBS-9
10: PRBS-15
11: PRBS-31
1
0
RW
N
PRBS_POL_OV
1: Override PRBS pattern auto
polarity detection. Forces the
pattern checker to only lock
onto the polarity defined in bit
0 of this register.
0: Normal operation, pattern
checker will automatically
detect the PRBS pattern
polarity
0
0
RW
N
PRBS_POL
Usage is enabled with channel
register 0x82[1]
0: Forced polarity = true
1 - Forced polarity = inverted
7:3
2
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
PRBS_ERR_CNT10
PRBS_ERR_CNT9
PRBS_ERR_CNT8
PRBS_ERR_CNT7
PRBS_ERR_CNT6
PRBS_ERR_CNT5
PRBS_ERR_CNT4
PRBS_ERR_CNT3
PRBS_ERR_CNT2
PRBS_ERR_CNT1
PRBS_ERR_CNT0
83
84
1
PRBS error count MSB
0
7
6
5
4
PRBS error count LSB
3
2
1
0
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
PRBS_DATA_CNT46
PRBS_DATA_CNT45
PRBS_DATA_CNT44
PRBS_DATA_CNT43
PRBS_DATA_CNT42
PRBS_DATA_CNT41
PRBS_DATA_CNT40
PRBS_DATA_CNT39
PRBS_DATA_CNT38
PRBS_DATA_CNT37
PRBS_DATA_CNT36
PRBS_DATA_CNT35
PRBS_DATA_CNT34
PRBS_DATA_CNT33
PRBS_DATA_CNT32
PRBS_DATA_CNT31
PRBS_DATA_CNT30
PRBS_DATA_CNT29
PRBS_DATA_CNT28
PRBS_DATA_CNT27
PRBS_DATA_CNT26
PRBS_DATA_CNT25
PRBS_DATA_CNT24
PRBS_DATA_CNT23
PRBS_DATA_CNT22
PRBS_DATA_CNT21
PRBS_DATA_CNT20
PRBS_DATA_CNT19
PRBS_DATA_CNT18
PRBS_DATA_CNT17
PRBS_DATA_CNT16
PRBS_DATA_CNT15
PRBS_DATA_CNT14
PRBS_DATA_CNT13
PRBS_DATA_CNT12
PRBS_DATA_CNT11
PRBS_DATA_CNT10
PRBS_DATA_CNT9
PRBS_DATA_CNT8
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
85
86
87
88
89
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
PRBS_DATA_CNT7
R
PRBS_DATA_CNT6
R
PRBS_DATA_CNT5
PRBS bit count, 47-bit word
from channel registers 0x85 to
0x8A
R
PRBS_DATA_CNT4
8A
R
PRBS_DATA_CNT3
R
PRBS_DATA_CNT2
R
PRBS_DATA_CNT1
R
PRBS_DATA_CNT0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
UNCORR_ERR_PATT15
UNCORR_ERR_PATT14
UNCORR_ERR_PATT13
UNCORR_ERR_PATT12
UNCORR_ERR_PATT11
UNCORR_ERR_PATT10
UNCORR_ERR_PATT9
UNCORR_ERR_PATT8
UNCORR_ERR_PATT7
UNCORR_ERR_PATT6
UNCORR_ERR_PATT5
UNCORR_ERR_PATT4
UNCORR_ERR_PATT3
UNCORR_ERR_PATT2
UNCORR_ERR_PATT1
UNCORR_ERR_PATT0
RESERVED
This feature is reserved for
future use.
8B
This feature is reserved for
future use.
8C
EQ_EN_HR_MODE
Used with bit 2 to set Full rate,
Mid rate or Half rate EQ
bandwidth. Bit 6 is MSB. Bit 2
is LSB.
00: Full rate
01: Mid rate
11: Half rate
5
4
3
2
0
0
0
1
RW
RW
RW
RW
Y
Y
Y
Y
PFD_EN_HR_MODE
DIV_EN_HR_MODE
DIV_EN_HR_MODE
EQ_EN_MR_MODE
8D
Used with bit 6 to set Full rate,
Mid rate or Half rate EQ
bandwidth. Bit 6 is MSB. Bit 2
is LSB.
00: Full rate
01: Mid rate
10: Alternate mid rate
11: Half rate
1
0
1
0
RW
RW
Y
Y
SD_DC_EN
This feature is reserved for
future use.
EQ_SEL_LOOP_OUT
This feature is reserved for
future use.
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
RW
EEPROM
FIELD NAME
SD_CAL_RESET_LV
DESCRIPTION
7
6
0
N
N
This feature is reserved for
future use.
0
RW
SEL_DIV48_LV
Output reference clock
selection
1: Selects reference clock
from in channel digital
0: Selects reference clock
from adjacent channel output
8E
5
0
RW
Y
EN_CLK_LOOPTHRU_LV
1: Enable the reference clock
loop through mux
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
R
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
FIR_SEL_EDGE2
FIR_SEL_EDGE1
FIR_SEL_EDGE0
DFE_SEL_GAIN1
DFE_SEL_GAIN0
EQ_BST_TO_ANA7
EQ_BST_TO_ANA6
EQ_BST_TO_ANA5
EQ_BST_TO_ANA4
EQ_BST_TO_ANA3
EQ_BST_TO_ANA2
EQ_BST_TO_ANA1
EQ_BST_TO_ANA0
Edge rate (slew rate) control
VGA gain control
R
R
R
Primary observation point for
the EQ boost setting.
8F
R
R
R
R
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
4
0
0
0
0
RW
RW
RW
RW
Y
Y
Y
Y
K28P5_COMPR_PERIOD3
K28P5_COMPR_PERIOD2
K28P5_COMPR_PERIOD1
K28P5_COMPR_PERIOD0
Used when one of these
modes are enabled, k28.5 lock
check(channel register
0x79[5]), 64b66b lock
check(channel register
0x36[3]), k28.5 or 64b66b
Interrupt(register 0x36[0])
k28.5_compr_period defines
period within which k28.5 is
expected to be seen.
Also used for expected
frequency of 64B66B
transitions
The number of bits to check is
equal to
2^(min_k28.5_reqd[11:0]) * 32
Enable K28.5 checking with
reg_79[3]
90
3
2
1
0
0
0
0
0
RW
RW
RW
RW
Y
Y
Y
Y
MIN_K28P5_REQD11
MIN_K28P5_REQD10
MIN_K28P5_REQD9
MIN_K28P5_REQD8
Used when one of these
modes are enabled, k28.5 lock
check(channel register
0x79[5]), 64b66b lock
check(channel register
0x36[3]), k28.5 or 64b66b
Interrupt(register 0x36[0])
Channel register 0x90[3:0]
together with channel register
0x91[7:0] defines number of
k28.5+ patterns that need to
be detected in the number of
bits checked(set by channel
register 0x90[7:4]
Also used for expected
frequency of 64B66B
transitions
Enable k28.5 checking with
channel register 0x79[3]
7
6
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
N
MIN_K28P5_REQD7
MIN_K28P5_REQD6
MIN_K28P5_REQD5
MIN_K28P5_REQD4
MIN_K28P5_REQD3
MIN_K28P5_REQD2
MIN_K28P5_REQD1
MIN_K28P5_REQD0
RESERVED
5
4
91
See channel register 0x90[3:0]
3
2
1
0
92
93
7:0
7:0
RESERVED
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
7
MODE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
EEPROM
FIELD NAME
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
DFE_EN
DFE_DIS
EOM_EN
EOM_DIS
DRV_EN
DRV_DIS
This feature is reserved for
future use.
6
This feature is reserved for
future use.
5
This feature is reserved for
future use.
4
This feature is reserved for
future use.
94
3
This feature is reserved for
future use.
2
This feature is reserved for
future use.
1
PEAK_DET_EN
PEAK_DET_DIS
SD_EN
This feature is reserved for
future use.
0
This feature is reserved for
future use.
7
This feature is reserved for
future use.
6
SD_DIS
This feature is reserved for
future use.
5
DC_OFF_EN
DC_OFF_DIS
EQ_EN
This feature is reserved for
future use.
4
This feature is reserved for
future use.
95
3
This feature is reserved for
future use.
2
EQ_DIS
This feature is reserved for
future use.
1
COMP_EN
COMP_DIS
This feature is reserved for
future use.
0
This feature is reserved for
future use.
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7
6
5
0
0
0
RW
RW
RW
N
N
Y
RESERVED
RESERVED
XPNT_SLAVE
A channel that it is configured
in a 1-to-many xpnt setup
must be slaved to the channel
from which it is taking input
data.
1: Channel is a slave
0: Channel is a master
4
0
RW
Y
XPNT_EN
1: Cross Point is enabled
0: Cross Point is disabled
3
2
0
1
RW
RW
Y
Y
EQ_BUFFER_EN[1]
EQ_BUFFER_EN[0]
Enable EQ output buffers:
00: Neither buffer in ON (not
recommended)
96
01: Only local buffer is ON
10: Only multi-drive buffer is
ON
11: Both buffers are ON
1
0
0
0
RW
RW
Y
Y
EQ_DATA_MUX_IN[1]
EQ_DATA_MUX_IN[0]
Select EQ data and signal
detect bus from one channel:
00: channel A
01: Channel B
10: Channel C
11: Channel D
Channel A = 0,4,8,12
Channel B = 1,5,9,13
Channel C = 2,6,10,14
Channel D = 3,7,11,15
7
6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
R
R
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
PRBS_FIXED15
PRBS_FIXED14
PRBS_FIXED13
PRBS_FIXED12
PRBS_FIXED11
PRBS_FIXED10
PRBS_FIXED9
PRBS_FIXED8
RESERVED
5
R
Pattern generator user defined
pattern MSB. LSB located at
channel register 0x7C.
4
R
97
98
99
3
R
2
R
1
R
0
R
7:6
5:0
7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESERVED
DIVSEL_START1_OV
DIVSEL_STOP1_OV
DIVSEL_START2
DIVSEL_START1
DIVSEL_START0
DIVSEL_STOP2
DIVSEL_STOP1
DIVSEL_STOP0
This feature is reserved for
future use.
6
5
This feature is reserved for
future use.
4
3
2
This feature is reserved for
future use.
1
0
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Table 6. Channel Registers, 5A to 9B (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
RW
EEPROM
FIELD NAME
DIVSEL_START0_OV
DESCRIPTION
7
6
0
Y
Y
This feature is reserved for
future use.
0
RW
DIVSEL_STOP0_OV
This feature is reserved for
future use.
5
4
1
1
1
1
1
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
N
Y
Y
DIVSEL_START0[2]
DIVSEL_START0[1]
DIVSEL_START0[0]
DIVSEL_STOP0[2]
DIVSEL_STOP0[1]
DIVSEL_STOP0[0]
RESERVED
This feature is reserved for
future use.
9A
3
2
This feature is reserved for
future use.
1
0
7:2
1
EQ_CTRL_MUX_IN[1]
EQ_CTRL_MUX_IN[0]
Select EQ control bus from
one channel:
00: channel A
0
01: Channel B
10: Channel C
9B
11: Channel D
Channel A = 0,4,8,12
Channel B = 1,5,9,13
Channel C = 2,6,10,14
Channel D = 3,7,11,15
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Typical Applications
Figure 5 and Figure 6 show a typical application of the DS110Df1610. In these diagrams, the DS110DF1610 is
configured for SMBus slave mode programming. Power is supplied to the device through a single 2.5V plane.
The power supply filtering shown in these diagrams may need to be adjusted to accommodate additional system
power noise. The SMBus and LVCMOS signals in this example use 2.5V logic. A differential reference clock for
the digital block is applied to the device through 1µF AC-coupling capacitors. In this example, the high speed
signals are connected to the device in groups of four to allow for the system designer to make use of the 4x4
cross point switches. Note that since the device contains AC-coupling capacitors on the high speed receiver
inputs, the signals can be directly connected to the device. The transmitter outputs of this device should connect
to AC-coupling capacitors placed near the receive inputs of the receiving ASIC.
2.5V
TMS_IO
TDO_IO
TRST_IO
TCK_IO
TDI_IO
VDD
C2
C2
C2
C1
C2
C2
C2
C2
GND
5{1105C1610
tower and /onꢀrol
tin /onnecꢀions
2.5V
2.5V
R2
R1
ADDR0
ADDR1
INTERR_IO
Populate as needed to set
desired SMBus address
R3
R2
R3
ALL_DONE
RESET_IO
READ_EN
EN_SMB
R2
C3
C3
REF_CLK_P
REF_CLK_N
2.5V
CLK_MON_P
R1
R1
CLK_MON_N
SDA_IO
SCL_IO
R1 = 4.7 kW
R2 = 1 kW
R3 = 1 kW or 20 kW
C1 = 22 mF
C2 = 0.1 mF
C3 = 1 mF
/opyrighꢀ © 2017, Çexas Lnsꢀrumenꢀs Lncorporaꢀed
Figure 5. Typical Connection Diagram: Power and Control Pins
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Typical Applications (continued)
5{1105C1610 Iigh
{peed /onnections
RX_0A
RX_0B
TX_0A
TX_0B
Quad 0
Cross Point Switch
RX_1A
RX_1B
TX_1A
TX_1B
Quad 1
Cross Point Switch
RX_2A
RX_2B
TX_2A
TX_2B
RX_3A
RX_3B
TX_3A
TX_3B
RX_4A
RX_4B
TX_4A
TX_4B
Quad 2
Cross Point Switch
RX_5A
RX_5B
TX_5A
TX_5B
RX_6A
RX_6B
TX_6A
TX_6B
Quad 3
Cross Point Switch
RX_7A
RX_7B
TX_7A
TX_7B
/opyright © 2017, Çexas Lnstruments Lncorporated
Figure 6. Typical Connection Diagram: High Speed Signals
7.2 Initialization Setup
The typical device initialization sequence for a DS110DF1610 includes the following:
•
Shared Register Configurations
–
Reference Clock Divider Setting (default is 125MHz)
–
:
Lock Sequencer Configuration (default is 8 channels allowed lock concurrently)
•
Channel Register Configurations repeated for all desired channels:
–
–
CDR reset
Adapt Mode Configuration
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Initialization Setup (continued)
–
–
–
–
–
–
–
Data rate selection
Output driver VOD and FIR configuration
Optional Continuous DFE adaption configuration
Optional Interrupt enable
Optional Reference clock loop through enable
Optional Cross point switch configuration
CDR reset release
7.2.1 Data Rate Selection (Rate/Sub-Rate Table)
The data rates for the DS110DF1610 must be known and programmed into each desired channel. The
DS110DF1610 will only lock to programmed data rates and the programmed divider settings. For ease of use
several common data rates have been preprogrammed into the DS110DF1610 along with the associated sub-
rates for those various standards. These rate/sub-rate settings comprise the Rate/Sub-rate Table. Note that each
channel operates independently, so different channels in the DS110DF1610 can operate at different data rates at
the same time.
The Rate/Sub-rate table for the DS110DF1610 shown below includes all of the available preprogrammed data
rates and associated divider groupings.
CHANNEL REGISTER
0x2F[7:4] SETTING
FIRST GROUP DIVIDER
SETTINGS
SECOND GROUP
DIVIDER SETTINGS
STANDARD
DATA RATES (Gbps)
0x0
0xC
0xD
Custom 1
Ethernet
5.0, 2.5
2, 4
8
2, 4
1
1.25, 10.3125
Fiber Channel
(2.125, 4.25, 8.5),
10.51875
1, 2, 4
1
0xE
0xF
SFF 8431
Custom 2
9.95328
1
1
8.625, 4.3125
1, 2
1, 2
7.2.2 Data Rate Selection (Manual Programming)
The DS110DF1610 is capable of supporting any data rate within the specified range of 8.5 Gbps to 11.3 Gbps
including the divide by 2, 4, and 8 sub-rates of this range. If it is desired to operate the DS110DF1610 at a data
rate or data rate and sub-rate combination that is not available in the Rate/Sub-rate Table, then these desired
data rates can be programmed into the device manually.
The following procedure describes how to calculate and manually program data rates into the DS110DF1610.
1. Select a divider grouping from the Rate/Sub-rate Table and program that value to channel register 0x2F.
When manually programming the data rate into the device, other rate/sub-rate values may be used to allow
for different divider and group combinations. A list of all preprogrammed divider, group combinations is
shown in the table below.
CHANNEL REGISTER
0x2F[7:4] SETTING
FIRST GROUP DIVIDER SETTINGS
SECOND GROUP DIVIDER SETTINGS
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
2, 4
1
2, 4
1
1, 2, 4
1, 2, 4
1
1, 2, 4
1, 2, 4
1
1
1
1
1
1, 2, 4
1, 2, 4
2, 4
1, 2, 4
1, 2, 4
1, 2, 4
2, 4
1, 2, 4
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CHANNEL REGISTER
0x2F[7:4] SETTING
FIRST GROUP DIVIDER SETTINGS
SECOND GROUP DIVIDER SETTINGS
0xB
0xC
0xD
0xE
0xF
8
8
1
1
1, 2, 4
1
1
1
1, 2
1, 2
2. Calculate the first group settings:
PARAMETER
VALUE/EQUATION
F0 = 25e6
COMMENT
Reference Clock
Internally the reference clock always operates at
25 MHz
Desired VCO Frequency
F1
F1 is the frequency of the VC0 which is equal to
the desired data rate. If the desired data rate
uses dividers, be sure to multiply the data rate by
the divide setting to get the correct VCO
frequency
Number of Reference Clocks
VCO Freq ÷ 32
N = 1024
F2 = F1 ÷ 32
F3 = F2 x N ÷ F0
F4
Counts of VCO Freq ÷ 32 required
Counts of VCO Freq ÷ 32 required rounded
Round F3 to the nearest integer value. Convert
this value to binary. Program the upper 8 bits to
ch register 0x61 and the lower 8 bits to ch
register 0x60. Be sure to set channel register
0x61[7] to 1 to enable the override function for
manual programming.
PPM error due to rounding
Required PPM tolerance
Err = 1e6 x (F4 – F3) ÷ F3
T
Enter the desired PPM tolerance
VCO Freq ÷ 32 +PPM tolerance
F5 = (1+ T÷1e6) ÷ F2
F6 = F5 x N ÷ F0
Rounded Counts of the VCO Freq ÷ 32 +PPM
tolerance required
Round F6 to the nearest integer value
PPM Counts delta
F7 = F6 – F3
Convert this value to binary. Program the most
significant bit channel register 0x67[7] and the
rest of the bits to channel register 0x64[7:4]
3. Calculate the second group settings:
PARAMETER
VALUE/EQUATION
COMMENT
Reference Clock
F0 = 25e6
Internally the reference clock always
operates at 25 MHz
Desired VCO Frequency
F1
F1 is the frequency of the VC0 which is
equal to the desired data rate. If the desired
data rate uses dividers, be sure to multiply
the data rate by the divide setting to get the
correct VCO frequency
Number of Reference Clocks
VCO Freq ÷ 32
N = 1024
F2 = F1 ÷ 32
F3 = F2 x N ÷ F0
F4
Counts of VCO Freq ÷ 32 required
Counts of VCO Freq ÷ 32 required rounded
Round F3 to the nearest integer value.
Convert this value to binary. Program the
upper 8 bits to ch register 0x63 and the lower
8 bits to ch register 0x62. Be sure to set
channel register 0x63[7] to 1 to enable the
override function for manual programming.
PPM error due to rounding
Required PPM tolerance
Err = 1e6 x (F4 – F3) ÷ F3
T
Enter the desired PPM tolerance
VCO Freq ÷ 32 +PPM tolerance
F5 = (1+ T÷1e6) ÷ F2
F6 = F5 x N ÷ F0
Rounded Counts of the VCO Freq ÷ 32
+PPM tolerance required
Round F6 to the nearest integer value
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PARAMETER
VALUE/EQUATION
COMMENT
PPM Counts delta
F7 = F6 – F3
Convert this value to binary. Program the
most significant bit channel register 0x67[6]
and the rest of the bits to channel register
0x64[3:0]
An example for setting group 0 and group 1 to 11.3 Gbps is shown in the table below.
CHANNEL REGISTER (HEX)
VALUE
0x80
0x60
0x61
0xB8
0x80
0x62
0x63
0xB8
0xEE
2'b00
0x64
0x67[7:6]
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8 Power Supply Recommendations
8.1 Power Supply Filtering
The power pins on the DS110DF1610 are all internally shorted together on the BGA substrate. This allows board
designers to more easily distribute the bypass capacitors for power supply filtering.
Power supply filtering typically consists of a bulk 22 µF capacitor with an array of 0.1 µF capacitors all placed
near the device. Additional bypass capacitors or capacitors of different values may be required depending on
system conditions.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
126
126
(1)
(2)
(3)
(4/5)
(6)
DS110DF1610FB/NOPB
DS110DF1610FBE/NOPB
ACTIVE
FCBGA
FCBGA
ABB
196
196
RoHS & Green
RoHS & Green
SNAGCU
Level-4-245C-72 HR
Level-4-245C-72 HR
-10 to 85
-10 to 85
DS110
DF1610
ACTIVE
ABB
SNAGCU
DS110
DF1610
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS110DF1610FB/NOPB
ABB
ABB
FCBGA
FCBGA
196
196
126
126
18 X 7
18 X 7
150
150
322.6 135.9 7620 17.2
322.6 135.9 7620 17.2
11.3 16.32
11.3 16.32
DS110DF1610FBE/
NOPB
Pack Materials-Page 1
PACKAGE OUTLINE
ABB0196A
FCBGA - 2.94 mm max height
SCALE 0.900
BALL GRID ARRAY
15.2
14.9
A
B
BALL A1 CORNER
PIN 1 ID
(OPTIONAL)
(
11)
15.2
14.9
(
9)
C
2.94 MAX
SEATING PLANE
0.2 C
0.6
BALL TYP
TYP
0.4
13 TYP
(1) TYP
(1) TYP
SYMM
1
TYP
P
N
M
L
K
J
SYMM
13
H
G
F
TYP
E
D
C
B
A
0.7
0.5
C A B
196X
0.25
0.1
C
1
2
3
4
5
6
7
8
9 10
11 12 13 14
1
TYP
4218164/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pb-Free die bump and solder ball.
www.ti.com
EXAMPLE BOARD LAYOUT
ABB0196A
FCBGA - 2.94 mm max height
BALL GRID ARRAY
(1) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13
14
A
B
C
(1) TYP
196X ( 0.45)
D
E
F
G
H
SYMM
J
K
L
M
N
P
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SNOWN
SCALE:6X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.45)
METAL
EXPOSED METAL
(
0.45)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4218164/A 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ABB0196A
FCBGA - 2.94 mm max height
BALL GRID ARRAY
(1) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13
14
A
B
C
(1) TYP
D
E
F
196X ( 0.45)
SYMM
G
H
J
K
L
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4218164/A 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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