DS25BR400 [TI]
具有发送去加重和接收均衡功能的四通道、2.5Gbps CML 收发器;型号: | DS25BR400 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有发送去加重和接收均衡功能的四通道、2.5Gbps CML 收发器 |
文件: | 总16页 (文件大小:357K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS25BR400
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SNLS230I –MAY 2006–REVISED FEBRUARY 2013
DS25BR400 Quad 2.5 Gbps CML Transceiver with Transmit
De-Emphasis and Receive Equalization
Check for Samples: DS25BR400
1
FEATURES
DESCRIPTION
The DS25BR400 is a quad 250 Mbps – 2.5 Gbps
2
•
•
•
•
•
•
•
250 Mbps – 2.5 Gbps Low Jitter Operation
Optional Fixed Input Equalization
Selectable Output De-Emphasis
Individual Loopback Controls
On-Chip Termination
CML transceiver, or 8-channel buffer, for use in
backplane and cable applications. With operation
down to 250 Mbps, the DS25BR400 can be used in
applications requiring both low and high frequency
data rates. Each input stage has a fixed equalizer to
reduce ISI distortion from board traces. The
equalizers are enabled through two control pins.
These control pins provide flexibility in applications
where ISI distortion may vary from one direction to
another. All output drivers have four selectable steps
of de-emphasis to compensate for transmission loss.
The de-emphasis blocks are also grouped in fours. In
addition, the DS25BR400 also has loopback control
capability on four channels. All the CML drivers have
50Ω termination to VCC. All receivers are internally
terminated with differential 100Ω.
+3.3V Supply
Lead-Less WQFN-60 Pin Package
–
(9 mm x9 mm x0.8 mm, 0.5 mm Pitch)
•
•
−40°C to +85°C Industrial Temperature Range
6 kV ESD Rating, HBM
APPLICATIONS
•
•
Backplane or Cable Driver
Signal Buffering and Repeating
Simplified Application Diagram
IA0
IA1
IA2
IA3
OA0
OA1
OA2
OA3
IA0
IA1
IA2
IA3
OA0
OA1
OA2
OA3
OB0
OB1
OB2
OB3
IB0
IB1
IB2
IB3
OB0
OB1
OB2
OB3
IB0
IB1
IB2
IB3
FPGA
FPGA
PreA_0
PreA_1
PreB_0
PreB_1
PreA_0
PreA_1
PreB_0
PreB_1
Lossy Backplane
or Cable Interconnect
EQA
EQB
EQA
EQB
NOTE
All CML inputs and outputs must be AC coupled for optimal performance.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS25BR400
SNLS230I –MAY 2006–REVISED FEBRUARY 2013
www.ti.com
Functional Block Diagram
EQB
EQB
Port 0/1
OB_0+-
OB_1+-
IB_0+-
PreB
IB_1+-
LB0
EQB
EQB
PreB
EQA
OA_0+-
IA_0+-
IA_1+-
EQA
PreA
OA_1+-
LB1
EQA
EQA
PreA
EQB
Port 2/3
OB_2+-
OB_3+-
IB_2+-
EQB
PreB
IB_3+-
LB2
EQB
EQB
PreB
EQA
OA_2+-
IA_2+-
IA_3+-
EQA
PreA
PreA
OA_3+-
LB3
EQA
EQA
PreA
PreB
EQA
EQB
V
DD
PreA_0
PreA_1
Equalizer
Enable
Control
GND
RSV
Pre-Emphasis
Control
PreB_0
PreB_1
EQA
EQB
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SNLS230I –MAY 2006–REVISED FEBRUARY 2013
Connection Diagram
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
PreA_1
GND
1
2
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PreB_1
LB1
OB_1+
OB_1-
3
IB_1+
IB_1-
4
5
V
V
CC
CC
IA_1+
IA_1-
GND
6
OA_1+
OA_1-
GND
7
60 Pin WQFN
8
Top View
IA_2-
IA_2+
9
OA_2-
OA_2+
DAP = GND
10
11
12
13
14
15
V
V
CC
CC
OB_2-
OB_2+
GND
IB_2-
IB_2+
LB2
PreA_0
PreB_0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 1. Leadless WQFN-60 Pin Package
(9 mm x 9 mm x 0.8 mm, 0.5 mm pitch)
See Package Number NKA0060A
Table 1. PIN DESCRIPTIONS
Pin Name
Pin Number I/O(1)
Description
DIFFERENTIAL I/O
IB_0+
IB_0−
51
52
I
O
I
Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OA_0+
OA_0−
48
49
Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to VCC
through a 50Ω resistor.
IB_1+
IB_1−
43
42
Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OA_1+
OA_1−
40
39
O
I
Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to VCC
through a 50Ω resistor.
IB_2+
IB_2−
33
34
Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OA_2+
OA_2−
36
37
O
I
Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to VCC
through a 50Ω resistor.
IB_3+
IB_3−
25
24
Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OA_3+
OA_3−
28
27
O
I
Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to VCC
through a 50Ω resistor.
IA_0+
IA_0−
58
57
Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
(1) I = Input, O = Output, P = Power
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Table 1. PIN DESCRIPTIONS (continued)
Pin Name
Pin Number I/O(1)
Description
OB_0+
OB_0−
55
54
O
Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to VCC
through a 50Ω resistor.
IA_1+
IA_1−
6
7
I
Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OB_1+
OB_1−
3
4
O
I
Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to VCC
through a 50Ω resistor.
IA_2+
IA_2−
10
9
Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OB_2+
OB_2−
13
12
O
I
Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to VCC
through a 50Ω resistor.
IA_3+
IA_3−
18
19
Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected to a
reference voltage through a 50Ω resistor. Refer to Figure 8.
OB_3+
OB_3−
21
22
O
Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to VCC
through a 50Ω resistor.
CONTROL (3.3V LVCMOS)
EQA
60
I
I
I
I
I
I
I
I
I
This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0±, IA_1±,
IA_2±, and IA_3±. By default, this pin is internally pulled high and equalization is disabled.
EQB
16
This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0±, IB_1±,
IB_2±, and IB_3±. By default, this pin is internally pulled high and equalization is disabled.
PreA_0
PreA_1
15
1
PreA_0 and PreA_1 select the output de-emphasis levels (OA_0±, OA_1±, OA_2±, and OA_3±).
PreA_0 and PreA_1 are internally pulled high. Please see Table 3 for de-emphasis levels.
PreB_0
PreB_1
31
45
PreB_0 and PreB_1 select the output de-emphasis levels (OB_0±, OB_1±, OB_2±, and OB_3±).
PreB_0 and PreB_1 are internally pulled high. Please see Table 3 for de-emphasis levels.
LB0
LB1
LB2
LB3
RSV
46
44
32
30
59
This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0± to OA_0±.
LB0 is internally pulled high. Please see Table 2 for more information.
This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1± to OA_1±.
LB1 is internally pulled high. Please see Table 2 for more information.
This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2± to OA_2±.
LB2 is internally pulled high. Please see Table 2 for more information.
This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3± to OA_3±.
LB3 is internally pulled high. Please see Table 2 for more information.
Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through
an external pull-down resistor.
POWER
VCC
5, 11, 20, 26,
35, 41, 50,
56
P
VCC = 3.3V ± 5%.
Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a
via located as close as possible to the landing pad of the VCC pin.
It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin
to ground plane.
GND
GND
2, 8, 14, 17,
23, 29, 38,
47, 53
P
P
Ground reference. Each ground pin should be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
DAP
DAP is the metal contact at the bottom side, located at the center of the WQFN-60 pin package. It
should be connected to the GND plane with at least 4 via to lower the ground impedance and improve
the thermal performance of the package.
Functional Description
The DS25BR400 is a quad 250 Mbps – 2.5 Gbps CML transceiver, or 8-channel buffer, for use in backplane and
cable applications. The DS25BR400 is not designed to operate with data rates below 250 Mbps or with a DC
bias applied to the CML inputs or outputs. Most high speed links are encoded for DC balance and have been
defined to include AC coupling capacitors allowing the DS25BR400 to be directly inserted into the datapath
without any limitation. The ideal AC coupling capacitor value is often based on the lowest frequency component
embedded within the serial link. A typical AC coupling capacitor value ranges between 100 and 1000nF, some
specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted
parasitics around and within the AC coupling capacitor, a body size of 0402 is recommended. Figure 7 shows the
AC coupling capacitor placement in an AC test circuit.
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To compensate for the high frequency losses incurred during signal transmission in cables and backplanes the
DS25BR400 employs input and output signal conditioning. Each input stage has a fixed equalizer and all output
drivers have four selectable steps of de-emphasis to reduce deterministic jitter on the serial link. All the CML
output drivers have 50Ω termination to VCC. All receiver inputs are internally terminated with differential 100Ω
impedance.
Table 2. Logic Table for Loopback Controls
LB0
Loopback Function
0
Enable loopback from IB_0± to OA_0±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB1
0
Enable loopback from IB_1± to OA_1±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB2
0
Enable loopback from IB_2± to OA_2±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB3
0
Enable loopback from IB_3± to OA_3±.
Normal mode. Loopback disabled.
1 (default)
Table 3. De-Emphasis Controls
De-Emphasis Level in mVPP
(VODPE)
PreA_[1:0]
Default VOD Level in mVPP (VODB)
De-Emphasis in dB (VODPE/VODB)
0 0
1200
1200
1200
1200
1200
850
600
426
0
0 1
−3
−6
−9
1 0
1 1 (Default)
De-Emphasis Level in mVPP
(VODPE)
PreB_[1:0]
Default VOD Level in mVPP (VODB)
De-Emphasis in dB (VODPE/VODB)
0 0
1200
1200
1200
1200
1200
850
600
426
0
0 1
−3
−6
−9
1 0
1 1 (Default)
Output De-Emphasis
De-emphasis is the conditioning function for use in compensating against backplane transmission loss. The
DS25BR400 provides four steps of de-emphasis ranging from 0, −3, −6 and −9 dB, user-selectable dependent
on the loss profile of the backplane. Figure 2 shows a driver de-emphasis waveform. The de-emphasis duration
is nominal 200 ps, corresponding to 50% bit-width at 2.5 Gbps. The de-emphasis levels of switch-side and line-
side can be individually programmed.
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1-bit
1 to N bits
1-bit
1 to N bits
0 dB
-3 dB
-6 dB
-9 dB
VODB
VODPE3
0V
VODPE2
VODPE1
Figure 2. Driver De-Emphasis Differential Waveform (showing all 4 de-emphasis steps)
Input Equalization
Each differential input of the DS25BR400 has a fixed equalizer front-end stage. Input group A and B can be
individually enabled and disabled. It is designed to provide fixed equalization for short board traces with
transmission losses of approximately 5 dB between 375 MHz to 1.875 GHz. Programmable de-emphasis
together with input equalization ensures an acceptable eye opening for a 40-inch FR-4 backplane.
The differential input equalizer for inputs on Channel A and inputs on Channel B can be bypassed by using EQA
and EQB, respectively. By default, the equalizers are internally pulled high and disabled. Therefore, EQA and
EQB must be asserted LOW to enable equalization.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to 4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
+150°C
CMOS/TTL Input Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
Lead Temperature
Soldering, 4 sec
+260°C
22.3°C/W
3.2°C/W
Thermal Resistance, θJA
Thermal Resistance, θJC
Thermal Resistance, ΦJB
10.3°C/W
(3)
ESD Ratings
HBM
CDM
MM
6kV
1kV
350V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. For guaranteed specifications and the test conditions, see Electrical Characteristics. Operation of the
device beyond the maximum Operating Ratings is not recommended.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) ESD tests conform to the following standards:
Human Body Model (HBM) applicable standard: MIL-STD-883, Method 3015.7
Machine Model (MM) applicable standard: JESD22-A115-A (ESD MM std. of JEDEC)
Field -Induced Charge Device Model (CDM) applicable standard: JESD22-C101-C (ESD FICDM std. of JEDEC)
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Recommended Operating Ratings
Min
Typ
Max
3.465
100
Units
V
Supply Voltage (VCC-GND)
3.135
3.3
Supply Noise Amplitude
10 Hz to 2 GHz
mVPP
Ambient Temperature
Case Temperature
−40
+85
100
°C
°C
Electrical Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Typ
Parameter
Test Conditions
Min
Max
Units
(3)
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input
Voltage
2.0
VCC +0.3
0.8
V
V
Low Level Input
Voltage
−0.3
High Level Input
Current
VIN = VCC
−10
10
µA
IIL
Low Level Input Current VIN = GND
Pull-High Resistance
75
94
35
124
µA
RPU
kΩ
RECEIVER SPECIFICATIONS
VID
Differential Input
Voltage Range
AC Coupled Differential Signal.
Below 1.25 Gb/s
100
100
100
1750
1560
1200
mVP-P
mVP-P
mVP-P
At 1.25 Gbps–3.125 Gbps
Above 3.125 Gbps
This parameter is not production tested.
VICM
RITD
Common Mode Voltage Measured at receiver inputs reference to ground.
at Receiver Inputs
1.3
V
Input Differential
Termination
On-chip differential termination between
IN+ or IN−. Figure 8
84
100
116
Ω
DRIVER SPECIFICATIONS
VODB
Output Differential
Voltage Swing without
De-Emphasis
RL = 100Ω ±1%
PreA_1 = 0; PreA_0 = 0
PreB_1 = 0; PreB_0 = 0
Driver de-emphasis disabled.
Running K28.7 pattern at 2.5 Gbps.
(Figure 7)
1000
1200
1400
mVP-P
VPE
Output De-Emphasis
Voltage Ratio
RL = 100Ω ±1%
Running K28.7 pattern at 2.5 Gbps
20*log(VODPE/VODB) PreX_[1:0] = 00
PreX_[1:0] = 01
0
dB
dB
dB
dB
−3
−6
−9
PreX_[1:0] = 10
PreX_[1:0] = 11
X = A/B channel de-emphasis drivers
(Figure 2 / Figure 7)
tPE
De-Emphasis Width
Output Termination
Tested at −9 dB de-emphasis level, PreX[1:0] = 11
X = A/B channel de-emphasis drivers
See Figure 6 on measurement condition.
125
42
200
250
58
ps
ROTSE
ROTD
On-chip termination from OUT+ or OUT− to VCC
50
Ω
Ω
Output Differential
Termination
On-chip differential termination between OUT+ and
OUT−
100
(1) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}K28.5 pattern is a 20-bit repeating pattern of +K28.5 and
−K28.5 code groups {110000 0101 001111 1010}
(2) IN+ and IN− are generic names that refer to one of the many pairs of complementary inputs of the DS25BR400. OUT+ and OUT− are
generic names that refer to one of the many pairs of the complementary outputs of the DS25BR400. Differential input voltage VID is
defined as |IN+ – IN−|. Differential output voltage VOD is defined as |OUT+ – OUT−|.
(3) Typical specifications are at TA = 25 °C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
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Electrical Characteristics(1)(2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Typ
Parameter
Test Conditions
Min
Max
Units
%
(3)
ΔROTSE
Mis-Match in Output
Termination Resistors
Mis-match in output termination resistors
5
VOCM
Output Common Mode
Voltage
2.7
V
POWER DISSIPATION
PD
Power Dissipation
VDD = 3.465V
All outputs terminated by 100Ω ±1%.
PreB_[1:0] = 0, PreA_[1:0] = 0
Running PRBS 27-1 pattern at 2.5 Gbps
1.3
W
AC CHARACTERISTICS(4)
tR
Differential Low to High Measured with a clock-like pattern at 2.5 Gbps,
80
80
ps
ps
ns
Transition Time
between 20% and 80% of the differential output
voltage.
De-emphasis disabled.
Transition time is measured with the fixture shown in
Figure 7 adjusted to reflect the transition time at the
output pins.
tF
Differential High to Low
Transition Time
tPLH
tPHL
Differential Low to High Measured at 50% differential voltage from input to
1
Propagation Delay
output.
Differential High to Low
Propagation Delay
1
ns
ps
tSKP
tSKO
Pulse Skew
|tPHL–tPLH
|
20
Output Skew
Difference in propagation delay between channels
on the same part
(5)
100
165
4
ps
ps
ns
(Channel-to-Channel Skew)
tSKPP
Part-to-Part Skew
Difference in propagation delay between devices
across all channels operating under identical
conditions
(5)
tLB
Loopback Delay Time
Delay from enabling loopback mode to signals
appearing at the differential outputs
Figure 5
RJ
Device Random Jitter
At 0.25 Gbps
At 1.5 Gbps
At 2.5 Gbps
2
2
2
ps rms
ps rms
ps rms
(6)
Alternating-10 pattern.
De-emphasis disabled.
(Figure 7)
DJ
Device Deterministic
Jitter
At 0.25 Mbps, PRBS7 pattern
At 1.5 Gbps, K28.5 pattern
At 2.5 Gbps, K28.5 pattern
At 2.5 Gbps, PRBS7 pattern
De-emphasis disabled.
(Figure 7)
25
25
25
25
ps pp
ps pp
ps pp
ps pp
(7)
DR
Data Rate
Alternating-10 pattern
0.25
2.5
Gbps
(8)
(4) All CML Inputs and Outputs must be AC coupled for optimal jitter performance.
(5) tSKO is the magnitude difference in propagation delays between all data paths on one device. This is channel-to-channel skew. tSKPP is
the worst case difference in propagation delay across multiple devices on all channels and operating under identical conditions. For
example, for two devices operating under the same conditions, tSKPP is the magnitude difference between the shortest propagation
delay measurement on one device to the longest propagation delay measurement on another device.
(6) Device output random jitter is a measurement of random jitter contributed by the device. It is derived by the equation SQRT[(RJOUT)2 –
(RJIN)2], where RJOUT is the total random jitter measured at the output of the device in ps(rms), RJIN is the random jitter of the pattern
generator driving the device. Below 400 Mbps, system jitter and device jitter could not be separated. The 250 Mbps specification
includes system random jitter. Please see Figure 7 for the AC test circuit.
(7) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJOUT - DJIN), where DJOUT is the total peak-to-peak deterministic jitter measured at the output of the device in ps(p-p). DJIN is the
peak-to-peak deterministic jitter at the input of the test board. Please see Figure 7 for the AC test circuit.
(8) This parameter is guaranteed by design and/or characterization and is not tested in production.
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TIMING DIAGRAMS
80%
0V
80%
VODB
20%
20%
t
R
t
F
Figure 3. Driver Output Transition Time
50% VID
IN
t
t
PHL
PLH
50% VOD
OUT
Figure 4. Propagation Delay
Loopback
Enable
50%
t
LB
50%
Data Output
Data Input
Figure 5. Loopback Delay Timing
1-bit
1 to N bits
1-bit
1 to N bits
t
PE
20%
-9 dB
80%
0V
VODB
VODPE3
Figure 6. Output De-Emphasis Duration
Copyright © 2006–2013, Texas Instruments Incorporated
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9
Product Folder Links: DS25BR400
DS25BR400
SNLS230I –MAY 2006–REVISED FEBRUARY 2013
www.ti.com
DS25BR400 Test Fixture
Oscilloscope or
Jitter Measurement
Instrument
DC
Block
DC
Block
INPUT
TL
Pattern
Generator
V
CC
50W TL
DS25BR400
Coax
Coax
Coax
Coax
50+-1%
50 +-1%
OUT+
OUT-
D+
IN+
IN-
M
U
X
R
< 2"
EQ
D
D-
1000 mVpp
Differential
INPUT
TL
GND
50W TL
Figure 7. AC Test Circuit
VCC
5k
IN+
50
EQ
50
IN -
3.9k
180 pF
Figure 8. Receiver Input Termination
10
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR400
DS25BR400
www.ti.com
SNLS230I –MAY 2006–REVISED FEBRUARY 2013
REVISION HISTORY
Changes from Revision H (February 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: DS25BR400
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS25BR400TSQ/NOPB
ACTIVE
WQFN
NKA
60
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS25BR400
TSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS25BR400TSQ/NOPB WQFN
NKA
60
250
178.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN NKA 60
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
DS25BR400TSQ/NOPB
250
Pack Materials-Page 2
MECHANICAL DATA
NKA0060A
SQA60A (Rev A)
www.ti.com
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