DS25C400 [NSC]
Quad 2.5 Gbps Serializer/Deserializer; 四核2.5 Gbps的串行器/解串器
| 型号： | DS25C400 |
| 厂家： | 
National Semiconductor |
| 描述： | Quad 2.5 Gbps Serializer/Deserializer |
| 文件： | 总26页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
September 2002
DS25C400
Quad 2.5 Gbps Serializer/Deserializer
General Description
Features
n Quad Serializer/Deserializer
The DS25C400 is
a four-channel serializer/deserializer
(SERDES) for high-speed serial data transmission over con-
trolled impedance transmission media such as a printed
circuit board backplane or twin-axial cable. It is capable of
transmitting and receiving serial data of 2.125 - 2.5 Gbps or
1.0625 - 1.25 Gbps per channel.
n Data rate per channel: 2.125 - 2.5 Gbps or 1.0625 -
1.25 Gbps
n Supports 106.25 - 125 MHz differential reference input
clock
n Low jitter clock synthesizers for clock distribution
n 8-bit or 10-bit parallel I/O Interface conforms to
SSTL_18 Class 1 (also interfaces to 1.8V HSTL or 1.8V
LVCMOS)
n On-chip 8b/10b encoder and decoder
n High speed serial CML drivers
n High speed serial CML on-chip terminations
n Selectable pre-emphasis and equalization
n On-chip Comma Detect for character alignment
n On-chip local loopback test mode
n On-chip pattern generator and error checker to support
BIST
n Hot plug protection
n Low power, 420 mW (typ) per channel
n 324-ball TE-PBGA package
Each transmit section of the DS25C400 contains a low-jitter
clock synthesizer, an 8-bit or 10-bit parallel to serial con-
verter with built in 8b/10b encoder, and a CML output driver
with selectable pre-emphasis optimized for backplane appli-
cations. Its receive section contains an input limiting ampli-
fier with on-chip terminations and selectable equalization
levels, a clock/data recovery PLL, a comma detector and a
serial to parallel converter with built-in 8b/10b decoder.
The DS25C400 has built-in local loopback test mode,
pseudo-random pattern generator and error detector to sup-
port self-testing.
The DS25C400 requires no external components for its
clock synthesizers and clock recovery PLL’s. Three external
resistors are needed to set the proper bias currents and
compensate for process variations to achieve tight tolerance
on-chip terminations.
n Operating temperature −40˚C to +85˚C
General Function Diagram
20030101
© 2002 National Semiconductor Corporation
DS200301
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Functional Block Diagram
20030102
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2
Absolute Maximum Ratings (Note 1)
Maximum Package Power Dissipation at 25˚C
DS25C400TUT
5.68 W
45.45 mW/˚C
22 ˚C/W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Derating above 25˚C
Thermal Resistance, θJA
Junction-to-case Conductive
Thermal Resistance, θJC
ESD Rating
Supply Voltage
(VDDQ, DVDD
)
−0.3V to +2.3V
6.5 ˚C/W
Supply Voltage
(VDDIO, VDDHS, VDDB
SSTL Input Voltage
)
−0.3V to +3.0V
−0.3V to (VDDQ + 0.3V)
−0.3V to (DVDD + 0.3V)
−0.3V to (DVDD + 0.3V)
−0.3V to (VDDHS + 0.3V)
−0.3V to (VDDHS + 0.3V)
+125˚C
>
HBM, 1.5 kΩ, 100 pF
EIAJ, 0Ω, 200 pF
2 kV
>
200 V
LVCMOS Input Voltage
LVCMOS Output Voltage
CML Receiver Input Voltage
CML Driver Output Voltage
Junction Temperature
Storage Temperature
Recommended Operating
Conditions
Min Typ Max Unit
Supply Voltage
−65˚C to +150˚C
VDDQ and DVDD to DGND
1.7 1.8 1.9
V
Lead Temperature
V
DDIO, VDDHS and VDDB to DGND or AGND
2.35 2.5 2.65
−40 25 85
Soldering, 4 Seconds
+260˚C
V
Temperature
˚C
<
<
Supply Noise Amplitude
Supply Noise Frequency
100mVP-P
1
MHz
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
SSTL_18 DC SPECIFICATIONS—Parallel I/O, Class I
VREF
VTT
Reference Voltage
Termination Voltage
0.83
VREF
0.04
0.90
0.97
VREF
0.04
V
V
−
+
VREF
VIH (dc)
VIH (ac)
VIL (dc)
VIL (ac)
High Level Input Voltage
AC Input Logic High
Low Level Input Voltage
AC Input Logic Low
VREF
+0.125
VREF
VDDQ
V
V
V
V
+0.300
+0.250
VREF
−0.125
VREF
−0.250
+50
−0.300
IIH
IIL
High Level Input Current
Low Level Input Current
VIN = VDDQ = 1.9 V
−10
−10
µA
µA
VIN = GND, VDDQ = 1.9 V
IOH = −6.3 mA, Unterminated,
CL = 8pF
+10
VOH (dc) High Level Output Voltage
VDDQ
−0.400
VDDQ
−0.550
V
V
Terminated, R = 50 Ω to VTT
VOL (dc) Low Level Output Voltage
IOL = 6.3 mA, Unterminated,
CL = 8pF
0.400
0.550
V
V
Terminated, R = 50 Ω to VTT
LVCMOS DC SPECIFICATIONS—Control Pins EIA/JESD8-7 Compliant
*
0.65
VIH
High Level Input Voltage
DVDD
V
V
DVDD
*
VIL
Low Level Input Voltage
0.35
0
DVDD
3
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise
specified. (Continued)
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
LVCMOS DC SPECIFICATIONS—Control Pins EIA/JESD8-7 Compliant
IIH
High Level Input Current
High Level Input Current
Low Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
VIN = DVDD = 1.9 V
(input and pull-low)
VIN = DVDD = 1.9 V
(input with pull-high)
VIN = GND, DVDD = 1.9 V
(input with pull-low)
VIN = GND, DVDD = 1.9 V
(input with pull-high)
IOH = −2 mA
0.1
mA
µA
IIH
−10
−10
+10
+10
IIL
µA
IIL
−0.1
mA
VOH
VOL
DVDD
−0.45
V
V
IOL = 2 mA
0.45
SUPPLY CURRENT
IDD Total Supply Current
K28.5 pattern at 2.5 Gbps with no
pre-emphasis. SSTL outputs no load
termination resistors, Tx high speed
serial outputs driving 100Ω
differential, no high speed Rx input
data.
VDDHS + VDDIO + VDDB
572
130
600
mA
mA
DVDD + VDDQ
136.5
PD
Total Power Consumption
K28.5 pattern at 2.5 Gbps with no
pre-emphasis. SSTL outputs no load
termination resistors, Tx high speed
serial outputs driving 100Ω
differential, no high speed Rx input
data.
SERDES and SSTL I/O
1708
1940
1500
mW
RECOMMENDED INPUT REFERENCE CLOCK (REFCLK ) AC coupled differential signal
VIDSRCLK Differential Input Voltage
Terminated by 50Ω parallel
termination
600
1.0
mVp-p
Figure 1
VICM
Common Mode Voltage
Terminated by 50Ω Parallel
Termination
VDDHS
−0.5
V
RREFCLK Input Termination to GND
Equivalent Parallel Input Termination
at REFCLK+ or REFCLK− to GND
100
50
Ω
fREF
REFCLK Frequency Range
REFCLK Frequency Variation
REFCLK Duty Cycle (Note 3)
106.25
−100
125
MHz
ppm
dfREF
tREF-DC
Variation from Nominal Frequency
Between 50% of the differential
voltage across REFCLK+ and
REFCLK−
+100
40
60
%
tREF-RJ
tREF-RJ
tREF-X
REFCLK Input
3
5
ps
ps
Random (rms) Jitter
REFCLK Input
25
40
Peak-to-Peak Jitter
REFCLK Transition Time
Figure 1
Transition time between 20% and
80% of the differential voltage across
REFCLK+ and REFCLK−
0.2
1
ns
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4
Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise
specified. (Continued)
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
SERIALIZER
DRDO
Transmit Data Rate
Data Rate at DO
High Data Rate Mode (EN_HDR = 1)
Low Data Rate Mode (EN_HDR = 0)
DO+, DO− are terminated by external
2.125
2.5
Gbps
Gbps
1.0625
1.25
VODS
Output Differential Voltage
Swing (DO+ − DO−) WITHOUT 50Ω to VDDHS
850
1065
1280
mVp-p
Pre-emphasis
PSEL1 = 0, PSEL0 = 0
Output Differential Voltage
Swing (DO+ − DO−) WITH
Pre-emphasis
DO+, DO− are terminated by external
50Ω to VDDHS
PSEL1 = 0, PSEL0 = 1
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL0 = 1
DO+, DO− are terminated by external
50Ω to VDDHS
PSEL1 = 0, PSEL0 = 0
DO+, DO− are terminated by external
50Ω to VDDHS
TBD
TBD
TBD
1330
1600
1850
TBD
TBD
TBD
mVp-p
VCM
Output Common Mode Offset
Voltage WITHOUT
VDDHS
−0.3
−10%
+10%
V
V
Pre-emphasis
Output Common Mode Offset
Voltage WITH Pre-emphasis
VDDHS
−0.37
VDDHS
−0.43
VDDHS
−0.50
PSEL1 = 0, PSEL0 = 1
−10%
+10%
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL0 = 1
RDO
Output Resistance
On-chip termination DO+ or DO− to
VDDHS, RTERM = 249Ω
DO+ or DO− to GND
45
50
1
55
Ω
pF
ps
CDO
Capacitance to GND
Serial Data Output Transition
Time
tDO-X
Measured between 20% and 80% of
VODS
100
120
160
0.13
JITDO-DJ Serial Data Output
Deterministic Jitter
Output K28.5 at 2.5 Gbps
0.1
UI
UI
(Peak-to-Peak),
(Notes 4, 5)
JITDO-RJ Serial Data Output Random
Jitter (Peak-to-Peak),
(Notes 4, 5)
Output D21.5 at 2.5 Gbps
0.13
0.2
0.15
JITDO-TJ Serial Data Output Total Jitter, Output K28.5 pattern at 2.5 Gbps at
0.25
48
UI
(Notes 4, 5)
BER of 10−12
tLAT-TX
Transmit Latency Figure 2
Transmit K28.5 from TD[0–9] to DO
at 2.5 Gbps, EN_10B = 1
35
45
Bits
Bits
ms
Transmit K28.5 from TD[0–9] to DO
at 2.5 Gbps, EN_10B = 0
58
tDO-LOCK Lock Time
Time to achieve frequency lock to
REFCLK. Output K28.5 at 2.5 Gbps.
0.5
DESERIALIZER
DRRI
Receive Data Rate
High Data Rate (EN_HDR = 1)
Low Data Rate (EN_HDR = 0)
RI+ – RI−
2.125
1.0625
200
2.5
Gbps
Gbps
mVp-p
1.25
1500
VIDSRI
RRI
Differential Input Voltage
Input Termination to VDDHS
On-chip termination RI+ to RI− to
VDDHS
EN_RAC = 0, RTERM = 249Ω:
45
50
55
Ω
5
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise
specified. (Continued)
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
DESERIALIZER
CRI
Input Capacitance to GND
Input Bias Voltage
RI+ or RI− to GND
1
pF
V
VRI-BIAS
DC bias at RI+ or RI− when
configure for AC couple
*
*
*
0.92
0.9
0.91
VDDHS
VDDHS
VDDHS
(EN_RAC = 1)
RRIAC
Equivalent Parallel Input
Termination
Equivalent parallel termination at RI+
or RI− to GND
EN_RAC = 1, RTERM = 249Ω:
Receive K28.5 from RI to RD[0–9]
at 2.5 Gbps, EN_10B = 1
Receive K28.5 from RI to RD[0–9]
at 2.5 Gbps, EN_10B = 0
Receiving RPAT pattern at 2.5Gbps
at BER of 10−12 of random jitter
(1.5MHz to 1.25GHz)
45
76
50
55
95
Ω
tLAT-RX
Receive Latency Figure 3
Bits
86
105
Bits
UI
JITRI-TL
Input Jitter Tolerance Without
Equalizer,
0.22
(Notes 4, 5)
Receiving RPAT pattern at 2.5Gbps
at BER of 10−12 of non-sinusoidal
deterministic jitter (1.5MHz to
1.25GHz)
0.5
UI
FFRI-LOCK Receiver Lock Range
Input data rate reference to local
transmit data rate
−200
+200
ppm
tRI-LOCK
LOSTH
Maximum Lock Time
Loss of Signal Detect
Thresholds
500
200
µs
Loss of Signal OFF
Loss of Signal ON
mVp-p
mVp-p
80
TLOSOFF Loss of Signal Detect Off
Timing
Loss of signal OFF time.
VIDS = 200 mVp-p
Loss of signal ON time.
VIDS = 80 mVp-p
100
100
µs
µs
TLOSON
Loss of Signal Detect on
Timing
TIMING SPECIFICATIONS—Serializer, Low-Data-Rate Mode at 1.25 Gbps, EN_HDR = 0
tS
Setup Time Figure 4
Hold Time Figure 4
TBC Frequency
TBC Falling Edge to TD[0–9] Valid
TBC Falling Edge to TD[0–9] Invalid
At Line Date Rate of 1.0625 Gbps
At Line Date Rate of 1.25 Gbps
1.4
1.4
ns
ns
tH
fTBC
106.25
125
MHz
MHz
TIMING SPECIFICATIONS—Serializer, High-Data-Rate Mode at 2.5 Gbps, EN_HDR = 1
tVALID
tSK
tTXCT
fTBC
Valid Time Figure 5
Edge Skew Figure 5
Transition Time Figure 5
TBC Frequency
TBC and TD[0–9] Valid
1.0
ns
ns
TBC and TD[0–9] Valid
1.5
3.0
TBC or TD[0–9] Transition Time
At Line Data Rate of 2.125 Gbps
At Line Data Rate of 2.5 Gbps
ns
106.25
125
MHz
MHz
TIMING SPECIFICATIONS—Deserializer, High-Data-Rate Mode at 2.5 Gbps, EN_RBC = 0
tS
Setup Time Figure 6
RBC1 or RBC0 Rising Edge to the
Corresponding Data Word at
RD[0–9] Valid
1.4
1.4
ns
ns
tH
Hold Time Figure 6
RBC1 or RBC0 Rising Edge to the
Corresponding Data Word at
RD[0–9] Invalid
tDC
Duty Cycle
RBC1 or RBC0 Duty Cycle
Rising Edge of RBC1 to Rising Edge
of RBC0
40
60
%
tA-B
RBC Clock Skew Figure 6
3.8
4.2
ns
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6
Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise
specified. (Continued)
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
TIMING SPECIFICATIONS—Deserializer, High-Data-Rate Mode at 2.5 Gbps, EN_RBC = 0
fRBC
RBC Frequency
At Line Date Rate of 2.125 Gbps
At Line Date Rate of 2.5 Gbps
106.25
125
MHz
MHz
TIMING SPECIFICATIONS—Deserializer, Low-Data-Rate Mode at 1.25 Gbps, EN_RBC = 0
tS
Setup Time Figure 6
Hold Time Figure 6
Duty Cycle
RBC1 Rising Edge to RD[0–9] Valid
RBC1 Rising Edge to RD[0–9] Invalid
RBC1 Duty Cycle
3.0
3.0
40
ns
ns
%
tH
tDC
tA-B
60
RBC Clock Skew Figure 6
Rising Edge of RBC1 to Rising Edge
of RBC0
7.6
8.4
ns
fRBC
RBC Frequency
At Line Date Rate of 1.0625 Gbps
At Line Date Rate of 1.25 Gbps
53.125
62.5
MHz
MHz
TIMING SPECIFICATIONS—Deserializer, High-Data-Rate Mode at 2.5 Gbps, EN_RBC = 1
tS
Setup Time Figure 7
Hold Time Figure 7
RBC Frequency
RBC1 Rising Edge to RD[0–9] Valid
RBC1 Rising Edge to RD[0–9] Invalid
At High Data Rate (EN_HDR = 1)
2.125 Gbps
1.4
1.4
ns
ns
tH
fRBC
212.5
MHz
At High Data Rate (EN_HDR = 1)
2.5 Gbps
250
0.6
MHz
ns
tXRBC
tX
RBC Transition Time
VREF − 0.25 V to VREF + 0.25V
For RD[0–9], CDET, LOS and ER
pins. Measured between 20% and
80% Levels
0.4
0.6
0.8
1.5
Output Data Transition Time
1.0
ns
TIMING SPECIFICATIONS—Deserializer, Low-Data-Rate Mode at 1.25 Gbps, EN_RBC = 1
tS
Setup Time Figure 7
Hold Time Figure 7
RBC Frequency
RBC1 Rising Edge to RD[0–9] Valid
RBC1 Rising Edge to RD[0–9] Invalid
At Low Data Rate (EN_HDR = 0)
1.0625 Gbps
3.0
3.0
ns
ns
tH
fRBC
106.25
125
MHz
MHz
At Low Data Rate (EN_HDR = 0)
1.25 Gbps
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at V
= 1.8 V, DV = 1.8 V, V
= 2.5 V, V
= 2.5 V,V
= 2.5 V, T = 25˚C. They are for reference purposes,
DDB A
DDQ
DD
DDHS
DDIO
and are not production-tested.
Note 3: Duty cycle is defined as high period (t ) or low period (t ) ratio to clock period (t
+ t ), measured at 50% of the differential voltage across REFCLK+
WL
WH
WL
WH
and REFCLK−.
Note 4: K28.5 is a repeating periodic pattern (hex: 283, 17C - bin: 110000 0101, 001111 1010). D21.5 is a repeating periodic pattern (hex: 155 - bin: 1010101010).
RPAT is a random data pattern with valid 8b/10b data codes of K28.5, K28.5, D3.1, D7.2, D11.3, D15.4, D19.5, D23.6, D27.7, D20.0, D21.1, D25.2 (hex: 283, 283,
263, 2B8, 30B, 2C5, 153, 197, 1E4, 0B4, 255, 299).
Note 5: Output Jitter and Jitter Tolerance are measured through characterization on sample basis. They are not production-tested. Output jitter is measured at a
sample size of TBD. REFCLK differential amplitude is 1.2 V
with jitter of 3 ps (rms) or 25 ps (pk-pk) for Tx output jitter testing.
p-p
7
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AC Timing Diagrams
20030104
FIGURE 1. REFCLK Timing
20030105
FIGURE 2. Transmit Latency (High Data Rate Mode)
20030106
FIGURE 3. Receive Latency (EN_RBC = 1)
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8
AC Timing Diagrams (Continued)
20030107
FIGURE 4. Transmit Input Data Bus Timing—Low Data Rate Mode
20030108
FIGURE 5. Transmit Input Data Timing—High Data Rate Mode
20030109
FIGURE 6. Receive Output Data Bus Timing—Low Data Rate or High Data Rate Mode (EN_RBC = 0)
9
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AC Timing Diagrams (Continued)
20030110
FIGURE 7. Receive Output Data Bus Timing—Low Data Rate or High Data Rate Mode (EN_RBC = 1)
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10
Termination at the High Speed Interface
20030111
FIGURE 8. High Speed Interface — Direct-Coupled Mode (EN_RAC = 0)
20030112
FIGURE 9. High Speed Interface — AC-Coupled Mode (EN_RAC = 1)
11
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Termination at REFCLK
20030113
FIGURE 10. LVDS Terminations at REFCLK
20030114
FIGURE 11. LVPECL Terminations at REFCLK
The inputs to the DS25C400 have parallel termination resis-
tors, thevenin equivalent to 100Ω single-ended. The value of
R1 and R2 must be selected such that VT = VDD − 2V and
that the equivalent resistance is also 100Ω single-ended.
Termination values for different VDD supply voltages:
For VDD = 2.5V; R1 = 500 Ω; R2 = 125.5 Ω
For VDD = 3.3V; R1 = 253 Ω; R2 = 165 Ω
For VDD = 5.0V; R1 = 167 Ω; R2 = 250 Ω
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Termination at the Parallel I/O Interface
20030116
FIGURE 12. SSTL_18 Class 1, 1.8V HSTL or 1.8V LVCMOS I/O Termination
13
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14
Pin Descriptions
Pin
I/O,
Type
Pin #
Name
Description
HIGH SPEED DIFFERENTIAL I/O
DO_A+
DO_A−
D20
E20
O, CML
Inverting and non-inverting high speed CML differential outputs of the
serializer, channel A. On-chip termination resistors connect from DO_A+ and
DO_A− to VDDHS
.
DO_B+
DO_B−
L20
K20
O, CML
O, CML
O, CML
Inverting and non-inverting high speed CML differential outputs of the
serializer, channel B. On-chip termination resistors connect from DO_B+ and
DO_B− to VDDHS
.
DO_C+
DO_C−
M20
N20
Inverting and non-inverting high speed CML differential outputs of the
serializer, channel C. On-chip termination resistors connect from DO_C+ and
DO_C− to VDDHS
.
DO_D+
DO_D−
W20
V20
Inverting and non-inverting high speed CML differential outputs of the
serializer, channel D. On-chip termination resistors connect from DO_D+ and
DO_D− to VDDHS
.
RI_A+
RI_A−
E22
F22
I, CML
I, CML
I, CML
I, CML
Inverting and non-inverting high speed differential inputs of the deserializer,
channel A. On-chip termination resistors connect from RI_A+ and RI_A− to
VDDHS
.
RI_B+
RI_B−
J22
Inverting and non-inverting high speed differential inputs of the deserializer,
channel B. On-chip termination resistors connect from RI_B+ and RI_B− to
H22
VDDHS
.
RI_C+
RI_C−
P22
R22
Inverting and non-inverting high speed differential inputs of the deserializer,
channel C. On-chip termination resistors connect from RI_C+ and RI_C− to
VDDHS
.
RI_D+
RI_D−
V22
U22
Inverting and non-inverting high speed differential inputs of the deserializer,
channel D. On-chip termination resistors connect from RI_D+ and RI_D− to
VDDHS
.
DIFFERENTIAL REFERENCE CLOCK
REFCLK+
REFCLK−
A15
A14
I, CML or AC
coupled inputs
Inverting and non-inverting differential reference clock to the clock
synthesizers for clock generation. A low jitter clock source should be
connected to REFCLK . The REFCLK is shared by all four channels.
PARALLEL I/O DATA
D11
TD_A[0]
TD_A[1]
TD_A[2]
TD_A[3]
TD_A[4]
TD_A[5]
TD_A[6]
TD_A[7]
TD_A[8]
TD_A[9]
TD_B[0]
TD_B[1]
TD_B[2]
TD_B[3]
TD_B[4]
TD_B[5]
TD_B[6]
TD_B[7]
TD_B[8]
TD_B[9]
I, SSTL_18,
Pull-Low
Transmit data word for channel A.
C11
B11
A11
B10
D9
B9
D8
C8
B8
L3
In the 10-bit mode, the 10-bit code-group at TD_A[0–9] is serialized with the
internal 8b/10b encoder disabled. Bit 9 is the MSB.
In the 8-bit mode, TD_A[0–7] is first converted into 10-bit code-group by the
internal 8b/10b encoder before it is serialized. Bit 7 is the MSB. TD_A[8] is
used as K-code select pin. When TD_A[8] is low, TD_A[0–7] is mapped to
the corresponding 10-bit D-group. When TD_A[8] is high, TD_A[0–7] is
mapped to the corresponding 10-bit K-group. The 8b/10b code group
conversion is implemented in according to 802.3z standard.
I, SSTL_18,
Pull-Low
Transmit data word for channel B.
L2
In the 10-bit mode, the 10-bit code-group at TD_B[0–9] is serialized with the
internal 8b/10b encoder disabled. Bit 9 is the MSB.
K4
K3
K2
J2
In the 8-bit mode, TD_B[0–7] is first converted into 10-bit code-group by the
internal 8b/10b encoder before it is serialized. Bit 7 is the MSB. TD_B[8] is
used as K-code select pin. When TD_B[8] is low, TD_B[0–7] is mapped to
the corresponding 10-bit D-group. When TD_B[8] is high, TD_B[0–7] is
mapped to the corresponding 10-bit K-group.
J1
H4
H2
H1
15
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Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
PARALLEL I/O DATA
TD_C[0]
TD_C[1]
TD_C[2]
TD_C[3]
TD_C[4]
TD_C[5]
TD_C[6]
TD_C[7]
TD_C[8]
TD_C[9]
TD_D[0]
TD_D[1]
TD_D[2]
TD_D[3]
TD_D[4]
TD_D[5]
TD_D[6]
TD_D[7]
TD_D[8]
TD_D[9]
TBC_A
M3
I, SSTL_18,
Pull-Low
Transmit data word for channel C.
M2
In the 10-bit mode, the 10-bit code-group at TD_C[0–9] is serialized with the
internal 8b/10b encoder disabled. Bit 9 is the MSB.
N3
N2
In the 8-bit mode, TD_C[0–7] is first converted into 10-bit code-group by the
internal 8b/10b encoder before it is serialized. Bit 7 is the MSB. TD_C[8] is
used as K-code select pin. When TD_C[8] is low, TD_C[0–7] is mapped to
the corresponding 10-bit D-group. When TD_C[8] is high, TD_C[0–7] is
mapped to the corresponding 10-bit K-group.
N1
P2
P1
R4
R2
R1
AA11
AB11
W10
Y10
AA10
AA9
W8
Y8
I, SSTL_18,
Pull-Low
Transmit data word for channel D.
In the 10-bit mode, the 10-bit code-group at TD_D[0–9] is serialized with the
internal 8b/10b encoder disabled. Bit 9 is the MSB.
In the 8-bit mode, TD_D[0–7] is first converted into 10-bit code-group by the
internal 8b/10b encoder before it is serialized. Bit 7 is the MSB. TD_D[8] is
used as K-code select pin. When TD_D[8] is low, TD_D[0–7] is mapped to
the corresponding 10-bit D-group. When TD_D[8] is high, TD_D[0–7] is
mapped to the corresponding 10-bit K-group.
AA8
AB8
A8
I, SSTL_18,
Pull-Low
Transmit byte clock for channel A.
Transmit byte clock for channel B.
Transmit byte clock for channel C.
Transmit byte clock for channel D.
TBC_B
TBC_C
TBC_D
G2
T2
I, SSTL_18,
Pull-Low
I, SSTL_18,
Pull-Low
W7
I, SSTL_18,
Pull-Low
RD_A[0]
RD_A[1]
RD_A[2]
RD_A[3]
RD_A[4]
RD_A[5]
RD_A[6]
RD_A[7]
RD_A[8]
RD_A[9]
RD_B[0]
RD_B[1]
RD_B[2]
RD_B[3]
RD_B[4]
RD_B[5]
RD_B[6]
RD_B[7]
RD_B[8]
RD_B[9]
D6
B6
A6
D5
C5
B5
D4
C4
B4
A3
F4
F3
F1
E4
E3
E1
D3
D2
C2
C1
O, SSTL_18
Deserialized receive data word for channel A.
In the 10-bit mode, RD_A[0–9] is the deserialized received data word in
10-bit code group. Bit 9 is the MSB.
In the 8-bit mode, RD_A[0–7] is the deserialized received data byte. Bit 7 is
the MSB. RD_A[9] is the 8b/10b error monitor. RD_A[8] is the K-group
indicator. A low at RD_A[8] indicates RD_A[0–7] belongs to the D-group,
while a high indicates it belongs to the K-group.
O, SSTL_18
Deserialized receive data word for channel B.
In the 10-bit mode, RD_B[0–9] is the deserialized received data word in
10-bit code group. Bit 9 is the MSB.
In the 8-bit mode, RD_B[0–7] is the deserialized received data byte. Bit 7 is
the MSB. RD_B[9] is the 8b/10b error monitor. RD_B[8] is the K-group
indicator. A low at RD_B[8] indicates RD_B[0–7] belongs to the D-group,
while a high indicates it belongs to the K-group.
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16
Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
PARALLEL I/O DATA
RD_C[0]
RD_C[1]
RD_C[2]
RD_C[3]
RD_C[4]
RD_C[5]
RD_C[6]
RD_C[7]
RD_C[8]
RD_C[9]
RD_D[0]
RD_D[1]
RD_D[2]
RD_D[3]
RD_D[4]
RD_D[5]
RD_D[6]
RD_D[7]
RD_D[8]
RD_D[9]
RBC0_A
RBC1_A
RBC0_B
RBC1_B
RBC0_C
RBC1_C
RBC0_D
RBC1_D
VREF1
U4
O, SSTL_18
Deserialized receive data word for channel C.
U3
In the 10-bit mode, RD_C[0–9] is the deserialized received data word in
10-bit code group. Bit 9 is the MSB.
V4
V2
In the 8-bit mode, RD_C[0–7] is the deserialized received data byte. Bit 7 is
the MSB. RD_C[9] is the 8b/10b error monitor. RD_C[8] is the K-group
indicator. A low at RD_C[8] indicates RD_C[0–7] belongs to the D-group,
while a high indicates it belongs to the K-group.
V1
W4
W2
Y3
Y2
Y1
W6
AB6
W5
Y5
O, SSTL_18
Deserialized receive data word for channel D.
In the 10-bit mode, RD_D[0–9] is the deserialized received data word in
10-bit code group. Bit 9 is the MSB.
In the 8-bit mode, RD_D[0–7] is the deserialized received data byte. Bit 7 is
the MSB. RD_D[9] is the 8b/10b error monitor. RD_D[8] is the K-group
indicator. A low at RD_D[8] indicates RD_D[0–7] belongs to the D-group,
while a high indicates it belongs to the K-group.
AA5
Y4
AA4
AA3
AB3
AA2
A7
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, Analog
Complementary receive byte clocks for channel A.
Complementary receive byte clocks for channel B.
Complementary receive byte clocks for channel C.
Complementary receive byte clocks for channel D.
D7
G1
G4
U2
T4
AA6
AB7
B3
SSTL_18 reference voltages. Generated internally by a resistive divider from
VDDQ to DGND. A X7R 0.01 µF bypass capacitor should be connected from
each VREF pin to GND plane.
VREF2
AB2
LINE STATUS
LOS_A
C18
B18
A18
D17
B7
O, LVCMOS
O, LVCMOS
O, LVCMOS
O, LVCMOS
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
O, SSTL_18
Signal detector output.
LOS_B
0 = Signal level at RI above signal detector’s ON threshold.
1 = Signal level at RI below signal detector’s OFF threshold.
LOS_C
LOS_D
CDET_A
CDET_B
CDET_C
CDET_D
ER_A
Comma Detected.
G3
Logic high at CDET indicates that the internal Comma Detector detects a
Comma bit sequence from the incoming bit stream. The serial to parallel
converter is aligned to the proper 10-bit word boundary.
PRBS Error when EN_ERR is low, 8b/10b disparity or code violation error
when EN_ERR is high. Upon detection of an error, ER will go high for one
word period.
T3
AA7
AA15
W14
Y15
AB16
ER_B
ER_C
ER_D
BIAS REFERENCE
RTERM
W12
I, Analog
I, Analog
An external resistor is connected from RTERM to RTERM_RTN for use as
reference to control process variation of the internal on-chip terminations. An
external resistor of 249Ω 1% provides an on-chip termination of 50Ω
10%.
RTERM_RTN
AB13
17
www.national.com
Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
BIAS REFERENCE
RbiasTx
Y14
I, Analog
An external resistor is connected from RbiaxTx to RBIAS_RTN to set up the
proper internal bias Tx current. An external resistor is connected from
RbiasRx to RBIAS_RTN to set up the proper internal bias Rx current. The
external resistor should be 6.3 kΩ 1%.
RbiasRx
W13
I, Analog
I, Analog
RBIAS_RTN
AB14
CONFIGURATION CONTROL—AFFECT ALL FOUR CHANNELS
EN_CDET
C17
I, CMOS,
Pull-High
Enable Comma Detector to align the correct bit boundary of the 10-bit word.
1 = Enables Comma Detector.
0 = Disable Comma Detector.
EN_10B
D14
I, CMOS,
Pull-High
Enable 10-bit mode.
1 = Selects 10-bit mode. Disables internal 8b/10b encoder and decoder.
0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder.
0 = Selects low-data-rate mode for the serdes.
EN_HDR
EN_RBC
EN_RAC
C16
D16
A16
I, CMOS,
Pull-High
I, CMOS,
Pull-Low
I, CMOS,
Pull-High
1 = Selects high-data-rate mode for the serdes.
0 = RBC1 and RBC0 strobe even and odd data word at RD[0–9].
1 = Data words at RD[0–9] are strobed by RBC1.
0 = Connects internal CML input 50Ω terminations from RI+ and RI− to
VDDHS
.
1 = Configure internal termination resistors to form an internal bias network
for RI+ and RI− when AC coupling is used. The divider forms a parallel
termination of 50Ω. Please refer to Figures 8, 9.
Local parallel loopback from TD[0–9] to RD[0–9] have been removed and
only serial local loopback is functional. User should tie this pin to DGND or
leave open.
EN_PLB
EN_SLB
EN_LOS
C14
C13
C12
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
Local serial loopback.
1 = Enables internal local serial loopback.
0 = Disables internal local serial loopback.
I, CMOS,
Pull-Low
Loss Of Signal Output Control
0 = enables the LOS output control of RD[0-9] (output will be pull-high when
LOS is detected)
1 = disable the LOS output control of RD[0-9] (output will not be pull-high).
Select internal test pattern generator.
EN_PTN1
EN_PTN0
C15
B15
I, CMOS,
Pull-Low
EN_PTN1EN_PTN0
0
0:
Disable internal test pattern generator for normal
operation.
0
1
1
1:
0:
1:
Enable internal PRBS = 27−1 pattern generator.
Enable D21.5 - Alterating 1_0 pattern.
Enable repeating K28.5 pattern.
EN_ERR
D15
I, CMOS,
Pull-Low
Enable and synchronize the internal PRBS error checker in the receivers,
and select types of errors detected.
0 = Enables internal PRBS error checker. Receiver expects pseudo-random
pattern (27 − 1) bit stream. ER_n pin only reports any PRBS error detected.
EN_ERR must be pulsed high then low with a minimum pulse period of 10
µs to synchronize the internal PRBS checker.
1 = Disable internal PRBS error checker for normal operation. ER_n pin only
reports 8b/10b code error or disparity error detected.
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18
Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
CONFIGURATION CONTROL—AFFECT INDIVIDUAL CHANNEL
PSEL0_A
PSEL1_A
W15
I, CMOS,
Pull-Low
Pre-emphasis select for channel A CML driver.
AA16
Select one of the three pre-emphasis current-drive settings for output drivers.
See Functional Description.
PSEL0_A and PSEL1_A should be tied to DGND if no pre-emphasis is
needed.
PSEL0_B
PSEL1_B
AB17
W16
I, CMOS,
Pull-Low
Pre-emphasis select for channel B CML driver.
Select one of the three pre-emphasis current-drive settings for output drivers.
See Functional Description.
PSEL0_B and PSEL1_B should be tied to DGND if no pre-emphasis is
needed.
PSEL0_C
PSEL1_C
W17
I, CMOS,
Pull-Low
Pre-emphasis select for channel C CML driver.
AA17
Select one of the three pre-emphasis current-drive settings for output drivers.
See Functional Description.
PSEL0_C and PSEL1_C should be tied to DGND if no pre-emphasis is
needed.
PSEL0_D
PSEL1_D
AA18
AB18
I, CMOS,
Pull-Low
Pre-emphasis select for channel D CML driver.
Select one of the three pre-emphasis current-drive settings for output drivers.
See Functional Description.
PSEL0_D and PSEL1_D should be tied to DGND if no pre-emphasis is
needed.
EQ0_A
EQ1_A
A22
A21
I, CMOS,
Pull-Low
Receive equalization select for channel A.
Select one of the three equalization filters to compensate for transmission
medium’s frequency response. See Functional Description.
EQ0_A and EQ1_A should be tied to DGND if no equalization is needed.
Receive equalization select for channel B.
EQ0_B
EQ1_B
B21
B20
I, CMOS,
Pull-Low
Select one of the three equalization filters to compensate for transmission
medium’s frequency response. See Functional Description.
EQ0_B and EQ1_B should be tied to DGND if no equalization is needed.
Receive equalization select for channel C.
EQ0_C
EQ1_C
A19
C19
I, CMOS,
Pull-Low
Select one of the three equalization filters to compensate for transmission
medium’s frequency response. See Functional Description.
EQ0_C and EQ1_C should be tied to DGND if no equalization is needed.
Receive equalization select for channel D.
EQ0_D
EQ1_D
B19
D18
I, CMOS,
Pull-Low
Select one of the three equalization filters to compensate for transmission
medium’s frequency response. See Functional Description.
EQ0_D and EQ1_D should be tied to DGND if no equalization is needed.
Power down control signals.
PD0
PD1
AA12
W11
I, CMOS,
Pull-Low
PD1
PD0
0
0
1
1
0
1
0
1
All 4 channels powered down
Only Channel A powered up
Channels A and B powered up
All 4 channels powered up
RESERVED TEST PINS
RES1
RES2
RES3
AB15
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
Loop filter test points.
User should tie this pin to DGND or leave open.
Termination resistor calibration.
D13
User should tie this pin to DGND or leave open.
REFCLK rate select.
A17
User should tie this pin to DGND or leave open.
19
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Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
RESERVED TEST PINS
RES4
RES5
RES6
RES7
RES8
RES9
RES10
RES11
RES12
D19
L22
O, Analog
Loop filter test points.
Leave open (no connection).
M22
W19
G20
H20
R20
T20
B13
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, CMOS,
Pull-Low
I, Power/
I, CMOS,
Pull-High
I, Power/
I, CMOS,
Pull-High
I, Power/
I, CMOS,
Pull-High
I, Power/
I, CMOS,
Pull-High
User should tie this pin to DGND or leave open.
User should tie this pin to DGND or leave open.
Leave open (no connection).
RES13
RES15
RES16
RES17
RES18
RES19
RES20
B12
AB19
AA19
Y19
Leave open (no connection).
Leave open (no connection).
AB20
AA20
AA21
Leave open (no connection).
Leave open (no connection).
User should tie this pin to DVDD or leave open.
RES21
RES22
RES23
W18
AB21
Y18
User should tie this pin to DVDD or leave open.
Leave open (no connection).
Leave open (no connection).
POWER
VDDQ
B2, C3,
D1, F2,
J3, L1,
I, Power
VDDQ = 1.8V 5%. It powers the SSTL interface. A X7R 0.01 µF bypass
capacitor should be connected from each VDDQ pin to DGND plane.
M4, P3,
T1, V3,
AA1,
AB4, Y6,
AB9, Y11,
AA13,
Y17, A10,
C7, A5
DVDD
U20, U21, I, Power
P20, P21,
DVDD = 1.8V 5%. Power to internal logic. A X7R 0.01 µF bypass capacitor
should be connected from each DVDD pin to DGND plane.
J20, J21,
F20, F21
www.national.com
20
Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
POWER
VDDHS
Y22,
I, Power
VDDHS = 2.5V 5%. It powers the high speed CML I/O circuitry, the analog
PLL circuitry, and reference clock buffer. A X7R 0.01 µF bypass capacitor
should be connected from each VDDHS pin to AGND plane.
W21,
W22,
T19, T21,
T22, N21,
M19,
K21, G19,
G21,
G22,
D21, D22,
C22, A20,
B16, A13
K1, N4,
Y9, D10
Y13
VDDIO
VDDB
I, Power
I, Power
VDDIO = 2.5V 5%. Power to Parallel I/O input buffers. A X7R 0.01 µF
bypass capacitor should be connected from each VDDIO pin to DGND plane.
VDDB = 2.5V 5%. Power to BIAS circuit. A X7R 0.01 µF bypass capacitor
should be connected from each VDDB pin to DGND plane.
GROUND
DGND
C10, J4,
P4, W9,
A1, B1,
A2, E2,
H3, L4,
M1, R3,
U1, W1,
W3, AB1,
AB5, Y7,
AB10,
I, Ground
Digital ground pins. DGND should be tied to a solid ground plane through a
low inductive path.
Y12,
AA14,
Y16,
AB22, A4,
A9, C9,
C6,
AB12,
V21, U19,
P19, N19,
K19, J19,
F19, E21,
J[9–11],
K[9–11],
L[9–11],
M[9–11],
N[9–11],
P[9–11]
21
www.national.com
Pin Descriptions (Continued)
Pin
Name
I/O,
Type
Pin #
Description
GROUND
AGND
A12, B14, I, Ground
B17, B22,
C20, C21,
D12, E19,
H19, H21,
K22, L19,
L21, M21,
N22, R19,
R21, V19,
Y20, Y21,
AA22,
Analog ground pins. AGND should be tied to a solid ground plane through a
low inductive path.
J[12–14],
K[12–14],
L[12–14],
M[12–14],
N[12–14],
P[12–14]
Note:
I = Input
O = Output
Pull-Low = input pin is pulled-low by an internal resistor.
Pull-High = input pin is pulled-high by an internal resistor.
directly to DO . The Tx output jitter specification is relaxed
below a frequency of bit rate/1,667 because the Rx PLL can
Functional Descriptions
The serial interface is optimized for backplane applications
with user selectable pre-emphasis at driver and/or equaliza-
tion filters at receivers. A typical point-to-point backplane link
consists of two high-speed connectors (such as Teradyne
HSD family) and 20 inches 100Ω coupled differential traces
usually implemented with strip-lines on FR4 or Getek board
material.
track very low frequency jitter. To ensure good output jitter
performance, REFCLK should be free from excessive low
frequency jitter and have random jitter less than 30–40 ps
p-p. The REFCLK input amplitude should be a minimum of
1 Vp-p differential for the best Tx output jitter performance.
The reference clock input has an internal bias network that
sets its common mode voltage to 1.75V. The REFCLK dif-
ferential input impedance is 200Ω. To terminate into 100Ω
differential, an additional external 200Ω termination imped-
ance is required. If the common mode voltage of the driver
does not match the REFCLK common mode voltage cou-
pling capacitors can be used to remove the driver DC volt-
age. This AC coupled mode allows the REFCLK to be inter-
faced to LVDS, PECL, LVPECL, LVEP, PECL, and other
differential logic levels. See Figures 10, 11.
REFERENCE CLOCK
Each of the four serializers is clocked by a high speed clock
derived from its own internal low jitter clock synthesizer,
which is phase-locked to the input clock at REFCLK . No
external components are required for the clock synthesizing
PLL’s. REFCLK should be a differential CML, or AC
coupled differential clock. Any termination resistors should
be located close to the REFCLK input pins. REFCLK
should be connected to a balanced differential clock from a
crystal source or clock driver.
The frequency range of REFCLK is 106.25 - 125 MHz to
support data rate of 1.0625 - 1.25 Gbps or 2.125 - 2.5 Gbps
at high data rate mode. The frequency accuracy should be
better than 100 ppm.
The clock synthesizers are low pass in nature. REFCLK jitter
above 10 MHz will be attenuated by the Tx PLL. Any low
frequency jitter component at REFCLK will be transferred
REFCLK
(RES3=0)
Transmit and Receive Data Rate
(Low Data Rate Mode, EN_HDR=0)
Transmit and Receive Data Rate
(High Data Rate Mode, EN_HDR=1)
2.125 Gbps
106.25 MHz
125.00 MHz
1.0625 Gbps
1.25 Gbps
2.500 Gbps
TRANSMIT PARALLEL INPUT DATA
When the 8-bit mode is enabled (EN_10B=0), an internal
8b/10b encoder is activated to convert TD[0–8] into the
corresponding 10-bit code group. TD[0–7] is the data byte,
while TD[8] is used as the D-group or K-group qualifier.
Each serializer accepts parallel transmit data at TD[0–9],
clocked in by an input clock TBC. TBC must be synchronized
to REFCLK 100 ppm. An input FIFO is used to compensate
for the phase difference between TBC and the internal byte
clock that samples TD[0–9].
www.national.com
22
switching is used. TD[0–9] transitions are synchronous to
both the rising and falling edges of TBC. The frequency of
TBC is thus half the transfer rate frequency at TD[0–9]. See
Figure 5.
Functional Descriptions (Continued)
When 10-bit mode is used (EN_10B=1), the serializer ex-
pects coded 10-bit data at TD[0–9], with its internal 8b/10b
encoder disabled.
In the low-data-rate mode, (EN_HDR=0), the serializer runs
at half data rate. TD[0–9] is clocked in at the falling strobe
edge of TBC. See Figure 4.
The serializer can be configured in the high-data-rate mode
or low-data-rate mode determined by EN_HDR pin. In the
high-data-rate mode (EN_HDR=1), source-synchronous
TBC at Low-Data-Rate Mode
Transfer Rate at TD[0–9]
Line Rate at DO
REFCLK (RES3=0)
(EN_TDR=0)
= Line Rate / 10
106.25 MHz
125.0 MHz
106.25 MHz
125 MHz
106.25 Mword/s
125 Mword/s
1.0625 Gbps
1.25 Gbps
TBC at High-Data-Rate Mode
(EN_HDR=1)
Transfer Rate at TD[0–9]
= Line Rate / 10
212.5 Mword/s
REFCLK (RES3=0)
Line Rate at DO
106.25 MHz
125.0 MHz
106.25 MHz
2.125 Gbps
2.50 Gbps
125 MHz
250 Mword/s
The internal 10-bit coded data word is serialized and clocked
out at DO . Bit 0 (LSB) of the 10-bit code-group is shifted
out first.
10%. The limiting amplifier is capable to work with mini-
mum input differential voltage of 200 mVp-p across RI+ and
RI−.
TD[0–9] and TBC are single-ended SSTL logic. They expect
input signal swing of 1.8V, and switch at approximately 0.9V.
When serial bit stream is AC coupled to RI , the internal
termination resistors can be configured as a divider to pro-
vide DC bias to RI+ and RI−, and form an equivalent 50Ω
parallel termination. EN_RAC is set to logic high to enable
the receiver’s bias network.
TRANSMIT SERIAL DATA OUTPUT
The serialized data bit stream is output at DO , driven by a
differential current mode logic (CML) driver. Both DO+ and
DO− are terminated with on-chip resistors to VDDHS. The
values of the internal termination resistors are tightly con-
trolled to 50Ω 10%.
With an external load of 50Ω to VDDHS or AC coupled to
GND, the driver provides single-ended voltage swing of
533 mV nominal, with a common mode voltage of about
(VDDHS −0.27V). To compensate against edge degradation
due to bandwidth-limited transmission medium, the driver
has 3 selectable steps of pre-emphasis providing additional
current drive for one bit period following a data level transi-
tion. The pre-emphasis improves signal quality at the receiv-
ing end of the transmission medium and enhances error rate
performance of the downstream receiver.
SIGNAL DETECT
The signal detect circuit generates a Loss of Signal (LOS) to
indicate the amplitude of incoming serial data is less than
minimum level allowed by the link budget. Its purpose is to
indicate a complete loss of signal such as a disconnected or
broken cable. A poor quality link may provide enough signal
for LOS to remain off, even though the signal level is non-
compliant and the BER objective is not met. Hysteresis is
used to so that the LOS output does not rapidly change state
with small variations in received power. The lower bound is
set high enough so that Near End Cross Talk (NEXT) will not
cause a false signal detect. When the input differential volt-
age at RI falls below 80 mVp-p max, Loss of Signal Detect
Indicator is turned on (LOS=1) to signal for invalid data
transmission. RD[0–9] are forced high during loss of signal.
Once LOS has gone high the input signal must reach the
higher differential voltage of 200 mV (max) to indicate that
the incoming signal is above the minimum level. Common
control pin EN_LOS is a LOS output control pin. When
EN_LOS = 1, the LOS circuit which control the RD[0-9]
outputs are disabled. The RD[0-9] will not be forced high
upon LOS detection.
PSEL1
PSEL0
Descriptions
Pre-emphasis disabled. Drive
current = 24 mA.
0
0
0
1
1
1
0
1
Pre-emphasis enabled. Drive
current = 29.3 mA at first bit after
data transition.
Pre-emphasis enabled. Drive
current = 34.7 mA at first bit after
data transition.
EQUALIZATION
The receiver front-end provides 3 steps of equalization filter
to improve the eye opening of the input data at RI . The
equalization filter is a first order, designed to equalize trans-
mission loss and reduce ISI for long board traces in a
backplane.
Pre-emphasis enabled. Drive
current = 39.7 mA at first bit after
data transition.
Note: The Pre-emphasis current is only applied to the load termination for
the first bit after a data transition. However, the pre-emphasis current in-
creases the power supply DC current by the same amount. For power and
thermal calculations consideration must be paid to on chip vs. off chip power
dissipation.
EQ1
EQ0
Descriptions
Equalization disabled
0
0
0
1
Equalization filter’s zero location
set at about 800 MHz
RECEIVE SERIAL DATA INPUT
The receiver front-end is a limiting amplifier with on-chip
CML terminations from RI+ and RI− to VDDHS. The values of
the internal termination resistors are tightly controlled to 50Ω
1
0
Equalization filter’s zero location
set at about 500 MHz
23
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The re-timed bit stream is deserialized into 10-bit word
clocked by the recovered clock. In the 10-bit mode
(EN_10B=1), the parallel recovered data code-group is out-
put at RD[0–9]. In the 8-bit mode (EN_10B=0), the internal
8b/10b decoder is enabled to convert the 10-bit code-group
into the corresponding 8-bit data byte and output at RD[0–7].
RD[8] is used as qualifier to indicate if RD[0–7] belongs to
the D-group (RD8=0), or K-group (RD8=1). RD[9] is used as
a second error pin that is only used to flag 8b/10b code and
disparity errors.
Functional Descriptions (Continued)
EQ1
EQ0
Descriptions
Equalization filter’s zero location
set at about 400 MHz
1
1
DESERIALIZER
The clock and data recovery PLL accepts serial NRZ
re-shaped bit stream from the receiver front-end. It recovers
clock from the incoming bit stream, and re-times the data. It
is optimized to work with 10-bit coded bit stream to maintain
DC balance and ensure enough edge transitions to maintain
synchronization. The data rate of the PLL can be 2.125 - 2.5
Gbps or 1.0625 - 1.25 Gbps determined by REFCLK and
EN_HDR. In the absence of input bit stream, the PLL is
centered to the internal local transmit clock. It is capable to
re-time data with maximum frequency tolerance of 200
ppm from its local transmit clock. No external component is
needed for the PLL.
Two recovered byte clock RBC0 and RBC1 are available for
clocking the parallel data bus RD[0–9]. RBC0 and RBC1 are
180˚ out of phase. Users can latch even- and odd-numbered
data word at RD[0–9] with the rising edge of successive
RBC1 and RBC0. RBC0 and RBC1 have half the transfer
rate frequency. In the low-data-rate mode (EN_HDR=0), the
deserializer runs at half data rate.
When EN_RBC=1, RBC frequency is same as the bus trans-
fer rate. Each rising edge of RBC1 strobes data word at
RD[0–9]. See Figure 7.
RBC1 (EN_RBC=1)
RBC0, RBC1 (EN_RBC=0)
See Figure 6
Transfer Rate at RD[0–9]
= Line Rate / 10
212.5 Mword/s
Line Rate at RI
(High Data Rate Mode)
See Figure 7
212.5 MHz
250.0 MHz
106.25 MHz
2.125 Gbps
2.50 Gbps
Line Rate at DO
(Low Data Rate Mode)
1.0625 Gbps
1.25 Gbps
125 MHz
250 Mword/s
Transfer Rate at RD[0–9]
= Line Rate / 10
RBC1 (EN_RBC=1)
RBC0, RBC1 (EN_RBC=0)
106.25 MHz
125 MHz
53.125 MHz
62.5 MHz
106.25 Mword/s
125 Mword/s
When parallel data is serialized, the character alignment is
lost. The Deserializer uses Comma character detection to
establish the correct bit boundary of the 10-bit word. This
process is called “code-group alignment”. When a Comma
character is detected, the CDET indicator is pulsed high, the
corresponding Comma character is output at RD[0–9] (10-bit
mode), or RD[0–8] (8-bit mode). During the alignment,
RBC1 is stretched and the rising edge of RBC1 is aligned
with the Comma character. The code-group alignment is
enabled by EN_CDET active. When EN_CDET is low, the
CDET indicator still functions, but no alignment is initiated
when a comma character is detected.
BIST
DS25C400 has a built-in 27−1 PRBS (pseudo-random bit
sequence) generator, an alternating 1_0 generator, and a
repeating
K28.5 pattern, selected by EN_PTN0 and
EN_PTN1. When internal pattern generator is enabled, the
parallel input data at TD[0–9] are ignored. The Serializer
converts the test pattern into serial bit stream at DO . When
the internal PRBS pattern is selected (EN_PTN1=0,
EN_PTN0=1), an external bit error rate tester can be used to
measure the error rate of the Serializer.
The DS25C400 has a built-in 27−1 PRBS checker in the
Deserializer data path. It is initialized when EN_ERR is
pulsed high then low with a minimum period of 10 µs. This
will allow the internal error checker to achieve synchroniza-
tion with the incoming (27−1) bit stream. With EN_ERR=0,
ER_n pulses high for 10-bit period if the PRBS checker
detects an error in the receive data word. It provides a simple
mechanism to monitor the Deserializer’s error rate perfor-
mance by measuring the number of pulses at ER_n pin over
a period of time. When EN_ERR is left high, ER_n will flag
8b/10b disparity and code violation errors instead of PRBS
errors. When the 8b/10b mode is activated, RD[9] becomes
a second error pin that flags 8b/10b errors.
DS25C400 detects both the +K28.5 and −K28.5 comma
characters. These are unique binary patterns that cannot
occur in valid data. A bit error could produce a misaligned
comma character. This would cause an improper word re-
alignment, if comma detect is enabled. Any higher order
comma detect function that required the detection of multiple
misaligned comma characters before initiating word realign-
ment must be added externally by the user.
SERIAL LOCAL LOOPBACK
DS25C400 provides an internal loopback of the serial trans-
mit data to the receiver’s limiting amplifier of each channel.
EN_SLB = 1 activates serial local loopback path for all four
channels. DO are disabled with output current = 0, and
incoming data at RI are ignored. Self test can be performed
by comparing the parallel recovered output data at RD[0–9]
to the parallel transmit input data at TD[0–9]. EN_LOS pin
must be tied high (disabled LOS control of RD[0-9]) during
serial local loopback testing. For normal data transmission
operation using cable or PCB trace, set EN_SLB = 0 and
EN_LOS can be tied low.
The built-in PRBS generator and error checker, together with
the internal loopback offer very powerful high speed self-test
capability for the DS25C400.
POR
Upon application of power, the DS25C400 generates a
power-on reset. During reset, RD[0–9] are set to logic low,
and the LOS outputs are put into inactive state. RBC0 and
RBC1 are at unknown state. The POR circuit monitors both
www.national.com
24
_RTN. The on-chip termination resistors can be maintained
to within a 10%. The external resistor at RTERM should be
249Ω 1% for 50Ω on-chip terminations.
Functional Descriptions (Continued)
the 2.5V supply and the 1.8V supply. The 2.5V POR thresh-
old voltage is approzimately 2.0V. There is about 50mV of
hysteresis for this threshold. The 1.8V POR threshold is
about 1.1V with 50mV of hysteresis. When the POR circuit is
active, the PLL VCO capacitors are discharged to allow
correct operation when a good power level is again estab-
lished. Futhermore, the POR resets the internal digital
counters to correct settings to be in a ready condition when
supplies have been corrected. A termination resistor calibra-
tion sequence will also be executed.
POWER DOWN
There are two control lines that control the power down
modes, PD0 and PD1. With PD0=0 and PD1=0 all four
channels are powered down, which subsequently power
down the reference clock buffers as well as the bias circuits.
This mode will allow measuring an IDDQ or leakage current
test. To properly measure the IDDQ, the following sequence
must be followed: first power up the device, then apply the
reference clock and finally set the device to power down
mode (PD0=0, PD1=0) and remove the reference clock. The
other three states allow one, two, or four channels to be
powered up. The reference clock buffers and bias circuits
are powered up in these states.
RTERM
During power-on reset, the on-chip input termination resis-
tors at RI and the termination resistors at DO are ad-
justed at power up and compared to the current through an
external resistor connected from RTERM pin to RTERM-
PD1
PD0
IDD2.5
TBD
TBD
TBD
TBD
IDD1.8
TBD
TBD
TBD
TBD
Description
0
0
1
1
0
1
0
1
All 4 channels powered down
Only Channel A powered up
Channels A and B powered up
All 4 channels powered up
POWER SEQUENCE REQUIREMENT
The 2.5 V supplies (VDDHS, VDDIO and VDDB) should be
supplied, followed by the 1.8 V supplies. All the 2.5 V sup-
plies should be tied to a common power plane.
25
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25C400TUT
See NS Package Number UFJ324
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: support@nsc.com
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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