DS25CP102TSQ/NOPB [TI]
具有 TX 预加重和 RX 均衡功能的 3.125Gbps 2x2 LVDS 交叉点开关 | RGH | 16 | -40 to 85;型号: | DS25CP102TSQ/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 TX 预加重和 RX 均衡功能的 3.125Gbps 2x2 LVDS 交叉点开关 | RGH | 16 | -40 to 85 开关 输出元件 |
文件: | 总18页 (文件大小:434K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS25CP102
www.ti.com
SNLS262E –OCTOBER 2007–REVISED MARCH 2013
DS25CP102 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS25CP102
1
FEATURES
APPLICATIONS
2
•
DC - 3.125 Gbps Low Jitter, Low Skew, Low
Power Operation
•
•
•
•
High-Speed Channel Select Applications
Clock and Data Buffering and Muxing
OC-48 / STM-16
•
•
Pin Configurable, Fully Differential, Non-
Blocking Architecture
SD/HD/3GHD SDI Routers
Pin Selectable Transmit Pre-Emphasis and
Receive Equalization Eliminate Data
Dependant Jitter
DESCRIPTION
The DS25CP102 is
a 3.125 Gbps 2x2 LVDS
•
•
Wide Input Common Mode Voltage Range
Allows DC-Coupled Interface to CML and
LVPECL Drivers
crosspoint switch optimized for high-speed signal
routing and switching over lossy FR-4 printed circuit
board backplanes and balanced cables. Fully
differential signal paths ensure exceptional signal
integrity and noise immunity. The non-blocking
architecture allows connections of any input to any
output or outputs.
On-Chip 100Ω Input and Output Termination
Minimizes Insertion and Return Losses,
Reduces Component Count, Minimizes Board
Space
The DS25CP102 features two levels (Off and On) of
transmit pre-emphasis (PE) and two levels (Off and
On) of receive equalization (EQ).
•
•
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 4 mm x 4 mm WQFN-16 Space Saving
Package
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device
insertion and return losses, reduce component count
and further minimize board space.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS25CP102
SNLS262E –OCTOBER 2007–REVISED MARCH 2013
Typical Application
INPUT CARD
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OUTPUT CARD
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
BACKPLANES
DS25CP102
2x2 LVDS
DS25CP102
2x2 LVDS
Crosspoint Switch
Crosspoint Switch
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
DS25CP102
2x2 LVDS
DS25CP102
2x2 LVDS
Crosspoint Switch
Crosspoint Switch
SD/HD/3G HD
Reclocker +
Cable Driver
SD/HD/3G HD
Adaptive Equalizer
Large
(e.g. 128x128)
Crosspoint
Switch
CROSSPOINT CARD
Block Diagram
SEL1 SEL0
EN0
IN0+
OUT0+
EQ
PE
PE
IN0-
OUT0-
EN1
2 X 2
IN1+
IN1-
OUT1+
OUT1-
EQ
EQ
PE
Connection Diagram
IN0+
IN0-
IN1+
IN1-
1
2
3
4
12
11
10
9
OUT0+
OUT0-
OUT1+
OUT1-
DAP
(GND)
2
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Pin Name
SNLS262E –OCTOBER 2007–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin Description
Pin
Number
I/O, Type
I, LVDS
IN0+, IN0- ,
IN1+, IN1-
1, 2,
3, 4
Inverting and non-inverting high speed LVDS input pins.
Inverting and non-inverting high speed LVDS output pins.
OUT0+, OUT0-,
OUT1+, OUT1-
12, 11,
10, 9
O, LVDS
SEL0, SEL1
EN0, EN1
PE
7, 8
14, 13
15
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Power
Switch configuration pins. There is a 20k pulldown resistor on this pin.
Output enable pins. There is a 20k pulldown resistor on this pin.
Transmit Pre-Emphasis select pin. There is a 20k pulldown resistor on this pin.
Receive Equalization select pin. There is a 20k pulldown resistor on this pin.
Power supply pin.
EQ
6
VDD
16
GND
5, DAP
Power
Ground pin and Device Attach Pad (DAP) ground.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1.0V
LVCMOS Input Voltage
LVDS Input Voltage
Differential Input Voltage |VID|
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
0V to 1.0V
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
5 ms
+150°C
−65°C to +150°C
+260°C
Maximum Package Power Dissipation at 25°C
RGH0016A Package
2.99W
Derate RGH0016A Package
Package Thermal Resistance
θJA
23.9 mW/°C above +25°C
+41.8°C/W
+6.9°C/W
θJC
ESD Susceptibility
(3)
HBM
≥8 kV
≥250V
(4)
MM
(5)
CDM
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Copyright © 2007–2013, Texas Instruments Incorporated
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SNLS262E –OCTOBER 2007–REVISED MARCH 2013
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Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
1
Units
Supply Voltage (VCC
)
3.3
V
V
Receiver Differential Input Voltage (VID
)
Operating Free Air Temperature (TA)
−40
+25
+85
°C
DC Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
GND
40
VCC
0.8
V
V
VIN = 3.6V
VCC = 3.6V
175
0
250
μA
IIL
Low Level Input Current
Input Clamp Voltage
VIN = GND
VCC = 3.6V
±10
μA
VCL
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
mV
mV
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
−100
VCMR
0.05
VCC -
0.05
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
±10
μA
IIN
Input Current
CIN
RIN
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
Input Termination Resistor
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
(4)
IOS
Output Short Circuit Current
OUT to GND
-35
7
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC
Supply Current
Supply Current with Outputs Disabled
PE = OFF, EQ = OFF
EN0 = EN1 = 0
77
23
90
29
mA
mA
ICCZ
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
4
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SNLS262E –OCTOBER 2007–REVISED MARCH 2013
(1)
AC Electrical Characteristics
(2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
LVDS OUTPUT AC SPECIFICATIONS
tPLHD Differential Propagation Delay Low to
Parameter
Conditions
Min
Typ
Max
Units
365
345
500
500
ps
ps
High
RL = 100Ω
tPHLD
Differential Propagation Delay High to
Low
(4)
tSKD1
tSKD2
tSKD3
tLHT
Pulse Skew |tPLHD − tPHLD
|
20
12
50
65
65
7
55
25
ps
ps
ps
ps
ps
μs
ns
ns
(5)
Channel to Channel Skew
(6)
Part to Part Skew ,
150
120
120
20
Rise Time
RL = 100Ω
tHLT
Fall Time
tON
Output Enable Time
Output Disable Time
Select Time
ENn = LH to output active
ENn = HL to output inactive
SELn LH or HL to output
tOFF
tSEL
5
12
3.5
12
JITTER PERFORMANCE WITH EQ = Off, PE = Off (Figure 5)
tRJ1
tRJ2
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
6
1
1
ps
ps
No Test Channels
(7)
3.125 Gbps
2.5 Gbps
tDJ1
tDJ2
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
22
ps
No Test Channels
(8)
3.125 Gbps
2.5 Gbps
6
22
ps
tTJ1
tTJ2
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.03
0.05
0.08
0.11
UIP-P
UIP-P
No Test Channels
(9)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = Off, PE = On (Figure 6, Figure 9)
tRJ1B
tRJ2B
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
3
1
1
ps
ps
Test Channel B
(7)
3.125 Gbps
2.5 Gbps
tDJ1B
tDJ2B
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
12
ps
Test Channel B
(8)
3.125 Gbps
2.5 Gbps
3
12
ps
tTJ1B
tTJ2B
Total Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.03
0.04
0.06
0.09
UIP-P
UIP-P
Test Channel B
(9)
3.125 Gbps
JITTER PERFORMANCE WITH EQ = On, PE = Off (Figure 7, Figure 9)
tRJ1D
tRJ2D
Random Jitter (RMS Value)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
16
1
1
ps
ps
ps
ps
Test Channel D
(7)
3.125 Gbps
2.5 Gbps
tDJ1D
tDJ2D
Deterministic Jitter (Peak to Peak)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
24
24
Test Channel D
(8)
3.125 Gbps
12
(1) Specification is guaranteed by characterization and is not tested in production.
(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
(4) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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AC Electrical Characteristics (1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (2) (3)
Symbol
Parameter
Conditions
2.5 Gbps
Min
Typ
Max
Units
tTJ1D
tTJ2D
Total Jitter (Peak to Peak)
Test Channel D
VID = 350 mV
VCM = 1.2V
0.07
0.11
0.11
UIP-P
(9)
3.125 Gbps
0.07
UIP-P
PRBS-23 (NRZ)
JITTER PERFORMANCE WITH EQ = On, PE = On (Figure 8, Figure 9)
tRJ1BD
tRJ2BD
Random Jitter (RMS Value)
Input Test Channel D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
14
1
1
ps
ps
Output Test Channel B
3.125 Gbps
2.5 Gbps
(7)
tDJ1BD
tDJ2BD
Deterministic Jitter (Peak to Peak)
Input Test Channel D
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
31
ps
Output Test Channel B
3.125 Gbps
2.5 Gbps
6
21
ps
(8)
tTJ1BD
tTJ2BD
Total Jitter (Peak to Peak)
Input Test Channel D
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
0.08
0.10
0.15
0.16
UIP-P
UIP-P
Output Test Channel B
3.125 Gbps
(9)
DC TEST CIRCUITS
V
OH
OUT+
IN+
Power Supply
R
L
R
D
Power Supply
IN-
OUT-
V
OL
Figure 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
6
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SNLS262E –OCTOBER 2007–REVISED MARCH 2013
Figure 4. LVDS Output Transition Times
Pre-Emphasis and Equalization Test Circuits
DS25CP102
CHARACTERIZATION BOARD
50W
Microstrip
50W
Microstrip
½ DS25CP102
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 5. Jitter Performance Test Circuit
DS25CP102
CHARACTERIZATION BOARD
TEST
CHANNEL
½ DS25CP102
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
Figure 6. Pre-Emphasis Performance Test Circuit
TEST
DS25CP102
CHANNEL
CHARACTERIZATION BOARD
½ DS25CP102
50W MS
50W MS
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W MS
50W MS
Figure 7. Equalization Performance Test Circuit
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SNLS262E –OCTOBER 2007–REVISED MARCH 2013
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TEST
DS25CP102
TEST
CHANNEL
CHARACTERIZATION BOARD
CHANNEL
50W
Microstrip
50W
Microstrip
½ DS25CP102
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 8. Pre-Emphasis and Equalization Performance Test Circuit
50W MS
50W MS
L = A, B or C
L=1"
L=1"
L=1"
L=1"
100W Diff.
Stripline
50W MS
50W MS
Figure 9. Test Channel Block Diagram
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
1000 MHz 1250 MHz
-2.0 -2.4
500 MHz
-1.2
750 MHz
-1.7
1500 MHz
-2.7
1560 MHz
-2.8
A
B
C
D
E
F
10
20
30
15
30
60
-2.6
-3.5
-4.1
-7.0
-2.7
-5.6
-12.4
-4.8
-8.2
-3.2
-6.6
-14.5
-5.5
-5.6
-4.3
-5.7
-9.4
-9.7
-1.6
-2.2
-3.7
-3.8
-3.4
-4.5
-7.7
-7.9
-7.8
-10.3
-16.6
-17.0
8
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SNLS262E –OCTOBER 2007–REVISED MARCH 2013
Functional Description
The DS25CP102 is a 3.125 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Switch Configuration Truth Table
SEL1
SEL0
OUT1
IN0
OUT0
IN0
0
0
1
1
0
1
0
1
IN0
IN1
IN1
IN0
IN1
IN1
Table 2. Output Enable Truth Table
EN1
EN0
OUT1
OUT0
0
0
1
1
0
1
0
1
Disabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
In addition, the DS25CP102 has a pre-emphasis control pin for switching the transmit pre-emphasis to ON and
OFF setting and an equalization control pin for switching the receive equalization to ON and OFF setting. The
following are the transmit pre-emphasis and receive equalization truth tables.
Table 3. Transmit Pre-Emphasis Truth Table(1)
OUTPUTS OUT0 and OUT1
CONTROL Pin (PE) State
Pre-Emphasis Level
0
1
OFF
ON
(1) Transmit Pre-Emphasis Level Selection
Table 4. Receive Equalization Truth Table(1)
INPUTS IN0 and IN1
CONTROL Pin (EQ) State
Equalization Level
0
1
OFF
ON
(1) Receive Equalization Level Selection
Input Interfacing
The DS25CP102 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25CP102 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25CP102 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS25CP102
Receiver
100W Differential T-Line
OUT+
IN+
100W
IN-
OUT-
Figure 10. Typical LVDS Driver DC-Coupled Interface to DS25CP102 Input
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CML3.3V or CML2.5V
Driver
V
CC
DS25CP102
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 11. Typical CML Driver DC-Coupled Interface to DS25CP102 Input
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 12. Typical LVPECL Driver DC-Coupled Interface to DS25CP102 Input
Output Interfacing
The DS25CP102 outputs signals that are compliant to the LVDS standard. Its outputs can be DC-coupled to
most common differential receivers. The following figure illustrates typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended
to check respective receiver's data sheet prior to implementing the suggested interface implementation.
DS25CP102
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 13. Typical DS25CP102 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Typical Performance Characteristics
60
60
V
CC
= 3.3V
V
= 3.3V
CC
T
= 25°C
A
50
40
50
40
T
= 25°C
NRZ PRBS-7
EQ = Off
PE = Off
A
3.125 Gbps
NRZ PRBS-7
VID = 350 mV
PE = Off
30
30
EQ = Off
20
10
20
10
0
0
0
0.8
1.6
2.4
3.2
4.0
0
0.66
1.32
1.98
2.64
3.3
DATA RATE (Gbps)
INPUT COMMON MODE VOLTAGE (V)
Figure 14. Total Jitter as a Function of Data Rate
Figure 15. Total Jitter as a Function of Input Common Mode
Voltage
120
120
V
CC
= 3.3V
V
CC
= 3.3V
T
= 25°C
T = 25°C
A
NRZ PRBS7
EQ = ON
A
100
80
100
80
NRZ PRBS7
PE = ON
40" FR4 Stripline
20" FR4 Stripline
60
60
30" FR4 Stripline
10" FR4 Stripline
40
20
40
20
20" FR4 Stripline
0
0
0
0.8
1.6
2.4
3.2
4.0
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 16. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and PE Level
Figure 17. Residual Jitter as a Function of Data Rate, FR4
Stripline Length and EQ Level
Copyright © 2007–2013, Texas Instruments Incorporated
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Product Folder Links: DS25CP102
DS25CP102
SNLS262E –OCTOBER 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
120
V
CC
= 3.3V
T
= 25°C
A
110
100
NRZ PRBS7
Dual Buffer
PE = ON
90
PE = OFF
80
70
60
0
0.8
1.6
2.4
3.2
4.0
DATA RATE (Gbps)
Figure 18. Supply Current as a Function of Data Rate and
PE Level
Figure 19. A 3.125 Gbps NRZ PRBS-7 without PE or EQ
After 2" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
Figure 20. A 3.125 Gbps NRZ PRBS-7 without PE or EQ
After 40" Differential FR-4 Stripline
Figure 21. A 3.125 Gbps NRZ PRBS-7 with PE
After 40" Differential FR-4 Stripline
H: 50 ps / DIV, V: 100 mV / DIV
H: 50 ps / DIV, V: 100 mV / DIV
12
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25CP102
DS25CP102
www.ti.com
SNLS262E –OCTOBER 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2007–2013, Texas Instruments Incorporated
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13
Product Folder Links: DS25CP102
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS25CP102TSQ/NOPB
ACTIVE
WQFN
RGH
16
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
2C102SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS25CP102TSQ/NOPB WQFN
RGH
16
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RGH 16
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
DS25CP102TSQ/NOPB
1000
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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