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DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

DS280BR820 低功耗 28Gbps 8 通道线性中继器

1 特性

DS280BR820 将小型封装尺寸、经优化的高速信号退

1

出和引脚兼容的重定时器相结合，使其成为高密度背板

应用的理想选择。。凭借简化的均衡控制、低功耗和

超低附加抖动特性，该器件适用于 100G-

•

八通道多协议线性均衡器，可支持传输速率高达

28Gbps 的接口

•

低功耗：93mW/通道（典型值）

无需散热器

SR4/LR4/CR4 等前端接口。8mm x 13mm 小型封装

适用于 QSFP、SFP、CFP2、CFP4 和 CDFP 等多种

标准前端口连接器，并且无需散热器。

无缝支持链路协商、自动协商和前向纠错 (FEC) 直

通功能的直线均衡

•

扩展通道长度，超出正常专用集成电路 (ASIC) 到

ASIC 性能 17dB+

集成交流耦合电容（Rx 侧）免除了集成电路板 (PCB)

对于外部电容的需求。DS280BR820 具备一个单电

源，能够最大限度地降低外部组件的数量。这些特性

降低了 PCB 布局布线复杂度以及物料清单 (BOM) 成

本。

•

超低延迟：100ps（典型值）

低附加随机抖动

采用集成 Rx 和 Tx 交流耦合电容的小型 8mm x

13mm 小型球状引脚栅格阵列 (BGA) 封装，可实现

简易直通路由

引脚兼容的重定时器可用于距离较长的应用。

•

独特的引脚分配支持在封装下对高速信号进行路由

提供引脚兼容的重定时器

DS280BR820 可通过 SMBus 或外部 EEPROM 进行

配置。单个 EEPROM 最多可由 16 个器件共享。

2.5V±5% 单电源

运行温度范围：–40°C 至 +85°C

器件信息 ⁽¹⁾

器件型号

封装

封装尺寸（标称值）

2 应用

DS280BR820

nFBGA (135)

8.0mm x 13.0mm

•

背板和中板长度延长

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

用于光纤铜缆和无源铜缆 (100G-SR4/LR4/CR4) 的

前端口眼图开启器

简化电路原理图

•

QSFP28、SFP28、CFP2、CFP4、CDFP

RX0P

RX0N

TX0P

TX0N

3 说明

DS280BR820 是一款超低功耗、高性能八通道线性均

衡器，支持数据传输速率高达 28Gbps 的多速率、多

协议接口。该器件可用于扩展长度范围并提高背板、前

端口和芯片至芯片应用的高速串行链路的稳定性。应

用。

.

RX7P

RX7N

TX7P

TX7N

VDD

1 kΩ

SDA⁽¹⁾

SDC⁽¹⁾

To system SMBus

SMBus

Slave mode

ADDR0

ADDR1

Address straps

(pull-up, pull-down, or float)

EN_SMB

Float for SMBus Slave

mode, or connect to next

device‘s READ_EN_N for

SMBus Master mode

DS280BR820 均衡器的线性特质保留了发射信号的特

性，因此允许主机与链路合作伙伴 ASIC 自由协商发射

均衡器系数 (100G-CR4/KR4)。这种链路协商协议的透

明管理有助于在对延迟影响最小的情况下实现系统级互

操作性。每条通道独立运行，允许 DS280BR820 进行

独立信道前向纠错 (FEC)。

SMBus Slave

mode

READ_EN_N

VDD

ALL_DONE_N

GND

2.5 V

1 ꢀF

(2x)

0.1 ꢀF

(4x)

(1) SMBus signals need to be pulled up elsewhere in the system.

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS544

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 17

7.5 Programming........................................................... 18

7.6 Register Maps ........................................................ 19

Application and Implementation ........................ 29

8.1 Application Information............................................ 29

8.2 Typical Applications ............................................... 29

8.3 Initialization Set Up ................................................ 41

Power Supply Recommendations...................... 41

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 7

8

9

10 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 42

10.2 Layout Examples................................................... 42

11 器件和文档支持 ..................................................... 45

11.1 文档支持................................................................ 45

11.2 接收文档更新通知 ................................................. 45

11.3 商标....................................................................... 45

11.4 静电放电警告......................................................... 45

11.5 Glossary................................................................ 45

6.6 Electrical Characteristics – Serial Management Bus

Interface ................................................................... 12

6.7 Timing Requirements – Serial Management Bus

Interface ................................................................... 12

6.8 Typical Characteristics............................................ 13

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (October 2017) to Revision B

Page

•

首次公开发布 ......................................................................................................................................................................... 1

2

DS280BR820

www.ti.com.cn

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

5 Pin Configuration and Functions

Top View

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

TX1N

GND

TX2N

GND

TX3N

GND

TX4N

GND

TX5N

GND

TX6N

GND

VDD

J

H

G

F

J

H

G

F

Ground pin

TX0N

TX0P

GND

TX1P

GND

SDC

SDA

GND

TX2P

GND

RX2P

GND

VDD

GND

TX3P

GND

VDD

GND

RX3P

GND

VDD

GND

TX4P

GND

VDD

GND

RX4P

GND

VDD

GND

TX5P

GND

VDD

GND

RX5P

GND

TX6P

GND

TX7N

TX7P

GND

High-speed pin

Power pin

READ

_EN_

N

INT_N

(NC)

Control/Status pin

CAL_

CLK_

OUT

CAL_

CLK_

IN

No connect on

package

TEST ADDR

1

EN_S TEST

MB

E

D

C

B

A

E

D

C

B

A

1

0

ALL_

GND DONE GND

_N

ADDR

0

GND

RX0P

RX0N

GND

RX7P

RX7N

Test pin

GND

RX1P

RX6P

GND

RX1N

GND

RX2N

GND

RX3N

GND

RX4N

GND

RX5N

GND

RX6N

GND

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Pin Functions

I/O

DESCRIPTION

NAME

NO.

HIGH SPEED DIFFERENTIAL I/O

RX0N

RX0P

RX1N

RX1P

RX2N

RX2P

RX3N

RX3P

RX4N

RX4P

RX5N

RX5P

RX6N

RX6P

RX7N

RX7P

B15

C15

A13

B13

A11

B11

A9

Input

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

B9

A7

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

B7

A5

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

B5

A3

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

B3

B1

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination

resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors

assembled on the package substrate.

C1

TX0N

TX0P

TX1N

TX1P

H15

G15

J13

Output

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H13

3

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

TX2N

TX2P

TX3N

TX3P

TX4N

TX4P

TX5N

TX5P

TX6N

TX6P

TX7N

TX7P

NO.

J11

H11

J9

Output

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H9

J7

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H7

J5

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H5

J3

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H3

H1

G1

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

CALIBRATION CLOCK PINS (FOR SUPPORTING UPGRADE PATH TO PIN-COMPATIBLE RETIMER DEVICE)

25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase

noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is

a need to support a future upgrade to the pin-compatible Retimer device. If there is no

need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is

not required. This input pin has a weak active pull-down and can be left floating if the

CAL_CLK feature is not required.

CAL_CLK_IN

E1

Input

CAL_CLK_

OUT

2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a

daisy-chained fashion.

E15

Output

SYSTEM MANAGEMENT BUS (SMBus) PINS

ADDR0

D13

Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on

power-up. The multi-level nature of these pins allows for 16 unique device addresses. The

four strap options include:

0: 1 kΩ to GND

R: 10 kΩ to GND

ADDR1

E13

Input, 4-Level

F: Float

1: 1 kΩ to VDD

Indicates the completion of a valid EEPROM register load operation when in SMBus master

mode (EN_SMB = Float):

High = External EEPROM load failed or incomplete.

Low = External EEPROM load successful and complete.

When in SMBus slave mode (EN_SMB = 1 kΩ to VDD), this output will be high-Z until

READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. This behavior

allows the reset signal connected to READ_EN_N of one device to propagate to the

subsequent devices when ALL_DONE_N is connected to READ_EN_N in an SMBus slave

mode application.

ALL_DONE_

N

Output,

LVCMOS

D3

E3

4-level 2.5-V input used to select between SMBus master mode (float) and SMBus slave

mode (high). The four defined levels are:

0: 1 kΩ to GND - RESERVED

EN_SMB

Input, 4-Level

R: 10 kΩ to GND - RESERVED

F: Float - SMBus master mode

1: 1 kΩ to VDD - SMBus slave mode

Pin has weak pull-up.

This pin is 3.3 V tolerant.

SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master

mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device operation.

Input,

LVCMOS

READ_EN_N

F13

E12

SMBus slave mode (EN_SMB = 1 kΩ to VDD): When asserted low, this causes the device to

be held in reset (SMBus state machine reset and register reset). This pin should be pulled

high or left floating for normal operation in SMBus slave mode.

I/O, 3.3-V

LVCMOS,

Open Drain

SMBus data input and open drain output. External 2-kΩ to 5-kΩ pull-up resistor is required.

This pin is 3.3-V LVCMOS tolerant.

SDA

4

DS280BR820

www.ti.com.cn

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

I/O, 3.3-V

LVCMOS,

Open Drain

SMBus clock input and open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is

required. This pin is 3.3-V LVCMOS tolerant.

SDC

F12

MISCELLANEOUS PINS

No connect on package. For applications using multiple repeaters and retimers, this pin

should be connected to other devices’ INT_N pins. This is only a recommendation for cases

where there is a need to support a potential future upgrade to the pin-compatible retimer

device, which uses this pin as an interrupt signal to a system controller.

INT_N

TEST0

F3

No Connect

Input,

LVCMOS

E2

Reserved test pin. During normal (non-test-mode) operation, this pin is configured as an

input and therefore is not affected by the presence of a signal. This pin may be left floating,

tied to GND, or connected to a 2.5-V (max) output.

Input,

LVCMOS

TEST1

E14

POWER

A1, A2, A4,

A6, A8, A10,

A12, A14,

A15, B2, B4,

B6, B8, B10,

B12, B14,

C2, C3, C4,

C5, C6, C7,

C8, C9, C10,

C11, C12,

C13, C14,

D1, D2, D4,

D5, D7, D9,

D11, D12,

D14, D15,

Ground reference. The GND pins on this device should be connected through a low-

impedance path to the board GND plane.

GND

Power

E4, E11, F1,

F2, F4, F5,

F7, F9, F11,

F14, F15,

G2, G3, G4,

G5, G6, G7,

G8, G9, G10,

G11, G12,

G13, G14,

H2, H4, H6,

H8, H10,

H12, H14, J1,

J2, J4, J6,

J8, J10, J12,

J14, J15

Power supply, VDD = 2.5 V ±5%. Use at least six de-coupling capacitors between the

Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four

0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD

pins as possible. The VDD pins on this device should be connected through a low-resistance

path to the board VDD plane. For more information, see Power Supply Recommendations.

D6, D8, D10,

E5, E6, E7,

E8, E9, E10,

F6, F8, F10

VDD

Power

5

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).

(1)

MIN

–0.5

MAX

2.75

UNIT

V

VDD_ABSMAX

Supply voltage (VDD)

VIO_2.5V,ABSMAX

2.5 V I/O voltage (LVCMOS and CMOS)

V

Open drain and 3.3 V-tolerance I/O voltage (SDA, SDC,

READ_EN_N)

VIO_3.3V,ABSMAX

–0.5

4

V

VIO_HS,ABSMAX

TJ_ABSMAX

T_stg

High-speed I/O voltage (RXnP, RXnN, TXnP, TXnN)

Junction temperature

2.75

150

V

°C

Storage temperature

-40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

(1)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Charged-device model (CDM), per JEDEC specification JESD22-C101

±2000

V_(ESD)

Electrostatic discharge

V

±750

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV

may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN

NOM

MAX

UNIT

DC plus AC power should not

exceed these limits

VDD

N_VDD

Supply voltage, VDD to GND

2.375

2.5

2.625

V

Supply noise, DC to <50 Hz,

sinusoidal

250

20

mVpp

Supply noise, 50 Hz to 10 MHz,

sinusoidal

(1)

Supply noise tolerance

Supply noise, >10 MHz,

sinusoidal

10

T_RampVDD

VDD supply ramp time

From 0 V to 2.375 V

150

-40

µs

C

T_J

Operating junction temperature

Operating ambient temperature

110

85

T_A

C

SMBus SDA and SDC Open

Drain Termination Voltage

Supply voltage for open drain

pull-up resistor

VDD_SMBUS

3.6

V

SMBus clock (SDC) frequency in

SMBus slave mode

F_SMBus

400

kHz

(1) Sinusoidal noise is superimposed to supply voltage with negligible impact to device function or critical performance shown in the

Electrical Table.

6

DS280BR820

www.ti.com.cn

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

6.4 Thermal Information

(1)

THERMAL METRIC

CONDITIONS / ASSUMPTIONS

4-layer JEDEC board

VALUE

45.2

26.3

24.8

22.7

26.6

25.8

13.3

13.0

22.8

21.4

21.1

20.8

UNIT

10-layer 8-in x 6-in board

20-layer 8-in x 6-in board

30-layer 8-in x 6-in board

4-layer JEDEC board

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

4-layer JEDEC board

10-layer 8-in x 6-in board

20-layer 8-in x 6-in board

30-layer 8-in x 6-in board

4-layer JEDEC board

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

°C/W

10-layer 8-in x 6-in board

20-layer 8-in x 6-in board

30-layer 8-in x 6-in board

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

Channel enabled and in linear mode

with maximum driver VOD

(DRV_SEL_VOD = 3).

(1)

82

97

mW

Static power consumption not

included.

W_channel

Power consumption per active channel

Channel enabled and in linear mode

with minimum driver VOD

(DRV_SEL_VOD = 0).

Static power consumption not

included.

(1)

75

105

97

89

mW

Channel enabled and in FIR limiting

mode with C0 = 31 and maximum

driver VOD (DRV_SEL_VOD = 3).

Static power consumption not

included.

(1)

123

W_{channel_FIR}

Power consumption per active channel

Channel enabled and in FIR limiting

mode with C0 = 31 and minimum

driver VOD (DRV_SEL_VOD = 0).

Static power consumption not

included.

(1)

115

132

Channels disabled and powered down

(DRV_PD = 1, EQ_PD = 1).

Idle (static) mode total device power

consumption

W_{static_total}

110

307

mW

mA

All channels enabled and in linear

mode with maximum driver VOD

(DRV_SEL_VOD = 3).

347

Active mode total device supply

current consumption

I_total

All channels enabled and in linear

mode with minimum driver VOD

(DRV_SEL_VOD = 0).

283

322

mA

(1) Max values assume VDD = 2.5 V + 5%.

7

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All channels enabled and in FIR

limiting mode with C0 = 31 and

maximum driver VOD

380

426

mA

(DRV_SEL_VOD = 3).

Active mode total device supply

current consumption

I_{total_FIR}

All channels enabled and in FIR

limiting mode with C0 = 31 and

minimum driver VOD

355

44

401

50

mA

(DRV_SEL_VOD = 0).

All channels disabled and powered

down

(DRV_PD = 1, EQ_PD = 1).

Idle (static) mode total device supply

current consumption

I_{static_total}

LVCMOS DC SPECIFICATIONS (CAL_CLK_IN, CAL_CLK_OUT, READ_EN_N, ALL_DONE_N, TEST[1:0])

1.75

VDD

3.6

V

V_IH

High level input voltage

READ_EN_N pin only

1.75

GND

2

V_IL

Low level input voltage

High level output voltage

Low level output voltage

0.7

V

V_OH

V_OL

IOH = 4 mA

V

IOL = –4 mA

0.4

16

66

1

V

Vinput = VDD, TEST[1:0] pins

Vinput = VDD, CAL_CLK_IN pin

Vinput = VDD, READ_EN_N pin

Vinput = 0 V, TEST[1:0] pins

µA

I_IH

Input high leakage current

Input low leakage current

(2)

–38

–1

(3)

I_IL

Vinput = 0 V, CAL_CLK_IN pin

Vinput = 0 V, READ_EN_N pin

(2)

–55

4-LEVEL LOGIC ELECTRICAL SPECIFICATIONS (APPLIES TO 4-LEVEL INPUT CONTROL PINS ADDR0, ADDR1, and EN_SMB)

I_IH

I_IL

Input high leakage current

Input low leakage current

105

µA

–253

0.95 ×

VDD

High level (1) input voltage

Float level input voltage

V

0.67 ×

VDD

V_TH

0.33 ×

VDD

10 K to GND input voltage

Low level (0) input voltage

V

0.1

HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)

Measured with maximum CTLE setting

and maximum BW setting (EQ_BST1

= 7, EQ_BST2 = 7, EQ_BW = 3).

Boost is defined as the gain at 14 GHz

relative to 20 MHz.

25.6

dB

BST

CTLE high-frequency boost

Measured with maximum CTLE setting

and maximum BW setting (EQ_BST1

= 7, EQ_BST2 = 7, EQ_BW = 3).

Boost is defined as the gain at 12.9

GHz relative to 20 MHz.

25.3

(2) This pin has an internal weak pull-up.

(3) This pin has an internal weak pull-down.

8

DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured with minimum CTLE setting

and minimum BW setting (EQ_BST1 =

0, EQ_BST2 = 0, EQ_BW = 0,

EQ_EN_BYPASS = 1). Boost is

defined as the gain at 14 GHz relative

to 20 MHz.

2.4

dB

BST

CTLE high-frequency boost

Measured with minimum CTLE setting

and minimum BW setting (EQ_BST1 =

0, EQ_BST2 = 0, EQ_BW = 0,

EQ_EN_BYPASS = 1). Boost is

defined as the gain at 12.9 GHz

relative to 20 MHz.

2.4

dB

Measured with maximum CTLE setting

(EQ_BST1 = 7, EQ_BST2 = 7). Gain

variation is defined as the total change

in gain at 14 GHz due to temperature

and voltage variation.

< 3

dB

BST_delta

CTLE high-frequency gain variation

Measured with maximum CTLE setting

(EQ_BST1 = 7, EQ_BST2 = 7). Gain

variation is defined as the total change

in gain at 12.9 GHz due to

temperature and voltage variation.

Measured with minimum CTLE setting

(EQ_BST1 = 0, EQ_BST2 = 0,

EQ_EN_BYPASS = 1). Gain variation

is defined as the total change in gain

at 14 GHz due to temperature and

voltage variation.

< 2

dB

BST_delta

CTLE high-frequency gain variation

Measured with minimum CTLE setting

(EQ_BST1 = 0, EQ_BST2 = 0,

EQ_EN_BYPASS = 1). Gain variation

is defined as the total change in gain

at 12.9 GHz due to temperature and

voltage variation.

50 MHz to 3.7 GHz

3.7 GHz to 10 GHz

10 GHz to 14.1 GHz

14.1 GHz to 20 GHz

100 MHz to 3.3 GHz

3.3 GHz to 12.9 GHz

12.9 GHz to 20 GHz

100 MHz to 10 GHz

10 GHz to 20 GHz

< -14

< -12

< -8

dB

RL_SDD11

Input differential return loss

< -6

< -35

< -26

< -22

< -7

Input differential-to-common-mode

return loss

RL_SDC11

RL_SCC11

Input common-mode return loss

< -8

Minimum input peak-to-peak amplitude

level at device pins required to assert

signal detect. 25.78125 Gbps with

PRBS7 pattern and 20 dB loss

channel.

AC signal detect assert (ON)

differential voltage threshold level

V_SDAT

196

147

mVpp

Maximum input peak-to-peak

amplitude level at device pins which

causes signal detect to de-assert.

25.78125 Gbps with PRBS7 pattern

and 20 dB loss channel.

AC signal detect de-assert (OFF)

differential voltage threshold level

V_SDDT

9

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured with the highest wide-band

gain setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 3). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

850

mVpp

Measured with a mid wide-band gain

setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 0). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

900

1050

1250

mVpp

Input amplitude linear range. The

maximum VID for which the repeater

remains linear, defined as ≤1 dB

compression of Vout/Vin.

VID_linear

Measured with a mid wide-band gain

setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 3). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

Measured with the lowest wide-band

gain setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 0). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)

Measured with an 16T pattern at

28.125 Gbps using C(0),

Maximum pre-cursor de-emphasis in

PRE_DEM-MAX

Reg_0x0B[4:0], set to 0x0C, C(-1),

Reg_0x0D[3:0], set to 0xF, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

-11

dB

FIR limiting mode

Measured with an 16T pattern at

28.125 Gbps using C(0),

Maximum post-cursor de-emphasis in Reg_0x0B[4:0], set to 0x0C, C(-1),

PST_DEM-MAX

FIR limiting mode

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0xF. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

Pre-cursor FIR tap delay in FIR

limiting mode

T_PRE

T_PST

Independent of data rate

28

25

ps

Post-cursor FIR tap delay in FIR

limiting mode

Measured with a 16T pattern at

25.78125 Gbps using C(0),

Reg_0x0B[4:0], set to 0x00, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

VOD, Reg_0x06[7:6], set to 0x0.

185

360

mVpp

Minimum differential output amplitude

in FIR limiting mode

VOD_LIM-MIN

Measured with a 16T pattern at

25.78125 Gbps using C(0),

Reg_0x0B[4:0], set to 0x00, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

VOD, Reg_0x06[7:6], set to 0x3.

10

DS280BR820

www.ti.com.cn

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured with a 16T pattern at

25.78125 Gbps using C(0),

Reg_0x0B[4:0], set to 0x1F, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

VOD, Reg_0x06[7:6], set to 0x0.

705

mVpp

Maximum differential output amplitude

in FIR limiting mode

VOD_LIM-MAX

Measured with a 16T pattern at

25.78125 Gbps using C(0),

Reg_0x0B[4:0], set to 0x1F, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

VOD, Reg_0x06[7:6], set to 0x3.

1260

mVpp

Differential output amplitude, TX

disabled or otherwise muted

VOD_idle

< 10

4.5

mVpp

dB

Measured with the highest wide-band

gain setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 3) at 20 MHz.

Vout/Vin wide-band amplitude gain in

linear mode

G_DC

Measured with the lowest wide-band

gain setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 0) at 20 MHz.

–5

Defined as (TXP + TXN)/2. Measured

with a low-pass filter with 3-dB

bandwidth at 33 GHz.

V_cm-TX-AC

Common-mode AC output noise

Common-mode DC output

6

mV, RMS

V

Defined as (TXP + TXN)/2. Measured

with a DC signal.

V_cm-TX-DC

0.75

0.96

1.05

Measured single-endedly on a

Keysight E5505A phase noise

measurement solution with a 28-Gbps

1010 pattern, from 2 kHz to 20 MHz.

RJ_ADD-RMS

Additive random jitter

11

fs RMS

dB

50 MHz to 4.8 GHz

4.8 GHz to 10 GHz

10 GHz to 14.1 GHz

14.1 GHz to 20 GHz

50 MHz to 6.0 GHz

6.0 GHz to 12.9 GHz

12.9 GHz to 14.1 GHz

14.1 GHz to 20 GHz

50 MHz to 3.3 GHz

3.3 GHz to 10.3 GHz

10.3 GHz to 20 GHz

< –16

< –15

< –8

Output differential-to-differential return

loss

RL_SDD22

< –8

< –21

< –22

< –21

< –20

< –13

< –11

< –9

Output common-mode-to-differential

return loss

RL_SCD22

dB

RL_SCC22

Output common-mode return loss

Measured at 28.125 Gbps with 16T

data pattern using C(0),

Reg_0x0B[4:0], set to 0x00, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

19.9

25.8

ps

Transition time (20%-80%) in FIR

limiting mode

t_r, t_f

Measured at 28.125 Gbps with 16T

data pattern using C(0),

Reg_0x0B[4:0], set to 0x1F, C(-1),

Reg_0x0D[3:0], set to 0x0, and C(+1),

Reg_0x0C[3:0], set to 0x0. TX

drv_sel_fir, Reg_0x06[0], set to 0x1.

11

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

OTHER PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input-to-output latency (propagation

delay) through a channel

t_D

Linear mode

100

ps

Input-to-output latency (propagation

delay) through a channel

t_D

FIR limiting mode, Reg_0x06[0]=1

160

<14

ps

t_SK

Channel-to-channel interpair skew

Latency difference between channels.

Time to assert ALL_DONE_N after

REAN_EN_N has been asserted.

Single device reading its configuration

from an EEPROM with common

channel configuration. This time scales

with the number of devices reading

from the same EEPROM. Does not

include power-on reset time.

4

T_EEPROM

EEPROM configuration load time

ms

Time to assert ALL_DONE_N after

REAN_EN_N has been

asserted. Single device reading its

configuration from an EEPROM. Non-

common channel configuration. This

time scales with the number of devices

reading from the same EEPROM.

Does not include power-on reset time.

7

Internal power-on reset (PoR) stretch

between stable power supply and de-

assertion of internal PoR. The SMBus

address is latched on the completion

of the PoR stretch, and SMBus

accesses are permitted once PoR

completes.

T_POR

Power-on reset assertion time

60

ms

6.6 Electrical Characteristics – Serial Management Bus Interface

PARAMETER

TEST CONDITIONS

MIN

1.75

GND

TYP

MAX

3.6

UNIT

V

V_IH

V_IL

Input high level voltage

Input low level voltage

Output low level voltage

Input pin capacitance

SDA and SDC

0.8

V

V_OL

C_IN

SDA and SDC, I_OL= 1.25 mA

SDA and SDC

0.4

V

15

pF

SDA or SDC, VINPUT = VIN, VDD,

GND

I_IN

Input current

–18

18

µA

6.7 Timing Requirements – Serial Management Bus Interface

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SMBus SLAVE MODE)

f_SDC

SDC clock frequency

Data hold time

EN_SMB = 1 k to VDD (Slave Mode)

10

100

0.75

100

150

4.5

400

kHz

ns

T_SDA-HD

T_SDA-SU

T_SDA-R

T_SDA-F

Data setup time

ns

SDA rise time, read operation

SDA fall time, read operation

Pull-up resistor = 1 kΩ, Cb = 50 pF

ns

SMBus SWITCHING CHARACTERISTICS (SMBus MASTER MODE)

f_SDC

SDC clock frequency

SDC low period

EN_SMB = Float (Master Mode)

260

1.66

1.22

303

1.90

1.40

0.6

346

2.21

1.63

kHz

µs

T_SDC-LOW

T_SDC-HIGH

T_HD-START

SDC high period

µs

Hold time start operation

µs

12

DS280BR820

www.ti.com.cn

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Timing Requirements – Serial Management Bus Interface (continued)

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

Setup time start operation

Data hold time

TEST CONDITIONS

MIN

TYP

0.6

MAX

UNIT

µs

T_SU-START

T_SDA-HD

T_SDA-SU

T_SU-STOP

T_BUF

0.9

µs

Data setup time

0.1

µs

Stop condition setup time

Bus free time between Stop-Start

SDC rise time

0.6

µs

1.3

µs

T_SDC-R

Pull-up resistor = 1 kΩ

300

ns

T_SDC-F

SDC fall time

ns

6.8 Typical Characteristics

1.3

1.2

1.1

1

1.3

0

6

12

18

24

31

0

6

1.2

1.1

1

12

18

24

31

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.9

0.8

0.7

0.6

0.5

0.4

0.3

-50

25

Temperature (°C)

105

2.35

2.5

Voltage (V)

2.65

D002

D003

图 1. Limiting Mode: FIR VOD Variation Across Temperature

图 2. Limiting Mode: FIR VOD Variation Across VDD

1.4

1.2

1

0.8

0.6

0.4

0.2

EQ High Gain Mode 0

EQ High Gain Mode 3

EQ Low Gain Mode 0

EQ Low Gain Mode 3

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

Input Differential Voltage (V_P-P

1.1 1.2 1.3 1.4

)

D001

图 3. Typical Vin/Vout Linearity

13

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

7 Detailed Description

7.1 Overview

The DS280BR820 is an eight-channel multi-rate linear repeater with integrated signal conditioning. The eight

channels operate independently from one another. Each channel includes a continuous-time linear equalizer

(CTLE), an optional FIR filter and a linear output driver, which compensate for the presence of a dispersive

transmission channel between the source transmitter and the final receiver.

All receive channels on the DS280BR820 are AC-coupled with physical AC coupling capacitors (220 nF ±20%)

on the package substrate. This ensures common mode voltage compatibility with all link partner transmitters and

eliminates the need for AC coupling capacitors on the system PCB, thereby saving cost and greatly reducing

PCB routing complexity.

The DS280BR820 is configurable through a single SMBus port. The DS280BR820 can also act as an SMBus

master to configure itself from an EEPROM.

注

The DS280BR820 offers improved high-frequency boost and bandwidth compared to the

DS280BR810. The DS280BR810 has series AC coupling capacitors on both the RX and

TX pins, whereas the DS280BR820 has series AC coupling capacitors on the RX inputs

only. The DS280BR820 and DS280BR810 are otherwise pin-to-pin compatible and share

the same register programming interface.

The sections which follow describe the functionality of various circuits and features within the DS280BR820. For

more information about how to program or operate these features, consult the DS280BR820 Programming

Guide.

7.2 Functional Block Diagram

One of Eight Channels

Term

Bypass

Linear Path

RXnP

RXnN

TXnP

TXnN

Boost

Stage 1

Boost

Stage 2

Driver

220 nF

FIR Limiting Path

3-Tap FIR

Signal

Detect

Voltage

Regulator

Channel Digital Core

ADDRn

SDC

SDA

Power-On

Reset

Shared Digital Core

Always-On 10 MHz

READ_EN_N

EN_SMB

ALL_DONE_N

CAL_CLK_OUT

CAL_CLK_IN

Buffer

Shared Digital Core (common to all channels)

14

DS280BR820

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7.3 Feature Description

7.3.1 Device Data Path Operation

The DS280BR820 data path consists of several key blocks as shown in Functional Block Diagram. These key

circuits are:

•

AC-Coupled Receiver Inputs

Signal Detect

2-Stage CTLE

Driver DC Gain Control

FIR Filter (Limiting Mode)

Configurable SMBus Address

7.3.2 AC-Coupled Receiver Inputs

The differential receiver for each DS280BR820 channel contains an integrated on-die 100-Ω differential

termination as well as 220-nF ±20% series AC coupling capacitors embedded onto the package substrate.

7.3.3 Signal Detect

Each DS280BR820 high speed receiver has a signal detect circuit which monitors the energy level on the inputs.

The signal detect circuit will enable the high-speed data path if a signal is detected, or power it off if no signal is

detected. By default, this feature is enabled, but can be manually controlled though the SMBus channel registers.

This can be useful if it is desired to manually force channels to be disabled. For information on how to manually

operate the signal detect circuit refer to the DS280BR820 Programming Guide.

7.3.4 2-Stage CTLE

The continuous-time linear equalizer (CTLE) in the DS280BR820 consists of two stages which are configurable

via the SMBus channel registers. This CTLE is designed to be highly linear to allow the DS280BR820 to

preserve the transmitter's pre-cursor and post cursor signal characteristics. This highly linear behavior enables

the DS280BR820 to be used in applications that use protocols such as link training, where it is important to

recover and pass through incremental changes in transmit equalization.

Each stage in the CTLE has 3-bit boost control. The first CTLE stage provides a coarse adjustment of the total

boost. Larger settings correspond to higher total boost. The first stage can be bypassed entirely to achieve the

lowest possible total boost. The second CTLE stage acts as a fine adjustment on the total boost and impacts the

shape of the boost curve accordingly. Larger settings correspond to higher total boost. The bandwidth of the

CTLE can be adjusted using a 2-bit bandwidth control. Larger settings correspond to higher total bandwidth. For

information on how to program the CTLE refer to the DS280BR820 Programming Guide.

In addition to high-frequency boost, the CTLE can apply wide-band amplitude gain. There are two settings (high-

gain and low-gain) which work together with the driver DC gain control to affect the total input-to-output wide-

band amplitude gain.

7.3.5 Driver DC Gain Control

In addition to the high-frequency boost provided by the CTLE, the DS280BR820 is also able to provide additional

DC or low-frequency gain. The effective DC gain is controlled by a 3-bit field, allowing for eight levels of DC

attenuation or DC gain. For information on how to configure the DC gain refer to the DS280BR820 Programming

Guide.

7.3.6 FIR Filter (Limiting Mode)

The DS280BR820 has an optional limiting mode with a fixed-delay 3-tap finite impulse response (FIR) filter to

provide transmit equalization. This FIR can be configured to apply pre-cursor and post-cursor boost to the high

speed signal. The FIR filter also allows for main cursor amplitude control. The tap polarities in the FIR filter are

fixed to allow for pre-cursor or post-cursor boost to be applied to the signal.

15

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www.ti.com.cn

Feature Description (接下页)

CTLE

Output

FIR filter

output

x

C[-1]

x

+

Fixed

Delay

Fixed

Delay

C[0]

x

C[+1]

图 4. 3-Tap FIR Filter Block Diagram

Linear mode is recommended for the majority of applications, especially those which require Link Training.

Common protocols such as 100 GbE and 40 GbE CR4/KR4, 50 GbE and 25 GbE CR, 10 GbE KR, InfiniBand

EDR, and others require Link Training. Linear mode is required for Link Training so that the ASIC transmitter pre-

cursor and post-cursor coefficients can propagate through the DS280BR820 in a transparent fashion. For

applications which do not utilize Link Training, limiting mode may be used to provide output pre-cursor and post-

cursor equalization for the purpose of improving the far-end eye opening. If the downstream receiver SerDes

uses a decision feedback equalizer (DFE) to equalize the signal, the linear mode may be preferable to the

limiting mode. DFE circuits often perform best when operating on a linear signal.

7.3.7 Configurable SMBus Address

The DS280BR820’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is

read on power up, after the internal power-on reset completes. The ADDR[1:0] pins are four-level LVCMOS IOs,

which provide for 16 unique SMBus addresses. 表 1 lists the DS280BR820 SMBus slave address options.

表 1. SMBus Address Map

REQUIRED ADDRESS PIN STRAP VALUE

7-BIT SLAVE ADDRESS

8-BIT WRITE ADDRESS

ADDR1

ADDR0

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x30

0x32

0x34

0x36

0x38

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x48

0x4A

0x4C

0x4E

0

R

F

1

0

R

F

1

0

R

F

1

0

R

F

1

0

1

R

F

1

16

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

7.4 Device Functional Modes

7.4.1 SMBus Slave Mode Configuration

To configure the DS280BR820 for SMBus slave mode connect the EN_SMB pin to VDD with a 1 kΩ resistor.

When the DS280BR820 is configured for SMBus slave mode operation the READ_EN_N becomes an active-low

reset pin, resetting register values when driven to LOW, or V_IL. Additionally, when the DS280BR820 is configured

for SMBus slave mode the ALL_DONE_N output pin is high-Z; except for when READ_EN_N is driven LOW

which causes ALL_DONE_N to also be driven LOW. Refer to Register Maps for additional register information.

7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)

To configure the DS280BR820 for SMBus master mode, leave the EN_SMB pin floating (no connect). If the

DS280BR820 is configured for SMBus master mode, it will remain in the SMBus IDLE state until the

READ_EN_N pin is asserted to LOW. Once the READ_EN_N pin is driven LOW, the DS280BR820 becomes an

SMBus master and attempts to self-configure by reading device settings stored in an external EEPROM (SMBus

8-bit address 0xA0). When the DS280BR820 has finished reading from the EEPROM successfully, it will drive

the ALL_DONE_N pin LOW and then change from an SMBus master to an SMBus slave. Not all bits in the

register map can be configured through an EEPROM load. Refer to the Programming Guide for more

information.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

•

Maximum EEPROM size is 8 kb (1024 x 8-bit)

Set EN_SMB = FLOAT, configure for SMBus master mode

The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 2.5-V or 3.3-

V supply.

•

Configure the ADDR[1:0] inputs to select the SMBus slave address for the DS280BR820. Once the

DS280BR820 completes its EEPROM load the device becomes a slave on the control bus.

EEPROM

8-bit SMBus

SMBus address

address: 0xA0

SDC

SDA

DS280BR820

SDC

SDA

SDC

SDA

SDC

SDA

EN_SMB

READ_EN_N

ALL_DONE_N

READ_EN_N

ALL_DONE_N

READ_EN_N

ALL_DONE_N

Leave final device‘s ALL_DONE_N pin

floating or connect to a control chip to

monitor completion of final EEPROM read.

Tie first device‘s READ_EN_N pin low to automatically

initiate EEPROM read at power up, or control this pin from

a device to initiate EEPROM read manually.

图 5. Example Daisy Chain for Multiple Device Single EEPROM Configuration

When tying multiple DS280BR820 devices to the SDA and SDC bus, use these guidelines to configure the

devices for SMBus master mode:

•

Use SMBus ADDR[1:0] address bits so that each device can load its configuration from the EEPROM. The

example below is for four devices. The first device in the sequence conventionally uses the 8-bit slave write

address 0x30, while subsequent devices follow the address order listed below.

–

DS280BR820 instance 1 (U1): ADDR[1:0] = {0, 0} = 0x30

DS280BR820 instance 2 (U2): ADDR[1:0] = {0, R} = 0x32

DS280BR820 instance 3 (U3): ADDR[1:0] = {0, F} = 0x34

DS280BR820 instance 4 (U4): ADDR[1:0] = {0, 1} = 0x36

•

Use a pull-up resistor on SDA and SDC; resistor value = 2 kΩ to 5 kΩ is adequate.

Float (no connect) the EN_SMB pin (E3) on all DS280BR820 devices to configure them for SMBus master

mode. The EN_SMB pin should not be dynamically changed between the high and float states.

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Device Functional Modes (接下页)

•

Daisy-chain READ_EN_N (pin F13) and ALL_DONE_N (pin D3) from one device to the next device in the

following sequence so that they do not compete for master control of the EEPROM at the same time.

1. Tie READ_EN_N of the first device in the chain (U1) to GND to trigger EEPROM read immediately after

the DS280BR820 power-on reset (PoR) completes. Alternatively, drive the READ_EN_N pin from a

control device (micro-controller or FPGA) to trigger the EEPROM read at a specific time.

2. Tie ALL_DONE_N of U1 to READ_EN_N of U2

3. Tie ALL_DONE_N of U2 to READ_EN_N of U3

4. Tie ALL_DONE_N of U3 to READ_EN_N of U4

5. Optional: Tie ALL_DONE_N output of U4 to a micro-controller or an LED to show the devices have been

loaded successfully.

Once the ALL_DONE_N status pin of the last device is flagged to indicate that all devices sharing the SMBus

line have been successfully programmed, control of the SMBus line is released by the DS280BR820. The device

then reverts back to SMBus slave mode. At this point, an external MCU can perform any additional Read or

Write operations to the DS280BR820.

Refer to the Programming Guide for additional information concerning SMBus master mode.

7.5 Programming

The DS280BR820 can be programmed in two ways. The DS280BR820 can be configured as an SMBus slave

(EN_SMB = HIGH) or the device can temporarily act as an SMBus master and load its configuration settings

from an external EEPROM (EN_SMB = FLOAT). Refer to SMBus Slave Mode Configuration and SMBus Master

Mode Configuration (EEPROM Self Load) for details.

7.5.1 Transfer of Data with the SMBus Interface

The System Management Bus (SMBus) is a two-wire serial interface through which a master can communicate

with various system components. Slave devices are identified by a unique device address. The two-wire serial

interface consists of SDC and SDA signals. SDC is a clock output from the master to all of the slave devices on

the bus. SDA is a bidirectional data signal between the master and slave devices. The DS280BR820 SMBus

SDC and SDA signals are open drain and require external pull-up resistors.

Start and Stop Conditions:

The master generates Start and Stop conditions at the beginning and end of each transaction:

•

Start: HIGH to LOW transition (falling edge) of SDA while SDC is HIGH.

Stop: LOW to HIGH transition (rising edge) of SDA while SDC is HIGH.

The master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the acknowledge

(ACK) cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the

device pulls SDA LOW, while a NACK (no acknowledge) is recorded if the line remains HIGH.

Writing data from a master to a slave consists of three parts:

•

The master begins with a start condition followed by the slave device address with the R/W bit cleared.

The master sends the 8-bit register address that will be written.

The master sends the data byte to write for the selected register address. The register address pointer will

then increment, so the master can send the data byte for the subsequent register without re-addressing the

device, if desired. The final data byte to write should be followed by a stop condition.

SMBus read operations consist of four parts:

•

The master initiates the read cycle with start condition followed by slave device address with the R/W bit

cleared.

•

The master sends the 8-bit register address that will be read.

After acknowledgment from the slave, the master initiates a re-start condition.

The slave device address is resent followed with R/W bit set.

After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is

HIGH if there are no more bytes to read.

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7.6 Register Maps

Many of the registers in the DS280BR820 are divided into bit fields. This allows a single register to serve multiple

purposes which may be unrelated. Often, configuring the DS280BR820 requires writing a bit field that makes up

only part of a register value while leaving the remainder of the register value unchanged. The procedure for

accomplishing this task is to read in the current value of the register to be written, modify only the desired bits in

this value, and write the modified value back to the register. This sequence is commonly referred to as Read-

Modify-Write. If the entire register is changed, rather than just a bit field within the register, it is not necessary to

read in the current value of the register first.

Most register bits can be read or written to. However, some register bits are constrained to specific interface

instructions.

Register bits can have the following interface constraints:

•

R - Read only

RW - Read/Write

RWSC - Read/Write, Self-Clearing

7.6.1 Register Types: Global, Shared, and Channel

The DS280BR820 has 3 types of registers:

1. Global Registers - These registers can be accessed at any time and are used to select between individual

channel registers and shared registers, or to read back the TI ID and version information.

2. Shared Registers - These registers are used for device-level configuration, status read back or control. Set

register 0xFF[0] = 0 and configure 0xFF[5:4] to access the shared registers.

3. Channel Registers – These registers are used to control and configure specific features for each individual

channel. All channels have the same channel register set and can be configured independent of each other.

Set register 0xFF[0] = 1 and configure register 0xFC to access the desired channel register set.

Refer to the Programming Guide for additional information on register configuration.

7.6.2 Global Registers: Channel Selection and ID Information

The global registers can be accessed at any time, regardless of whether the shared or channel register set is

selected. The DS280BR820 global registers are located at address 0xEF - 0xFF.

表 2. Global Register Map

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

0xEF

0x0C

General

7

6

5

4

3

0

1

RW

R

N

RESERVED

DEVICE_ID_QUAD_ TI device ID (quad count). Contains 0x0C.

CNT[3]

2

1

0

1

0

R

N

DEVICE_ID_QUAD_

CNT[2]

DEVICE_ID_QUAD_

CNT[1]

DEVICE_ID_QUAD_

CNT[0]

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Register Maps (接下页)

表 2. Global Register Map (接下页)

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

0xF0

0xF1

0xF3

0xFC

0xFD

0x00

Version Revision

TYPE

7

6

5

4

3

2

1

0

R

N

TI version ID. Contains 0x00.

0

VERSION[6]

VERSION[5]

VERSION[4]

VERSION[3]

VERSION[2]

VERSION[1]

VERSION[0]

Channel Control

DEVICE_ID[7]

DEVICE_ID[6]

DEVICE_ID[5]

DEVICE_ID[4]

DEVICE_ID[3]

DEVICE_ID[2]

DEVICE_ID[1]

DEVICE_ID[0]

Channel Control

0

0x40

7

6

5

4

3

2

1

0

R

N

TI device ID. Contains 0x40.

1

0

0x00

7

6

5

4

3

2

1

0

R

N

CHAN_VERSION[3] TI digital channel version ID. Contains 0x00.

CHAN_VERSION[2]

0

CHAN_VERSION[1]

0

CHAN_VERSION[0]

0

SHARE_VERSION[3] TI digital share version ID. Contains 0x00.

SHARE_VERSION[2]

0

SHARE_VERSION[1]

0

SHARE_VERSION[0]

0x00

0

General

7

6

5

4

3

2

1

0

RW

N

EN_CH7

EN_CH6

EN_CH5

EN_CH4

EN_CH3

EN_CH2

EN_CH1

EN_CH0

Select channel 7

Select channel 6

Select channel 5

Select channel 4

Select channel 3

Select channel 2

Select channel 1

Select channel 0

0

0x00

0

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

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Register Maps (接下页)

表 2. Global Register Map (接下页)

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

0xFE

0x03

Vendor ID

7

6

5

4

3

2

1

0

R

N

VENDOR_ID[7]

VENDOR_ID[6]

VENDOR_ID[5]

VENDOR_ID[4]

VENDOR_ID[3]

VENDOR_ID[2]

VENDOR_ID[1]

VENDOR_ID[0]

Channel Control

RESERVED

TI vendor ID. Contains 0x03.

0

1

0xFF

0x10

0

7

6

5

4

3

2

1

RW

N

RESERVED

0

RESERVED

0

EN_SHARE_Q1

EN_SHARE_Q0

RESERVED

Select shared registers for Quad 1 (Channels 4-7).

Select shared registers for Quad 0 (Channels 0-3).

RESERVED

1

0

RESERVED

0

WRITE_ALL_CH

Allows customer to write to all channels as if they are the same, but only

allows to read back from the channel specified in 0xFC and 0xFD.

Note: EN_CH_SMB must be = 1 or else this function is invalid.

1: Enables SMBus access to the channels specified in register 0xFC.

0: The shared registers are selected, see 0xFF[5:4].

0

RW

N

EN_CH_SMB

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7.6.3 Shared Registers

表 3. Shared Register Map

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

General

Description

0x00

0x0C

I²C_ADDR[3]

I²C_ADDR[2]

I²C_ADDR[1]

I²C_ADDR[0]

RESERVED

Version Revision

RESERVED

Channel Control

RESERVED

Channel Control

RESERVED

General

I²C strap observation. The device 7-bit slave address is 0x18 +

I²C_ADDR[3:0].

7

6

5

4

3

2

1

0

R

N

0

RESERVED

0

0x01

0x02

0x03

0x04

0x00

7

6

5

4

3

2

1

0

R

N

RESERVED

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x01

0

7

6

RW

N

RESERVED

RST_I²C_REGS

RESERVED

0

RWSC

1: Reset shared registers, bit is self-clearing.

0: Normal operation

RST_I²C_MAS

1: Self-clearing reset for I²C master.

0: Normal operation

5

4

0

RWSC

RW

N

FRC_EEPRM_RD

1: Override EN_SMB and input chain status to force EEPROM

Configuration.

0: Normal operation

RESERVED

3

2

1

0

1

RW

N

RESERVED

REGS_CLOCK_EN RESERVED

I²C_MAS_CLK_EN

RESERVED

I²CSLV_CLK_EN

RESERVED

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表 3. Shared Register Map (接下页)

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

0x05

0x00

General

7

0

RW

N

DISAB_EEPRM_CFG 1: Disable Master Mode EEPROM Configuration (If not started, not

effective midway or after configuration).

0: Normal operation

6

5

0

RW

N

CRC_EN

RESERVED

ML_TEST

_CONTROL

4

0

R

N

EEPROM_READING Sets 1 when EEPROM reading is done.

_DONE

3

2

0

R

N

Y

RESERVED

CAL_CLK_INV_DIS 1: Disable the inversion of CAL_CLK_OUT.

0: Normal operation, CAL_CLK_OUT is inverted with respect to

RESERVED

CAL_CLK_IN.

RESERVED

1

0

R

N

RESERVED

TEST0_AS_CAL

_CLK

0x06

0x00

General

RESERVED

General

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x07

0x00

0

7

6

RW

R

N

RESERVED

CAL_CLK_DET

RESERVED

0

1: Indicates that CAL_CLK has been detected.

0: Indicates that CAL_CLK has not been detected.

RESERVED

5

4

3

0

RW

N

RESERVED

MR_CAL_CLK_DET 1: Disable CAL_CLK detect.

_DIS

0: Enable CAL_CLK detect.

2

1

0

RW

N

Y

RESERVED

DIS_CAL_CLK_OUT 1: Disable CAL_CLK_OUT, output is high-Z.

0: Enable CAL_CLK_OUT.

0x08

0x00

General

7

6

5

4

3

2

1

0

RW

N

RESERVED

General

RESERVED

0

0x09

0x00

0

7

6

5

4

3

R

N

RESERVED

0

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表 3. Shared Register Map (接下页)

Addr

[HEX]

Default

[HEX]

Bit

2

Mode

EEPROM

Field

Description

RESERVED

0

R

N

RESERVED

General

1

0

0x0A

0x00

7

6

5

4

3

2

1

0

RW

R

N

RESERVED

0

R

0x0B

0x00

0

7

6

R

N

EECFG_CMPLT

EECFG_FAIL

11: Not valid

10: EEPROM load completed successfully.

01: EEPROM load failed after 64 attempts.

00: EEPROM load in progress.

0

5

4

3

2

1

0

R

N

EECFG_ATMPT[5]

EECFG_ATMPT[4]

EECFG_ATMPT[3]

EECFG_ATMPT[2]

EECFG_ATMPT[1]

EECFG_ATMPT[0]

Indicates number of attempts made to load EEPROM image.

0

0x0C

0x91

1

I²C_FAST

1: EEPROM load uses Fast I²C Mode (400 kHz).

0: EEPROM load uses Standard I²C Mode (100 kHz).

7

RW

N

I²C_SDA_HOLD[2]

I²C_ SDA_HOLD[1]

I²C_ SDA_HOLD[0]

6

5

4

3

2

1

0

1

0

1

RW

N

Internal SDA Hold Time

This field configures the amount of internal hold time provided for the SDA

input relative to the SDC input. Units are 100 ns.

I²C_FLTR_DEPTH[3] I²C Glitch Filter Depth

This field configures the maximum width of glitch pulses on the SDC and

SDA inputs that will be rejected. Units are 100 ns.

I²C_FLTR_DEPTH[2]

I²C_FLTR_DEPTH[1]

I²C_FLTR_DEPTH[0]

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7.6.4 Channel Registers

表 4. Channel Register Map

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

0x00

General

7

0

RW

N

CLK_CORE_DISAB 1: Disables 10 M core clock. This is the main clock domain for all the state

machines.

0: Normal operation

6

0

RW

N

CLK_REGS_EN

1: Force enable the clock to the registers. Normally, the register clock is

enabled automatically on a needed basis.

0: Normal operation

5

4

0

RW

N

RESERVED

CLK_REF_DISAB

1: Disables the 25 MHz CAL_CLK domain.

0: Normal operation

3

2

0

RW

N

RST_CORE

RST_REGS

1: Reset the 10 M core clock domain. This is the main clock domain for all

the state machines.

0: Normal operation

RWSC

1: Reset channel registers to power-up defaults.

0: Normal operation

1

0

RW

N

RESERVED

RST_CAL_CLK

1: Resets the 25 MHz reference clock domain.

0: Normal operation

0x01

0x00

SIG_DET

7

0

R

N

SIGDET

Signal detect status.

1: Signal detected at RX inputs.

0: No signal detected at RX inputs.

6

5

4

3

2

1

0

R

N

RESERVED

0

0x02

0x00

7

6

5

4

3

2

1

0

R

N

RESERVED

CTLE_BOOST

EQ_BW[1]

RESERVED

0

R

0

R

0

RW

0

0x03

0x80

1

7

6

RW

Y

EQ stage one buffer current (strength) control. Impacts EQ bandwidth.

2'b11 yields highest bandwidth, 2'b00 yields lowest bandwidth. Refer to the

Programming Guide for more information.

0

EQ_BW[0]

5

4

3

2

1

0

RW

Y

EQ_BST2[2]

EQ_BST2[1]

EQ_BST2[0]

EQ_BST1[2]

EQ_BST1[1]

EQ_BST1[0]

EQ boost stage 2 controls. Directly goes to analog. No override bit is

needed. Refer to the Programming Guide for more information.

0

EQ boost stage 1 controls. Directly goes to analog. No override bit is

needed. Refer to the Programming Guide for more information.

0

0x04

0x90

1

7

6

RW

N

RESERVED

EQ_PD_SD

RESERVED

0

1: Power down signal detect

0: Normal operation

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表 4. Channel Register Map (接下页)

Addr

[HEX]

Default

[HEX]

Bit

Mode

EEPROM

Field

Description

5

0

RW

Y

EQ_HIGH_GAIN

1: Enable EQ high gain

0: Enable EQ low gain

RESERVED

4

3

1

0

RW

Y

EQ_EN_DC_OFF

EQ_PD_EQ

1: Power down EQ

0: Enable EQ

2

1

0

RW

N

Y

RESERVED

BG_SEL_IPP100[2] CTLE bias programming. BG_SEL_IPP100[1:0] is in Reg_0x0F[5:4].

EQ_EN_BYPASS

1: Enable EQ boost stage 1 (BST1) bypass

0: Normal operation, signal travels through boost stage 1 (BST1)

0x05

0x04

SIG_DET_CONFIG

EQ_SD_PRESET

7

6

0

RW

Y

1: Force signal detect result to 1

0: Normal operation

This bit should not be set if 0x05[6] is also set.

1: Force signal detect result to 0

0: Normal operation

0

EQ_SD_RESET

This bit should not be set if 0x05[7] is also set.

5

4

3

2

1

0

RW

Y

N

EQ_REFA_SEL[1]

EQ_REFA_SEL[0]

EQ_REFD_SEL[1]

EQ_REFD_SEL[0]

RESERVED

Signal detect assert thresholds. Refer to the Programming Guide for more

information.

0

Signal detect de-assert thresholds. Refer to the Programming Guide for

more information.

1

0

RESERVED

0

RESERVED

0x06

0xC0

7

6

5

1

0

RW

Y

DRV_SEL_VOD[1]

DRV_SEL_VOD[0]

DRV_EQ_PD_OV

Driver VOD adjust (DC gain), applicable to both linear and FIR limiting

mode. Refer to the Programming Guide for more information.

1: Driver and equalizer power down manually with Reg_0x06[3] and

Reg_0x04[3], respectively.

0: Driver and equalizer are powered down or up by default when LOS=1/0.

Driver mute override:

4

0

RW

Y

DRV_SEL_MUTE

_OV

1: Use register 0x06[1] for mute control.

0: Normal operation. Mute is automatically controlled by signal detect.

1: Power down the driver.

3

2

1

0

RW

Y

DRV_PD

0: Normal operation, driver power on or off is controlled by signal detect.

DRV_PD_CM_LOOP 1: Disable the driver’s common mode loop control circuit.

0: Normal operation, common mode loop enabled.

DRV_SEL_MUTE

1: Mute driver if override bit is enabled.

0: Normal operation

DRV_SEL_FIR

Linear versus Limiting Mode select. Refer to the Programming Guide for

more information.

1: Enable Limiting FIR mode.

0: Enable Linear mode (disable limiting FIR).

0x07

0x20

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

1

0

0x08

0x54

0

7

RW

Y

RESERVED

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表 4. Channel Register Map (接下页)

Default

[HEX]

0x09

0x0A

Bit

Mode

RW

EEPROM

Field

Description

RESERVED

6

1

0

1

0

Y

RESERVED

5

RW

RESERVED

4

RW

RESERVED

3

RW

BG_SEL_IPTAT25

1: Increases the current to the CTLE by 5%.

0: Default

2

1

0

1

RW

N

RESERVED

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x30

0

7

6

5

4

RW

N

Y

RESERVED

SD_REF_HIGH

SD_GAIN

RESERVED

0

1

Signal detect threshold controls:

11: Normal operation

10: Signal detect assert or de-assert thresholds reduced.

01: Signal detect assert or de-assert thresholds reduced.

00: Signal detect assert or de-assert thresholds reduced.

1

3

2

1

0

RW

N

RESERVED

0

0x0B

0x0C

0x0D

0x1A

7

6

5

4

3

2

1

0

RW

N

Y

N

Y

RESERVED

FIR_MAIN[4]

FIR_MAIN[3]

FIR_MAIN[2]

FIR_MAIN[1]

FIR_MAIN[0]

RESERVED

0

1

FIR Limiting mode main-cursor control. Refer to the Programming Guide for

more information.

1

0

1

0

0x40

7

6

5

4

3

2

1

0

1

RW

N

Y

N

Y

RESERVED

FIR_PST[3]

FIR_PST[2]

FIR_PST[1]

FIR_PST[0]

RESERVED

0

FIR Limiting mode post-cursor control. There is no sign bit for the post-

cursor. The post-cursor always provides a high-pass filter effect. Refer to

the Programming Guide for more information.

0

0x40

0

7

6

5

4

RW

N

Y

N

RESERVED

1

0

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表 4. Channel Register Map (接下页)

Addr

[HEX]

Default

[HEX]

Bit

3

Mode

RW

EEPROM

Field

Description

0

Y

FIR_PRE[3]

FIR_PRE[2]

FIR_PRE[1]

FIR_PRE[0]

FIR Limiting mode pre-cursor control. There is no sign bit for the pre-

cursor. The pre-cursor always provides a high-pass filter effect. Refer to the

Programming Guide for more information.

2

0

RW

1

0

RW

0

RW

0x0E

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x0F

0x00

0

7

6

5

4

RW

N

Y

RESERVED

0

BG_SEL_IPP100[1] CTLE bias programming. BG_SEL_IPP100[2] is in Reg_0x04[1].

000: 0% additional current (Default)

001: 5% additional current

0

BG_SEL_IPP100[0]

010: 10% additional current

011: 15% additional current

100: 20% additional current

101: 25% additional current

110: 30% additional current

111: 35% additional current

3

2

0

RW

Y

BG_SEL_IPH200

_v1[1]

Program pre-driver bias current:

00: 0% additional current (Default)

01: 12.5% additional current

10: 25% additional current

BG_SEL_IPH200

_v1[0]

11: 37.5% additional current

1

0

RW

Y

BG_SEL_IPH200

_v0[1]

Program driver bias current:

00: 0% additional current (Default)

01: 12.5% additional current

10: 25% additional current

BG_SEL_IPH200

_v0[0]

11: 37.5% additional current

28

DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS280BR820 is a high-speed linear repeater which extends the reach of differential channels impaired by

loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The

following sections outline typical applications and their associated design considerations.

8.2 Typical Applications

The DS280BR820 is typically used in three main application scenarios:

1. Backplane and mid-plane reach extension

2. Front-port eye opening for copper and optical applications

Line Card

Switch Fabric Card

25 G / 28 G-LR

25 G / 28 G-VSR

DS280BR820

Optical

x8

X8 25 G

/ 28 G-LR

DS280BR820

CFP/SFP28/QSFP28

ASIC

FPGA

25 G / 28 G-LR

25 G / 28 G-VSR

X8 25 G

/ 28 G-LR

DS280BR820

Passive Copper

Optical

Cable

x8

DS280BR820

CFP/SFP28/QSFP28

Backplane /

Midplane

图 6. Typical Application Diagram

注

TI recommends to AC couple the DS280BR820's high-speed outputs. In some cases,

ASIC or FPGA SerDes receivers support DC coupling, and it may be desirable to DC

couple the DS280BR820 output with the ASIC/FPGA RX input to reduce the PCB area

which would normally be consumed by AC coupling capacitors. To DC couple the

DS280BR820 output with an ASIC RX input, the ASIC RX must support DC coupling and

it must support an input common mode voltage of 1.05 V. To determine if the ASIC RX

supports DC coupling, here are some items to consider based on 图 7:

1. The ASIC RX must be AC coupled on-chip.

2. The ASIC RX should not force a DC bias on the RX pins.

3. System designers should ensure that when the PCB powers on, the power supply

rails are appropriately sequenced to prevent the DS280BR820's output common mode

voltage from forward-biasing the ESD structure of the ASIC or violating the absolute

maximum input voltage specifications of the ASIC.

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

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Typical Applications (接下页)

ASIC or FPGA RX

(3)

VCC

Termination

/ Bias

(2)

DS280BR820

RX

Rx Pins

(1)

VSS

图 7. Considerations for DC Coupling to ASIC RX

8.2.1 Backplane and Mid-Plane Reach Extension

The DS280BR820 has strong equalization capabilities that allow it to equalize insertion loss and extend the

reach of backplane channels by 17-22 dB beyond the normal capabilities of the ASICs operating over the

channel. The DS280BR820 is designed to apply gain in a linear fashion. In most cases, the DS280BR820 should

be placed with the higher loss channel segment at the input and the lower loss channel segment at the output;

however, since the DS280BR820 operates in a linear fashion, it can also be used in applications where the lower

loss channel segment is at the input and the higher loss channel segment is at the output. Refer to 图 8.

Passive Backplane/

Midplane

Line Card

Switch Fabric Card

x8 25 G / 28 G

ASIC

FPGA

x8 25 G / 28 G

Passive Backplane/

Midplane

Line Card

Switch Fabric Card

x8 25 G / 28 G

ASIC

FPGA

x8 25 G / 28 G

图 8. Typical Backplane and Mid-Plane Application Diagram

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DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Typical Applications (接下页)

Repeater

AC coupling implemented close to or inside ASIC RX

No AC coupling capacitors needed

RX0P

RX0N

TX0P

TX0N

RX1P

TX1P

TX1N

RX1N

.

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

VDD

SMBus

Slave mode

1 kΩ

EN_SMB

SDA

SDC

To system

SMBus⁽¹⁾

Address straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

SMBus Slave

mode

Float for SMBus

Slave mode

READ_EN_N

ALL_DONE_N

2.5 V

GND

VDD

Minimum

recommended

decoupling

0.1 ꢀF

(4x)

1 ꢀF

(2x)

Backplane / Mid-

plane Connector

ASIC / FPGA

Repeater

AC coupling implemented

close to or inside ASIC RX

No AC coupling

capacitors needed

RX0P

RX0N

RX1P

TX0P

TX0N

TX1P

TX1N

RX1N

.

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

VDD

SMBus

Slave mode

1 kΩ

EN_SMB

SDA

SDC

Address straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

SMBus Slave

mode

READ_EN_N

ALL_DONE_N

2.5 V

GND

VDD

Minimum

recommended

decoupling

0.1 ꢀF

(4x)

1 ꢀF

(2x)

(1) SMBus signals need to be pulled up elsewhere in the system.

图 9. Typical Backplane and Mid-Plane Schematic

31

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Typical Applications (接下页)

8.2.1.1 Design Requirements

For backplane and mid-plane reach extension application use the guidelines in the table below.

DESIGN PARAMETER

REQUIREMENT

AC Coupling Capacitors

Generally not required. 220-nF AC coupling capacitors are included

in the DS280BR820 package on the RX side.

Input Channel Insertion Loss

≥ 10 dB at 14 GHz as a rough guideline. For best performance, the

input channel insertion loss should be greater than or equal to the

equalizer boost setting used in the DS280BR820.

Output Channel Insertion Loss

Depends on downstream ASIC or FPGA SerDes capabilities. Should

be ≥ 5 dB at 14 GHz as a rough guideline.

Total (Input + Output) Channel Insertion Loss

Depends on downstream ASIC or FPGA SerDes capabilities. The

DS280BR820 can extend the reach between two ASICs by 17 to 22

dB beyond the ASICs' normal capabilities.

Link Partner TX Launch Amplitude

Link Partner TX FIR Filter

800 mV_PPto 1200 mV_PPdifferential.

Depends on the channel loss.

8.2.1.2 Detailed Design Procedure

The design procedure for backplane and mid-plane applications is as follows:

1. Determine the total number of channels on the board which require a DS280BR820 for signal conditioning.

This will dictate the total number of DS280BR820 devices required. It is generally recommended that

channels with similar total insertion loss on the board be grouped together in the same DS280BR820 device.

This will simplify the device settings, as similar loss channels generally utilize similar settings.

2. Determine the maximum current draw required for all DS280BR820 devices. This may impact the selection

of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum

power supply current by the total number of DS280BR820 devices.

3. Determine the SMBus address scheme needed to uniquely address each DS280BR820 device on the board,

depending on the total number of devices identified in step 1. Each DS280BR820 can be strapped with one

of 16 unique SMBus addresses. If there are more DS280BR820 devices on the board than the number of

unique SMBus addresses which can be assigned, then use an I²C expander like the TCA/PCA family of

I²C/SMBus switches and multiplexers to split the SMBus into multiple busses.

4. Determine if the device will be configured from EEPROM (SMBus master mode) or from the system SMBus

(SMBus slave mode).

a. If SMBus master mode will be used, provisions should be made for an EEPROM on the board with 8-bit

SMBus address 0xA0.

b. If SMBus slave mode will be used for all device configurations, an EEPROM is not needed.

5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to Power Supply Recommendations for more information.

6. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then make provisions in the

schematic and layout for a 25-MHz (±100 ppm) single-ended CMOS clock. Each DS280BR820 buffers the

clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. This allows

multiple (up to 20) DS280BR820 calibration clocks to be daisy chained to avoid the need for multiple

oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output, then no AC coupling

capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or resistor ladder is

needed between one DS280BR820 CAL_CLK_OUT output and the next DS280BR820’s CAL_CLK_IN input.

The final DS280BR820’s CAL_CLK_OUT output can be left floating. A 25 MHz clock is not required for the

DS280BR820, but it is good practice to provision for it in case there is a future plan to upgrade to a pin-

compatible TI Retimer device.

7. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then connect the INT_N pin to

an FPGA or CPU for interrupt monitoring. Note that multiple INT_N outputs can be connected together. The

common INT_N net should be pulled high to 2.5 V or 3.3 V. The INT_N pin on the DS280BR820 does not

perform the interrupt functionality that the equivalent pin on the pin-compatible Retimer device does;

however, it is good practice to provision for this in case there is a future plan to upgrade to a pin-compatible

TI Retimer device.

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DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

8.2.2 Front-Port Applications

The DS280BR820 has strong equalization capabilities that allow it to equalize insertion loss and extend the

reach of front-port channels by 17 dB beyond the normal capabilities of the ASIC while support CAUI-4 and CR4

electrical requirements. The DS280BR820 is designed to apply gain in a linear fashion in order to support longer

distances between the switch ASIC and the front-port module. A single DS280BR820 can be used to support all

eight egress channels or all eight ingress channels for two 100 GbE ports. 图 10 illustrates this configuration.

Line Card or Top-of-Rack Switch

Egress signal

conditioning

x8 25 G SR/MR/LR

DS280BR820

VSR

DS280BR820

Optical or Copper

Optical

x8 25 G SR/MR/LR

Ingress signal conditioning

(optional in some systems)

CFP/SFP28/QSFP28

Mezzanine

ASIC

FPGA

Mezzanine

DS280BR820

Optical or Copper

x8 25 G SR/MR/LR

Optical

DS280BR820

Ingress signal conditioning

(optional in some systems)

CFP/SFP28/QSFP28

图 10. Typical Front-Port Application Diagram

Standard front-port modules have AC coupling capacitors included inside the module. The DS280BR820,

therefore, is ideal for front-port Egress signal conditioning applications since it includes AC coupling capacitors

on the input (RX) side and does not include AC coupling capacitors on the output (TX) side.

Egress signal

conditioning

x8 25G SR/MR/LR

VSR

DS280BR820

QSFP,

SFP, etc.

ASIC or

FPGA

图 11. DS280BR820 Recommended for Front-port Egress

The optimum solution for front-port Ingress signal conditioning applications depends on whether the ASIC RX

supports DC coupling and whether it can support an input common mode voltage of 1.05 V. For further guidance

on determining if the ASIC RX supports DC coupling, refer to 图 7. If the ASIC RX supports DC coupling and can

tolerate an input common mode voltage of 1.05 V or less, then the DS280BR820 is the optimum solution for

front-port Ingress signal conditioning. If the ASIC RX does not support DC coupling or cannot tolerate an input

common mode voltage of 1.05 V, then the pin-compatible DS280BR810 may be the optimum solution.

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

ASIC or FPGA

SerDes RX supports

DC coupling and

tolerates DC input

common mode

QSFP,

SFP, etc.

DS280BR820

G1.05V

x8 25G SR/MR/LR

Ingress signal

conditioning

图 12. DS280BR820 Recommended for Front-port Ingress

QSFP,

SFP, etc.

ASIC or FPGA

SerDes RX does not

DS280BR810

support DC

x8 25G SR/MR/LR

Ingress signal

conditioning

coupling or

requires DC input

common mode

<<1.05V

QSFP,

SFP, etc.

DS280BR820

x8 25G SR/MR/LR

图 13. DS280BR820 or DS280BR810 Recommended for Front-port Ingress

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DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Egress Repeater

AC coupling implemented close to or inside ASIC RX

No AC coupling capacitors needed

RX0P

RX0N

TX0P

TX0N

RX1P

RX1N

TX1P

TX1N

.

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

VDD

SMBus

Slave mode

1 kΩ

EN_SMB

SDA

SDC

To system

SMBus⁽¹⁾

Address straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

SMBus Slave

mode

Float for SMBus

Slave mode

READ_EN_N

ALL_DONE_N

2.5 V

GND

VDD

Minimum

recommended

decoupling

0.1 ꢀF

(4x)

1 ꢀF

(2x)

Two 100 G ports

(e.g. 2x1 stacked

QSFP28)

Switch ASIC

Ingress Repeater

AC coupling implemented

close to or inside ASIC RX

No AC coupling

capacitors needed

RX0P

RX0N

RX1P

TX0P

TX0N

TX1P

TX1N

RX1N

.

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

VDD

SMBus

Slave mode

1 kΩ

EN_SMB

SDA

SDC

Address straps

(pull-up, pull-

down, or float)

ADDR0

ADDR1

SMBus Slave

mode

READ_EN_N

ALL_DONE_N

2.5 V

GND

VDD

Minimum

recommended

decoupling

0.1 ꢀF

(4x)

1 ꢀF

(2x)

(1) SMBus signals need to be pulled up elsewhere in the system.

图 14. Typical Front-port Schematic

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

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8.2.2.1 Design Requirements

This section lists some critical areas for high speed printed circuit board design consideration and study.

DESIGN PARAMETER

REQUIREMENT

AC Coupling Capacitors

Generally not required. 220 nF AC coupling capacitors are included

in the DS280BR820 package on the RX side.

Input Channel Insertion Loss

Output Channel Insertion Loss

≥ 10 dB at 14 GHz as a rough guideline. For best performance, the

input channel insertion loss should be greater than or equal to the

equalizer boost setting used in the Repeater.

For best performance in egress applications, place the Repeater

close to the front-port cage.

For best performance in ingress applications, place the Repeater

with ≥ 5 dB loss at 14 GHz between the output and the downstream

ASIC.

Switch ASIC TX Launch Amplitude

600 mVppd to 1000 mVppd

8.2.2.2 Detailed Design Procedure

The design procedure for front-port applications is as follows:

1. Determine the total number of channels on the board which require a DS280BR820 for signal conditioning.

This will dictate the total number of DS280BR820 devices required for the board. It is generally

recommended that channels belonging to the same QSFP port be grouped together in the same

DS280BR820 device. This will simplify the device settings, as similar loss channels generally utilize similar

settings.

2. Determine the maximum current draw required for all DS280BR820 devices. This may impact the selection

of the regulator for the 2.5 V supply rail. To calculate the maximum current draw, multiply the maximum

power supply current by the total number of DS280BR820 devices.

3. Determine the SMBus address scheme needed to uniquely address each DS280BR820 device on the board,

depending on the total number of devices identified in step 1. Each DS280BR820 can be strapped with one

of 16 unique SMBus addresses. If there are more DS280BR820 devices on the board than the number of

unique SMBus addresses which can be assigned, then use an I²C expander like the TCA/PCA family of

I²C/SMBus switches and multiplexers to split the SMBus into multiple busses.

4. Determine if the device will be configured from EEPROM (SMBus master mode) or from the system I²C bus

(SMBus slave mode).

1. If SMBus master mode will be used, provisions should be made for an EEPROM on the board with 8-bit

SMBus address 0xA0.

2. If SMBus slave mode will be used for all device configurations, an EEPROM is not needed.

5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to Power Supply Recommendations for more information.

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DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

8.2.3 Application Curves

8.2.3.1 Pattern Generator Characteristics

All of the example application results in the sections which follow were tested using a pattern generator with the

following characteristics.

Pattern

Generator

VOD = 0.8 V-pp,

DE = 0 dB,

PRBS9

Sampling Scope

BW = 35 GHz,

Built-in CDR and

Precision

Keysight 11742A

DC block

Transmission Line

Timebase

图 15. Pattern Generator Test Setup

图 16. Pattern Generator Output at 25.78125 Gbps, 800

图 17. Pattern Generator Output at 10.31250 Gbps, 800

mVppd, PRBS9

表 5. Pattern Generator Characteristics

25.78125 Gbps

10.3125 Gbps

~800 mVppd

Differential peak-to-peak voltage (VOD)

~800 mVppd

Channel loss between Pattern Generator and

Scope

2 dB @ 12.9 GHz

1 dB @ 5.2 GHz

Total Jitter @ 1E-15

8.0 ps_P-P

13.4 ps_P-P

596 mV_P-P

Differential Eye Height @ 1E-15

448 mV_P-P

8.2.3.2 Equalizing Moderate Pre-Channel Loss

This example application result demonstrates the DS280BR820 equalizing for pre-channel insertion loss

introduced by an FR4 channel.

Sampling Scope

Pattern Generator

VOD = 0.8 V-pp,

DE = 0 dB, PRBS9

DS280

EVM

Keysight 11742A

DC block

BW = 35 GHz,

Built-in CDR and

Precision Timebase

Transmission Line

IN

OUT

图 18. 5 in input Channel and Minimal Output Channel Test Setup

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DS280BR820

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图 19. 25.78125 Gbps CAUI-4 Eye Mask with 5 in Input

图 20. 10.3125 Gbps nPPI Eye Mask with 5 in Input

Channel and Minimal Output Channel

表 6. Settings and Measurements for CAUI-4 and nPPI with 5 in Input Channel and Minimal Output

Channel

25.78125 Gbps (CAUI-4)

10.3125 Gbps (nPPI)

Transmission Line 1

DS280BR820 Rx Channel Loss

DS280BR820 Tx Channel Loss

EQ BST1

5 in 5 mil FR4 + 8 in SMA cable

14 dB @ 12.9 GHz

6 dB @ 5.2 GHz

4.5 dB @ 12.9 GHz

2 dB @ 5.2 GHz

3

EQ BST2

0

EQ BW

3

VOD

3

Low

2

Low

EQ DC Gain Mode

Total Jitter @ 1E-15

Differential Eye Height @ 1E-15

Mask violations

11.9 ps_P-P

338 mV_P-P

0

13.0 ps_P-P

544 mV_P-P

0

8.2.3.3 Equalizing High Pre-Channel Loss

This example application result demonstrates the DS280BR820 equalizing for pre-channel insertion loss

introduced by an FR4 channel.

Sampling Scope

Pattern Generator

VOD = 0.8 V-pp,

DE = 0 dB, PRBS9

DS280

EVM

Keysight 11742A

DC block

BW = 35 GHz,

Built-in CDR and

Precision Timebase

Transmission Line

IN

OUT

图 21. 10 in Input Channel and Minimal Output Channel Test Setup

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DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

图 22. 25.78125 Gbps CAUI-4 Eye Mask with 10 in Input

Channel and Minimal Output Channel

图 23. 10.1325 Gbps nPPI Eye Mask with 10 in Input

Channel and Minimal Output Channel

表 7. Settings and Measurements for CAUI-4 and nPPI with 10 in Input Channel and Minimal Output

Channel

25.78125 Gbps (CAUI-4)

10.3125 Gbps (nPPI)

Transmission Line 1

DS280BR820 Rx Channel Loss

DS280BR820 Tx Channel Loss

EQ BST1

10 in 5 mil FR4 + 8 in SMA cable

22 dB @ 12.9 GHz

10 dB @ 5.2 GHz

4.5 dB @ 12.9 GHz

2 dB @ 5.2 GHz

6

EQ BST2

1

EQ BW

3

VOD

3

Low

2

Low

EQ DC Gain Mode

Total Jitter @ 1E-15

Differential Eye Height @ 1E-15

Mask violations

11.3 ps_P-P

210 mV_P-P

0

13.5 ps_P-P

532 mV_P-P

0

8.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss

This example application result demonstrates the DS280BR820 equalizing for pre-channel and post-channel

insertion loss introduced by FR4 channels.

Sampling Scope

Pattern Generator

VOD = 0.8 V-pp,

DE = 0 dB, PRBS9

DS280

EVM

Keysight 11742A

DC block

BW = 35 GHz,

Built-in CDR and

Precision Timebase

Transmission Line 1

IN

OUT

Transmission Line 2

图 24. 10 in Input Channel and 5 in Output Channel Test Setup

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DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Time (6.46 ps/DIV)

图 26. 25.78125 Gbps CAUI-4 Eye Mask with 10 in Input

图 25. 25.78125 Gbps Eye Diagram with 10 in Input

Channel and 5 in Output Channel, FIR Limiting Mode

Channel and 5 in Output Channel, Linear Mode

图 27. 10.1325 Gbps nPPI Eye Mask with 10 in Input Channel and 5 in Output Channel, Linear Mode

表 8. Settings and Measurements for CAUI-4 and nPPI with 10 in Input Channel and 5 in Output Channel

25.78125 Gbps (CAUI-4)

10.3125 Gbps (nPPI)

Transmission Line 1

Transmission Line 2

DS280BR820 Rx Channel Loss

DS280BR820 Tx Channel Loss

EQ BST1

10 in 5 mil FR4 + 8 in SMA cable 10 in 5 mil FR4 + 8 in SMA cable 10 in 5 mil FR4 + 8 in SMA cable

5 in 5 mil FR4 + 8 in SMA cable

22 dB @ 12.9 GHz

10 dB @ 5.2 GHz

14.5 dB @ 12.9 GHz

6 dB @ 5.2 GHz

7

EQ BST2

7

EQ BW

3

2

VOD

3

EQ DC Gain Mode

Tx Mode

Low

Linear

N/A

Low

FIR Limiting

Linear

N/A

Tx Main-Cursor

16

Tx Pre-Cursor

N/A

5

10

N/A

Tx Post-Cursor

N/A

Total Jitter @ 1E-15

Differential Eye Height @ 1E-15

Mask violations

14.8 ps_P-P

67 mV_P-P

N/A

14.8 ps_P-P

118 mV_P-P

0

17.0 ps_P-P

407 mV_P-P

0

40

DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

8.2.3.5 Output in FIR Limiting Mode with 16T Pattern

This example application result demonstrates the DS280BR820's output in FIR limiting mode.

Pattern Generator

VOD = 0.8 V-pp,

DE = 0 dB, 16T

Pattern

Sampling Scope

DS280

EVM

Keysight 11742A

DC block

BW = 35 GHz,

Built-in CDR and

Precision Timebase

IN

OUT

图 28. FIR Test Setup

Time (100 ps/DIV)

图 29. FIR Post-Cursor Example

图 30. FIR Pre-Cursor Example

表 9. Example FIR Settings

图 29

图 30

(Pre, Main, Post) = (0, 12, 0)

(Pre, Main, Post) = (0, 16, 15)

(Pre, Main, Post) = (0, 12, 0)

(Pre, Main, Post) = (11, 12, 0)

8.3 Initialization Set Up

The DS280BR820 does not require any particular start-up or initialization sequence. The device defaults to a

medium boost value for each channel. It is recommend that the channels be appropriately configured before data

traffic is transmitted to the DS280BR820 to avoid issues with the link partner ASIC's adaption. Example

configuration settings can be found in the DS280BR820 Programming Guide.

9 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the recommended operating conditions outlined in

Specifications in terms of DC voltage, AC noise, and start-up ramp time.

2. The maximum current draw for the DS280BR820 is provided in Specifications. This figure can be used to

calculate the maximum current the supply must provide. Typical mission-mode current draw can be inferred

from the typical power consumption in Specifications.

3. The DS280BR820 does not require any special power supply filtering, such as ferrite beads, provided the

recommended operating conditions are met. Only standard supply decoupling is required. Typical supply

decoupling consists of a 0.1-μF capacitor per power pin, and single 1.0-μF and 10-μF bulk capacitors.

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DS280BR820

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10 Layout

10.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly

underneath the device is one option if the board design permits.

2. High-speed differential signals should be tightly coupled, skew matched, and impedance controlled.

3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care

should be taken to minimize the via stub, either by transitioning through most or all layers, or by back drilling.

4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by

counteracting the pad capacitance.

5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to

the GND planes on other layers. This has the added benefit of improving thermal conductivity from the

device to the board.

6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual

size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined

solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References

website.

10.2 Layout Examples

10.2.1 Stripline Example

The following example layout demonstrates how all signals can be escaped from the BGA array using stripline

routing on a generic 8+ layer stackup. This example layout assumes the following:

•

Trace width: 0.15 mm (6 mil)

Trace edge-to-edge spacing: 0.16 mm (6.4 mil)

VIA finished hole size (diameter): 0.254 mm (10 mil)

VIA-to-VIA spacing: 1.0 mm (39 mil), to enhance PCB manufacturability

No VIA-in-pad used

Note that many other escape routing options exist using different trace width and spacing combinations. The

optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.

Microstrip escape routing is also possible and may be preferable in some application scenarios such as front-port

applications.

图 32. Stripline Example, Internal Signal Layer 1

图 31. Stripline Example, Top Layer

42

DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

Layout Examples (接下页)

图 34. Stripline Example, Bottom Layer

图 33. Stripline Example, Internal Signal Layer 2

10.2.2 Microstrip Example

The following example layout demonstrates how all signals can be escaped from the BGA array using microstrip

routing on a generic 8+ layer stackup. This example layout assumes the following:

•

Normal trace width: 0.27 mm (10.5 mil)

Neck-down trace width: 0.18 mm (7 mil)

Trace edge-to-edge spacing: 0.51 mm (20 mil)

VIA finished hole size (diameter): 0.203 mm (8 mil)

VIA-to-VIA spacing: 0.8 mm (31.5 mil)

No VIA-in-pad used

Note that many other escape routing options exist using different trace width and spacing combinations. The

optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.

Stripline escape routing is also possible and may be preferable in some application scenarios such as backplane

applications.

图 36. Microstrip Example, Internal Signal Layer 1

图 35. Microstrip Example, Top Layer

43

DS280BR820

ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

www.ti.com.cn

Layout Examples (接下页)

图 38. Microstrip Example, Bottom Layer

图 37. Microstrip Example, Internal Signal Layer 2

44

DS280BR820

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ZHCSKG2B –SEPTEMBER 2016–REVISED OCTOBER 2019

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《DS280BR810EVM 用户指南》

德州仪器 (TI)，《DS280BR810 编程指南》

德州仪器 (TI)，《了解 25G 和 28G 中继器和重定时器的 EEPROM 编程》应用报告

德州仪器 (TI)，《TI 25G 和 28G 重定时器和中继器的选择指南》应用报告

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 商标

All trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

45

PACKAGE OUTLINE

ZBL0135A

NFBGA - 1.43 mm max height

SCALE 1.300

PLASTIC BALL GRID ARRAY

13.1

12.9

A

B

BALL A1 CORNER

8.1

7.9

(0.97)

1.43 MAX

C

SEATING PLANE

0.2 C

0.46

0.25

BALL TYP

TYP

11.2 TYP

SYMM

(0.9) TYP

J

H

G

F

(0.8) TYP

SYMM

6.4

E

D

C

TYP

0.51

135X

0.41

B

A

0.15

0.08

C A B

C

0.8 TYP

1

2

3

4

5

6

7

8

9

10 11 12 13

14 15

BALL A1 CORNER

0.8 TYP

4222880/A 04/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZBL0135A

NFBGA - 1.43 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

135X ( 0.4)

4

5

6

7

9

10

14 15

1

2

3

8

11 12 13

A

B

C

(0.8) TYP

D

E

F

G

H

J

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

METAL

UNDER

SOLDER MASK

0.05 MAX

0.05 MIN

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4222880/A 04/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

ZBL0135A

NFBGA - 1.43 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

4

5

6

7

8

9

10

14 15

1

2

3

11 12 13

A

B

(0.8) TYP

C

D

E

F

SYMM

G

H

J

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4222880/A 04/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DS280BR820ZBLR
厂家：	TEXAS INSTRUMENTS
描述：	28Gbps 低功耗 8 通道转接驱动器 \| ZBL \| 135 \| -40 to 85 驱动驱动器
文件：	总53页 (文件大小：4429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS280BR820ZBLR [TI]

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DS2890-000

DS2890-000/TR