DS80EP100SD/NOPB [TI]
适用于背板和电缆的 5 至 12.5Gbps 省电均衡器 | NGF | 6 | -40 to 85;
| 型号： | DS80EP100SD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于背板和电缆的 5 至 12.5Gbps 省电均衡器 | NGF | 6 | -40 to 85 电信 光电二极管 电信集成电路 |
| 文件： | 总17页 (文件大小：4888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables
Check for Samples: DS80EP100
1
FEATURES
DESCRIPTION
TI’s Power-saver equalizer compensates for
transmission medium losses and minimizes medium-
2
•
5 to 12.5 Gbps Operation
•
•
•
•
No Power or Ground Required
induced
deterministic
jitter.
Performance
is
Equalization Effective Anywhere in Data Path
Equalizes CML, LV-PECL, LVDS Signals
guaranteed over the full range of 5 to 12.5 Gbps. The
DS80EP100 requires no power to operate. The
equalizer operates anywhere in the data path to
minimize media-induced deterministic jitter in both
FR4 traces and cable applications. Symmetric I/O
structures support full duplex or half duplex
applications. Linear compensation is provided
independent of line coding or protocol. The device is
ideal for both bi-level and multi-level signaling.
Symmetric I/O Structures Provide Equal Boost
for Bi-directional Operation
•
•
•
7 dB Maximum Boost
Code Independent, 8b/10b or Scrambled
Supports Both Bi-level and Multi-level
Signaling
The equalizer is available in a 6 pin leadless WSON
package with a space saving 2.2 mm X 2.5 mm
footprint. This tiny package provides maximum
flexibility in placement and routing of the Power-saver
equalizer.
•
•
•
•
Extends Reach Over Backplanes and Cables
Compatible with PCI-Express Gen1 and Gen2
Compatible with XAUI
Will Operate in Series with Existing Active
Equalizer
•
Easy to Handle 6 Pin WSON
Simplified Application Diagram
LINE CARD
Tx/Rx
DS80EP100
SWITCH CARD
Rx/Tx
IOA+
IOB+
Z
= 100W
Diff
IOA-
IOB-
PASSIVE BACKPLANE/CABLE INTERCONNECT
DS80EP100
IOA+
IOB+
Tx/Rx
Z
= 100W
Z
Diff
= 100W
Rx/Tx
Diff
IOA-
IOB-
Note: The DS80EP100 provides the flexibility of passing the data from either side of the device. It can be placed
anywhere in the data path.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
PIN DESCRIPTIONS
Pin Name
Pin Number
I/O Type(1)
Description
High speed differential I/O
IOA-
IOA+
3
1
I/O
I/O
N/A
Symmetric differential I/O
Symmetric differential I/O
IOB-
IOB+
4
6
NC
2, 5
Reserved.
Exposed
Pad
DAP
Do not connect.
(1) I = Input / O = Output
Connection Diagram
IOA+ NC
IOA-
3
1
2
DAP - NC
5
6
4
IOB+ NC
IOB-
Figure 1. Bottom View
2.2mm x 2.5mm 6-Pin WSON Package
See Package Number NHK0014A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
INPUT/OUTPUT
(IOA+ and IOB+) or (IOA- and IOB-)
(IOA+ and IOA-) or (IOB+ and IOB-)
(IOA+ and IOB-) or (IOA- and IOB+)
+2V
+4V
+4V
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
Lead Temperature
Soldering, 4 sec
+260°C
1.3kV
ESD Rating
HBM, 1.5 kΩ, 100 pF
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Recommended Operating Conditions
Min
−40
5
Typ
Max
+85
12.5
Units
°C
Ambient Temperature
Bit Rate
25
Gbps
2
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
(1)
Electrical Characteristics
Over recommended operating conditions unless other specified. All parameters are guaranteed by test, statistical analysis or
design.
(2)
Symbol
Parameter
Input voltage swing
Equalization
Conditions
Min
Typ
1000
6
Max
Units
mVp-p
dB
VIN
See(3)
3600
6.25 GHz relative to 100MHz
Differential input return
loss
100 MHz – 6.25 GHz, with fixture's effect de-
embedded
RLI
RLO
RIN
RO
15
15
dB
dB
Ω
Differential output return
loss
100 MHz – 6.25 GHz, with fixture's effect de-
embedded IOA+, or IOB+ = static high.
Differential across IOA+ and IOA-, or IOB+ and
IOB-, ZLOAD = 100Ω
100
Input Impedance
Differential across IOA+ and IOA-, or IOB+ and
IOB-, ZSOURCE = 100Ω
Ω
Output Impedance
Through Response
100
Relative to ideal load, see Figure 3 for setup
See Figure 4 and Table 1 for limits
Resistance IOA+ to IOA-
and IOB+ to IOB-
R1
R2
R3
150
Ω
Ω
Ω
No load, high impedance on all ports
Resistance IOA+ to IOB+
and IOA- to IOB-
50
No load, high impedance on all ports
No load, high impedance on all ports
Resistance IOA+ to IOB-
and IOA- to IOB+
150
DC Gain
ZLOAD = 100Ω
0.4
(IOA/IOB or IOB/IOA)
5 Gbps, 20 in of 6mil microstrip FR4
Residual deterministic
jitter
DJ1
DJ2
DJ3
0.15
UIp-p
UIp-p
UIp-p
(4)
See
6.25 Gbps, 20 in of 6mil microstrip FR4
Residual deterministic
jitter
0.15
0.15
0.20
0.20
(4) (5)
See
8 Gbps, 20 in of 6mil microstrip FR4
Residual deterministic
jitter
(4) (5)
See
Residual deterministic
jitter
10 Gbps, 20 in of 6mil microstrip FR4
See
DJ4
DJ5
0.15
0.15
UIp-p
UIp-p
(4)
Residual deterministic
jitter
12.5 Gbps, 14 in of 6mil microstrip FR4
(4)
See
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Typical values represent most likely parametric norms, TA = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
(3) Differential signal to Equalizer, measured at the input to a transmission line, see point A of Figure 2. The transmission line is Z0 = 100Ω,
6-mil, microstrip in FR4 material.
(4) Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Test pattern: PRBS- 7 .
(5) Specification is guaranteed by characterization and is not tested in production.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS80EP100
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
TEST SETUP DIAGRAMS
A
B
C
Test Board
FR4 Test Channel
0 in < L < 20 in
Signal Source
DS80EP100
Oscilloscope
= Edge-Mounted SMA Connector
Figure 2. Transient Test Setup Diagram
Ç 0.5 in DUAL 50W
MICROSTRIP LINE
Ç 0.5 in DUAL 50W
MICROSTRIP LINE
VNA Source
DS80EP100
VNA Detector
= Edge-Mounted SMA Connector
Figure 3. Frequency Response Test Circuit
Typical Equalizer Transfer Function
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
Figure 4. Typical Equalizer Transfer Function
4
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
Table 1. Typical Through Response
Frequency (GHz)
DS80EP100 Attenuation Typ (dB)
0.1
0.5
1
-8.25
-7.64
-6.12
-4.68
-3.57
-2.22
-1.66
-1.53
-1.77
-2.28
-2.8
1.5
2
3
4
5
6
7
8
9
-3.47
-3.91
10
Block Diagram
Z3
Z2
Z3
IOA+
Z1
Z1
IOB+
A
B
IOA-
Z1
Z1
IOB-
Figure 5. Simplified Block Diagram
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS80EP100
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
APPLICATION INFORMATION
DS80EP100 DEVICE DESCRIPTION
The DS80EP100 Power-Saver equalizer is a passive network circuit composed of resistive, capacitive, and
inductive components (See Figure 5). A Differential bridged T-network compensates for the transmission medium
losses and minimizes medium-induced deterministic jitter with FR4 and cables. The equalizer attenuates low
frequency signals and is a bandpass filter at the resonant frequency. The response is linear and symmetric.
I/O TERMINATIONS
The DS80EP100 I/O impedance is 100Ω differential. The equalizer is designed for 100Ω-balanced differential
signals and is not intended for single-ended transmission.
LINEAR COMPENSATION
The unique linear compensation feature of the DS80EP100 combined with the tiny package allows maximum
flexibility in placement. The equalizer can be placed anywhere in the data path and will provide the same
compensation at the receiving circuit. (See Simplified Application Diagram)
SYMMETRIC I/O STRUCTURES
The symmetry of the passive equalization network allows bi-directional operation. Signals receive equal
compensation regardless of the direction of data flow. (See Figure 5).
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS AND NO CONNECT PADS
The differential I/Os must have a controlled differential impedance of 100Ω. It is preferable to route all differential
lines exclusively on one layer of the board. The use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmetrically for each side of a given differential pair.
Differential signals should be routed away from other signals and noise sources on the printed circuit board. Pin
2, Pin 5, and the center DAP have to be left as no connect. Therefore, do not connect the landing pads of these
pins to the power or ground plane. See AN-1187 for additional information on the WSON package.
6
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
Typical Characteristics
Residual Deterministic Jitter
Residual Deterministic Jitter
vs.
vs.
FR4 Length
FR4 Length
0.5
0.4
0.3
0.2
0.1
0
0.5
10 Gbps
Unequalized
6.25 Gbps
0.4
0.3
0.2
0.1
0
8 Gbps
5 Gbps
Unequalized
Equalized
Equalized
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FR4 LENGTH (in)
FR4 LENGTH (in)
Figure 6.
Figure 7.
Eye Height
vs.
FR4 Length
Eye Height
vs.
FR4 Length
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
Unequalized
Unequalized
5 Gbps
8 Gbps
10 Gbps
6.25 Gbps
Equalized
Equalized
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FR4 LENGTH (in)
FR4 LENGTH (in)
Figure 8.
Figure 9.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS80EP100
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total Jitter
Unequalized Signal (20in FR4, 5Gbps, PRBS7)
Equalized Signal (20in FR4, 5Gbps, PRBS7)
Figure 10.
Figure 11.
Equalized Signal (Zoom) (20in FR4, 5Gbps, PRBS7)
Unequalized Signal (20in FR4, 6.25Gbps, PRBS7)
Figure 12.
Figure 13.
Equalized Signal (20in FR4, 6.25Gbps, PRBS7)
Equalized Signal (Zoom) (20in FR4, 6.26Gbps, PRBS7)
Figure 14.
Figure 15.
8
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total
Jitter (continued)
Unequalized Signal (20in FR4, 8Gbps, PRBS7)
Equalized Signal (20in FR4, 8Gbps, PRBS7)
Figure 16.
Figure 17.
Equalized Signal (Zoom) (20in FR4, 8Gbps, PRBS7)
Unequalized Signal (20in FR4, 10Gbps, PRBS7)
Figure 18.
Figure 19.
Equalized Signal (20in FR4, 10Gbps, PRBS7)
Equalized Signal (Zoom) (20in FR4, 10Gbps, PRBS7)
Figure 20.
Figure 21.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS80EP100
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total
Jitter (continued)
Unequalized Signal (14in FR4, 12.5Gbps, PRBS7)
Equalized Signal (14in FR4, 12.5Gbps, PRBS7)
Figure 22.
Figure 23.
Unequalized Signal (5m 26AWG Twin-AX Cable, 5Gbps,
PRBS7)
Equalized Signal (Zoom) (14in FR4, 12.5Gbps, PRBS7)
Figure 24.
Figure 25.
Equalized Signal (5m 26AWG Twin-AX Cable, 5Gbps,
PRBS7)
Equalized Signal (Zoom) (5m 26AWG Twin-AX Cable,
5Gbps, PRBS7)
Figure 26.
Figure 27.
10
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
DS80EP100
www.ti.com
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total
Jitter (continued)
Unequalized Signal (5m 26AWG Twin-AX Cable, 8Gbps,
PRBS7)
Equalized Signal (5m 26AWG Twin-AX Cable, 8Gbps,
PRBS7)
Figure 28.
Figure 29.
Equalized Signal (Zoom) (5m 26AWG Twin-AX Cable,
8Gbps, PRBS7)
Unequalized Signal (5m 26AWG Twin-AX Cable, 10Gbps,
PRBS7)
Figure 30.
Figure 31.
Equalized Signal (5m 26AWG Twin-AX Cable, 10Gbps,
PRBS7)
Equalized Signal (Zoom) (5m 26AWG Twin-AX Cable,
10Gbps, PRBS7)
Figure 32.
Figure 33.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS80EP100
DS80EP100
SNLS279C –JULY 2007–REVISED FEBRUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (February 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS80EP100
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS80EP100SD/NOPB
ACTIVE
WSON
NGF
6
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
80S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS80EP100SD/NOPB
WSON
NGF
6
1000
178.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON NGF
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
DS80EP100SD/NOPB
6
1000
Pack Materials-Page 2
MECHANICAL DATA
NGF0006A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
DS80EP100SDX/NOPB
5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables 6-WSON -40 to 85
TI
DS80PCI102
DS80PCI102 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 1 Lane PCI Express Repeater with Equalization and De-Emphasis
TI
DS80PCI402
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis
TI
DS80PCI402SQ
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis
TI
DS80PCI402SQE
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis
TI
DS80PCI800
2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater with Equalization and De-Emphasis
TI
©2020 ICPDF网 联系我们和版权申明