DS80PCI800SQE/NOPB [TI]
DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater; DS80PCI800的2.5Gbps / 5.0 Gbps的/ 8.0 Gbps的8通道的PCI Express中继器
| 型号： | DS80PCI800SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater |
| 文件： | 总45页 (文件大小：3790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS80PCI800
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SNLS334E –APRIL 2011–REVISED MARCH 2012
DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express
Repeater with Equalization and De-Emphasis
Check for Samples: DS80PCI800
1
FEATURES
mode)
•
•
0.2 UI of residual deterministic jitter at 8 Gbps
after 40” of FR4 or 10m 30awg PCIe Cable
2
•
Comprehensive family, proven system inter-
operability
Low power dissipation with ability to turnoff
unused channels: 65 mW/channel
–
–
–
DS80PCI102 : x1 PCIe Gen-1/2/3
DS80PCI402 : x4 PCIe Gen-1/2/3
DS80PCI800 : x8/x16 PCIe Gen-1/2/3
•
•
Automatic receiver detect (hot-plug)
Multiple configuration modes:
Pins/SMbus/Direct-EEPROM load
•
•
•
Automatic rate detect and adaptation to Gen-
1/2/3 speeds
•
Flow-thru pinout: 54-pin LLP (10 mm x 5.5 mm,
0.5 mm pitch)
Seamless support for Gen-3 transmit FIR
handshake
•
•
•
Single supply voltage: 2.5V or 3.3V (selectable)
3 kV HBM ESD rating
Rate adaptive receive EQ (up to 36 dB),
transmit de-emphasis (up to 12 dB) only Gen-
1/2
−40 to 85°C operating temperature range
•
Adjustable Transmit VOD: 0.8 to 1.3 Vp-p (pin
DESCRIPTION
The DS80PCI800 is a low power, 8 channel repeater with 4-stage input equalization, and output de-emphasis
driver to enhance the reach of PCI express serial links in board-to-board or cable interconnects. Ideal for higher
density x8 and x16 PCI express configurations, the DS80PCI800 automatically detects and adapts to Gen-1,
Gen-2 and Gen-3 data rates for easy system upgrade.
Each channel supports seamless detection and management of the new Gen-3 transmit equalizer coefficients
(FIR tap) handshake protocol and PCIe control signals such as transmit idle, beacon etc. without external system
intervention. An automatic receive detection circuitry controls the input termination impedance based upon
endpoint insertion (hot-plug events). These features guarantee PCIe interoperability at both the electrical and
system level, while reducing design complexity.
Powered by National’s SiGe BiCMOS process, DS80PCI800 offers programmable transmit de-emphasis (up to
12 dB), transmit VOD (up to 1300 mVp-p) and receive equalization (up to 36 dB) to enable longer distance
transmission in lossy copper cables (10m+), or backplanes (40”+) with multiple connectors. The receiver is
capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) introduced by the
interconnect medium.
The programmable settings can be applied easily via pins, software (SMBus/I2C) or loaded via an external
EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power
up, which eliminates the need for an external microprocessor or software driver.
With a low power consumption and control to turn-off unused channels, the DS80PCI800 is part of National's
PowerWise family of energy efficient devices.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
DS80PCI800
SNLS334E –APRIL 2011–REVISED MARCH 2012
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Typical Application
8
TX
RX
Add-in Card
End Point
PCIe
Connector
8
DS80PCI800
8
8
RX
System Board
Root Complex
DS80PCI800
PCIe
Connector
TX
Block Diagram - Detail View Of Channel (1 Of 8)
VOD/DeEMPHASIS
CONTROL
VDD
DEMA/B
SMBus
RATE
DET
Auto/Manual
RXDET
EQ
INx_n+
INx_n-
OUTBUF
OUTx_n+
OUTx_n-
TX Idle Enable
IDLE
DET
EQA/B
SMBus
SMBus
2
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SNLS334E –APRIL 2011–REVISED MARCH 2012
Pin Diagram
SMBUS AND CONTROL
45
44
43
42
41
40
39
38
OUTB_0+
INB_0+
INB_0-
INB_1+
INB_1-
1
2
3
4
OUTB_0-
OUTB_1+
OUTB_1-
VDD
INB_2+
INB_2-
INB_3+
INB_3-
5
6
7
8
OUTB_2+
OUTB_2-
OUTB_3+
9
DAP = GND
OUTB_3-
VDD
VDD
37
36
35
34
33
32
31
10
11
12
13
14
15
16
17
INA_0+
INA_0-
INA_1+
OUTA_0+
OUTA_0-
OUTA_1+
OUTA_1-
OUTA_2+
OUTA_2-
OUTA_3+
OUTA_3-
INA_1-
VDD
INA_2+
INA_2-
30
29
28
INA_3+
INA_3-
18
Figure 1. DS80PCI800 Pin Diagram 54 lead
Pin Descriptions
Pin Functions
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
INB_0+, INB_0-,INB_1+,
INB_1-,INB_2+, INB_2-
,INB_3+, INB_3-,
1, 2, 3, 4,
5, 6, 7, 8,
I
Inverting and non-inverting differential inputs to bank B equalizer. A
gated on-chip 50Ω termination resistor connects INB_n+ to VDD and
INB_n- to VDD when enabled.
INA_0+, INA_0-,INA_1+,
INA_1-,INA_2+, INA_2-
,INA_3+, INA_3-
10, 11, 12, 13,
15, 16, 17, 18
I
Inverting and non-inverting differential inputs to bank B equalizer. A
gated on-chip 50Ω termination resistor connects INA_n+ to VDD and
INA_n- to VDD when enabled.
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Pin Descriptions (continued)
Pin Name
Pin Number
I/O, Type
Pin Description
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
45, 44, 43, 42,
40, 39, 38, 37
O
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34, 33, 32,
31, 30, 29, 28
O
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB 48
I, FLOAT,
LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS
ENSMB Master or Slave mode
O, OPEN Drain SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, LVCMOS,
ENSMB Master or Slave mode
O, OPEN Drain The SMBus bi-directional SDA pin is enabled. Data input or open drain
(pull-down only) output.
AD0-AD3
54, 53, 47, 46
26
I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
READ_EN
I, LVCMOS
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19,
46, 47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 2.
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver when in Gen1/2 mode. The pins are only active when ENSMB is
de-asserted (low). The 8 channels are organized into two banks. Bank A
is controlled with the DEMA[1:0] pins and bank B is controlled with the
DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted
to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1
inputs.
See Table 3.
RATE
21
26
I, 4-LEVEL,
LVCMOS
RATE control pin selects GEN 1,2 and GEN 3 operating modes.
Tie 1kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
SD_TH
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold.
See Table 5.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50Ω or >50kΩ termination to the power rail is enabled.
See Table 4.
RESERVED
VDD_SEL
23
25
I, FLOAT
I, FLOAT
Float (leave pin open) = Normal Operation
Controls the internal regulator
FLOAT = 2.5V mode
Tie GND = 3.3V mode
PRSNT
52
I, LVCMOS
Cable Present Detect input. high when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When LOW (normal
operation) part is enabled.
See Table 4.
4
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SNLS334E –APRIL 2011–REVISED MARCH 2012
Pin Descriptions (continued)
Pin Name
Outputs
Pin Number
I/O, Type
Pin Description
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
Power
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating
VDD
9, 14, 36, 41, 51 Power
Power supply pins CML/analog
2.5V mode, connect to 2.5V supply
3.3V mode, connect 0.1uF cap to each VDD pin
GND
DAP
Power
Ground pad (DAP - die attach pad)
Notes:
LVCMOS inputs without the “FLOAT” conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VDD - 2.5V mode)
Supply Voltage (VIN - 3.3V mode)
LVCMOS Input/Output Voltage
CML Input Voltage
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
CML Input Current
Junction Temperature
Storage Temperature
-40°C to +125°C
+260°C
Lead Temperature Range Soldering
(4 sec.)
SQA54A Package
Derate SQA54A Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114F
3 kV
200 V
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
1000 V
Thermal Resistance
θJC
11.5°C/W
19.1°C/W
θJA, No Airflow, 4 layer JEDEC
For soldering specifications: see product folder at www.national.com/ms/MS/MS-SOLDERING.pdf
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
Recommended Operating Conditions
Min
Typ
2.5
3.3
Max
2.625
3.6
Units
V
Supply Voltage (2.5V mode)
Supply Voltgae (3.3V mode)
2.375
3.0
V
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Recommended Operating Conditions (continued)
Ambient Temperature
-40
25
+85
3.6
°C
V
SMBus (SDA, SCL)
Supply Noise up to 50 MHz
100
mVp-p
(1)
(1) Allowed supply noise (mVp-p sine wave) under typical conditions.
6
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SNLS334E –APRIL 2011–REVISED MARCH 2012
Electrical Characteristics
Symbol
Power
PD
Parameter
Conditions
Min
Typ
Max
Units
Power Dissipation
VDD = 2.5 V supply,
EQ Enabled,
500
700
mW
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
VIN = 3.3 V supply,
EQ Enabled,
660
900
mW
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0
LVCMOS / LVTTL DC Specifications
Vih
High Level Input
Voltage
2.0
0
3.6
0.8
V
V
V
Vil
Low Level Input
Voltage
Voh
High Level Output
Voltage
Ioh= −4mA
2.0
(ALL_DONE pin)
Vol
Low Level Output
Voltage
Iol= 4mA
0.4
V
(ALL_DONE pin)
Iih
Input High Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
-15
+15
uA
uA
Input High Current
with internal resistors
(4–level input pin)
+20
+150
Iil
Input Low Current
(PRSNT pin)
VIN = 3.6 V,
LVCMOS = 0 V
-15
+15
-40
uA
uA
Input Low Current
with internal resistors
(4–level input pin)
-160
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RX Differential return
loss
0.05 - 1.25 GHz
1.25 - 2.5 GHz
2.5 - 4.0 GHz
0.05 - 2.5 GHz
2.5 - 4.0 GHz
-16
-16
-14
-12
-8
dB
dB
dB
dB
dB
Ω
RLrx-cm
RX Common mode
return loss
Zrx-dc
RX DC common mode Tested at VDD = 2.5 V
impedance
40
80
50
60
120
1.2
Zrx-diff-dc
Vrx-diff-dc
RX DC differntial mode Tested at VDD = 2.5 V
impedance
100
1.0
50
Ω
V
Differential RX peak to Tested at pins
peak voltage (VID)
0.6
Zrx-high-imp-dc- DC Input common
pos
VID = 0 to 200mV,
ENSMB = 0, RXDET = 0,
VDD = 2.5 V
KΩ
mode impedance for
V>0
Vrx-signal-det-
diff-pp
Signal detect assert
level for active data
signal
SD_TH = float,
0101 pattern at 8 Gbps
180
110
mVp-p
mVp-p
Vrx-idle-det-diff- Signal detect de-assert SD_TH = float,
pp level for electrical idle 0101 pattern at 8 Gbps
High Speed Outputs
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Electrical Characteristics (continued)
Vtx-diff-pp
Output Voltage
Differential Swing
Differential measurement with
OUT_n+ and OUT_n-,
0.8
1.0
1.2
Vp-p
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0,
(1)
Vtx-de-ratio_3.5
TX de-emphasis ratio
TX de-emphasis ratio
TX Dj > 1.5 MHz
VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R,
GEN 1, 2 modes only
-3.5
-6
dB
dB
Vtx-de-ratio_6
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R,
GEN 1, 2 modes only
TTX-HF-DJ-DD
TTX-HF-DJ-DD
0.15
3.0
UI
TX RMS jitter < 1.5
MHz
ps RMS
TTX-RISE-FALL
TRF-MISMATCH
RLTX-DIFF
TX rise/fall time
20% to 80% of differential
output voltage
35
45
ps
UI
TX rise/fall mismatch
20% to 80% of differential
output voltage
0.01
0.1
TX Differential return
loss
0.05 - 1.25 GHz
1.25 - 2.5 GHz
2.5 - 4 GHz
-16
-12
-11
-12
-8
dB
dB
dB
dB
dB
Ω
RLTX-CM
TX Common mode
return loss
0.05 - 2.5 GHz
2.5 - 4 GHz
ZTX-DIFF-DC
VTX-CM-AC-PP
ITX-SHORT
DC differential TX
impedance
100
TX AC common mode VOD = 1.0 Vp-p,
voltage DEM0 = 1, DEM1 = 0
100
mVpp
mA
TX short circuit current Total current the transmitter
20
limit
can supply when shorted to
VDD or GND
VTX-CM-DC-
ACTIVE-IDLE-DELTA
Absolute delta of DC
common mode voltage
during L0 and electrical
idle
100
25
mV
VTX-CM-DC-LINE-
DELTA
Absolute delta of DC
common mode voltgae
between TX+ and TX-
mV
ns
TTX-IDLE-DATA
TTX-DATA-IDLE
TPLHD/PHLD
Max time to transition
to differential DATA
signal after IDLE
VID = 1.0 Vp-p, 8 Gbps
VID = 1.0 Vp-p, 8 Gbps
3.5
6.2
200
Max time to transition
to IDLE after differential
DATA signal
ns
(2)
High to Low
EQ = 00,
ps
and Low to High
Differential Propagation
Delay
TLSK
Lane to lane skew
T = 25C, VDD = 2.5V
25
40
ps
ps
TPPSK
Part to part propagation T = 25C, VDD = 2.5V
delay skew
Equalization
(1) In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output
VOD level set by DEMA/B[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS80PCI800 repeater in
GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake
negotiation link training.
(2) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
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Electrical Characteristics (continued)
DJE1
DJE2
DJE3
DJE4
DJE5
DJE6
Residual deterministic
jitter at 8 Gbps
35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.14
0.1
UI
UI
UI
UI
UI
UI
Residual deterministic
jitter at 5 Gbps
35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15,EQ = 1F'h,
DEM = 0 dB
Residual deterministic
jitter at 2.5 Gbps
35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.05
0.16
0.1
Residual deterministic
jitter at 8 Gbps
10 meters 30 awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
Residual deterministic
jitter at 5 Gbps
10 meters 30 awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 2F'h,
DEM = 0 dB
Residual deterministic
jitter at 2.5 Gbps
10 meters 30 awg cable,
VID = 0.8 Vp-p,
0.05
PRBS15, EQ = 2F'h,
DEM = 0 dB
De-emphasis (GEN 1,2 mode only)
DJD1
Residual deterministic
jitter at 2.5 Gbps and
5.0 Gbps
10” 4mils FR4,
0.1
0.1
UI
UI
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −3.5 dB
DJD2
Residual deterministic
jitter at 2.5 Gbps and
5.0 Gbps
20” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −9 dB
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Units
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
3.6
V
V
VIH
2.1
4
IPULLUP
Current Through Pull-Up Resistor
or Current Source
High Power Specification
mA
VDD
Nominal Bus Voltage
2.375
-200
3.6
V
(1)
ILEAK-Bus
ILEAK-Pin
CI
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
+200
µA
µA
pF
-15
(1) (2)
10
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
Pullup VDD = 3.3V,
2000
1000
Ω
Ω
(1) (2) (3)
Pullup VDD = 2.5V,
(1) (2) (3)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
400
520
kHz
kHz
ENSMB = FLOAT (Master Mode)
280
1.3
400
TBUF
Bus Free Time Between Stop and
Start Condition
µs
µs
µs
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
0.6
TSU:STA
Repeated Start Condition Setup
Time
0.6
TSU:STO
THD:DAT
TSU:DAT
TLOW
Stop Condition Setup Time
Data Hold Time
0.6
0
µs
ns
ns
µs
µs
ns
ns
Data Setup Time
100
1.3
0.6
Clock Low Period
(4)
(4)
THIGH
tF
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
50
300
300
(4)
tR
(4) (5)
tPOR
Time in which a device must be
operational after power-on reset
500
ms
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(5) Guaranteed by Design. Parameter not tested in production.
Timing Diagrams
(OUT+)
80%
80%
0V
20%
VOD (p-p) = (OUT+) œ (OUT-)
20%
(OUT-)
t
t
RISE
FALL
Figure 2. CML Output and Rise and FALL Transition Time
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+
IN
0V
-
t
t
PHLD
PLHD
+
OUT
0V
-
Figure 3. Propagation Delay Timing Diagram
+
0V
IN
DATA
-
t
t
IDLE-DATA
DATA-IDLE
DATA
+
0V
OUT
-
IDLE
IDLE
Figure 4. Transmit IDLE-DATA and DATA-IDLE Response Time
t
LOW
t
R
t
HIGH
SCL
SDA
t
t
t
t
SU:STA
HD:STA
F
HD:DAT
t
t
BUF
SU:STO
t
SU:DAT
ST
SP
SP
ST
Figure 5. SMBus Timing Parameters
Functional Descriptions
The DS80PCI800 is a low power 8 channel repeater optimized for PCI Express Gen 1/2 and 3. The DS80PCI800
compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The DS80PCI800 operates in
3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB
= float) to load register informations from external EEPROM; please refer to SMBUS Master Mode for additional
information.
Pin Control Mode:
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When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side
independently. When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below.
The RXDET pins provides automatic and manual control for input termination (50Ω or >50KΩ). RATE setting is
also pin controllable with pin selections (Gen 1/2, auto detect and Gen 3). The receiver electrical idle detect
threshold is also adjustable via the SD_TH pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx
and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (RATE,
RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit
is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is
driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the
device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are set by
registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
Table 1. 4–Level Control Pin Settings
Pin Setting
Description(1)
Voltage at Pin
0.03 x VDD
1/3 x VDD
0
Tie 1kΩ to GND
Tie 20kΩ to GND
Float (leave pin open)
Tie 1kΩ to VDD
R
Float
1
2/3 x VDD
0.98 x VDD
(1) The above required resistor value is for a single device. When there are multiple devices connected to the pull-up / pull-down resistor,
the value must scale with the number of devices. If 4 devices are connected to a single pull-up or pull-down, the 1kΩ resistor value
should be 250Ω. For the 20kΩ to GND, this should also scale to 5kΩ.
3.3V or 2.5V Supply Mode Operation
The DS80PCI800 has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V
mode operation, the VIN pin = 3.3V is used to supply power to the device. The internal regulator will provide the
2.5V to the VDD pins of the device and a 0.1 uF cap is needed at each of the 5 VDD pins for power supply de-
coupling (total capacitance should be ≤0.5 uF), and the VDD pins should be left open. The VDD_SEL pin must
be tied to GND to enable the internal regulator. In 2.5V mode operation, the VIN pin should be left open and 2.5V
supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left open (no connect)
to disable the internal regulator.
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3.3V mode
2.5V mode
VDD_SEL
VDD_SEL
open
open
Enable
Disable
3.3V
Internal
voltage
regulator
Internal
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
voltage
VIN
VDD
VDD
VDD
VDD
VDD
VIN
VDD
VDD
VDD
VDD
VDD
regulator
2.5V
2.5V
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Capacitors can be
either tantalum or an
ultra-low ESR seramic.
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Place 0.1 uF close to VDD Pin
Place capcitors close to VDD Pin
Total capacitance should be 7 0.5 uF
Figure 6. 3.3V or 2.5V Supply Connection Diagram
System Information
When using the DS80PCI800 in CPU systems, there are specific signal integrity settings to ensure signal
integrity margin. The settings were achieved with completing extensive testing. Please contact your field
representative for more information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
•
•
•
EQ: use the guidelines outlined in table 2.
De-Emphasis: use the guidelines outlined in table 3.
VOD: use the guidelines outlined in table 3.
For tuning in the upstream direction (from EP to CPU).
•
•
EQ: use the guidelines outlined in table 2.
De-Emphasis:
–
–
For trace lengths < 15” set to -3.5 dB
For trace lengths > 15” set to -6 dB
•
VOD: set to 900 mV
Table 2. Equalizer Settings
Level
1
EQA1
EQB1
EQA0
EQB0
EQ – 8 bits [7:0]
dB at
1.25 GHz
dB at
2.5 GHz
dB at
4 GHz
Suggested Use
0
0
0000 0000 = 0x00
2.1
3.7
4.9
FR4 < 5 inch trace
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Table 2. Equalizer Settings (continued)
2
3
0
0
R
0000 0001 = 0x01
0000 0010 = 0x02
0000 0011 = 0x03
0000 0111 = 0x07
0001 0101 = 0x15
0000 1011 = 0x0B
0000 1111 = 0x0F
0101 0101 = 0x55
0001 1111 = 0x1F
0010 1111 = 0x2F
0011 1111 = 0x3F
1010 1010 = 0xAA
0111 1111 = 0x7F
1011 1111 = 0xBF
1111 1111 = 0xFF
3.4
4.8
5.8
7.9
FR4 5 inch 5–mil trace
FR4 5 inch 4–mil trace
FR4 10 inch 5–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
Float
7.7
9.9
4
0
1
5.9
8.9
11.0
14.3
14.6
17.0
18.5
18.0
22.0
24.4
25.8
27.4
29.0
31.4
32.7
5
R
0
R
7.2
11.2
11.4
13.5
15.0
12.8
17.4
19.7
21.1
21.7
23.5
25.8
27.3
6
R
6.1
7
R
Float
1
8.8
8
R
10.2
7.5
FR4 25 to 30 inch 4–mil trace
FR4 30 inch 4–mil trace
FR4 35 inch 4–mil trace
10m, 30awg cable
9
Float
Float
Float
Float
1
0
10
11
12
13
14
15
16
R
11.4
13.0
14.2
13.8
15.6
17.2
18.4
Float
1
10m – 12m cable
0
1
R
1
Float
1
1
Table 3. Output Voltage and De-emphasis Settings
Level
DEMA1
DEMB1
DEMA0
DEMB0
VOD Vp-p
DEM dB
(see note below)
Inner Amplitude
Vp-p
Suggested Use
1
2
0
0
0.8
0.9
0.9
1.0
1.0
1.0
1.1
1.1
1.1
1.2
1.2
1.2
1.3
1.3
1.3
1.3
0
0
0.8
0.9
0.6
1.0
0.7
0.5
1.1
0.7
0.6
1.2
0.8
0.6
1.3
0.9
0.7
0.5
FR4 <5 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 <5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
0
0
R
3
Float
- 3.5
0
4
0
1
5
R
0
R
- 3.5
- 6
0
6
R
7
R
Float
1
8
R
- 3.5
- 6
0
9
Float
Float
Float
Float
1
0
10
11
12
13
14
15
16
R
Float
1
- 3.5
- 6
0
0
1
R
- 3.5
- 6
- 9
1
Float
1
1
Note: The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are also available in GEN 3 mode when RATE = 1 (tied to VDD).
Table 4. RX-Detect Settings
PRSNT#
RXDET
0
SMBus REG
bit[3:2]
Input Termination
Termination sensed Comments
on output pins
0
0
00
High Impedance
X
Manual RX-Detect, input is high impedance
mode
Tie 20kΩ
01
High Impedance
High Z until receiver Auto RX-Detect, outputs test every 12 msec
to GND
50 Ω
is detected
for 600 msec then stops; termination is high-z
until detection; once detected input termination
is 50 Ω
Reset function by pulsing PRSNT# high for 5
usec then low again
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Table 4. RX-Detect Settings (continued)
0
Float
(Default)
10
11
High Impedance
High Z until recevier Auto RX-Detect, outputs test every 12 msec
50 Ω
is detected
until detection occurs; termination is high-z
until detection; once detected input termination
is 50 Ω
0
1
1
50 Ω
X
X
Manual RX-Detect, input is 50 Ω
X
High Impedance
Power down mode, input is high impedance,
output drivers are disabled
Used to reset RX-Detect State Machine when
held high for 5 usec
Table 5. Signal Detect Threshold Level(1)
SD_TH
SMBus REG bit [3:2] and [1:0]
Assert Level (typ)
210 mVp-p
De-assert Level (typ)
150 mVp-p
0
10
01
00
11
R
160 mVp-p
100 mVp-p
F (default)
1
180 mVp-p
110 mVp-p
190 mVp-p
130 mVp-p
(1) VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
SMBUS Master Mode
The DS80PCI800 devices support reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS80PCI800 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines.
•
•
Set ENSMB = Float — enable the SMBUS master mode.
The external EEPROM device address byte must be 0xA0'h and capable of 400 kHz operation at 2.5V and
3.3V supply.
•
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS80PCI800 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
•
Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for 4 device.
–
–
–
–
U1: AD[3:0] = 0000 = 0xB0'h,
U2: AD[3:0] = 0001 = 0xB2'h,
U3: AD[3:0] = 0010 = 0xB4'h,
U4: AD[3:0] = 0011 = 0xB6'h
•
•
Use a pull-up resistor on SDA and SCL; value = 2k ohms
Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
–
–
–
–
–
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE# of U1 to READEN# of U2
3. Tie ALL_DONE# of U2 to READEN# of U3
4. Tie ALL_DONE# of U3 to READEN# of U4
5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS80PCI800 device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed
pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the
MAP bit is not present the configuration data start address is derived from the DS80PCI800 address and the
configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS80PCI800 device.
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:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
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Table 6. EEPROM Register Map - Single Device with Default Value
EEPROM Address
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
Description
0
CRC EN
Address Map
Present
EEPROM > 256
Bytes
RES
DEVICE
COUNT[3]
DEVICE
COUNT[2]
DEVICE
COUNT[1]
DEVICE
COUNT[0]
Value
0
0
0
0
0
0
0
0
Description
Value
1
2
RES
0
RES
0
RES
0
RES
0
RES
0
RES
0
RES
0
RES
0
Description
Max EEPROM
Burst size[7]
Max EEPROM
Burst size[6]
Max EEPROM
Burst size[5]
Max EEPROM
Burst size[4]
Max EEPROM
Burst size[3]
Max EEPROM
Burst size[2]
Max EEPROM
Burst size[1]
Max EEPROM
Burst size[0]
Value
0
0
0
0
0
0
0
0
Description
Value
3
4
5
6
7
8
9
PWDN_ch7
PWDN_ch6
PWDN_ch5
PWDN_ch4
PWDN_ch3
PWDN_ch2
PWDN_ch1
PWDN_ch0
0
0
0
0
0
0
0
0
Description
Value
lpbk_1
lpbk_0
PWDN_INPUTS
PWDN_OSC
Ovrd_PRSNT
RES
RES
RES
0
0
0
0
0
0
0
0
Description
Value
RES
RES
RES
RES
RES
rxdet_btb_en
Ovrd_idle_th
Ovrd_RES
0
0
0
0
0
1
0
0
Description
Value
Ovrd_IDLE
Ovrd_RX_DET
Ovrd_RATE
RES
RES
rx_delay_sel_2
rx_delay_sel_1
rx_delay_sel_0
0
0
0
0
0
1
1
1
Description
Value
RD_delay_sel_3
RD_delay_sel_2
RD_delay_sel_1
RD_delay_sel_0
ch0_Idle_auto
ch0_Idle_sel
ch0_RXDET_1
ch0_RXDET_0
0
0
0
0
0
0
0
0
Description
Value
ch0_BST_7
ch0_BST_6
ch0_BST_5
ch0_BST_4
ch0_BST_3
ch0_BST_2
ch0_BST_1
ch0_BST_0
0
0
1
0
1
1
1
1
Description
Value
ch0_Sel_scp
1
ch0_Sel_mode
ch0_RES_2
ch0_RES_1
ch0_RES_0
ch0_VOD_2
ch0_VOD_1
ch0_VOD_0
0
1
0
1
1
0
1
Description
Value
10 ch0_DEM_2
ch0_DEM_1
ch0_DEM_0
ch0_Slow
ch0_idle_tha_1
ch0_idle_tha_0
ch0_idle_thd_1
ch0_idle_thd_0
0
1
0
0
0
0
0
0
Description
Value
11 ch1_Idle_auto
ch1_Idle_sel
ch1_RXDET_1
ch1_RXDET_0
ch1_BST_7
ch1_BST_6
ch1_BST_5
ch1_BST_4
0
0
0
0
0
0
1
0
Description
Value
12 ch1_BST_3
ch1_BST_2
ch1_BST_1
ch1_BST_0
ch1_Sel_scp
ch1_Sel_mode
ch1_RES_2
ch1_RES_1
1
1
1
1
1
0
1
0
Description
Value
13 ch1_RES_0
ch1_VOD_2
ch1_VOD_1
ch1_VOD_0
ch1_DEM_2
ch1_DEM_1
ch1_DEM_0
ch1_Slow
1
1
0
1
0
1
0
0
Description
Value
14 ch1_idle_tha_1
ch1_idle_tha_0
ch1_idle_thd_1
ch1_idle_thd_0
ch2_Idle_auto
ch2_Idle_sel
ch2_RXDET_1
ch2_RXDET_0
0
0
0
0
0
0
0
0
Description
Value
15 ch2_BST_7
0
ch2_BST_6
0
ch2_BST_5
1
ch2_BST_4
0
ch2_BST_3
1
ch2_BST_2
1
ch2_BST_1
1
ch2_BST_0
1
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Table 6. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
Description
Value
16 ch2_Sel_scp
ch2_Sel_mode
ch2_RES_2
ch2_RES_1
ch2_RES_0
ch2_VOD_2
ch2_VOD_1
ch2_VOD_0
1
0
1
0
1
1
0
1
Description
Value
17 ch2_DEM_2
ch2_DEM_1
ch2_DEM_0
ch2_Slow
ch2_idle_tha_1
ch2_idle_tha_0
ch2_idle_thd_1
ch2_idle_thd_0
0
1
0
0
0
0
0
0
Description
Value
18 ch3_Idle_auto
ch3_Idle_sel
ch3_RXDET_1
ch3_RXDET_0
ch3_BST_7
ch3_BST_6
ch3_BST_5
ch3_BST_4
0
0
0
0
0
0
1
0
Description
Value
19 ch3_BST_3
ch3_BST_2
ch3_BST_1
ch3_BST_0
ch3_Sel_scp
ch3_Sel_mode
ch3_RES_2
ch3_RES_1
1
1
1
1
1
0
1
0
Description
Value
20 ch3_RES_0
ch3_VOD_2
ch3_VOD_1
ch3_VOD_0
ch3_DEM_2
ch3_DEM_1
1
ch3_DEM_0
0
ch3_Slow
0
1
1
0
1
0
Description
Value
21 ch3_idle_tha_1
ch3_idle_tha_0
ch3_idle_thd_1
ch3_idle_thd_0
ovrd_fast_idle
en_high_idle_th_n en_high_idle_th_s en_fast_idle_n
0
0
0
0
0
0
0
1
Description
Value
22 en_fast_idle_s
eqsd_mgain_n
eqsd_mgain_s
ch4_Idle_auto
ch4_Idle_sel
ch4_RXDET_1
ch4_RXDET_0
ch4_BST_7
1
0
0
0
0
0
0
0
Description
Value
23 ch4_BST_6
ch4_BST_5
ch4_BST_4
ch4_BST_3
ch4_BST_2
ch4_BST_1
ch4_BST_0
ch4_Sel_scp
0
1
0
1
1
1
1
1
Description
Value
24 ch4_Sel_mode
ch4_RES_2
ch4_RES_1
ch4_RES_0
ch4_VOD_2
ch4_VOD_1
ch4_VOD_0
ch4_DEM_2
0
1
0
1
1
0
1
0
Description
Value
25 ch4_DEM_1
ch4_DEM_0
ch4_Slow
ch4_idle_tha_1
ch4_idle_tha_0
ch4_idle_thd_1
ch4_idle_thd_0
ch5_Idle_auto
1
0
0
0
0
0
0
0
Description
Value
26 ch5_Idle_sel
ch5_RXDET_1
ch5_RXDET_0
ch5_BST_7
ch5_BST_6
ch5_BST_5
ch5_BST_4
ch5_BST_3
0
0
0
0
0
1
0
1
Description
Value
27 ch5_BST_2
ch5_BST_1
ch5_BST_0
ch5_Sel_scp
ch5_Sel_mode
ch5_RES_2
ch5_RES_1
ch5_RES_0
1
1
1
1
0
1
0
1
Description
Value
28 ch5_VOD_2
ch5_VOD_1
ch5_VOD_0
ch5_DEM_2
ch5_DEM_1
ch5_DEM_0
ch5_Slow
ch5_idle_tha_1
1
0
1
0
1
0
0
0
Description
Value
29 ch5_idle_tha_0
ch5_idle_thd_1
ch5_idle_thd_0
ch6_Idle_auto
ch6_Idle_sel
ch6_RXDET_1
ch6_RXDET_0
ch6_BST_7
0
0
0
0
0
0
0
0
Description
Value
30 ch6_BST_6
ch6_BST_5
ch6_BST_4
ch6_BST_3
ch6_BST_2
ch6_BST_1
ch6_BST_0
ch6_Sel_scp
0
1
0
1
1
1
1
1
Description
Value
31 ch6_Sel_mode
0
ch6_RES_2
1
ch6_RES_1
0
ch6_RES_0
1
ch6_VOD_2
1
ch6_VOD_1
0
ch6_VOD_0
1
ch6_DEM_2
0
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Table 6. EEPROM Register Map - Single Device with Default Value (continued)
EEPROM Address
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
Description
Value
32 ch6_DEM_1
ch6_DEM_0
ch6_Slow
ch6_idle_tha_1
ch6_idle_tha_0
ch6_idle_thd_1
ch6_idle_thd_0
ch7_Idle_auto
1
0
0
0
0
0
0
0
Description
Value
33 ch7_Idle_sel
ch7_RXDET_1
ch7_RXDET_0
ch7_BST_7
ch7_BST_6
ch7_BST_5
ch7_BST_4
ch7_BST_3
0
0
0
0
0
1
0
1
Description
Value
34 ch7_BST_2
ch7_BST_1
ch7_BST_0
ch7_Sel_scp
ch7_Sel_mode
ch7_RES_2
ch7_RES_1
ch7_RES_0
1
1
1
1
0
1
0
1
Description
Value
35 ch7_VOD_2
ch7_VOD_1
ch7_VOD_0
ch7_DEM_2
ch7_DEM_1
ch7_DEM_0
ch7_Slow
ch7_idle_tha_1
1
0
1
0
1
0
0
0
Description
Value
36 ch7_idle_tha_0
ch7_idle_thd_1
ch7_idle_thd_0
iph_dac_ns_1
iph_dac_ns_0
ipp_dac_ns_1
0
ipp_dac_ns_0
0
ipp_dac_1
0
0
0
0
0
0
Description
Value
37 ipp_dac_0
RD23_67
RD01_45
RD_PD_ovrd
RD_Sel_test
RD_RESET_ovrd PWDB_input_DC
DEM_VOD_ovrd
0
0
0
0
0
0
0
0
Description
Value
38 DEM_ovrd_N2
DEM_ovrd_N1
DEM_ovrd_N0
VOD_ovrd_N2
VOD_ovrd_N1
VOD_ovrd_N0
SPARE0
SPARE1
0
1
0
1
0
1
0
0
Description
Value
39 DEM__ovrd_S2
0
DEM__ovrd_S1
1
DEM_ovrd_S0
0
VOD_ovrd_S2
1
VOD_ovrd_S1
0
VOD_ovrd_S0
1
SPARE0
0
SPARE1
0
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Table 7. Example of EEPROM for 4 Devices using 2 Address Maps
EEPROM Address
Address (Hex)
EEPROM Data
Comments
0
00
0x43
CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device
Count[3:0] = 3
1
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
0x00
0x08
0x00
0x0B
0x00
0x0B
0x00
0x30
0x00
0x30
0x00
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
2
EEPROM Burst Size
CRC not used
3
4
Device 0 Address Location
CRC not used
5
6
Device 1 Address Location
CRC not used
7
8
Device 2 Address Location
CRC not used
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Device 3 Address Location
Begin Device 0, 1 - Address Offset 3
EQ CHB0 = 00
VOD CHB0 = 1.0V
DEM CHB0 = 0 (0dB)
EQ CHB1 = 00
VOD CHB1 = 1.0V
DEM CHB1 = 0 (0dB)
EQ CHB2 = 00
VOD CHB2 = 1.0V
DEM CHB2 = 0 (0dB)
EQ CHB3 = 00
VOD CHB3 = 1.0V
DEM CHB3 = 0 (0dB)
EQ CHA0 = 00
VOD CHA0 = 1.0V
DEM CHA0 = 0 (0dB)
EQ CHA1 = 00
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
EQ CHA2 = 00
VOD CHA2 = 1.0V
DEM CHA2 = 0 (0dB)
EQ CHA3 = 00
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
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Table 7. Example of EEPROM for 4 Devices using 2 Address Maps (continued)
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
0x54
0x00
0x00
0x04
0x07
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x00
0x00
0xAB
0x00
0x00
0x0A
0xB0
0x01
0x80
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x01
0x56
0x00
0x00
0x15
0x60
0x00
0x00
0x54
0x54
End Device 0, 1 - Address Offset 39
Begin Device 2, 3 - Address Offset 3
EQ CHB0 = 00
VOD CHB0 = 1.0V
DEM CHB0 = 0 (0dB)
EQ CHB1 = 00
VOD CHB1 = 1.0V
DEM CHB1 = 0 (0dB)
EQ CHB2 = 00
VOD CHB2 = 1.0V
DEM CHB2 = 0 (0dB)
EQ CHB3 = 00
VOD CHB3 = 1.0V
DEM CHB3 = 0 (0dB)
EQ CHA0 = 00
VOD CHA0 = 1.0V
DEM CHA0 = 0 (0dB)
EQ CHA1 = 00
VOD CHA1 = 1.0V
DEM CHA1 = 0 (0dB)
EQ CHA2 = 00
VOD CHA2 = 1.0V
DEM CHA2 = 0 (0dB)
EQ CHA3 = 00
VOD CHA3 = 1.0V
DEM CHA3 = 0 (0dB)
End Device 2, 3 - Address Offset 39
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8–channels
set to EQ = 00 (min boost), VOD = 1.0V, DEM = 0 (0dB) and multiple device can point to the same address map.
System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS80PCI800 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is B0'h. Based on the SMBus 2.0 specification, the DS80PCI800 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the
AD[3:0] inputs. Below are the 16 addresses.
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Table 8. Device Slave Address Bytes
AD[3:0] Settings
0000
Address Bytes (HEX)
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
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1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see SMBus Register Map Table for more information.
Table 9. SMBUS Slave Mode Register Map
Address
Register Name
Bit (s) Field
Type Default
Description
0x00
Observation,
Reset
7
Reserved
R/W
R
0x00
Set bit to 0.
6:3
Address Bit
AD[3:0]
Observation of AD[3:0] bit
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2
EEPROM Read
Done
R
1: Device completed the read from external
EEPROM.
1
Block Reset
R/W
R/W
R/W
1: Block bit 0 from resettting the registers; self
clearing.
0
Reset
SMBus Reset
1: Reset registers to default value; self clearing.
0x01
PWDN Channels
7:0
PWDN CHx
0x00
Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Note: override PRSNT pin.
0x02
Override
PRSNT Control
7:1
0
Reserved
R/W
0x00
Set bits to 0.
Override PRSNT
1: Block PRSNT pin control
0: Allow PRSNT pin control
0x05
0x06
Slave Mode CRC Bits 7:0
CRC bits
Reserved
Reserved
Slave CRC
R/W
R/W
0x00
0x10
CRC bits [7:0]
Set bits to 0.
Set bit to 1.
Slave CRC Control
7:5
4
3
1: Disables the slave CRC mode
0: Enables the slave CRC mode
Note: In order to change VOD, DEM and EQ of the
channels in slave mode, set bit to 1 to disable the
CRC.
2:0
Reserved
Set bits to 0.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
R/W 0x00
Description
0x08
Override
Pin Control
7
6
Reserved
Set bit to 0.
Override SD_TH
1: Block SD_TH pin control
0: Allow SD_TH pin control
5
4
Reserved
Set bit to 0.
Override IDLE
1: IDLE control by registers
0: IDLE control by signal detect
3
2
Override RXDET
Override RATE
1: Block RXDET pin control
0: Allow RXDET pin control
1: Block RATE pin control
0: Allow RATE pin control
1
Reserved
Reserved
Reserved
IDLE_AUTO
Set bit to 0.
Set bit to 0.
Set bits to 0.
0
0x0E
CH0 - CHB0
7:6
5
R/W
0x00
IDLE, RXDET
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x0F
0x10
CH0 - CHB0
EQ
EQ Control
R/W
R/W
0x2F
IB0 EQ Control - total of 256 levels.
See Table 2.
CH0 - CHB0
VOD
7
6
Short Circuit
Protection
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x11
CH0 - CHB0
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH0 - CHB0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12
CH0 - CHB0
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x15
CH1 - CHB1
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x16
CH1 - CHB1
EQ
EQ Control
R/W
0x2F
IB1 EQ Control - total of 256 levels.
See Table 2.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x17
CH1 - CHB1
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x18
CH1 - CHB1
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH1 - CHB1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19
CH1 - CHB1
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x1C
CH2 - CHB2
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
IDLE_SEL
RXDET
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x1D
0x1E
CH2 - CHB2
EQ
EQ Control
R/W
R/W
0x2F
IB2 EQ Control - total of 256 levels.
See Table 2.
CH2 - CHB2
VOD
7
6
Short Circuit
Protection
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x1F
CH2 - CHB2
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH2 - CHB2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
R/W 0x00
Description
0x20
CH2 - CHB2
IDLE Threshold
7:4
3:2
Reserved
Set bits to 0.
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x23
CH3 - CHB3
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x24
0x25
CH3 - CHB3
EQ
EQ Control
R/W
R/W
0x2F
IB3 EQ Control - total of 256 levels.
See Table 2.
CH3 - CHB3
VOD
7
6
Short Circuit
Protection
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x26
CH3 - CHB3
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH3 - CHB3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x27
CH3 - CHB3
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x2B
CH4 - CHA0
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x2C
CH4 - CHA0
EQ
EQ Control
R/W
0x2F
IA0 EQ Control - total of 256 levels.
See Table 2.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x2D
CH4 - CHA0
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x2E
CH4 - CHA0
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH4 - CHA0.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x2F
CH4 - CHA0
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x32
CH5 - CHA1
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
IDLE_SEL
RXDET
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x33
0x34
CH5 - CHA1
EQ
EQ Control
R/W
R/W
0x2F
IA1 EQ Control - total of 256 levels.
See Table 2.
CH5 - CHA1
VOD
7
6
Short Circuit
Protection
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x35
CH5 - CHA1
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH5 - CHA1.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
R/W 0x00
Description
0x36
CH5 - CHA1
IDLE Threshold
7:4
3:2
Reserved
Set bits to 0.
IDLE thd
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x39
CH6 - CHA2
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x3A
0x3B
CH6 - CHA2
EQ
EQ Control
R/W
R/W
0x2F
IA2 EQ Control - total of 256 levels.
See Table 2.
CH6 - CHA2
VOD
7
6
Short Circuit
Protection
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x3C
CH6 - CHA2
DEM
7
RXDET STATUS
R
0x02
Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
R
Observation bit for RATE_DET CH6 - CHA2.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3D
CH6 - CHA2
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x40
CH7 - CHA3
IDLE, RXDET
7:6
5
Reserved
R/W
0x00
Set bits to 0.
IDLE_AUTO
1: Automatic IDLE detect
0: Allow IDLE_SEL control in bit 4
Note: override IDLE control.
4
IDLE_SEL
RXDET
1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2
00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is high-z until detection; once
detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs;
termination is high-z until detection; once detected
input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0
7:0
Reserved
Set bits to 0.
0x41
CH7 - CHA3
EQ
EQ Control
R/W
0x2F
IA3 EQ Control - total of 256 levels.
See Table 2.
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Table 9. SMBUS Slave Mode Register Map (continued)
Address
Register Name
Bit (s) Field
Type Default
Description
0x42
CH7 - CHA3
VOD
7
Short Circuit
Protection
R/W
0xAD
1: Enable the short circuit protection
0: Disable the short circuit protection
6
RATE_SEL
1: Gen 1/2,
0: Gen 3
Note: override the RATE pin.
5:3
2:0
Reserved
Set bits to default value - 101.
VOD Control
OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x43
CH7 - CHA3
DEM
7
RXDET STATUS
R
R
0x02
Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
6:5
RATE_DET
STATUS
Observation bit for RATE_DET CH7 - CHA3.
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3
2:0
Reserved
R/W
R/W
Set bits to 0.
DEM Control
OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x44
CH7 - CHA3
IDLE Threshold
7:4
3:2
Reserved
IDLE thd
R/W
0x00
Set bits to 0.
De-assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
1:0
IDLE tha
Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
0x51
Device ID
7:5
4:0
VERSION
ID
R
0x45
010'b
00101'b
Applications Information
GENERAL RECOMMENDATIONS
The DS80PCI800 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high
speed design tips to address signal integrity design issues.
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PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-
1187 for additional information on LLP packages.
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
1
2
12
10
8
6
5
4
3
18
16
14 13
15
11
9
7
17
54
53
52
19
20
21
22
23
24
25
26
27
51
50
49
BOTTOM OF PKG
GND
48
47
46
VDD
44
29
32
36 37
39 40 41 42
38
43
45
28
30 31
33 34
35
VDD
VDD
Figure 7. Typical Routing Options
The graphic shown above depicts different transmission line topologies which can be used in various
combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be
minimized or eliminated by increasing the swell around each hole and providing for a low inductance return
current path. When the via structure is associated with thick backplane PCB, further optimization such as back
drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.
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POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS80PCI800 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS80PCI800. Smaller
body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in
the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These
capacitors can be either tantalum or an ultra-low ESR ceramic.
Typical Performance Curves Characteristics
640.0
VDD = 2.625V
620.0
VDD = 2.5V
600.0
VDD = 2.375V
580.0
560.0
540.0
520.0
500.0
480.0
T = 25oC
460.0
440.0
420.0
0.8
0.9
1
1.1
1.2
1.3
VOD (Vp-p)
Figure 8. Power Dissipation (PD) vs. Output Differential Voltage (VOD)
1021
T = 25°C
1019
1016
1013
1010
1007
2.375
2.5
2.625
VDD (V)
Figure 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Supply Voltage (VDD)
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1020
1018
1016
1014
1012
V
DD
= 2.5 V
-40
-15
10
35
60
85
TEMPERATURE (°C)
Figure 10. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature
Typical Performance Eye Diagrams Characteristics
Pattern
Generator
Scope
BW = 50 GHz
TL
Lossy Channel
IN
OUT
DS80PCI800
V
= 1.0 Vp-p,
ID
DE = 0 dB
8 Gb/s, PRBS23
Figure 11. Test Setup Connections Diagram
Figure 12. TL = 20 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
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Figure 13. TL = 35 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = float, R = 1F'h, DEM[1:0] = float, float
Pattern
Generator
Scope
BW = 50 GHz
TL1
TL2
IN
OUT
DS80PCI800
V
ID
= 1.0 Vp-p,
Lossy Channel
Lossy Channel
DE = -9 dB
8 Gb/s, PRBS23
Figure 14. Test Setup Connections Diagram
Figure 15. TL1 = 20 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, R = 15'h, DEM[1:0] = float, float
Figure 16. TL1 = 30 inch 4–mil FR4 trace, TL2 = 15 inch 4–mil FR4 trace,
DS80PCI800 settings: EQ[1:0] = R, 1 = 0F'h, DEM[1:0] = float, float
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
DS80PCI800SQ/NOPB
DS80PCI800SQE/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
WQFN
NJY
54
54
2000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-2-260C-1 YEAR
DS80PCI800SQ
ACTIVE
NJY
250
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 85
DS80PCI800SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS80PCI800SQ/NOPB
WQFN
NJY
NJY
54
54
2000
250
330.0
178.0
16.4
16.4
5.8
5.8
10.3
10.3
1.0
1.0
12.0
12.0
16.0
16.0
Q1
Q1
DS80PCI800SQE/NOPB WQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS80PCI800SQ/NOPB
DS80PCI800SQE/NOPB
WQFN
WQFN
NJY
NJY
54
54
2000
250
367.0
213.0
367.0
191.0
38.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
3.51±0.1
(0.1)
SEE TERMINAL
DETAIL
19
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
46
0.3
54X
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
54X
0.1
C A
C
B
0.05
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54X (0.25)
SEE DETAILS
54
46
1
45
50X (0.5)
(7.5)
(9.8)
SYMM
(1.17)
TYP
2X
(1.16)
28
18
(
0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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