DS90C032_16 [TI]
Quad CMOS Differential Line Receiver;
| 型号： | DS90C032_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad CMOS Differential Line Receiver |
| 文件： | 总18页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C032
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SNLS094D –JUNE 1998–REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
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1
FEATURES
DESCRIPTION
TheDS90C032 is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
2
•
•
>155.5 Mbps (77.7 MHz) switching rates
Accepts small swing (350 mV) differential
signal levels
•
•
•
•
•
•
Ultra low power dissipation
600 ps maximum differential skew (5V, 25°C)
6.0 ns maximum propagation delay
Industrial operating temperature range
Military operating temperature range option
TheDS90C032 accepts low voltage (350 mV)
differential input signals and translates them to
CMOS (TTL compatible) output levels. The receiver
supports a TRI-STATE function that may be used to
multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe with
the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
Available in surface mount packaging (SOIC)
and (LCCC)
•
Pin compatible with DS26C32A, MB570
(PECL), and 41LF (PECL)
TheDS90C032
and
companion
line
driver
•
•
Supports OPEN input fail-safe
(DS90C031) provide a new alternative to high power
pseudo-ECL devices for high speed point-to-point
interface applications.
Supports short and terminated input fail-safe
with the addition of external failsafe biasing
•
Compatible with IEEE 1596.3 SCI LVDS
standard
•
•
Conforms to ANSI/TIA/EIA-644 LVDS standard
Available to Standard Microcircuit Drawing
(SMD) 5962-95834
Connection Diagram
Dual-In-Line
Figure 1. See Package Number D (R-PDSO-G16)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS90C032
SNLS094D –JUNE 1998–REVISED APRIL 2013
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Functional Diagram and Truth Table
Receiver
ENABLES
INPUTS
OUTPUT
EN
EN*
RIN+ − RIN−
ROUT
L
H
X
Z
H
L
V
ID ≥ 0.1V
V
ID ≤ −0.1V
All other combinations of
ENABLE inputs
Full Fail-safe
OPEN/SHORT or
Terminated
H
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VCC
Input Voltage (RIN+, RIN−
Enable Input Voltage (EN, EN*)
Output Voltage (ROUT
)
−0.3V to +6V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
)
)
Maximum Package Power Dissipation at +25°C
D Package
1025 mW
1830 mW
NAJ Package
Derate D Package
8.2 mW/°C above +25°C
12.2 mW/°C above +25°C
−65°C to +150°C
+260°C
Derate NAJ Package
Storage Temperature Range
Lead Temperature Range Soldering (4 seconds)
Maximum Junction Temperature (DS90C032T)
Maximum Junction Temperature (DS90C032E)
ESD Ratings
+150°C
+175°C
(HBM, 1.5 kΩ, 100 pF)
≥ 3500V
≥ 250V
(EIAJ, 0 Ω, 200 pF)
(1) "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
Recommended Operating Conditions(1)(2)
Min
+4.5
GND
−40
Typ
Max
+5.5
2.4
Units
V
Supply Voltage (VCC
)
+5.0
Receiver Input Voltage
V
Operating Free Air Temperature (TA)
DS90C032T
DS90C032E
+25
+25
+85
°C
°C
−55
+125
(1) "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
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Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol
VTH
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
Pin
Min
Typ
Max
Units
mV
mV
µA
µA
V
VCM = +1.2V
RIN+
RIN−
,
+100
VTL
−100
−10
−10
3.8
IIN
VIN = +2.4V
VIN = 0V
VCC = 5.5V
±1
±1
+10
+10
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
ROUT
4.9
4.9
IOH = −0.4 mA, Input
DS90C032T
3.8
V
terminated
VOL
IOS
IOZ
VIH
VIL
II
Output Low Voltage
Output Short Circuit Current
Output TRI-STATE Current
Input High Voltage
IOL = 2 mA, VID = −200 mV
0.07
−60
±1
0.3
−100
+10
V
(1)
Enabled, VOUT = 0V
−15
−10
2.0
mA
µA
V
Disabled, VOUT = 0V or VCC
EN,
EN*
Input Low Voltage
0.8
V
Input Current
−10
±1
−0.8
3.5
3.5
3.7
3.5
3.5
+10
µA
V
VCL
ICC
Input Clamp Voltage
ICL = −18 mA
−1.5
No Load Supply Current, Receivers EN, EN* = VCC or GND, Inputs DS90C032T
Enabled Open
VCC
10
11
11
10
11
mA
mA
mA
mA
mA
DS90C032E
EN, EN* = 2.4 or 0.5, Inputs Open
No Load Supply Current, Receivers EN = GND, EN* = VCC, Inputs DS90C032T
Disabled Open
ICCZ
DS90C032E
(1) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
Switching Characteristics
VCC = +5.0V, TA = +25°C, DS90C032T(1)(2)(3)(4)
Symbol
tPHLD
tPLHD
tSKD
Parameter
Conditions
Min
1.5
1.5
0
Typ
3.40
3.48
80
Max
5.0
5.0
600
1.0
2.0
2.0
15
Units
ns
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
CL = 5 pF,
VID = 200 mV,
See Figure 2 and Figure 3
ns
Differential Skew |tPHLD − tPLHD
|
ps
(3)
tSK1
Channel-to-Channel Skew
0
0.6
0.5
0.5
10
ns
tTLH
Rise Time
ns
tTHL
Fall Time
ns
tPHZ
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ,
ns
CL = 10 pF,
See Figure 4 and Figure 5
tPLZ
10
15
ns
tPZH
4
10
ns
tPZL
4
10
ns
(1) All typical values are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4) CL includes probe and jig capacitance.
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Switching Characteristics
VCC = +5.0V ± 10%, TA = −40°C to +85°C, DS90C032T(1)(2)(3)(4)(5)
Symbol
tPHLD
tPLHD
tSKD
tSK1
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Conditions
CL = 5 pF,
VID = 200 mV,
Min
1.0
1.0
0
Typ
3.40
3.48
0.08
0.6
Max
6.0
6.0
1.2
1.5
5.0
2.5
2.5
20
Units
ns
ns
See Figure 2 and Figure 3
Differential Skew |tPHLD − tPLHD
|
ns
(3)
Channel-to-Channel Skew
0
ns
(4)
tSK2
Chip to Chip Skew
ns
tTLH
Rise Time
0.5
0.5
10
10
4
ns
tTHL
Fall Time
ns
tPHZ
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ,
CL = 10 pF,
See Figure 4 and Figure 5
ns
tPLZ
20
ns
tPZH
15
ns
tPZL
4
15
ns
(1) All typical values are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5) CL includes probe and jig capacitance.
Switching Characteristics
VCC = +5.0V ± 10%, TA = −55°C to +125°C, DS90C032E(1)(2)(3)(4)(5)(6)
Symbol
tPHLD
tPLHD
tSKD
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Conditions
CL = 20 pF,
VID = 200 mV,
Min
1.0
1.0
0
Typ
3.40
3.48
0.08
0.6
Max
8.0
8.0
3.0
3.0
7.0
20
Units
ns
ns
See Figure 2 and Figure 3
Differential Skew |tPHLD − tPLHD
|
ns
(3)
tSK1
Channel-to-Channel Skew
0
ns
(4)
tSK2
Chip to Chip Skew
ns
tPHZ
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ,
CL = 10 pF,
See Figure 4 and Figure 5
10
10
4
ns
tPLZ
20
ns
tPZH
20
ns
tPZL
4
20
ns
(1) All typical values are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5) CL includes probe and jig capacitance.
(6) For DS90C032E propagation delay measurements are from 0V on the input waveform to the 50% point on the output (ROUT).
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Parameter Measurement Information
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
CL includes load and test jig capacitance.
S1 = VCC for tPZL and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 4. Receiver TRI-STATE Delay Test Circuit
Figure 5. Receiver TRI-STATE Delay Waveforms
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TYPICAL APPLICATION
Figure 6. Point-to-Point Application
APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of mid-stream connectors, cable stubs, and other impedance discontinuities as well as ground
shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-
mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins
should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
Receiver Fail-Safe
The LVDS receiver is a high-gain high-speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source or sink a small amount of current, providing fail-
safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs.
1. Open Input Pins. TheDS90C032 is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high-value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH stable output state for open inputs.
2. Terminated Input. TheDS90C032 requires external failsafe biasing for terminated input failsafe.
Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the
driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in power-
off condition. The use of external biasing resistors provide a small bias to set the differential input voltage
while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed
from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna
that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and
recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the
receiver may respond. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common
to both lines and rejected by the receivers.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (1.2V ±1V). It is only supported with inputs shorted
and no external common-mode voltage applied.
4. Operation in environment with greater than 10mV differential noise.
TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal
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quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the
amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific
application. In applications in low noise environments, they may choose to use a very small bias if any. For
applications with less balanced interconnects and/or in high noise environments they may choose to boost
failsafe further. TIs LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe
biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This
is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and
un-driven states, the common-mode modulation on the bus is held to a minimum.
For additional Failsafe Biasing information, please refer to Application Note AN-1194 (SNLA051) for more
detail.
The footprint of the DS90C032 is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
Pin Descriptions
Pin No. (SOIC)
Name
RIN+
RIN−
ROUT
EN
Description
2, 6, 10, 14
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
1, 7, 9, 15
3, 5, 11, 13
4
12
16
8
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
EN*
VCC
GND
8
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Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
Output High Voltage vs
Ambient Temperature
6
5
4
5.5
TA = 25 °C
VID = 200 mV
VCC = 5V
VID = 200 mV
5
4.5
200
100
0
4.5
4.75
5
5.25
5.5
œ40 œ15
10
35
60
85
VCC œ Power Supply Voltage (V)
TA œ Ambient Temperature (°C)
Figure 7.
Figure 8.
Output Low Voltage vs
Power Supply Voltage
Output Low Voltage vs
Ambient Temperature
200
100
0
VCC = 5V
VID = œ200 mV
TA = 25°C
VID = œ200 mV
œ40
4.5
5.5
œ15
60
85
4.75
5
5.25
10
35
VCC œ Power Supply Voltage (V)
TA œ Ambient Temperature (°C)
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
Output Short Circuit Current
vs Power Supply Voltage
Output Short Circuit Current
vs Ambient Temperature
œ100
œ80
œ60
œ40
œ20
0
œ100
œ80
œ60
œ40
œ20
0
VCC = 5V
VOUT = 0V
TA = 25°C
VOUT = 0V
œ40 œ15
10
35
60
85
4.5
4.75
5
5.25
5.5
VCC œ Power Supply Voltage (V)
TA œ Ambient Temperature (°C)
Figure 11.
Figure 12.
Differential Propagation Delay
vs
Differential Propagation Delay
vs Ambient Temperature
Power Supply Voltage
5
4
3
5
4
3
VCC = 5V
TA = 25°C
Freq = 65 MHz
VID = 200 mV
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
CL = 5 pF
tPLHD
tPHLD
tPLHD
tPHLD
2
1
2
1
5.5
4.5
4.75
5
5.25
œ40 œ15
35
60
85
10
VCC œ Power Supply Voltage (V)
TA œ Ambient Temperature (°C)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
1
1
TA = 25°C
VCC = 5V
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
œ40
10
35
œ15
60
85
5.5
4.5
4.75
5
5.25
TA œ Ambient Temperature (°C)
VCC œ Power Supply Voltage (V)
Figure 15.
Figure 16.
Transition Time vs
Transition Time vs
Power Supply Voltage
Ambient Temperature
1
1
VCC = 5V
TA = 25°C
Freq = 65 MHz
Freq = 65 MHz
0.8
0.8
tTLH
tTHL
0.6
0.4
0.2
0
0.6
0.4
0.2
0
tTHL
tTLH
5.5
œ40 œ15
10
35
60
85
4.5
4.75
5
5.25
VCC œ Power Supply Voltage (V)
TA œ Ambient Temperature (°C)
Figure 17.
Figure 18.
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
DS90C032TM
ACTIVE
SOIC
SOIC
D
16
16
48
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
DS90C032TM
DS90C032TM/NOPB
ACTIVE
D
48
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
DS90C032TM
DS90C032TMX
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
2500
2500
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
DS90C032TM
DS90C032TM
DS90C032TMX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C032TMX
SOIC
SOIC
D
D
16
16
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
10.3
10.3
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
DS90C032TMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90C032TMX
SOIC
SOIC
D
D
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
DS90C032TMX/NOPB
Pack Materials-Page 2
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