DS90CF363BMTX/NOPB [TI]
+3.3V 下降沿 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz | DGG | 48 | -10 to 70;
| 型号： | DS90CF363BMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V 下降沿 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz | DGG | 48 | -10 to 70 驱动 光电二极管 接口集成电路 线路驱动器或接收器 显示器 驱动程序和接口 |
| 文件： | 总15页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CF363B
www.ti.com
SNLS180D –JULY 2004–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
Check for Samples: DS90CF363B
1
FEATURES
•
•
•
•
•
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 48-lead TSSOP Package
Improved Replacement for:
2
•
No Special Start-up Sequence Required
between Clock/Data and /PD Pins. Input Signal
(Clock and Data) can be Applied Either Before
or After the Device is Powered.
•
•
Support Spread Spectrum Clocking up to
100KHz Frequency Modulation & Deviations of
±2.5% Center Spread or −5% Down Spread.
–
SN75LVDS84, DS90CF363A
DESCRIPTION
"Input Clock Detection" Feature will Pull all
LVDS Pairs to Logic Low when Input Clock is
Missing and when /PD Pin is Logic High.
The DS90CF363B transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz,
18 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughput
is 170 Mbytes/sec. The DS90CF363B is fixed as a
Falling edge strobe transmitter and will interoperate
with a Falling edge strobe Receiver (DS90CF366)
without any translation logic.
•
•
•
18 to 68 MHz Shift Clock Support
Best–in–Class Set & Hold Times on TxINPUTs
Tx Power Consumption < 130 mW (typ)
@65MHz Grayscale
•
40% Less Power Dissipation than BiCMOS
Alternatives
•
•
Tx Power-Down Mode < 37μW (typ)
Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
•
•
•
Narrow Bus Reduces Cable Size and Cost
Up to 1.3 Gbps Throughput
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Up to 170 Megabytes/sec Bandwidth
Block Diagram
Figure 1. DS90CF363B
See Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
DS90CF363B
SNLS180D –JULY 2004–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Value
Unit
Supply Voltage (VCC
)
−0.3 to +4
V
V
V
CMOS/TTL Input Voltage
−0.3 to (VCC + 0.3)
−0.3 to (VCC + 0.3)
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Continuous
+150
Junction Temperature
Storage Temperature
°C
°C
−65 to +150
Lead Temperature
(Soldering, 4 sec)
+260
1.98
°C
W
Maximum Package Power Dissipation Capacity @ 25°C
DGG-48 (TSSOP) Package:
DS90CF363B
Package Derating:
DS90CF363B
16 mW/°C above +25°C
ESD Rating (HBM, 1.5 kΩ, 100 pF)
ESD Rating (EIAJ, 0Ω, 200 pF)
7
kV
V
500
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be verified. They are not meant to imply that
the device should be operated at these limits. Electrical Characteristics specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
−10
+25
+70
200
68
°C
Supply Noise Voltage (VCC
)
mVPP
MHz
TxCLKIN frequency
18
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.79
+1.8
0
−1.5
+10
V
V IN = 0.4V, 2.5V or VCC
V IN = GND
μA
μA
−10
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
345
1.25
−3.5
450
35
mV
mV
ΔVOD
Change in VOD between complimentary
output states
(3)
VOS
Offset Voltage
1.13
1.38
35
V
ΔVOS
Change in VOS between complimentary
output states
mV
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100Ω
−5
mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD ).
(2) Typical values are given for VCC = 3.3V and T A = +25°C unless specified otherwise.
(3) VOS previously referred as VCM
.
2
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SNLS180D –JULY 2004–REVISED APRIL 2013
Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IOZ
Parameter
Conditions
Min
Typ(2)
Max
Units
Output TRI-STATE Current
Power Down = 0V,
±1
±10
μA
VOUT = 0V or V CC
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current
Worst Case
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figure 2 and Figure 5 ) "
Typ " values are given for
f = 25 MHz
f = 40 MHz
f = 65 MHz
29
34
42
40
45
55
mA
mA
mA
V CC = 3.6V and T A
=
+25°C, " Max " values are
given for V CC = 3.6V and T
A = −10°C
Transmitter Supply Current
16 Grayscale
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figure 3 and Figure 5 ) "
Typ " values are given for
f = 25 MHz
f = 40 MHz
f = 65 MHz
28
32
39
40
45
50
mA
mA
mA
V CC = 3.6V and T A
=
+25°C, " Max " values are
given for V CC = 3.6V and T
A = −10°C
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE under
Power Down Mode
11
150
μA
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
Parameter
Min
Typ
Max
Units
ns
TxCLK IN Transition Time (Figure 6 )
TxCLK IN Period (Figure 7 )
5
TCIP
TCIH
TCIL
TXIT
TXPD
14.7
T
50.0
ns
TxCLK IN High Time (Figure 7 )
TxCLK IN Low Time (Figure 7 )
0.35T 0.5T 0.65T
0.35T 0.5T 0.65T
ns
ns
TxIN, and Power Down pin transition Time
1.5
1
6.0
ns
Minimum pulse width for Power Down pin signal
us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 5 )
LVDS High-to-Low Transition Time (Figure 5 )
Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Min
Typ
Max
Units
ns
0.75
0.75
0
1.4
1.4
LHLT
ns
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
f = 65
MHz
−0.20
2.00
+0.20
2.40
4.60
6.79
8.99
11.19
13.39
ns
2.20
4.40
6.59
8.79
10.99
13.19
ns
4.20
ns
6.39
ns
8.59
ns
10.70
12.99
ns
ns
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
Copyright © 2004–2013, Texas Instruments Incorporated
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Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
Parameter
Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 12 )(1)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 7 )
Min
−0.25
3.32
Typ
0
Max
+0.25
3.82
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f = 40
MHz
3.57
7.14
10.71
14.29
17.86
21.43
0
6.89
7.39
10.46
14.04
17.61
21.18
−0.45
5.26
10.96
14.54
18.11
21.68
+0.45
6.16
f =
25MHz
5.71
11.43
17.14
22.86
28.57
34.29
10.98
16.69
22.41
28.12
33.84
2.5
11.88
17.59
23.31
29.02
34.74
THTC
TxIN Hold to TxCLK IN (Figure 7 )
0.5
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 8 ) 50% duty cycle input clock is assumed, T 3.011
A= −10°C, and 65MHz for " Min ", T A = 70°C, and 25MHz for " Max ", VCC = 3.6V
6.082
SSCG
Spread Spectrum Clock support; Modulation frequency with a linear
profile
f = 25
MHz
100KHz ±
2.5%/−5%
(2)
f = 40
MHz
100KHz ±
2.5%/−5%
f = 65
MHz
100KHz ±
2.5%/−5%
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 9 )
Transmitter Power Down Delay (Figure 11 )
10
ms
ns
100
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
Figure 2. “Worst Case” Test Pattern
4
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SNLS180D –JULY 2004–REVISED APRIL 2013
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. DS90CF363B (Transmitter) LVDS Output Load
Figure 5. DS90CF363B (Transmitter) LVDS Transition Times
Figure 6. DS90CF363B (Transmitter) Input Clock Transition Time
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SNLS180D –JULY 2004–REVISED APRIL 2013
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Figure 7. DS90CF363B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
Figure 8. DS90CF363B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
Figure 9. DS90CF363B (Transmitter) Phase Lock Loop Set Time
Figure 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
6
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SNLS180D –JULY 2004–REVISED APRIL 2013
Figure 11. Transmitter Power Down Delay
Figure 12. Transmitter LVDS Output Pulse Position Measurement
Copyright © 2004–2013, Texas Instruments Incorporated
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DS90CF363B
SNLS180D –JULY 2004–REVISED APRIL 2013
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DS90CF363B PIN DESCRIPTIONS — FPD LINK TRANSMITTER
Pin Name
TxIN
I/O
No.
Description
I
21
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
O
I
3
3
1
1
1
1
Positive LVDS differential data output.
TxOUT−
Negative LVDS differential data output.
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
See Applications Information .
VCC
I
I
I
I
I
I
4
4
1
2
1
3
1
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
NC
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No connect
APPLICATIONS INFORMATION
The DS90CF363B are backward compatible with the DS90C363/DS90CF363A and are a pin-for-pin
replacement.
This device may also be used as a replacement for the DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/modifications:
1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC of the transmitter.
TRANSMITTER INPUT PINS
The DS90CF363B transmitter input and control inputs accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90CF363B does not require any special requirement for sequencing of the input clock/data and PD
(PowerDown) signal. The DS90CF363B offers a more robust input sequencing feature where the input clock/data
can be inserted after the release of the PD signal. In the case where the clock/data is stopped and reapplied,
such as changing video mode within Graphics Controller, it is not necessary to cycle the PD signal. However,
there are in certain cases where the PD may need to be asserted during these mode changes. In cases where
the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the LVDS
transmitter, the LVDS Transmitter may attempt to lock onto this unstable clock signal but is unable to do so due
the instability or quality of the clock source. The PD signal in these cases should then be asserted once a stable
clock is applied to the LVDS transmitter. Asserting the PWR DOWN pin will effectively place the device in reset
and disable the PLL, enabling the LVDS Transmitter into a power saving standby mode. However, it is still
generally a good practice to assert the PWR DOWN pin or reset the LVDS transmitter whenever the clock/data is
stopped and reapplied but it is not mandatory for the DS90CF363B.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90CF363B can support Spread Spectrum Clocking signal type inputs. The DS90CF363B outputs will
accurately track Spread Spectrum Clock/Data inputs with modulation frequencies of up to 100KHz (max.)with
either center spread of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have VCC, LVDS VCC and PLL VCC from the same power source with
three separate de-coupling bypass capacitor groups. There is no requirement on which VCC entering the device
first.
8
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SNLS180D –JULY 2004–REVISED APRIL 2013
Pin Diagram
Figure 13.
Typical Application
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SNLS180D –JULY 2004–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
PACKAGING INFORMATION
Orderable Device
DS90CF363BMT/NOPB
DS90CF363BMTX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-10 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
DGG
48
48
38
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-2-260C-1 YEAR
DS90CF363BMT
ACTIVE
DGG
1000
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-10 to 70
DS90CF363BMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CF363BMTX/NOPB TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS90CF363BMTX/NOPB
1000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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