DS90CP04TLQ [TI]
1.5Gbps 4x4 LVDS 交叉点开关 | NJE | 32 | -40 to 85;型号: | DS90CP04TLQ |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.5Gbps 4x4 LVDS 交叉点开关 | NJE | 32 | -40 to 85 开关 |
文件: | 总24页 (文件大小:478K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS90CP04
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SNLS154I –JANUARY 2002–REVISED APRIL 2013
DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch
Check for Samples: DS90CP04
1
FEATURES
DESCRIPTION
DS90CP04 is a 4x4 digital cross-point switch with
broadside input and output pins for efficient board
layout. It utilizes Low Voltage Differential Swing
(LVDS) technology for low power, high-speed
operation. Data paths are fully differential from input
to output for low noise. The non-blocking architecture
allows connections of any input to any output or
outputs. The switch matrix consists of four differential
4:1 multiplexes. Each output channel connects to one
of the four inputs common to all multiplexers.
2
•
•
DC - 1.5 Gbps Low Jitter, Low Skew Operation
Pin and Serial Interface Configurable, Fully
Differential, Non-blocking Architecture
•
Wide Input Common Mode Voltage Range
Enables Easy Interface to LVDS/LVPECL/2.5V-
CML Drivers
•
•
TRI-STATE LVDS Outputs
Serial Control Interface with Read-back
Capability
A simple serial control interface or a configuration
select port is activated by the state of the MODE pin.
When utilizing the serial control interface a single
load command will update the new switch
configuration for all outputs simultaneously.
•
•
•
Double Register Loading
Single +2.5V Supply
Small 6x6 mm WQFN-32 Space Saving
Package
•
Fabricated with Advanced CMOS Process
Technology
Functional Block Diagrams
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
4:1 MUX1
4:1 MUX4
4:1 MUX2
4:1 MUX3
SCLK
SI/SEL1
EN1
EN2
EN3
EN4
Digital Control
Interface
SEL0
LOAD
MODE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
DS90CP04
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DIGITAL CONTROL INTERFACE
ROW
OUTPUT
REGISTER
INPUT
REGISTER
ROW
DECREMENT
SI/SEL1
RSO
RSCLK
COLUMN
OUTPUT
REGISTER
COLUMN
DECREMENT
CSO
SEL0
CLOCK AND
CONTROL
SCLK
MODE
CSCLK
LOAD
SWITCH
CONFIGURATION
REGISTER
LOAD
REGISTER
Figure 1. Functional Block Diagram
2
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Connection Diagram
8
7
6
5
4
3
2
1
DAP = GND
OUT4-
9
32
31
30
29
28
27
26
25
IN4-
10
11
12
13
14
15
16
OUT4+
OUT3-
IN4+
IN3-
IN3+
IN2-
IN2+
IN1-
IN1+
DS90CP04
WQFN-32
6x6x0.75mm body size
0.5mm pitch
OUT3+
OUT2-
Top View Shown
OUT2+
OUT1-
OUT1+
17
18
19
20
21
22
23
24
Figure 2. Connection Diagram - 32 Pin (Top View)
See Package Number NJE0032A
PIN DESCRIPTIONS
Pin
Name
Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN1+
IN1−
16
15
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Inverting and non-inverting differential inputs.
IN2+
IN2−
14
13
Inverting and non-inverting differential inputs.
Inverting and non-inverting differential inputs.
Inverting and non-inverting differential inputs.
IN3+
IN3−
12
11
IN4+
IN4−
10
9
SWITCHED DIFFERENTIAL OUTPUTS
OUT1+
OUT1−
25
26
O, LVDS
O, LVDS
O, LVDS
O, LVDS
Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
OUT2+
OUT2−
27
28
Inverting and non-inverting differential outputs. OUT2± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
OUT3+
OUT3−
29
30
Inverting and non-inverting differential outputs. OUT3± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4
OUT4+
OUT4−
31
32
Inverting and non-inverting differential outputs. OUT4± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
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PIN DESCRIPTIONS (continued)
Pin
Name
Pin
Number
I/O, Type
Description
DIGITAL CONTROL INTERFACE
SCLK
6
I, LVCMOS
Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK
should be burst of clock pulses active only while accessing the device. After completion of
programming, SCLK should be kept at logic low to minimize potential noise injection into
the high-speed differential data paths.
SI / SEL1
SEL0
7
5
I, LVCMOS
Programming data to select the switch configuration. Data is latched into the input buffer
register at the rising edge of SCLK.
I, LVCMOS
O, LVCMOS
Programming data to select the switch configuration.
CSO
RSO
18
2
With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device
in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with
the exception of the device column (row) address being decremented by one internally
before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising
edge of SCLK.
CSCLK
RSCLK
19
3
O, LVCMOS
I, LVCMOS
With MODE low, these pins function as a buffered control clock from SCLK. CSCLK
(RSCLK) is used for cascading the serial control bus to the next device in the serial chain.
LOAD
22
When LOAD is high and SCLK makes a LH transition, the device transfers the
programming data in the load register into the configuration registers. The new switch
configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK
cycle to complete the process, holding LOAD high longer repeats the transfer to the
configuration register.
MODE
23
I, LVCMOS
When MODE is low, the SCLK is active and a buffered SCLK signal is present at the
CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and
state machine internals. Internal registers will see an active low signal until MODE is
brought Low again.
POWER
VDD
1, 8, 17,
24
I, Power
I, Power
VDD = 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from
VDD to GND plane.
GND
4, 20, 21,
DAP
Ground reference to LVDS and CMOS circuitry.
DAP is the exposed metal contact at the bottom of the WQFN-32 package. The DAP is
used as the primary GND connection to the device. It should be connected to the ground
plane with at least 4 vias for optimal AC and thermal performance.
Serial Interface Truth Table
LOAD
MODE
SCLK
LH
Resulting Action
0
0
0
1
The current state on SI is clocked into the input shift register.
LH
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
LH
1
0
1
X
Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load
register into the configuration register. The switch configuration is updated asynchronously
from the SCLK input.
LH
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
Configuration Select Truth Table
MODE
SEL1
SEL0
Resulting Action
The SEL0/1 pins only function in configuration select mode. See below.
Distribution: IN1 - OUT1 OUT2 OUT3 OUT4
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Distribution: IN2 - OUT1 OUT2 OUT3 OUT4
Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4
Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4
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SEL0 = 1
SEL1 = 1
SEL0 = 0
SEL1 = 0
IN1+
IN1-
IN1+
IN1-
OUT1+
OUT1-
OUT1+
OUT1-
IN2+
IN2-
OUT2+
OUT2-
OUT2+
OUT2-
IN3+
IN3-
OUT3+
OUT3-
OUT3+
OUT3-
IN4+
IN4-
OUT4+
OUT4-
OUT4+
OUT4-
SEL0 = 0
SEL1 = 1
SEL0 = 1
SEL1 = 0
IN1+
IN1-
OUT1+
OUT1-
OUT1+
OUT1-
IN2+
IN2-
OUT2+
OUT2-
OUT2+
OUT2-
IN3+
IN3-
OUT3+
OUT3-
OUT3+
OUT3-
OUT4+
OUT4-
OUT4+
OUT4-
Figure 3. DS90CP04 Configuration Select Decode
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1)(2)
Absolute Maximum Ratings
Supply Voltage (VDD
)
−0.3V to +3V
−0.3V to (VDD +0.3V)
−0.3V to +3.3V
−0.3V to +3V
40mA
CMOS/TTL Input Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
WQFN-32
3200 mW
38 mW/°C
26.4°C/W
Derating above 25°C
Thermal Resistance, θJA
ESD Rating
HBM, 1.5 kΩ, 100 pF
LVDS Outputs
>1.0 kV
>1.5 kV
>4.0 kV
>100V
LVDS Inputs
All Other Pins
EIAJ, 0Ω, 200 pF
(1) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(2) “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
Recommended Operating Conditions
Min
2.375
0.05
−40
Typ
Max
2.625
3.3
Unit
V
Supply Voltage (VDD– GND)
Receiver Input Voltage
2.5
V
Operating Free Air Temperature
Junction Temperature
25
85
°C
°C
110
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
(1)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS (SCLK, SI/SEL1, SEL0, LOAD, MODE , CSCLK, RSCLK, CSO, RSO)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
1.7
GND
−10
−10
VDD
0.7
V
V
VIL
IIH
VIN = VDD = VDDMAX
+10
+10
µA
µA
pF
pF
V
IIL
VIN = VSS, VDD = VDDMAX
Any Digital Input Pin to VSS
Any Digital Output Pin to VSS
ICL = −18 mA
CIN1
COUT1
VCL
VOH
3.5
5.5
Output Capacitance
Input Clamp Voltage
−1.5
1.9
−0.8
High Level Output Voltage
IOH = −4.0 mA, VDD = VDDMIN
IOH = −100 µA, VDD = 2.5V
IOL = 4.0 mA, VDD = VDDMIN
IOL = 100 µA, VDD = 2.5V
V
2.4
V
VOL
Low Level Output Voltage
0.4
0.1
V
V
LVDS INPUT DC SPECIFICATIONS (IN1±, IN2±, IN3±, IN4±)
(1) “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
(2) Typical parameters are measured at VDD = 2.5V, TA = 25°C. They are for reference purposes, and are not production-tested.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. (1)
(2)
Symbol
VTH
Parameter
Conditions
Min
Typ
Max
Units
Differential Input High Threshold
VCM = 0.05V or 1.2V or 2.45V, VDD
2.5V
=
=
0
50
mV
(3)
VTL
Differential Input Low Threshold
VCM = 0.05V or 1.2V or 2.45V, VDD
2.5V
−50
0
mV
VID
Differential Input Voltage
Common Mode Voltage Range
Input Capacitance
VDD = 2.5V, VCM = 0.05V to 2.45V
VID = 100 mV, VDD = 2.5V
IN+ or IN− to VSS
100
VDD
mV
V
VCMR
CIN2
IIN
0.05
3.25
3.5
pF
µA
µA
Input Current
VIN = 2.5V, VDD = VDDMAX or 0V
VIN = 0V, VDD = VDDMAX or 0V
−10
−10
+10
+10
LVDS OUTPUT DC SPECIFICATIONS (OUT1±, OUT2±, OUT3±, OUT4±)
(3)
VOD
Differential Output Voltage
RL = 100Ω between OUT+ and OUT−
(see Figure 4)
250
−35
400
475
35
mV
mV
V
ΔVOD
Change in VOD between
Complementary States
(4)
VOS
Offset Voltage
1.125
−35
1.25
1.375
35
ΔVOS
Change in VOS between
Complementary States
mV
IOZ
Output TRI-STATE Current
TRI-STATE Output
VOUT = VDD or VSS
−10
−10
+10
µA
IOFF
IOS
Power Off Leakage Current
VDD = 0V, VOUT = 2.5V or GND
+10
-40
40
µA
mA
mA
mA
mA
Output Short Circuit Current, One OUT+ or OUT− Short to GND
Complementary Output
−15
15
OUT+ or OUT− Short to VDD
IOSB
Output Short Circuit Current, both OUT+ and OUT− Short to GND
Complementary Outputs
−15
15
-30
30
OUT+ and OUT− Short to VCM
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRI-
STATE
5.5
pF
SUPPLY CURRENT
ICCD Total Supply Current
All inputs and outputs enabled,
terminated with differential load of
100Ω between OUT+ and OUT-.
220
10
300
20
mA
mA
ICCZ
TRI-STATE Supply Current
TRI-STATE All Outputs
(6) (7)
SWITCHING CHARACTERISTICS—LVDS OUTPUTS ((5)
,
,
)
tLHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at
100
100
500
500
135
135
750
160
160
ps
ps
ps
Time
200 Mb/s, measure between 20%
and 80% of VOD
.
tHLT
Differential High to Low Transition
Time
tPLHD
tPHLD
tSKD1
Differential Low to High
Propagation Delay
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% VOD
between input to output.
1200
Differential High to Low
Propagation Delay
750
0
1200
30
ps
ps
Pulse Skew
|tPLHD–tPHLD|
(3) Differential output voltage VOD is defined as |OUT+–OUT−|. Differential input voltage VID is defined as |IN+–IN−|.
(4) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(5) Differential output voltage VOD is defined as |OUT+–OUT−|. Differential input voltage VID is defined as |IN+–IN−|.
(6) Characterized from any input to any one differential LVDS output running at the specified data rate and data pattern, with all other 3
channels running K28.5 pattern at 1.25 Gb/s asynchronously to the channel under test. Jitter is not production-tested, but ensured
through characterization on sample basis. Random Jitter is measured peak to peak with a histogram including 1000 histogram window
hits. K28.5 pattern is repeating bit streams of (0011111010 1100000101). This deterministic jitter or DJ pattern is measured to a
histogram mean with a sample size of 350 hits. Like RJ the Total Jitter or TJ is measured peak to peak with a histogram including 3500
window hits.
(7) The LVCMOS input and output AC specifications may also be verified and tested using an input attenuation network instead of a power
splitter.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. (1)
(2)
Symbol
tSKCC
Parameter
Conditions
Min
Typ
Max
Units
Output Channel to Channel Skew Difference in propagation delay (tPLHD
or tPHLD) among all output channels
in Broadcast mode (any one input to
0
50
100
ps
all outputs).
(6)
tJIT
Jitter
Alternating 1 and 0 Pattern
750 MHz
1.6
1.6
2.5
2.5
psrms
psrms
1.25 GHz
K28.5 Pattern
1.5 Gb/s
10
27
40
60
psp-p
psp-p
2.5 Gb/s
PRBS 223-1 Pattern
1.5 Gb/s
25
40
40
70
psp-p
psp-p
2.5 Gb/s
tON
LVDS Output Enable Time
LVDS Output Disable Time
Time from LOAD = LH or SELx to
OUT± change from TRI-STATE to
active.
50
150
3
300
5
ns
ns
tOFF
Time from LOAD = LH or SELx to
OUT± change from active to TRI-
STATE.
tSW
LVDS Switching Time
SELx to OUT±
Time from LOAD = LH to new switch
configuration effective for OUT±.
50
50
150
150
ns
ns
tSEL
Configuration select to new data at
OUT±.
SWITCHING CHARACTERISTICS — Serial control Interface ((8)
)
FSCLK
SCLK Clock Frequency
0
100
55
MHz
%
TDCCLK
CSCLK Duty Cycle
RSCLK Duty Cycle
Input SCLK Duty Cycle set at 50%
45
tS
tH
SI–SCLK or MODE–SCLK Setup
Time
From SI or MODE Input Data to
SCLK Rising Edge
1.5
1
ns
ns
SCLK–SI or SCLK–MODE Hold
Time
From SCLK Rising Edge to SI or
MODE Input Data
tDSO
SCLK to RSO or CSO Delay
From SCLK to RSO or CSO
1.5
4.0
4
ns
ns
tDSCLK
tDSDIF
SCLK to RSCLK or CSCLK Delay From SCLK to RSCLK or CSCLK
8.5
|SCLK to RSCLK or
CSCLK–SCLK to RSO or CSO|
Propagation Delay Difference
between tDSO and tDSCLK
1.5
4.5
ns
ns
ns
TRISE
TFALL
Logic Low to High Transition Time 20% to 80% at RSO, CSO, RSCLK,
or CSCLK
1.5
1.5
Logic High to Low Transition Time 80% to 20% at RSO, CSO, RSCLK,
or CSCLK
(8) Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
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DC
Source
>100K
VOUT+
IN+
IN-
RL/2
RL/2
OUT+
OUT-
M
U
X
VDC1
VDC2
D
R
>100K
VOD = |VOUT+ - VOUT-|
VOUT-
VOS
49.99
49.99
>100K
Figure 4. Differential Driver DC Test Circuit
OUT+ and OUT- are connected to a
100W differential transmission line
VDD = 2.50V
ADVANTEST D3186
Data Generator
CSA8000
DC
BLOCK
VID=250mV
VOS=1.20V
Coax
50
IN+
M
U
X
OUT+
OUT-
+
R
D
-
IN-
TRIG
DC
Coax
BLOCK
50W
50W
50
50
DUT
VOD = |VOUT+ - VOUT-|
Coax
VSS = 0.0V
Figure 5. Differential Driver AC Test Circuit
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950W resistors provide a 20:1 attenuation
network with CSA8000.
50W
Tek DG2020
Pulse Generator
CL is a lumped capacitance placed as
close as possible to the device output.
VDD= 2.50V
VOH = VDD
VOL = GND
CSA8000
50W Scope
Termination
950W
MODE
LOAD
MODE
LOAD
SI/SEL1
SCLK
RSO
RSCLK
SI/SEL1
SCLK
CSO
CSCLK
SEL0
SEL0
TRIG
DUT
CL = 15pF
VSS= 0.0V
50W Scope
Termination
450W
450W resistors provide a 10:1
attenuation network with CSA8000.
(9)
Figure 6. LVCMOS Driver AC Test Circuit
)
(9) The LVCMOS input and output AC specifications may also be verified and tested using an input attenuation network instead of a power
splitter.
Parameter Measurement Information
IN+
VOS=1.2V typical
IN-
IN+
VID
IN-
Figure 7. LVDS Signals
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(OUT+ - OUT-)
80%
20%
80%
0V
20%
tLHT
tHLT
OUT+
OUT-
VOD
Figure 8. LVDS Output Transition Time
(IN+ - IN-)
0.0V
tPLHD
tPHLD
(OUT+ - OUT-)
0.0V
Figure 9. LVDS Output Propagation Delay
SCLK
tS
tH
VALID
DATA
VALID
DATA
SI
WINDOW
WINDOW
tDSO
RSO
CSO
tDSCLK
RSCLK
CSCLK
tDSDIF
Figure 10. Serial Interface Propagation Delay and Input Timing Waveforms
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SCLK
tS
tH
MODE
SCLK
(Internal)
tDSCLK
RSCLK
CSCLK
Figure 11. Serial Interface— MODE Timing and Functionality
Load Configuration "A"
Load Configuration "B"
LOAD or
SELx
tSW
tSW
OUT±
Configuration "B"
Configuration "A"
tOFF
tON
50%
50%
50%
OUT+
OUT-
1.2V
1.2V
50%
Figure 12. Configuration and Output Enable/Disable Timing
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FUNCTIONAL DESCRIPTIONS
Programming with the Serial Interface
The configuration of the internal multiplexer is programmed through a simple serial interface consisting of serial
clock SCLK and serial input data line SI. The serial interface is designed for easy expansion to larger switch
array. A replicated output serial interface (RSCLK, RSO) is provided for propagating the control data to the
downstream device in the row of an array of DS90CP04 devices in a matrix. A similar replicated serial interface
(CSCLK, CSO) is provided for propagating the control data to the downstream devices in the first column of the
device matrix. Through this scheme, user can program all the devices in the matrix through one serial control bus
(SCLK and SI) with the use of the feed-through replicated control bus at RSCLK and RSO, CSCLK and CSO.
To program the configuration of the switch, a 30-bit control word is sent to the device. The first 6 bits shift the
start frame into SI. The only two valid start frames are 1F'h for a configuration load and 1E'h for a configuration
read. The start frame is followed by the row and column addresses of the device to be accessed, as well as the
switch configuration of the four channels of the device. Table 1 and Table 2 are the bit definitions of the control
word. D29 is the first bit that shifts into SI.
Table 1. 30-Bit Control Word
Bit
D29–D24
D23–D18
Bit Length
Descriptions
6
6
The start frame for control word synchronization (01 1111'b = LOAD).
Specify the row address of the device to be access. The serial interface can access up to 64 devices in the
row.
D17–D12
6
Specify the column address of the device to be access. The serial interface can access up to 64 devices in
the column.
D11–D9
D8–D6
D5–D3
D2–D0
3
3
3
3
Specify the switch configuration for Output 1. See Table 2.
Specify the switch configuration for Output 2. See Table 2.
Specify the switch configuration for Output 3. See Table 2.
Specify the switch configuration for Output 4. See Table 2.
Table 2. Switch Configuration Data
MSB
LSB
0
OUT1± Connects to
OUT2± Connects to
OUT3± Connects to
OUT4± Connects to
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Output 1 Tri-Stated
Output 2 Tri-Stated
Output 3 Tri-Stated
Output 4 Tri-Stated
1
IN1±
IN1±
IN2±
IN3±
IN4±
IN1±
IN2±
IN3±
IN4±
IN1±
IN2±
IN3±
IN4±
0
IN2±
1
IN3±
0
IN4±
1
Invalid.
0
Use of these invalid combinations may cause loss of synchronization.
1
Row and Column Addressing
The upper left device in an array of NxN devices is assigned row address 0, and column address 0. The devices
to its right have column addresses of 1 to N, whereas devices below it have row addresses of 1 to N. The Serial
Control Interface (SCLK and SI) is connected to the first device with the row and column addresses of 0. The
Serial Control Interface shifts in a control word containing the row and column address of the device it wants to
access. When the control data propagates through each device, the control word's address is internally
decremented by one before it is sent to the next row or column device. When the control data is sent out the
column interface (CSO and CSCLK) the row address is decremented by one. Similarly, when the column
address data is shifted out the row interface (RSO and RSCLK) the column address is decremented by one. By
the time the control word reaches the device it has been intended to program, both the row and column
addresses have been decremented to 0.
Each device constantly checks for the receipt of a frame start (D29-24=01 1111'b or 01 1110'b). When it detects
the proper start frame string, and the row and column addresses it receives are both 0, the device responds by
storing the switch configuration data of the 30-bit control word into its load register.
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Each device in the array is sequentially programmed through the serial interface. When programming is
completed for the entire array, LOAD is pulsed high and the load register's content is transferred to the
configuration register of each device. The LOAD pulse must wait until the final bit of the control word has been
placed into the "load" register. This timing is ensured to take place two clock cycles after programming has been
completed.
Due to internal shift registers additional SCLK cycles will be necessary to complete array programming. It takes 7
clock (SCLK) positive edge transitions for the control data to appear at RSO and CSO for its near neighbor.
Users must provide the correct number of clock transitions for the control data word to reach its destination in the
array. Table 3 shows an example of the control data words for a 4 device serial chain with connections
(OUT1=IN1, OUT2=IN2, OUT16=IN16). To program the array, it requires four 30-bit control words to ripple
through the serial chain and reach their destinations. In order to completely program the array in the 120 clock
cycles associated with the 30-bit control words it is important to program the last device in the chain first. The
following programming data pushes the initial data through the chain into the correct devices.
Read-Back Switch Configuration
The DS90CP04 is put into read-back mode by sending a special “Read” start frame (01 1110'b). Upon receipt of
the special read start frame the configuration register information is transferred into the shift register and output
at both RSO and CSO in the OUT1 to OUT4 bit segments of the read control word. Each time the read-back
data from a device passes through its downstream device, its default address (11 1111'b) is internally
decremented by one. The “relative” column address emerges at RSO of the last device in the row and is used to
determine (11 1111'b - N) the column of the sending device. Similarly, the row address emerges at CSO of the
sending device. After inserting the channel configuration information in the “read” control word, the device will
automatically revert to write mode, ready to accept a new control word at SI.
Table 4 shows an example of reading back the configuration registers of 4 devices in the first row of a 4x4 device
array. Again, due to internal shift registers additional SCLK cycles will be necessary to complete the array read. It
takes 4x30 SCLK clock cycles to shift out 4 30-bit configuration registers plus 7 SCLK cycles per device to
account for device latency making for a total SCLK count of 148. The serialized read data is sampled at RSO
and synchronized with RSCLK of the last device in the row. The user is recommended to backfill with all 0's at SI
after the four reads have been shifted in.
Table 3. Example to Program a 4 Device Array
Control Word
Row
Address
D23:D18
Column
Address
D17:D12
Number of
SCLK
Cycles
Destination
Device in Array
Row, Column
Frame
D29:D24
OUT1
D11:D9
OUT2
D8:D6
OUT3
D5:D3
OUT4
D2:D0
01 1111
01 1111
01 1111
01 1111
00 0000
00 0000
00 0000
00 0000
00 0011
00 0010
00 0001
00 0000
001
001
001
001
010
010
010
010
011
011
011
011
100
100
100
100
30
30
30
30
0, 3
0, 2
0, 1
0, 0
Shift in configuration information from device furthest from system SI input first to minimize array latency
during the programming process.
The 2 clock cycle delay ensures all channel information has reached the “load” register and all switches
are ready to be configured.
2
Table 4. A Read-Back Example from a 4 Device Array
Row
Address
D23:D18
Column
Address
D17:D12
Number of
SCLK
Cycles
Frame
OUT1
D11:D9
OUT2
D8:D6
OUT3
D5:D3
OUT4
D2:D0
Descriptions
D29:D24
Read-Back
(R,C)=0, 3
01 1110
01 1110
01 1110
01 1110
00 0000
00 0000
00 0000
00 0000
11 1111
11 1110
11 1101
11 1100
000
000
000
001
000
000
000
010
000
000
000
011
000
000
000
100
30
30
30
30
Read-Back
(R,C)=0, 2
Read-Back
(R,C)=0, 1
Read-Back
(R,C)=0, 0
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Switch Expansion For Minimum Programming Latency
Programming data ripples through the array through RSO and RSCLK in the row and CSO and CSCLK in the
first column. LOAD pins of all devices are electrically tied together and driven by the same “load” signal. To
prevent excessive stub length in the array from affecting the signal quality of LOAD, it is recommended that the
load signal is distributed to each row or column in large crosspoint array applications.
NUMBER OF SCLK POSITIVE EDGE TRANSITIONS
0
30
60
CONTROL WORD 1
[01 F] [1][0] [1][1][1][1]
CONTROL WORD 1
[01 F] [0][0] [2][2][4][4]
DEVICE 0
DEVICE 1
(+7 Clocks)
[01 F] [0][0] [1][1][1][1]
[01 F] [3F][0] [2][2][4][4]
Device 1
Configuration Ready to
Load
Device 0
Configuration Ready
to Load
Programming Example
CONFIGURATION WRITE
30 Bit Control Word: [WRITE FRAME] [ROW ADDRESS][COLUMN ADDRESS] [OUT1][OUT2][OUT3][OUT4]
ARRAY WRITE
[01 1111] [0][1] [1][1][1][1] //*Array position 1, Broadcast IN1 *//
[01 1111] [0][0] [2][2][4][4] //*Array position 0, Connect IN2 to OUT1 and 2, IN4 to OUT3 and OUT4 *//
LOAD = H and SCLK = LH
NUMBER OF SCLK POSITIVE EDGE TRANSITIONS
0
30
60
90
120
150
CONTROL WORD 1
[01 F] [0][3] [4][4][4][4]
CONTROL WORD 2
[01 F] [0][2] [0][3][0][0]
CONTROL WORD 3
[01 F] [0][1] [0][0][2][0]
CONTROL WORD 4
[01 F] [0][0] [1][2][3][4]
DEVICE 0
DEVICE 1
(+7 Clocks)
[01 F] [0][2] [4][4][4][4]
[01 F] [0][1] [0][3][0][0]
[01 F] [0][0] [0][0][2][0]
[01 F] [0][3F] [1][2][3][4]
DEVICE 2
(+14 Clocks)
[01 F] [0][1] [4][4][4][4]
[01 F] [0][0] [0][3][0][0]
[01 F] [0][3F] [0][0][2][0]
[01 F] [0][3E] [1][2][3][4]
DEVICE 3
(+21 Clocks)
[01 F] [0][0] [4][4][4][4]
[01 F] [0][3F] [0][3][0][0]
[01 F] [0][3E] [0][0][2][0] [01 F] [0][3D] [1][2][3][4]
Device 3
Configuration
Ready to Load
Device 2
Configuration
Ready to Load
Device 1
Configuration
Ready to Load
Device 0
Configuration
Ready to Load
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DEVICE 0 WRITE PROGRAMMING SEQUENCE
SCLK
Number
Event Description
Device 0 (R=0, C=0) detects “WRITE” frame of first Control Word.
6
18
Device 0 (R=0, C=0) sees Row = 1, Column = 0 of first Control Word. The Row address of the first Control Word is
decremented by 1 (Row Address = 0) and sent out RSO.
36
48
Device 0 (R=0, C=0) detects “WRITE” frame of second Control Word.
Device 0 (R=0, C=0) sees Row = 0, Column = 0 of second Control Word. This is a valid configuration write address, Device
1 prepares to receive configuration information.
60
Device 0 (R=0, C=0) has received configuration information and is waiting for a LOAD.
DEVICE 1 WRITE PROGRAMMING SEQUENCE
SCLK
Number
Event Description
13
25
Device 1 (R=1, C=0) detects “WRITE” frame of first Control Word.
Device 1 (R=1,C=0) sees Row = 0, Column = 0 of first Control Word. This is a valid configuration write address, Device 1
prepares to receive configuration information.
37
43
55
Device 1 (R=1,C=0) has received configuration information and is waiting for a LOAD.
Device 1 (R=1, C=0) detects “WRITE” frame of second Control Word.
Device 1 (R=1,C=0) sees Row = 3F, Column = 0 of second Control Word. The Row address of the second Control Word is
decremented by 1 (Row Address = 3E) and sent out RSO.
CONFIGURATION READ
30 Bit Control Word: [READ FRAME] [ROW ADDRESS][COLUMN ADDRESS] [OUT1][OUT2][OUT3][OUT4]
ARRAY WRITE
[01 1110] [1][0] [0][0][0][0] //*Array position 1, Return Configuration Information *//
[01 1110] [0][0] [0][0][0][0] //*Array position 0, Return Configuration Information *//
NUMBER OF SCLK POSITIVE EDGE TRANSITIONS
0
30
60
90
120
150
CONTROL WORD 1
[01 E] [0][3] [0][0][0][0]
CONTROL WORD 2
[01 E] [0][2] [0][0][0][0]
CONTROL WORD 3
[01 E] [0][1] [0][0][0][0]
CONTROL WORD 4
[01 E] [0][0] [0][0][0][0]
DEVICE 0
DEVICE 1
(+7 Clocks)
[01 E] [0][2] [0][0][0][0]
[01 E] [0][1] [0][0][0][0]
[01 E] [0][0] [0][0][0][0]
[01 E] [0][3F] [1][2][3][4]
DEVICE 2
(+14 Clocks)
[01 E] [0][1] [0][0][0][0]
[01 E] [0][0] [0][0][0][0]
[01 F] [0][3F] [0][0][2][0]
[01 E] [0][3E] [1][2][3][4]
DEVICE 3
(+21 Clocks)
[01 E] [0][0] [0][0][0][0]
[01 E] [0][3F] [0][3][0][0]
[01 E] [0][3E] [0][0][2][0]
[01 E] [0][3D] [1][2][3][4]
Device 3 Configuration Read Out
[01 E] [0][3F] [4][4][4][4]
Device 0 Configuration Read Out
[01 E] [0][3C] [1][2][3][4]
Device 2 Configuration Read Out
[01 E] [0][3E] [0][3][0][0]
Device 1 Configuration Read Out
[01 E] [0][3D] [0][0][2][0]
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DEVICE 0 READ PROGRAMMING SEQUENCE
SCLK
Number
Event Description
Device 0 (R=0, C=0) detects “READ” frame of first Control Word.
6
18
Device 0 (R=0,C=0) sees Row = 1, Column = 0 of first Control Word. The Row address of the first Control Word is
decremented by 1 (Row Address = 0) and sent out RSO.
36
48
Device 0 (R=0,C=0) detects "READ" frame of second Control Word.
Device 0 (R=0,C=0) sees Row = 0, Column = 0 of second Control Word. This is a valid configuration read address, Device
0 prepares to transmit configuration information. The Row address of the last Control Word is decremented by 1 (Row
Address = 3F) and sent out RSO.
60
74
Device 0 (R=0,C=0) has transmitted configuration information.
Finished transmitting configuration information at Array Output (RSO of Device 1).
DEVICE 1 READ PROGRAMMING SEQUENCE
SCLK
Number
Event Description
13
25
Device 1 (R=1, C=0) detects “READ” frame of first Control Word.
Device 1 (R=1,C=0) sees Row = 0, Column = 0 of first Control Word. This is a valid configuration read address, Device 1
prepares to transmit configuration information. The Row address of the last Control Word is decremented by 1 (Row
Address = 3F) and sent out RSO.
37
Device 1 (R=1,C=0) has transmitted configuration information at Array Output (RSO of Device 1).
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REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
(1)
(2)
(3)
(4/5)
(6)
DS90CP04TLQ
NRND
WQFN
WQFN
NJE
32
32
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
90CP04T
90CP04T
DS90CP04TLQ/NOPB
ACTIVE
NJE
RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CP04TLQ
WQFN
WQFN
NJE
NJE
32
32
250
250
178.0
178.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
DS90CP04TLQ/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CP04TLQ
WQFN
WQFN
NJE
NJE
32
32
250
250
208.0
208.0
191.0
191.0
35.0
35.0
DS90CP04TLQ/NOPB
Pack Materials-Page 2
MECHANICAL DATA
NJE0032A
LQA32A (REV A)
www.ti.com
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相关型号:
DS90CP04TLQX/NOPB
IC 4-CHANNEL, CROSS POINT SWITCH, PQCC32, 6 X 6 MM, PLASTIC, LLP-32, Multiplexer or Switch
NSC
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