DS90UB902QSQX/NOPB [TI]
具有双向控制通道的 10 - 43MHz 14 位色彩 FPD-Link III 解串器 | RTA | 40 | -40 to 105;
| 型号： | DS90UB902QSQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双向控制通道的 10 - 43MHz 14 位色彩 FPD-Link III 解串器 | RTA | 40 | -40 to 105 光电二极管 |
| 文件： | 总45页 (文件大小：1109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 25, 2012
DS90UB901Q/DS90UB902Q
10 - 43MHz 14 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Single differential pair interconnect
Bidirectional control interface channel with I2C support
■
■
■
General Description
The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link
III interface with a high-speed forward channel and a bidirec-
tional control channel for data transmission over a single
differential pair. The Serializer/Deserializer pair is targeted for
direct connections between automotive camera systems and
Host Controller/Electronic Control Unit (ECU). The primary
transport sends 16 bits of image data over a single high-speed
serial stream together with a low latency bidirectional control
channel transport that supports I2C. Included with the 16-bit
payload is a selectable data integrity option for CRC (Cyclic
Redundancy Check) to monitor transmission link errors. Us-
ing TI’s embedded clock technology allows transparent full-
duplex communication over a single differential pair, carrying
asymmetrical bidirectional control information without the de-
pendency of video blanking intervals. This single serial
stream simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems between
parallel data and clock paths. This significantly saves system
cost by narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
Embedded clock with DC Balanced coding to support AC-
coupled interconnects
Capable to drive up to 10 meters shielded twisted-pair
I2C compatible serial interface
■
■
■
■
Single hardware device addressing pin
16–bit data payload with CRC (Cyclic Redundancy Check)
for checking data integrity
Up to 6 Programmable GPIO's
■
■
LOCK output reporting pin and AT-SPEED BIST diagnosis
feature to validate link integrity
Integrated termination resistors
■
■
■
■
■
■
■
■
■
1.8V- or 3.3V-compatible parallel bus interface
Single power supply at 1.8V
ISO 10605 ESD and IEC 61000-4-2 ESD compliant
Automotive grade product: AEC-Q100 Grade 2 qualified
Temperature range −40°C to +105°C
No reference clock required on Deserializer
Programmable Receive Equalization
EMI/EMC Mitigation
In addition, the Deserializer inputs provide equalization con-
trol to compensate for loss from the media over longer dis-
tances. Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
DES Programmable Spread Spectrum (SSCG)
outputs
—
A Serializer standby function provides a low power-savings
mode with a remote wake up capability for signaling of a re-
mote device.
DES Receiver staggered outputs
—
Applications
The Serializer is offered in a 32-pin LLP (5mm x 5mm) pack-
age, and Deserializer is offered in a 40-pin LLP (6mm x 6mm)
package.
Automotive Vision Systems
■
■
■
■
Rear View, Side View Camera
Lane Departure Warning
Features
Parking Assistance
10 MHz to 43 MHz input PCLK support
■
■
Blind Spot View
■
160 Mbps to 688 Mbps data throughput
Typical Application Diagram
30113527
FIGURE 1. Typical Application Circuit
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301135 SNLS322D
www.ti.com
Block Diagrams
30113528
FIGURE 2. Block Diagram
30113529
FIGURE 3. Application Block Diagram
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2
Ordering Information
NSID
DS90UB901QSQE
Package Description
Quantity
250
SPEC
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
Package ID
SQA32A
SQA32A
SQA32A
SQA40A
SQA40A
SQA40A
32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch
32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch
32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch
40–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
40–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
40–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
DS90UB901QSQ
DS90UB901QSQX
DS90UB902QSQE
DS90UB902QSQ
DS90UB902QSQX
1000
2500
250
1000
2500
Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market,
including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades
defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to
http://www.ti.com/automotive.
DS90UB901Q Pin Diagram
30113519
Serializer - DS90UB901Q — Top View
3
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DS90UB901Q Serializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[13:0]
32, 31, 30, 29, Inputs, LVCMOS Parallel data inputs.
27, 26, 24, 23,
22, 21, 20, 19,
18, 17
w/ pull down
HSYNC
VSYNC
PCLK
1
2
3
Inputs, LVCMOS Horizontal SYNC Input
w/ pull down
Inputs, LVCMOS Vertical SYNC Input
w/ pull down
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
20, 19, 18, 17
Input/Output, DIN[3:0] general-purpose pins can be individually configured as either inputs or
LVCMOS outputs; used to control and respond to various commands.
Input/Output, General-purpose pins can be individually configured as either inputs or outputs;
LVCMOS used to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
GPIO[5:2]
GPIO[1:0]
16, 15
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO
Data line for the bidirectional control bus communication
Input/Output,
Open Drain
SCL
SDA
4
5
.
Input/Output,
Open Drain
SDA requires an external pull-up resistor to VDDIO
I2C Mode select
.
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Standby mode and is enabled through remote wakeup by Deserializer)
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C
controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Input, LVCMOS
w/ pull down
MODE
8
Device ID Address Select
ID[x]
6
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
w/ pull down
PDB
RES
9
7
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
FPD-LINK III INTERFACE
Input/Output, Non-inverting differential output, bidirectional control channel input. The
DOUT+
DOUT-
13
12
CML
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect
CML must be AC Coupled with a 100 nF capacitor.
interconnect must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL
VDDT
10
Power, Analog PLL Power, 1.8V ±5%
11
14
28
Power, Analog Tx Analog Power, 1.8V ±5%
Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
Power, Digital Digital Power, 1.8V ±5%
VDDCML
VDDD
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4
Pin Name
VDDIO
Pin No.
I/O, Type
Description
Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
25
Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 9 vias.
VSS
DAP
DS90UB902Q Pin Diagram
30113520
Deserializer - DS90UB902Q — Top View
5
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DS90UB902Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs,
LVCMOS
Parallel data outputs.
HSYNC
VSYNC
7
Output,
LVCMOS
Horizontal SYNC Output
Vertical SYNC Output
Pixel Clock Output Pin.
6
Output,
LVCMOS
Output,
LVCMOS
PCLK
5
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT OUTPUT (GPIO)
ROUT[3:0] /
GPIO[5:2]
Input/Output, ROUT[3:0] general-purpose pins can be individually configured as either inputs or
LVCMOS outputs; used to control and respond to various commands.
Input/Output, General-purpose pins can be individually configured as either inputs or outputs;
LVCMOS used to control and respond to various commands.
21, 22, 23, 24
GPIO[1:0]
26, 27
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO
Data line for bidirectional control bus communication
Input/Output,
Open Drain
SCL
SDA
3
2
.
Input/Output,
Open Drain
SDA requires an external pull-up resistor to VDDIO
I2C Mode select
.
MODE = L, Master mode; Device generates and drives the SCL clock line, where
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
MODE
40
w/ pull up
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to
an I2C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x]
1
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
Input, LVCMOS
w/ pull down
PDB
29
28
LOCK Status Output Pin.
LOCK = H, CDR/PLL is Locked, outputs are active
LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL
control register, the CDR/PLL is shutdown and IDD is minimized. May be used as
Link Status.
Output,
LVCMOS
LOCK
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the Link.
Output,
LVCOMS
PASS
RES
31
Reserved
Pin 39: This pin MUST be tied LOW.
32, 33, 39
-
Pins 32,33: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
BIST MODE
BIST Enable Pin.
Input, LVCMOS
w/ pull down
BISTEN
37
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
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6
Pin Name
Pin No.
I/O, Type
Description
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
Output,
LVCOMS
PASS
31
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
FPD-LINK III INTERFACE
Input/Output, Non-inverting differential input, bidirectional control channel output. The
CML interconnect must be AC Coupled with a 100 nF capacitor.
Input/Output, Inverting differential input, bidirectional control channel output. The interconnect
RIN+
RIN-
35
36
CML
must be AC Coupled with a 100 nF capacitor.
Non-inverting CML Output
CMLOUTP
CMLOUTN
32
33
Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
Inverting CML Output
Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
POWER AND GROUND
SSCG Power, 1.8V ±5%
Power, Digital
VDDSSCG
VDDIO1/2/3
4
Power supply must be connected regardless if SSCG function is in operation.
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
Power, Digital
25, 16, 8
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
13
30
34
38
Power, Digital Digital Core Power, 1.8V ±5%
Power, Analog Rx Analog Power, 1.8V ±5%
Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%
Power, Analog PLL Power, 1.8V ±5%
VDDR
VDDCML
VDDPLL
DAP must be grounded. DAP is the large metal contact at the bottom side, located
Ground, DAP at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
VSS
DAP
7
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Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (HBM)
ESD Rating (CDM)
ESD Rating (MM)
Absolute Maximum Ratings (Note 1)
≥±15 kV
≥±10 kV
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
≥±8 kV
≥±1 kV
≥±250 V
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDIO
−0.3V to +2.5V
−0.3V to +4.0V
LVCMOS Input Voltage I/O
Voltage
CML Driver I/O Voltage (VDD
−0.3V to + (VDDIO + 0.3V)
−0.3V to +(VDD + 0.3V)
For soldering specifications:
see product folder at www.ti.com
ꢀ
)
CML Receiver I/O Voltage
(VDD
)
−0.3V to (VDD + 0.3V)
+150°C
Junction Temperature
Storage Temperature
Maximum Package Power
Recommended Operating
Conditions
−65°C to +150°C
1/θJA °C/W above +25°
Dissipation Capacity Package
Min
Nom
Max
Units
Package Derating:
DS90UB901Q 32L LLP
Supply Voltage
(VDDn
LVCMOS Supply
1.71
1.8
1.89
V
)
34.3 °C/W
6.9 °C/W
1.71
3.0
1.8
3.3
1.89
3.6
V
V
ꢀθJA (based on 9 thermal vias)
ꢀθJC (based on 9 thermal vias)
DS90UB902Q 40L LLP
ꢀ
Voltage (VDDIO
)
OR
LVCMOS Supply
28.0 °C/W
4.4 °C/W
Voltage (VDDIO
Supply Noise
VDDn (1.8V)
)
θ
JA (based on 16 thermal vias)
ꢀ
25
25
50
mVp-p
mVp-p
mVp-p
θ
JC (based on 16 thermal vias)
VDDIO (1.8V)
VDDIO (3.3V)
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
≥±25 kV
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (ISO10605)
ESD Rating (ISO10605)
Operating Free Air
Temperature (TA)
-40
10
+25
+105
43
°C
≥±10 kV
PCLK Clock
Frequency
MHz
RD = 330Ω, CS = 150/330pF
RD = 2KΩ, CS = 150/330pF
Electrical Characteristics (Note 2, Note 3, Note 4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 3.0V to 3.6V
VIN = 3.0V to 3.6V
VIN
0.8
2.0
V
V
GND
VIN = 0V or 3.6V
-20
2.4
±1
+20
VDDIO
0.4
µA
V
VIN = 3.0V to 3.6V
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
VDDIO = 3.0V to 3.6V
IOH = -4 mA
VDDIO = 3.0V to 3.6V
IOL = +4 mA
GND
V
Output Short Circuit Current VOUT = 0V
Serializer
GPIO Outputs
-24
-39
±1
mA
µA
Deserializer
LVCMOS Outputs
PDB = 0V,
VOUT = 0V or VDD
IOZ
TRI-STATE® Output Current
LVCMOS Outputs
-20
+20
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VIN = 1.71V to 1.89V
VIN = 1.71V to 1.89V
0.65 VIN
GND
VIN +0.3
0.35 VIN
V
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8
Symbol
IIN
Parameter
Input Current
Conditions
VIN = 0V or 1.89V
Min
Typ
Max
Units
-20
±1
+20
µA
VIN = 1.71V to 1.89V
VOH
High Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −2 mA
Serializer
GPIO Outputs
VDDIO
0.45
-
VDDIO
V
V
VDDIO = 1.71V to 1.89V
IOH = −4 mA
Deserializer
LVCMOS Outputs
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOL = +2 mA
Serializer
GPIO Outputs
GND
0.45
VDDIO = 1.71V to 1.89V
IOL = +4 mA
Deserializer
LVCMOS Outputs
IOS
Output Short Circuit Current VOUT = 0V
Serializer
GPIO Outputs
-11
-20
±1
mA
µA
Deserializer
LVCMOS Outputs
IOZ
TRI-STATE® Output Current PDB = 0V,
LVCMOS Outputs
-20
+20
VOUT = 0V or VDD
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD
|
Output Differential Voltage
RT = 100Ω (Figure 7)
RL = 100Ω
268
340
1
412
50
mV
mV
Output Differential Voltage
Unbalance
ΔVOD
VOS
Output Differential Offset
Voltage
VDD (MIN)
-
VDD (MAX) -
RL = 100Ω (Figure 7)
VDD - VOD
V
VOD (MAX)
VOD (MIN)
Offset Voltage Unbalance
ΔVOS
IOS
RL = 100Ω
1
50
mV
mA
Output Short Circuit Current DOUT+/- = 0V,
-27
RT
Differential Internal
Termination Resistance
Differential across DOUT+ and DOUT-
80
100
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
Differential Threshold High
Voltage
(Figure 8)
VTH
VTL
+90
mV
Differential Threshold Low
Voltage
-90
180
-20
80
VIN
Differential Input Voltage
Range
RIN+ - RIN-
mV
µA
Ω
Input Current
VIN = VDD or 0V,
VDD = 1.89V
IIN
±1
+20
120
RT
Differential Internal
Termination Resistance
Differential across RIN+ and RIN-
100
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
Serializer (Tx)
VDDn = 1.89V
RT = 100Ω
VDDn Supply Current
(includes load current)
PCLK = 43 MHz
Default Registers
62
55
2
90
WORST CASE pattern
(Figure 5)
mA
mA
RT = 100Ω
RANDOM PRBS-7 pattern
IDDIOT
Serializer (Tx)
VDDIO Supply Current
(includes load current)
VDDIO = 1.89V
PCLK = 43 MHz
Default Registers
RT = 100Ω
WORST CASE pattern
(Figure 5)
5
VDDIO = 3.6V
PCLK = 43 MHz
Default Registers
7
15
9
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Symbol
IDDTZ
Parameter
Conditions
Min
Typ
370
55
Max
775
125
135
Units
Serializer (Tx) Supply Current PDB = 0V; All other
Power-down
VDDn = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
LVCMOS Inputs = 0V
IDDIOTZ
µA
65
IDDR
Deserializer (Rx) VDDn
Supply Current (includes load
current)
VDDn = 1.89V
CL = 8 pF
PCLK = 43 MHz
SSCG[3:0] = ON
Default Registers
60
53
16
38
96
WORST CASE Pattern
(Figure 5)
VDDn = 1.89V
PCLK = 43 MHz
Default Registers
CL = 8 pF
RANDOM PRBS-7 Pattern
mA
IDDIOR
Deserializer (Rx) VDDIO
Supply Current (includes load
current)
VDDIO = 1.89V
CL = 8 pF
PCLK = 43 MHz
Default Registers
25
64
WORST CASE Pattern
(Figure 5)
VDDIO = 3.6V
PCLK = 43 MHz
Default Registers
CL = 8 pF
WORST CASE Pattern
IDDRZ
Deserializer (Rx) Supply
Current Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
VDDn = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
42
8
400
40
IDDIORZ
µA
350
800
Recommended Serializer Timing for PCLK (Note 12)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Conditions
10 MHz – 43 MHz
Min
Typ
Max
Units
Transmit Clock Period
23.3
T
100
ns
tTCIH
tTCIL
tCLKT
fOSC
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
ns
Transmit Clock Input Low
Time
0.4T
0.5
0.5T
25
0.6T
3
ns
ns
PCLK Input Transition Time
(Figure 9)
Internal oscillator clock
source
MHz
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10
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLHT
Parameter
Conditions
RL = 100Ω (Figure 6)
Min
Typ
Max
Units
CML Low-to-High
Transition Time
150
330
ps
tHLT
CML High-to-Low
Transition Time
RL = 100Ω (Figure 6)
150
330
ps
tDIS
tDIH
tPLD
tSD
Data Input Setup to PCLK Serializer Data Inputs
2.0
2.0
ns
ns
(Figure 10)
Data Input Hold from PCLK
Serializer PLL Lock Time
Serializer Delay
RL = 100Ω (Note 5, Note 11)
1
2
ms
RT = 100Ω
6.386T
+ 5
6.386T
+ 12
6.386T
+ 19.7
PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
(Figure 12)
ns
UI
UI
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
PCLK = 43 MHz
(Note 4, Note 13)
0.13
0.04
tJINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz
(Note 4, Note 13)
tJINT
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
0.396
UI
PCLK = 43 MHz
(Note 4, Note 13)
Serializer Jitter Transfer
Function -3 dB Bandwidth Default Registers
PCLK = 43 MHz
λSTXBW
1.90
0.944
500
MHz
dB
(Figure 18) (Note 4)
Serializer Jitter Transfer
Function (Peaking)
PCLK = 43 MHz
Default Registers
(Figure 18 ) (Note 4)
δSTX
Serializer Jitter Transfer
Function (Peaking
Frequency)
PCLK = 43 MHz
Default Registers
(Figure 18) (Note 4)
δSTXf
kHz
11
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Receiver Output Clock Period
PCLK Duty Cycle
Conditions
tRCP = tTCP
Pin/Freq.
PCLK
PCLK
Min
Typ
Max
Units
23.3
T
100
ns
tPDC
Default Registers
SSCG[3:0] = OFF
45
50
55
%
LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or PCLK
tCLH
tCHL
1.3
2.0
2.8
Time
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 14) (Note 10)
ns
LVCMOS High-to-Low Transition
Time
1.3
1.6
2.0
2.4
2.8
3.3
3.3
LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or ROUT[13:0],
tCLH
tCHL
Time
HSYNC, VSYNC
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 14) (Note 10)
ns
LVCMOS High-to-Low Transition
Time
1.6
2.4
tROS
tROH
VDDIO: 1.71V to 1.89V or ROUT[13:0],
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
0.38T
0.5T
HSYNC, VSYNC
3.0V to 3.6V,
CL = 8 pF (lumped load)
Default Registers
(Figure 16)
ns
ns
0.38T
0.5T
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz–43 MHz
4.571T
+ 8
4.571T 4.571T
+ 12
tDD
Deserializer Delay
+ 16
(Figure 15)
tDDLT
tRJIT
(Figure 13) (Note 5)
10 MHz–43 MHz
43 MHz
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
10
ms
UI
(Figure 17, Figure 19)
(Note 13, Note 14)
0.53
300
120
425
320
320
300
tRCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
(Note 6, Note 10)
10 MHz
43 MHz
550
250
600
480
500
500
ps
ps
ps
tDPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF
(Note 7, Note 10)
10 MHz
43 MHz
tDCCJ
Deserializer Cycle-to-Cycle Clock PCLK
10 MHz
43 MHz
Jitter
SSCG[3:0] = OFF
(Note 8, Note 10)
fdev
Spread Spectrum Clocking
Deviation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 20)
20 MHz–43 MHz
20 MHz–43 MHz
±0.5% to
±2.0%
%
fmod
Spread Spectrum Clocking
Modulation Frequency
9 kHz to
66 kHz
kHz
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12
Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I2C
Compliant (Figure 4)
Over recommended supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECOMMENDED INPUT TIMING REQUIREMENTS (Note 12)
fSCL
SCL Clock Frequency
SCL Low Period
>0
4.7
4.0
100
kHz
µs
tLOW
tHIGH
fSCL = 100 kHz
SCL High Period
µs
Hold time for a start or a repeated start
condition
tHD:STA
tSU:STA
4.0
4.7
µs
µs
Set Up time for a start or a repeated
start condition
tHD:DAT
tSU:DAT
tSU:STO
tr
Data Hold Time
0
3.45
µs
ns
µs
ns
ns
pF
Data Set Up Time
250
4.0
Set Up Time for STOP Condition
SCL & SDA Rise Time
SCL & SDA Fall Time
Capacitive load for bus
1000
300
tf
Cb
400
SWITCHING CHARACTERISTICS (Note 11)
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
100
100
fSCL
SCL Clock Frequency
SCL Low Period
kHz
µs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
tLOW
4.7
4.0
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
tHIGH
SCL High Period
µs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Hold time for a start or a repeated start Serializer MODE = 0
tHD:STA
tSU:STA
4.0
4.7
µs
µs
condition
Register 0x05 = 0x40'h
Set Up time for a start or a repeated
start condition
Serializer MODE = 0
Register 0x05 = 0x40'h
tHD:DAT
tSU:DAT
tSU:STO
tf
Data Hold Time
0
3.45
300
µs
ns
µs
ns
Data Set Up Time
250
4.0
Serializer MODE = 0
Set Up Time for STOP Condition
SCL & SDA Fall Time
Bus free time between a stop and start Serializer MODE = 0
condition
tBUF
4.7
µs
Serializer MODE = 1
1
tTIMEOUT
NACK Time out
ms
Deserializer MODE = 1
Register 0x06 b[2:0]=111'b
25
13
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30113536
FIGURE 4. Bidirectional Control Bus Timing
Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Input High Level
Conditions
SDA and SCL
Min
Typ
Max
Units
VIH
VIL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
SDA and SCL
0.3 x
VDDIO
GND
V
VHY
IOZ
Input Hysteresis
SDA and SCL
>50
±1
mV
µA
TRI-STATE Output Current PDB = 0V
VOUT = 0V or VDD
SDA or SCL,
Vin = VDDIO or GND
-20
-20
+20
+20
IIN
Input Current
±1
<5
µA
pF
CIN
Input Pin Capacitance
VOL
Low Level Output Voltage SCL and SDA
VDDIO = 3.0V
0.36
0.36
V
V
IOL = 1.5 mA
SCL and SDA
VDDIO = 1.71V
IOL = 1 mA
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device
should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 5: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Note 6: tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
Note 7: tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
Note 8: tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 37, 38) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V)
supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows
no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.
Note 10: Specification is guaranteed by characterization and is not tested in production.
Note 11: Specification is guaranteed by design.
Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.
Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Note 14: tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
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14
AC Timing Diagrams and Test Circuits
30113552
FIGURE 5. “Worst Case” Test Pattern
30113546
30113547
FIGURE 6. Serializer CML Output Load and Transition Times
15
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30113548
30113530
FIGURE 7. Serializer VOD DC Diagram
30113534
FIGURE 8. Differential VTH/VTL Definition Diagram
30113516
FIGURE 9. Serializer Input Clock Transition Times
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16
30113549
FIGURE 10. Serializer Setup/Hold Times
30113532
FIGURE 11. Serializer Data Lock Time
30113550
FIGURE 12. Serializer Delay
30113513
FIGURE 13. Deserializer Data Lock Time
17
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30113514
FIGURE 14. Deserializer LVCMOS Output Load and Transition Times
30113511
FIGURE 15. Deserializer Delay
30113531
FIGURE 16. Deserializer Output Setup/Hold Times
30113558
FIGURE 17. Receiver Input Jitter Tolerance
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18
30113562
FIGURE 18. Typical Serializer Jitter Transfer Function Curve at 43 MHz
30113559
FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
30113535
FIGURE 20. Spread Spectrum Clock Output Profile
19
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TABLE 1. DS90UB901Q Control Registers
Addr
(Hex)
Name
Bits Field
R/W
Default Description
7-bit address of Serializer; 0x58'h
7:1 DEVICE ID
(1011_000X'b) default
I2C Device ID
0
RW
0xB0'h
0: Device ID is from ID[x]
0
SER ID SEL
1: Register I2C Device ID overrides ID[x]
7:3 RESERVED
0x00'h Reserved
Standby mode control. Retains control register data.
Supported only when MODE = 0
2
STANDBY
RW
0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1
2
Reset
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
DIGITAL
RESET0
0
1
0
RW
RW
self clear
0
1: Digital Reset, retains all register values
DIGITAL RESET1
self clear
Reserved
7:0 RESERVED
0x20'h Reserved
Back Channel CRC Enable
RX CRC
0: Disable
7
6
CHECKER
ENABLE
RW
1
1
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[6]
control register must be Enabled.
CRC Fault
Tolerant
Transmission
Foward Channel CRC Enable
0: Disable
1: Enable
For proper CRC operation, on Deserailizer 0x03h b[7]
control register must be Enabled.
TX CRC GEN
ENABLE
RW
RW
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO Mode
5
4
VDDIO CONTOL
VDDIO MODE
1
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through
0: Disabled
3
RW
RW
I2C Pass-
Through
I2C PASS-
THROUGH
3
2
1
0
1: Enabled
RESERVED
RESERVED
Reserved
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
PCLK_AUTO
1
PCLK_AUTO
RW
1
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
TRFB
0
TRFB
RW
RW
1
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
7:6 RESERVED
CRC RESET
10'b
0
Reserved
CRC
5
1: CRC Reset.
4
Transmission
Clears CRC Error counter.
4:0 RESERVED
00000'b Reserved
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20
Addr
(Hex)
Name
Bits Field
R/W
Default Description
I2C SCL frequency is determined by the following:
fSCL = 6.25 MHz / Register value (in decimal)
0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
I2C Bus Rate
I2C BUS RATE
5
7:0
RW
RW
0x40'h
0xC0'h Deserializer Device ID = 0x60'h
(1100_000X'b) default
7:1 DES DEV ID
6
7
DES ID
0
RESERVED
7:1 SLAVE DEV ID
RESERVED
Reserved
RW
0x00'h Slave Device ID. Sets remote slave I2C address.
Slave ID
0
Reserved
8
9
Reserved
Reserved
7:0 RESERVED
7:0 RESERVED
7:0 CRC ERROR B0
7:0 CRC ERROR B1
7:3 RESERVED
0x00'h Reserved
0x01'h Reserved
A
B
CRC Errors
CRC Errors
Reserved
R
R
0x00'h Number of CRC errors - 8 LSBs
0x00'h Number of CRC errors - 8 MSBs
0x00'h Reserved
1: Valid PCLK detected
0: Valid PCLK not detected
PCLK Detect
2
1
0
PCLK DETECT
DES ERROR
LINK DETECT
R
R
R
0
C
D
CRC Check
0
0
1: CRC error during communication with Deserializer
Cable Link
Detect Status
0: Cable link not detected
1: Cable link detected
7:4 RESERVED
3:2 RESERVED
0001'b Reserved
00'b
Reserved
0: Output
1: Input
GPIO[0] Config
GPIO[1] Config
GPIO[2] Config
GPIO[3] Config
GPIO[4] Config
1
0
GPIO0 DIR
GPIO0 EN
RW
RW
0
0: TRI-STATE
1: Enabled
1
7:4 RESERVED
3:2 RESERVED
0000'b Reserved
00'b
Reserved
0: Output
1: Input
E
1
0
GPIO1 DIR
GPIO1 EN
RW
RW
0
0: TRI-STATE
1: Enabled
1
7:4 RESERVED
3:2 RESERVED
0000'b Reserved
00'b
Reserved
0: Output
1: Input
F
1
0
GPIO2 DIR
GPIO2 EN
RW
RW
1
0: TRI-STATE
1: Enabled
1
7:4 RESERVED
3:2 RESERVED
0000'b Reserved
00'b
Reserved
0: Output
1: Input
10
11
1
0
GPIO3 DIR
GPIO3 EN
RW
RW
1
0: TRI-STATE
1: Enabled
1
7:4 RESERVED
3:2 RESERVED
0000'b Reserved
00'b
Reserved
0: Output
1: Input
1
0
GPIO4 DIR
GPIO4 EN
RW
RW
1
0: TRI-STATE
1: Enabled
1
21
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Addr
(Hex)
Name
Bits Field
R/W
Default Description
7:4 RESERVED
3:2 RESERVED
0000'b Reserved
00'b
Reserved
0: Output
1: Input
12
GPIO[5] Config
1
0
GPIO5 DIR
GPIO5 EN
RW
RW
1
0: TRI-STATE
1: Enabled
1
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
0: LOW
1: HIGH
General Purpose
Control Reg
13
7:0
RW
0x00'h
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22
TABLE 2. DS90UB902Q Control Registers
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
RW
0xC0'h 7-bit address of Deserializer;
0x60h
7:1 DEVICE ID
I2C Device ID
(1100_000X) default
0
0: Device ID is from ID[x]
0
DES ID SEL
1: Register I2C Device ID overrides ID[x]
0x00'h Reserved
Remote Wake-up Select
7:3 RESERVED
1: Enable
Generate remote wakeup signal automatically wake-up
the Serializer in Standby mode
0: Disable
Puts the Serializer (MODE = 0) in Standby mode when
Deserializer MODE = 1
2
REM_WAKEUP
RW
0
1
Reset
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
0
1
0
DIGITALRESET0
DIGITALRESET1
RW
RW
self clear
0
1: Digital Reset, retains all register values
self clear
RESERVED
Auto Clock
7:6 RESERVED
00'b
Reserved
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
5
AUTO_CLOCK
RW
RW
0
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
OSS Select
4
OSS_SEL
0
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
2
SSCG
3:0 SSCG
0000'b 0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
23
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Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
Back Channel CRC Enable
TX CRC
0: Disable
7
CHECKER
ENABLE
RW
1
1: Enable
For proper CRC operation, on Serailizer 0x03h b[6]
control register must be Enabled.
CRC Fault
Tolerant
Transmission
Foward Channel CRC Enable
0: Disable
1: Enable
For proper CRC operation, on Serailizer 0x03h b[7]
control register must be Enabled.
RX CRC GEN
ENABLE
6
RW
1
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO
CONTROL
VDDIO Control
VDDIO Mode
5
4
3
RW
RW
RW
1
0
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through Mode
0: Disabled
3
VDDIO MODE
I2C PASS-
THROUGH
I2C Pass-Through
1: Enabled
0: Disable
1: Enable
Auto ACK
2
1
AUTO ACK
RW
RW
0
0
CRC Reset
CRC RESET
1: CRC reset
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB
0
RRFB
RW
1
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
4
5
EQ Control
7:0 EQ
RW
0x00'h 07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
RESERVED
7:0 RESERVED
0x00'h Reserved
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24
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
RESERVED
7
RESERVED
0
Reserved
Prescales the SCL clock line when reading data byte
from a slave device (MODE = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
SCL Prescale
6:4 SCL_PRESCALE
RW
000'b
101 : ~11 kHz SCL
110 : ~33 kHz SCL
111 : ~50 kHz SCL
Other values are NOT supported.
Remote NACK Timer Enable
In slave mode (MODE = 1) if bit is set the I2C core will
REM_NACK_TIM
ER
automatically timeout when no acknowledge condition
was detected.
1: Enable
6
Remote NACK
3
RW
1
0: Disable
Remote NACK Timeout.
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
Remote NACK
2:0 NACK_TIMEOUT
RW
111'b
011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
RW
RW
0xB0'h Serializer Device ID = 0x58'h
(1011_000X'b) default
7:1 SER DEV ID
7
SER ID
0
RESERVED
7:1 ID[0] INDEX
RESERVED
7:1 ID[1] INDEX
RESERVED
7:1 ID[2] INDEX
RESERVED
7:1 ID[3] INDEX
RESERVED
7:1 ID[4] INDEX
RESERVED
7:1 ID[5] INDEX
RESERVED
7:1 ID[6] INDEX
RESERVED
7:1 ID[7] INDEX
RESERVED
7:1 ID[0] MATCH
RESERVED
7:1 ID[1] MATCH
RESERVED
7:1 ID[2] MATCH
RESERVED
7:1 ID[3] MATCH
RESERVED
Reserved
0x00'h Target slave Device ID slv_id0 [7:1]
Reserved
8
9
ID[0] Index
ID[1] Index
ID[2] Index
ID[3] Index
ID[4] Index
ID[5] Index
ID[6] Index
ID[7] Index
ID[0] Match
ID[1] Match
ID[2] Match
ID[3] Match
0
Target slave Device ID slv_id1 [7:1]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x00'h
0
Reserved
Target slave Device ID slv_id2 [7:1]
A
0x00'h
0
Reserved
Target slave Device ID slv_id3 [7:1]
B
0x00'h
0
Reserved
Target slave Device ID slv_id4 [7:1]
C
0x00'h
0
Reserved
Target slave Device ID slv_id5 [7:1]
D
0x00'h
0
Reserved
Target slave Device ID slv_id6 [7:1]
E
0x00'h
0
Reserved
Target slave Device ID slv_id7 [7:1]
F
0x00'h
0
Reserved
Alias to match Device ID slv_id0 [7:1]
10
11
12
13
0x00'h
0
Reserved
Alias to match Device ID slv_id1 [7:1]
0x00'h
0
Reserved
Alias to match Device ID slv_id2 [7:1]
0x00'h
0
Reserved
Alias to match Device ID slv_id3 [7:1]
0x00'h
0
Reserved
25
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Addr
(Hex)
Name
Bits
Field
R/W
RW
RW
RW
RW
Default
0x00'h
0x00'h
0x00'h
0x00'h
Description
7:1 ID[4] MATCH
RESERVED
7:1 ID[5] MATCH
RESERVED
7:1 ID[6] MATCH
RESERVED
7:1 ID[7] MATCH
RESERVED
Alias to match Device ID slv_id4 [7:1]
Reserved
14
15
16
17
ID[4] Match
ID[5] Match
ID[6] Match
ID[7] Match
0
Alias to match Device ID slv_id5 [7:1]
Reserved
0
Alias to match Device ID slv_id6 [7:1]
Reserved
0
Alias to match Device ID slv_id [7:1]
Reserved
0
18
19
1A
1B
RESERVED
RESERVED
CRC Errors
CRC Errors
RESERVED
7:0 RESERVED
0x00'h Reserved
7:0 RESERVED
0x01'h Reserved
7:0 CRC ERROR B0
7:0 CRC ERROR B1
7:3 RESERVED
R
R
0x00'h Number of CRC errors 8 LSBs
0x00'h Number of CRC errors 8 MSBs
0x00'h Reserved
CRC error during communication with Serializer on
Forward Channel
CRC Check
2
1
0
SER ERROR
R
R
R
0
1C
1D
1E
1F
20
Signal Detect
Status
0: Active signal not detected
1: Active signal detected
0
0: CDR/PLL Unlocked
1: CDR/PLL Locked
LOCK Pin Status
GPIO[0] Config
0
7:3 RESERVED
00010'b Reserved
1: Configured as GPIO
0: Configured as ROUT data (OSS_SEL controlled)
2
1
0
GPIO0 SET
GPIO0 DIR
GPIO0 EN
RW
RW
1
0: Output
1: Input
1
0: TRI-STATE
1: Enabled
1
7:3 RESERVED
0x00'h Reserved
1: Configured as GPIO
0: Configured as ROUT data (OSS_SEL controlled)
2
1
0
GPIO1 SET
GPIO1 DIR
GPIO1 EN
RW
RW
RW
1
GPIO[1] Config
GPIO[2] Config
GPIO[3] Config
0: Output
1: Input
1
0: TRI-STATE
1: Enabled
1
7:3 RESERVED
0x00'h Reserved
1: Configured as GPIO
0: Configured as ROUT0 data (OSS_SEL controlled)
2
1
0
GPIO2 SET
GPIO2 DIR
GPIO2 EN
RW
RW
RW
0
0: Output
1: Input
0
0: TRI-STATE
1: Enabled
1
7:3 RESERVED
0x00'h Reserved
1: Configured as GPIO
0: Configured as ROUT1 data (OSS_SEL controlled)
2
1
0
GPIO3 SET
GPIO3 DIR
GPIO3 EN
RW
RW
RW
0
0: Output
1: Input
0
0: TRI-STATE
1: Enabled
1
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Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
7:3 RESERVED
0x00'h Reserved
1: Configured as GPIO
0: Configured as ROUT2 data (OSS_SEL controlled)
2
1
0
GPIO4 SET
GPIO4 DIR
GPIO4 EN
RW
RW
RW
0
0
1
21
22
GPIO[4] Config
0: Output
1: Input
0: TRI-STATE
1: Enabled
7:3 RESERVED
0x00'h Reserved
1: Configured as GPIO
2
1
0
GPIO5 SET
GPIO5 DIR
GPIO5 EN
RW
RW
RW
0
0
1
0: Configured as ROUT3 data (OSS_SEL controlled)
GPIO[5] Config
0: Output
1: Input
0: TRI-STATE
1: Enabled
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
0: LOW
1: HIGH
General Purpose
Control Reg
23
7:0
RW
0x00'h
BIST Enable
24
25
BIST
0
BIST_EN
RW
R
0
0: Normal operation
1: Bist Enable
BIST_ERR
7:0 BIST_ERR
0x00'h Bist Error Counter
11: Enable remote wake mode
00'b
REM_WAKEUP_
EN
7:6
RW
00: Normal operation mode
Other values are NOT supported.
Remote Wake
Enable
26
27
3F
5:0 RESERVED
7:6 BCC
RW
RW
0
00'b
0
Reserved
11: Normal operation mode
Reserved
BCC
5:0 RESERVED
7:5 RESERVED
0
Reserved
CMLOUT P/N
Enable
1: Disabled (Default)
0: Enabled
CMLOUT Config
4
RW
1
0
3:0 RESERVED
Reserved
27
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The bidirectional control channel of the DS90UB901Q/902Q
provides bidirectional communication between the image
sensor and Electronic Control Unit (ECU) over the same dif-
ferential pair used for video data interface. This interface
offers advantages over other chipsets by eliminating the need
for additional wires for programming and control. The bidirec-
tional control channel bus is controlled via an I2C port. The
bidirectional control channel offers asymmetrical communi-
cation and is not dependent on video blanking intervals.
Functional Description
The DS90UB901Q/902Q FPD-Link III chipset is intended for
camera applications. The Serializer/ Deserializer chipset op-
erates from a 10 MHz to 43 MHz pixel clock frequency. The
DS90UB901Q transforms a 16-bit wide parallel LVCMOS da-
ta bus along with a bidirectional control bus into a single high-
speed differential pair. The high-speed serial bit stream
contains an embedded clock and DC-balance information
which enhances signal quality to support AC coupling. The
DS90UB902Q receives the single serial data stream and con-
verts it back into a 16-bit wide parallel data bus together with
the bidirectional control channel data bus.
SERIAL FRAME FORMAT
The DS90UB901Q/902Q chipset will transmit and receive a
pixel of data in the following format:
30113561
FIGURE 21. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol com-
posed of 16 bits of data containing camera data & control
information transmitted from Serializer to Deserializer. CLK1
and CLK0 represent the embedded clock in the serial stream.
CLK1 is always HIGH and CLK0 is always LOW. This data
payload is optimized for signal transmission over an AC cou-
pled link. Data is randomized, balanced and scrambled. The
data payload may be checked using a 4-bit CRC function. The
CRC monitors the link integrity of the serialized data and re-
ports when an error condition is detected.
the clock (SCL) and data (SDA) signals. Pull-up resistors or
current sources are required on the SCL and SDA busses to
pull them high when they are not being driven low. A logic zero
is transmitted by driving the output low. A logic high is trans-
mitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend
upon the total bus capacitance and operating speed. The
DS90UB901Q/902Q I2C bus data rate supports up to 100
kbps according to I2C specification.
To start any data transfer, the DS90UB901Q/902Q must be
configured in the proper I2C mode. Each device can function
as an I2C slave proxy or master proxy depending on the mode
determined by MODE pin. The Ser/Des interface acts as a
virtual bridge between Master controller (MCU) and the re-
mote device. When the MODE pin is set to High, the device
is treated as a slave proxy; acts as a slave on behalf of the
remote slave. When addressing a remote peripheral or Seri-
alizer/Deserializer (not wired directly to the MCU), the slave
proxy will forward any byte transactions sent by the Master
controller to the target device. When MODE pin is set to Low,
the device will function as a master proxy device; acts as a
master on behalf of the I2C master controller. Note that the
devices must have complementary settings for the MODE
configuration. For example, if the Serializer MODE pin is set
to High then the Deserializer MODE pin must be set to Low
and vice-versa.
The bidirectional control channel data is transferred along
with the high-speed forward data over the same serial link.
This architecture provides a full duplex low speed back chan-
nel across the serial link together with a high speed forward
channel without the dependence of the video blanking phase.
DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND
I2C MODES
The I2C compatible interface allows programming of the
DS90UB901Q, DS90UB902Q, or an external remote device
(such as a camera) through the bidirectional control channel.
Register
programming
transactions
to/from
the
DS90UB901Q/902Q chipset are employed through the clock
(SCL) and data (SDA) lines. These two signals have open-
drain I/Os and both lines must be pulled-up to VDDIO by
external resistor. Figure 4 shows the timing relationships of
30113560
FIGURE 22. Write Byte
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30113510
FIGURE 23. Read Byte
30113541
FIGURE 24. Basic Operation
30113542
FIGURE 25. START and STOP Conditions
SLAVE CLOCK STRETCHING
accesses, the “Response Delay” shown is on the order of 12
µs (typical). See Application Note AN-2173 / SNLA131 for
more details.
In order to communicate and synchronize with remote de-
vices on the I2C bus through the bidirectional control channel,
slave clock stretching must be supported by the I2C master
controller/MCU. The chipset utilizes bus clock stretching
(holding the SCL line low) during data transmission; where
the I2C slave pulls the SCL line low prior to the 9th clock of
every I2C data transfer (before the ACK signal). The slave
device will not control the clock and only stretches it until the
remote peripheral has responded.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave
address of the Serializer/Deserializer (I2C only) to allow up to
six devices on the bus using only a single pin. The pin sets
one of six possible addresses for each Serializer/Deserializer
device. The pin must be pulled to VDD (1.8V, NOT VDDIO))
with a 10 kΩ resistor and a pull down resistor (RID) of the
recommended value to set the physical device address. The
recommended maximum resistor tolerance is 0.1% worst
case (0.2% total tolerance).
Any remote access involves the clock stretching period fol-
lowing the transmitted byte, prior to completion of the ac-
knowledge bit. Since each byte transferred to the I2C slave
must be acknowledged separately, the clock stretching will be
done for each byte sent by the host controller. For remote
29
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30113543
FIGURE 26. Bidirectional Control Bus Connection
TABLE 3. ID[x] Resistor Value – DS90UB901Q
ID[x] Resistor Value - DS90UB901Q Ser
CAMERA MODE OPERATION
In Camera mode, I2C transactions originate from the Master
controller at the Deserializer side (Figure 27). The I2C slave
core in the Deserializer will detect if a transaction is intended
for the Serializer or a slave at the Serializer. Commands are
sent over the bidirectional control channel to initiate the trans-
actions. The Serializer will receive the command and gener-
ate an I2C transaction on its local I2C bus. At the same time,
the Serializer will capture the response on the I2C bus and
return the response on the forward channel link. The Deseri-
alizer parses the response and passes the appropriate re-
sponse to the Deserializer I2C bus.
Resistor
RID Ω
Address 7'b
(Note 11)
Address 8'b 0
appended (WRITE)
(±0.1%)
0
7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0)
GND
2.0k
4.7k
7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2)
7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4)
7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6)
7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8)
7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC)
8.2k
To configure the devices for camera mode operation, set the
Serializer MODE pin to Low and the Deserializer MODE pin
to High. Before initiating any I2C commands, the Deserializer
needs to be programmed with the target slave device ad-
dresses and Serializer device address. SER_DEV_ID Regis-
ter 0x07h sets the Serializer device address and
12.1k
39.0k
TABLE 4. ID[x] Resistor Value – DS90UB902Q
ID[x] Resistor Value - DS90UB902Q Des
SLAVE_x_MATCH/SLAVE_x_INDEX
registers
Resistor
RID Ω
(±0.1%)
0
GND
Address 7'b
(Note 11)
Address 8'b 0
appended (WRITE)
0x08h~0x17h set the remote target slave addresses. In slave
mode the address register is compared with the address byte
sent by the I2C master. If the addresses are equal to any of
registers values, the I2C slave will acknowledge and hold the
bus to propagate the transaction to the target device other-
wise it returns no acknowledge.
7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0)
2.0k
4.7k
7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2)
7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4)
7b' 110 0011 (h'63) 8b' 1101 0110 (h'C6)
7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8)
7b' 110 0110 (h'66) 8b' 1100 1100 (h'CC)
8.2k
12.1k
39.0k
30113540
FIGURE 27. Typical Camera System Diagram
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DISPLAY MODE OPERATION
data transmission error checking. The error detection oper-
ating modes support data validation of the following signals:
In Display mode, I2C transactions originate from the controller
attached to the Serializer. The I2C slave core in the Serializer
will detect if a transaction targets (local) registers within the
Serialier or the (remote) registers within the Deserializer or a
remote slave connected to the I2C master interface of the De-
serializer. Commands are sent over the forward channel link
to initiate the transactions. The Deserializer will receive the
command and generate an I2C transaction on its local I2C
bus. At the same time, the Deserializer will capture the re-
sponse on the I2C bus and return the response as a command
on the bidirectional control channel. The Serializer parses the
response and passes the appropriate response to the Serial-
izer I2C bus.
•
•
•
Bidirectional Channel Control
Control VSYNC and HSYNC signals across serial link
Parallel video/pixel data across serial link
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the
DS90UB901Q Serializer and DS90UB902Q Deserializer. It
must be used to access and program the extra features em-
bedded within the configuration registers. Refer to Table 1
and Table 2 for details of control registers.
MULTIPLE DEVICE ADDRESSING
The physical device ID of the I2C slave in the Serializer is
determined by the analog voltage on the ID[x] input. It can be
reprogrammed by using the DEVICE_ID register and setting
the bit . The device ID of the logical I2C slave in the Deseri-
alizer is determined by programming the DES ID in the Seri-
alizer. The state of the ID[x] input on the Deserializer is used
to set the device ID. The I2C transactions between Ser/Des
will be bridged between the host controller to the remote
slave.
Some applications require multiple camera devices with the
same fixed address to be accessed on the same I2C bus. The
DS90UB901/902 provides slave ID matching/aliasing to gen-
erate different target slave addresses when connecting more
than two identical devices together on the same bus. This al-
lows the slave devices to be independently addressed. Each
device connected to the bus is addressable through a unique
ID by programming of the SLAVE_ID_MATCH register on
Deserializer. This will remap the SLAVE_ID_MATCH address
to the target SLAVE_ID_INDEX address; up to 8 ID indexes
are supported. The ECU Controller must keep track of the list
of I2C peripherals in order to properly address the target de-
vice. In a camera application, the microcontroller is located
on the Deserializer side. In this case, the microcontroller pro-
grams the slave address matching registers and handles all
data transfers to and from all slave I2C devices. This is useful
in the event where camera modules are removed or replaced.
To configure the devices for display mode operation, set the
Serializer MODE pin to High and the Deserializer MODE pin
to Low. Before initiating any I2C commands, the Serializer
needs to be programmed with the target slave device address
and Serializer device address. DES_DEV_ID Register 0x06h
sets the Deserializer device address and SLAVE_DEV_ID
register 0x7h sets the remote target slave address. If the I2C
slave address matches any of registers values, the I2C slave
will hold the transaction allowing read or write to target device.
Note: In Display mode operation, registers 0x08h~0x17h on
Deserializer must be reset to 0x00.
For example in the configuration shown in Figure 28:
•
•
ECU is the I2C master and has an I2C master interface
The I2C interfaces in DES A and DES B are both slave
interfaces
CRC (CYCLIC REDUNDANCY CHECK) DETECTION
•
•
The I2C protocol is bridged from DES A to SER A and from
DES B to SER B
The I2C interfaces in SER A and SER B are both master
A 4-bit CRC per symbol is reserved for checking the link in-
tegrity during transmission. The reporting status pin (PASS)
is provided on the Deserializer side, which flags any mismatch
of data transmitted to and from the remote device. The
Deserializer's PLL must first be locked (LOCK pin HIGH) to
ensure the PASS status is valid. This error detection handling
generates an interrupt signal onto the PASS output pin; noti-
fying the host controller as soon as any errors are identified.
When an error occurs, the PASS asserts LOW. CRC registers
(CRC ERROR B0/B1) are also available for managing the
data error count.
interfaces
If master controller transmits I2C slave 0xA0, the DES A ad-
dress 0xC0 will forward the transaction to remote Camera A.
If the controller transmits slave address 0xA4, the DES B
0xC2 will recognize that 0xA4 is mapped to 0xA0 and will be
transmitted to the remote Camera B. If controller sends com-
mand to address 0xA6, the DES B 0xC2 will forward trans-
action to slave device 0xA2.
The Slave ID index/match is supported only in the camera
mode (SER: MODE pin = L; DES: MODE pin = H). For Multiple
device addressing in display mode (SER: MODE pin = H;
DES: MODE pin = L), use the I2C pass through function.
The DS90UB901Q/902Q chipset provides several mecha-
nisms (operations) for ensuring data integrity in long distance
transmission and reception. The data error detection function
offers user flexibility and usability of performing bit-by-bit and
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30113533
FIGURE 28. Multiple Device Addressing
I2C PASS THROUGH
communication to only specific devices on the remote bus.
The feature is effective for both Camera mode and Display
mode.
I2C pass-through provides an alternative means to indepen-
dently address slave devices. The mode enables or disables
I2C bidirectional control channel communication to the remote
I2C bus. This option is used to determine whether or not an
I2C instruction is to be transferred over to the remote I2C de-
vice. When enabled, the I2C bus traffic will continue to pass
through and will be received by I2C devices downstream. If
disabled, I2C commands will be blocked to the remote I2C
device. The pass through function also provides access and
For example in the configuration shown in Figure 29:
If master controller transmits I2C transaction for address
0xA0, the SER A with I2C pass through enabled will transfer
I2C commands to remote Camera A. The SER B with I2C pass
through disabled, any I2C commands will be bypassed on the
I2C bus to Camera B.
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30113504
FIGURE 29. I2C Pass Through
SYNCHRONIZING MULTIPLE CAMERAS
tional control channel, there will be a time variation of the
GPIO signals arriving at the different target devices (between
the parallel links). The maximum latency delta (t1) of the GPIO
data transmitted across multiple links is 25 us.
For applications requiring multiple cameras for frame-syn-
chronization, it is recommended to utilize the General Pur-
pose Input/Output (GPIO) pins to transmit control signals to
synchronize multiple cameras together. To synchronize the
cameras properly, the system controller needs to provide a
field sync output (such as a vertical or frame sync signal) and
the cameras must be set to accept an auxiliary sync input.
The vertical synchronize signal corresponds to the start and
end of a frame and the start and end of a field. Note this form
of synchronization timing relationship has a non-deterministic
latency. After the control data is reconstructed from the birec-
Note: The user must verify that the timing variations between
the different links are within their system and timing specifi-
cations.
For example in the configuration shown in (Figure 30):
The maximum time (t1) between the rising edge of GPIO (i.e.
sync signal) arriving at Camera A and Camera B is 25 us.
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30113553
FIGURE 30. Synchronizing Multiple Cameras
30113554
FIGURE 31. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
AT-SPEED BIST (BISTEN, PASS)
The DS90UB901Q/902Q has up to 6 GPIO (2 dedicated and
4 programmable). GPIO[0] and GPIO[1] are always available
and GPIO[2:5] are available depending on the parallel data
bus size. DIN/ROUT[0:3] can be programmed into GPIOs
(GPIO[2:5]) when the parallel data bus is less than 12 bits
wide (10-bit data + HS,VS). Each GPIO can be configured as
either an input or output port. The GPIO maximum switching
rate is up to 66 kHz when configured for communication be-
tween Deserializer GPI to Serializer GPO. Whereas data flow
configured for communication between Serializer GPI to De-
serializer GPO is limited by the maximum data rate of the
PCLK.
An optional AT SPEED Built in Self Test (BIST) feature sup-
ports at speed testing of the high-speed serial and the bidi-
rectional control channel link. Control pins at the Deserializer
are used to enable the BIST test mode and allow the system
to initiate the test and set the duration. A HIGH on PASS pin
indicates that all payloads received during the test were error
free during the BIST duration test. A LOW on this pin at the
conclusion of the test indicates that one or more payloads
were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST
starts when Deserializer LOCK goes HIGH and BISTEN is set
HIGH. BIST ends when BISTEN goes LOW. Any errors de-
tected after the BIST Duration are not included in PASS logic.
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34
Note: AT-SPEED BIST is only available in the Camera mode
and not the Display mode
The following diagram shows how to perform system AT
SPEED BIST:
30113545
FIGURE 32. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
Deserializer will communicate through the bidirectional con-
trol channel to configure Serializer into BIST mode. Once the
BIST mode is set, the Serializer will initiate BIST transmission
to the Deserializer.
Serializer and Deserializer power supply must be supplied.
Enable the AT SPEED BIST mode on the Deserializer by set-
ting the BISTEN pin High. The 902 GPIO[1:0] pins are used
to select the PCLK frequency of the on-chip oscillator for the
BIST test on high speed data path.
Wait 10 ms for Deserializer to acquire lock and then monitor
the LOCK pin transition from LOW to HIGH. At this point, AT
SPEED BIST is operational and the BIST process has begun.
The Serializer will start transfer of an internally generated
PRBS data pattern through the high speed serial link. This
pattern traverses across the interconnecting link to the De-
serializer. Check the status of the PASS pin; a HIGH indicates
a pass, a LOW indicates a fail. A fail will stay LOW for ½ a
clock cycle. If two or more bits in the serial frame fail, the
PASS pin will toggle ½ clock cycle HIGH and ½ clock cycle
low. The user can use the PASS pin to count the number of
fails on the high speed link. In addition, there is a defined SER
and DES register that will keep track of the accumulated error
count. The Serializer 901 GPIO[0] pin will be assigned as a
PASS flag error indicator for the bidirectional control channel
link.
TABLE 5. BIST Oscillator Frequency Select
Des GPIO
[1:0]
Oscillator
Source
min
typ
max
(MHz) (MHz) (MHz )
00
01
10
11
External PCLK
Internal
10
43
50
25
Internal
Internal
12.5
The Deserializer GPIO[1:0] set to 00 will bypass the on-chip
oscillator and an external oscillator to Serializer PCLK input
is required. This allows the user to operate BIST under dif-
ferent frequencies other than the predefined ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into
BIST mode.
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30113564
FIGURE 33. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the
Deserializer to determine Pass/Fail.
TEN width and Deserializer LOCK is HIGH; thus the Bit Error
Rate is determined by how long the system holds BISTEN
HIGH.
To end BIST, the system must pull BISTEN pin of the Dese-
rializer LOW. The BIST duration is fully defined by the BIS-
30113505
FIGURE 34. BIST BER Calculation
For instance, if BISTEN is held HIGH for 1 second and the
PCLK is running at 43 MHz with 16 bpp, then the Bit Error
Rate is no better than 1.46E-9.
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user seletable
to provide compatibility with 1.8V and 3.3V system interfaces.
Step 4: Place system in Normal Operating Mode by disabling
BIST at the Serializer.
REMOTE WAKE UP (Camera Mode)
After initial power up, the Serializer is in a low-power Standby
mode. The Deserializer (controlled by ECU/MCU) 'Remote
Wake-up' register allows the Deserializer side to generate a
signal across the link to remotely wake-up the Serializer.
Once the Serializer detects the wake-up signal Serializer
switches from Standby mode to active mode. In active mode,
the Serializer locks onto PCLK input (if present), otherwise
the on-chip oscillator is used as the input clock source. Note
the MCU controller should monitor the Deserializer LOCK pin
and confirm LOCK = H before performing any I2C communi-
cation across the link.
Once Step 3 is complete, AT SPEED BIST is over and the
Deserializer is out of BIST mode. To fully return to Normal
mode, apply Normal input data into the Serializer.
Any PASS result will remain unless it is changed by a new
BIST session or cleared by asserting and releasing PDB. The
default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine
if there is an issue on the link that is not related to the clock
and data recovery of the link (whose status is flagged with
LOCK pin).
For Remote Wake-up to function properly:
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36
•
The chipset needs to be configured in Camera mode:
Serializer MODE = 0 and Deserializer MODE = 1
Serializer expects remote wake-up by default at power on.
Configure the control channel driver of the Deserializer to
be in remote wake-up mode by setting Deserializer
Register 0x26h = 0xC0h.
ization is controlled via register setting. Note this function can
be observed at the CMLOUTP/N test port enabled via the
control registers.
•
•
EMI REDUCTION
Des - Receiver Staggered Output
•
•
Perform remote wake-up on Serializer by setting
Deserializer Register 0x01 b[2] = 1
Return the control channel driver of the Deserializer to the
normal operation mode by setting Deserializer Register
0x26h = 0x00h
Configure the control channel driver of the Deserializer to
be in normal operation mode by setting Deserializer
Register 0x27h = 0xC0h.
The Receiver staggered outputs allows for outputs to switch
in a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes
the number of outputs switching simultaneously and helps to
reduce supply noise. In addition it spreads the noise spectrum
out reducing overall EMI.
•
Des Spread Spectrum Clocking
The DS90UB902Q parallel data and clock outputs have pro-
grammable SSCG ranges from 9 kHz–66 kHz and ±0.5%–
±2% from 20 MHz to 43 MHz. The modulation rate and mod-
ulation frequency variation of output spread is controlled
through the SSC control registers.
Serializer can also be put into standby mode by programming
the Deserializer remote wake-up control register 0x01 b[2]
REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the
device. The modes can be controlled by the host and is used
to disable the Link to save power when the remote device is
not operational. An auto mode is also available. In this mode,
the PDB pin is tied High and the SER switches over to an
internal oscillator when the PCLK stops or not present. When
a PCLK starts again, the SER will then lock to the valid input
PCLK and transmits the data to the DES. In powerdown
mode, the high-speed driver outputs are static (High).
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is
used. For the SER, this register determines the edge that the
data is latched on. If TRFB register is 1, data is latched on the
Rising edge of the PCLK. If TRFB register is 0, data is latched
on the Falling edge of the PCLK. For the DES, this register
determines the edge that the data is strobed on. If RRFB reg-
ister is 1, data is strobed on the Rising edge of the PCLK. If
RRFB register is 0, data is strobed on the Falling edge of the
PCLK.
The DES has a PDB input pin to ENABLE or Powerdown the
device. This pin can be controlled by the system and is used
to disable the DES to save power. An auto mode is also avail-
able. In this mode, the PDB pin is tied High and the DES will
enter powerdown when the serial stream stops. When the
serial stream starts up again, the DES will lock to the input
stream and assert the LOCK pin and output valid data. In
powerdown mode, the Data and PCLK outputs are set by the
OSS_SEL control register.
30113551
POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after
VDD (VDDn and VDDIO) power supplies have settled to the
recommended operating voltages. A external RC network can
be connected to the PDB pin to ensure PDB arrives after all
the VDD have stabilized.
FIGURE 35. Programmable PCLK Strobe Select
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order
to compensate for loss from the media. The level of equal-
37
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nal AC coupling capacitors must be placed in series in the
FPD-Link III signal path as illustrated in Figure 36.
Applications Information
AC COUPLING
The SER/DES supports only AC-coupled interconnects
through an integrated DC balanced decoding scheme. Exter-
30113538
FIGURE 36. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest avail-
able package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
package parasitics. The I/O’s require a 100 nF AC coupling
capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 37 shows a typical connection of the DS90UB901Q
Serializer.
30113555
FIGURE 37. DS90UB901Q Typical Connection Diagram — Pin Control
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38
Figure 38 shows a typical connection of the DS90UB902Q
Deserializer.
30113556
FIGURE 38. DS90UB902Q Typical Connection Diagram — Pin Control
39
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TRANSMISSION MEDIA
the electrical environment (e.g. power stability, ground noise,
input clock jitter, PCLK frequency, etc.) and the application
environment.
The Ser/Des chipset is intended to be used over a wide variety
of balanced cables depending on distance and signal quality
requirements. The Ser/Des employ internal termination pro-
viding a clean signaling environment. The interconnect for
FPD-Link III interface should present a differential impedance
of 100 Ohms. Use of cables and connectors that have
matched differential impedance will minimize impedance dis-
continuities. Shielded or un-shielded cables may be used
depending upon the noise environment and application re-
quirements. The chipset's optimum cable drive performance
is achieved at 43 MHz at 10 meters length. The maximum
signaling rate increases as the cable length decreases.
Therefore, the chipset supports 50 MHz at shorter distances.
Other cable parameters that may limit the cable's perfor-
mance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew. The maximum length of cable that can
be used is dependant on the quality of the cable (gauge,
impedance), connector, board (discontinuities, power plane),
The resulting signal quality at the receiving end of the trans-
mission media may be assessed by monitoring the differential
eye opening of the CMLOUT P/N output. A differential probe
should be used to measure across the termination resistor at
the CMLOUT P/N pins.
For obtaining optimal performance, we recommend:
•
•
Use Shielded Twisted Pair (STP) cable
100Ω differential impedance and 24 AWG (or lower AWG)
cable
•
•
Low skew, impedance matched
Ground and/or terminate unused conductors
Figure 39 shows the Typical Performance Characteristics
demonstrating various lengths and data rates using Rosen-
berger HSD and Leoni DACAR 538 Cable.
30113557
*Note: Equalization is enabled for cable lengths greater than 7 meters
FIGURE 39. Rosenberger HSD & Leoni DACAR 538 Cable Performance
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
Circuit board layout and stack-up for the Ser/Des devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power for different portions
of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on
the PCB are typically not required. Pin Description tables typ-
ically provide guidance on which circuit blocks are connected
to which power pin pairs. In some cases, an external filter
many be used to provide clean power to sensitive circuits
such as PLLs.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the differential lines to
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40
prevent coupling from the LVCMOS lines to the differential
lines. Closely-coupled differential lines of 100 Ohms are typ-
ically recommended for differential interconnect. The closely
coupled lines help to ensure that coupled noise will appear as
common-mode and thus is rejected by the receivers. The
tightly coupled lines will also radiate less.
•
Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
Minimize the number of Vias
Use differential connectors when operating above
500Mbps line speed
•
•
Information on the LLP style package is provided in Applica-
tion Note: AN-1187 / SNOA401Q.
•
•
Maintain balance of the traces
Minimize skew within the pair
INTERCONNECT GUIDELINES
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the Texas In-
struments web site at: www.ti.com/lvds
See Application Notes AN-1108 / SNLA008 and AN-905 /
SNLA035 for full details.
•
Use 100Ω coupled differential pairs
41
www.ti.com
Revision History
04/17/2012
•
•
•
•
•
•
•
•
•
•
•
•
•
Added CMLOUT P/N to Deserializer Pin Descriptions
Added CMLOUT P/N to Deserializer Pin Diagram
Added ESD CDM and ESD MM values
Added 3.3V I/O VOH conditions: IOH = -4 mA
Corrected 3.3V I/O VOL conditions: IOL = +4 mA
Changed NSID DS90UB901/902QSQX to qty 2500
Added “Only used when VDDIOCONTROL = 0” note for Deserializer Register 0x03 bit[4] description
Added Register 0x27 BCC in Deserializer Register table
Added Register 0x3F CML Output in Deserializer Register table
Updated SLAVE CLOCK STRETCHING in Functional Description section
Updated REMOTE WAKE UP (Camera Mode) procedure in Functional Description section
Updated Des - Receiver Input Equalization (EQ) in Functional Description section
Updated TRANSMISSION MEDIA in Applications Information section
www.ti.com
42
Physical Dimensions inches (millimeters) unless otherwise noted
DS90UB901Q Serializer
Package Number SQA32A
DS90UB902Q Deserializer
Package Number SQA40A
43
www.ti.com
Notes
www.ti.com
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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