首页 > DS90UB925Q

DS90UB925Q

更新时间：2024-09-18 12:48:44

品牌：TI

描述：5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

PDF下载

中文翻译

PCB计价

概述
数据手册

如果您发现信息不准确，欢迎纠错

DS90UB925Q 概述

5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel 5 - 85 MHz的24位彩色FPD -Link的III串行器具有双向控制通道

DS90UB925Q 数据手册

通过下载DS90UB925Q数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载

DS90UB925Q

5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control

Channel

General Description

Features

The DS90UB925Q serializer, in conjunction with the

DS90UB926Q deserializer, provides a complete digital inter-

face for concurrent transmission of high-speed video, audio,

and control data for automotive display and image sensing

applications.

Bidirectional control interface channel interface with I2C

●

compatible serial control bus

Supports high definition (720p) digital video format

●

RGB888 + VS, HS, DE and I2S audio supported

Supports two 10–bit camera video streams

The chipset is ideally suited for automotive video-display sys-

tems with HD formats and automotive vision systems with

megapixel resolutions. The DS90UB925Q incorporates an

embedded bidirectional control channel and low latency GPIO

controls. This chipset translates a parallel interface into a sin-

gle pair high-speed serialized interface. The serial bus

scheme, FPD-Link III, supports full duplex of high-speed video

data transmission and bidirectional control communication

over a single differential link. Consolidation of video data and

control over a single differential pair reduces the interconnect

size and weight, while also eliminating skew issues and sim-

plifying system design.

5 – 85MHz PCLK supported

Single 3.3V Operation with 1.8V or 3.3V compatible

LVCMOS I/O interface

●

AC-coupled STP Interconnect up to 10 meters

●

Parallel LVCMOS video inputs

DC-balanced & scrambled Data w/ Embedded Clock

Supports repeater application

Internal pattern generation

Low power modes minimize power dissipation

Automotive grade product: AEC-Q100 Grade 2 qualified

The DS90UB925Q serializer embeds the clock, DC scram-

bles & balances the data payload, and level shifts the signals

to high-speed low voltage differential signaling. Up to 24 data

bits are serialized along the video control signals.

>8kV HBM and ISO 10605 ESD rating

Backward compatible to FPD-Link II

●

Applications

Serial transmission is optimized by a user selectable de-em-

phasis. EMI is minimized by the use of low voltage differential

signaling, data scrambling and randomization and spread

spectrum clocking compatibility.

Automotive Display for Navigation

●

Rear Seat Entertainment Systems

Automotive Driver Assistance

Automotive Megapixel Camera Systems

Typical Display Applications Diagram

30143327

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of

publication date. Products conform to specifications per

the terms of the Texas Instruments standard warranty.

Production processing does not necessarily include

testing of all parameters.

301433 SNLS407A

DS90UB925Q

Typical Camera Applications Diagram

30143326

DS90UB925Q Pin Diagram

30143319

DS90UB925Q — Top View

DS90UB925Q

Pin Descriptions

Pin Name

Pin #

I/O, Type Description

LVCMOS Parallel Interface

DIN[23:0] / R 25, 26, 27, 28, I, LVCMOS Parallel Interface Data Input Pins

[7:0], G[7:0], 29, 32, 33, 34, w/ pull down Leave open if unused

B[7:0]

35, 36, 37, 38,

39, 40, 41, 42,

43, 44, 45, 46,

47, 48, 1, 2

DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1

DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3

DIN16 / B0 can optionally be used as GPIO4 and DIN17 / B1 can optionally be used as

GPIO5

I, LVCMOS Horizontal Sync Input Pin

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse

when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130

PCLKs.

See Table 6

I, LVCMOS Vertical Sync Input Pin

w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width

is 130 PCLKs.

I, LVCMOS Data Enable Input Pin

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse

when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130

PCLKs.

See Table 6

PCLK

I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. SeeTable 6

w/ pull down

I2S_CLK,

I2S_WC,

I2S_DA

13, 12, 11

I, LVCMOS Digital Audio Interface Data Input Pins

w/ pull down Leave open if unused

I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as

GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.

Optional Parallel Interface

I2S_DB

I, LVCMOS

Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by

w/ pull down MODE_SEL pin or configuration register

Leave open if unused

I2S_DB can optionally be used as DIN17 or GPO_REG5.

GPIO[3:0]

36, 35, 26, 25 I/O,

LVCMOS

General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or

configuration register. SeeTable 6

w/ pull down Leave open if unused

Shared with DIN9, DIN8, DIN1 and DIN0

GPO_REG 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6

[8:4]

w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or DIN17, DIN16.

Optional Parallel Interface

PDB

I, LVCMOS Power-down Mode Input Pin

w/ pull-down PDB = H, device is enabled (normal operation)

Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL

is shutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL

IDx

I, Analog

Device Configuration Select. See Table 1

I2C Serial Control Bus Device ID Address Select

External pull-up to V_DD33is required under all conditions, DO NOT FLOAT.

Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure

DS90UB925Q

Pin Name

Pin #

I/O, Type Description

SCL

I/O,

I2C Clock Input / Output Interface

LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.

Open Drain

Recommended pull-up: 4.7kΩ.

SDA

I/O,

I2C Data Input / Output Interface

LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.

Open Drain

Recommended pull-up: 4.7kΩ.

Status

INTB

O, LVCMOS Interrupt

Open Drain INTB = H, normal

INTB = L, Interrupt request

Recommended pull-up: 4.7kΩ to V_DDIO

FPD-Link III Serial Interface

DOUT+

DOUT-

CMF

O, LVDS

Analog

True Output

The output must be AC-coupled with a 0.1µF capacitor.

Inverting Output

The output must be AC-coupled with a 0.1µF capacitor.

Common Mode Filter.

Connect 0.1µF to GND

Power and Ground

V_DD33

V_DDIO

Power

Ground

Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND

LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND

GND

DAP

DAP is the large metal contact at the bottom side, located at the center of the LLP

package. Connect to the ground plane (GND) with at least 9 vias.

Regulator Capacitor

CAPHS12,

CAPP12

17, 14

CAP

Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each

CAP pin.

CAPL12

Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this

CAP pin.

Others

Do not connect.

RES[1:0]

18, 15

GND

Reserved. Tie to Ground.

The VDD (V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

DS90UB925Q

Block Diagram

30143328

Ordering Information

QUANTITY

SPEC

NOPB

PACKAGE ID

SQA48A

ꢀPART NUMBER

DS90UB925QSQE

DS90UB925QSQ

DS90UB925QSQX

ꢀPACKAGE DESCRIPTION

48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch

250

1000

2500

SQA48A

Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market,

including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades

defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to

http://www.ti.com/automotive.

DS90UB925Q

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for

availability and specifications.

Supply Voltage – V_DD33

Supply Voltage – V_DDIO

LVCMOS I/O Voltage

−0.3V to +4.0V

−0.3V to (V_DDIO+ 0.3V)

−0.3V to +2.75V

+150°C

Serializer Output Voltage

Junction Temperature

Storage Temperature

−65°C to +150°C

48L LLP Package

Maximum Power Dissipation Capacity at 25°C

Derate above 25°C

1/ θ_JA°C/W

35 °C/W

ꢀθ_JA

5.2 °C/W

ꢀθ_JC

ESD Rating (IEC, powered-up only), R_D= 330Ω, C_S= 150pF

Air Discharge (D_OUT+, D_OUT−

Contact Discharge (D_OUT+, D_OUT−

ESD Rating (ISO10605), R_D= 330Ω, C_S= 150pF

Air Discharge (D_OUT+, D_OUT−

Contact Discharge(D_OUT+, D_OUT−

ESD Rating (ISO10605), R_D= 2kΩ, C_S= 150pF or 330pF

Air Discharge (D_OUT+, D_OUT−

)

≥±15 kV

≥±8 kV

)

≥±15 kV

≥±8 kV

)

≥±15 kV

≥±8 kV

≥±1.25 kV

≥±250 V

Contact Discharge (D_OUT+, D_OUT−

)

ESD Rating (HBM)

ESD Rating (CDM)

ESD Rating (MM)

For soldering specifications:

see product folder at www.ti.com and

www.ti.com/lit/an/snoa549c/snoa549c.pdf

Recommended Operating Conditions

Min

3.0

Nom

3.3

Max

3.6

Units

Supply Voltage (V_DD33

)

LVCMOS Supply Voltage (V_DDIO

)

3.3

3.6

LVCMOS Supply Voltage (V_DDIO

1.71

1.8

1.89

Operating Free Air Temperature (T_A)

PCLK Frequency

−40

+25

+105

°C

MHz

mV_P-P

Supply Noise (Note 7)

100

DS90UB925Q

DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

LVCMOS I/O DC SPECIFICATIONS

V_IH

V_IL

I_IN

V_DDIO= 3.0 to 3.6V

V_DDIO

0.8

High Level Input Voltage

Low Level Input Voltage

Input Current

2.0

GND

−10

2.0

V_DDIO= 3.0 to 3.6V

PDB

V_IN= 0V or V_DDIO= 3.0 to 3.6V

V_DDIO= 3.0 to 3.6V

±1

+10

μA

V_DDIO

V_IH

High Level Input Voltage

Low Level Input Voltage

0.65*

V_DDIO

V_DDIO= 1.71 to 1.89V

V_DDIO= 3.0 to 3.6V

V_DDIO= 1.71 to 1.89V

V_DDIO= 3.0

V_DDIO

DIN[23:0],

HS, VS, DE,

PCLK,

I2S_CLK,

I2S_WC,

I2S_DA,

I2S_DB

GND

0.8

V_IL

0.35*

V_DDIO

GND

−10

2.4

±1

+10

μA

V_IN= 0V or

V_DDIO

to 3.6V

I_IN

Input Current

V_DDIO= 1.71

to 1.89V

V_DDIO= 3.0

to 3.6V

V_DDIO

0.4

V_OH

I_OH= −4mA

High Level Output Voltage

Low Level Output Voltage

V_DDIO= 1.71

to 1.89V

V_DDIO

0.45

GPIO[3:0],

GPO_REG

[8:4]

V_DDIO= 3.0

to 3.6V

GND

V_OL

I_OL= +4mA

V_OUT= 0V

V_DDIO= 1.71

to 1.89V

0.35

I_OS

I_OZ

Output Short Circuit Current

TRI-STATE® Output Current

−50

V_OUT= 0V or V_DDIO, PDB = L,

−10

+10

μA

FPD-LINK III CML DRIVER DC SPECIFICATIONS

Differential Output Voltage

(DOUT+) – (DOUT-)

V_ODp-p

R_L= 100Ω, Figure 1

1160

1250

1340 mVp-p

ΔV_OD

Output Voltage Unbalance

2.5-0.2

5*V_ODp-

V_OS

Offset Voltage – Single-ended R_L= 100Ω, Figure 1

DOUT+,

DOUT-

p (TYP)

Offset Voltage Unbalance

Single-ended

ΔV_OS

I_OS

Ω

Output Short Circuit Current DOUT+/- = 0V, PDB = L or H

−38

Internal Termination Resistor

- Single ended

R_T

DS90UB925Q

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

SUPPLY CURRENT

I_DD1

V_DD33= 3.6V V_DD33

148

170

180

Supply Current

(includes load current)

Checker Board

Pattern,

Figure 2

V_DDIO= 3.6V

μA

I_DDIO1

I_DDS1

I_DDIOS1

I_DDS2

V_DDIO

1.89V

R_L= 100Ω, f = 85MHz

1.6

V_DD33= 3.6V V_DD33

V_DDIO= 3.6V

1.2

2.4

0x01[7] = 1,

deserializer is

powered down

Supply Current Remote Auto

Power Down Mode

150

μA

V_DDIO

1.89V

150

μA

PDB = L, All

LVCMOS

V_DD33= 3.6V V_DD33

V_DDIO= 3.6V

150

μA

Supply Current Power Down inputs are

floating or tied

to GND

I_DDIOS2

V_DDIO

1.89V

150

μA

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

GPIO BIT RATE

Forward Channel Bit Rate

f = 5 – 85

MHz

GPIO[3:0]

0.25* f

Mbps

kbps

B_R

(Note 8, Note 9)

Back Channel Bit Rate

RECOMMENDED TIMING FOR PCLK

t_TCP

t_CIH

t_CIL

PCLK Period

11.76

0.4*T

4.0

200

PCLK Input High Time

PCLK Input Low Time

(Note 8, Note 9)

PCLK

0.5*T

0.6*T

PCLK Input Transition Time

Figure 3 (Note 8, Note 9)

f = 5 MHz

t_CLKT

t_IJIT

f = 85 MHz

0.5

PCLK Input Jitter Tolerance,

Bit Error Rate ≤10^-10

f / 40 < Jitter Freq < f / 20

(Note 10, Note 8)

f = 5 –

78MHz

0.4

0.6

SWITCHING CHARACTERISTICS

t_LHT

t_HLT

t_DIS

CML Output Low-to-High

Transition Time

130

DOUT+,

DOUT-

See Figure 1, Figure 4

CML Output High-to-Low

Transition Time

DIN[23:0],

HS, VS, DE,

PCLK,

I2S_CLK,

I2S_WC,

I2S_DA,

Data Input Setup to PCLK

Data Input Hold from PCLK

2.0

See Figure 5

t_DIH

I2S_DB

t_PLD

t_SD

Figure 6 (Note 5)

f = 5 – 85

MHz

Serializer PLL Lock Time

131*T

145*T

0.25

f = 5 – 85

MHz

Delay — Latency

Output Total Jitter,

Bit Error Rate ≥10^-10

Figure 7 (Note 6, Note 8, Note

R_L= 100Ω

f = 85MHz, LFMODE = L

0.30

DOUT+,

DOUT-

t_TJIT

R_L= 100Ω

f = 5MHz, LFMODE = H

0.25

DS90UB925Q

Recommended Timing for the Serial Control Bus

Over 3.3V supply and temperature ranges unless otherwise specified.

Symbol

f_SCL

Parameter

Conditions

Min

Typ

Max

100

400

Units

kHz

Standard Mode

Fast Mode

SCL Clock Frequency

t_LOW

Standard Mode

Fast Mode

4.7

1.3

4.0

0.6

4.0

SCL Low Period

SCL High Period

t_HIGH

Standard Mode

Fast Mode

t_HD;STA

Hold time for a start or a

repeated start condition

Figure 8

Standard Mode

Fast Mode

0.6

4.7

0.6

t_SU:STA

Set Up time for a start or a

repeated start condition

Figure 8

Standard Mode

Fast Mode

t_HD;DAT

t_SU;DAT

t_SU;STO

Standard Mode

Fast Mode

3.45

0.9

Data Hold Time

Figure 8

Standard Mode

Fast Mode

250

100

4.0

0.6

4.7

Data Set Up Time

Figure 8

Standard Mode

Fast Mode

Set Up Time for STOP

Condition, Figure 8

Bus Free Time

Standard Mode

t_BUF

Between STOP and START,

Figure 8

Fast Mode

1.3

Standard Mode

Fast Mode

1000

300

SCL & SDA Rise Time,

Figure 8

t_r

t_f

Standard Mode

Fast mode

SCL & SDA Fall Time,

Figure 8

DC and AC Serial Control Bus Characteristics

Over 3.3V supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol

V_IH

Parameter

Input High Level

Conditions

Min

Typ

Max

Units

0.7*

V_DD33

SDA and SCL

V_IL

0.3*

V_DD33

Input Low Level Voltage

Input Hysteresis

GND

V_HY

V_OL

I_in

>50

SDA, IOL = 1.25mA

0.36

+10

SDA or SCL, Vin = V_DD33or GND

-10

µA

t_R

SDA RiseTime – READ

SDA Fall Time – READ

Set Up Time — READ

Hold Up Time — READ

Input Filter

430

SDA, RPU = 10kΩ, Cb ≤ 400pF, Figure 8

t_F

t_SU;DAT

t_HD;DAT

t_SP

Figure 8

560

615

C_in

Input Capacitance

SDA or SCL

DS90UB925Q

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or

specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: Typical values represent most likely parametric norms at V_DD= 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and

ΔVOD, which are differential voltages.

Note 5: t_PLDis the time required by the device to obtain lock when exiting power-down state with an active PCLK.

Note 6: UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.

Note 7: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DD33and V_DDIOsupplies with amplitude =

100 mVp-p measured at the device V_DD33and V_DDIOpins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when

the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

Note 8: Specification is guaranteed by characterization and is not tested in production.

Note 9: Specification is guaranteed by design and is not tested in production.

Note 10: Jitter Frequency is specified in conjunction with DS90UB926 PLL bandwidth.

DS90UB925Q

AC Timing Diagrams and Test Circuits

30143362

FIGURE 1. Serializer VOD DC Output

30143346

FIGURE 2. Checkboard Data Pattern

30143330

FIGURE 3. Serializer Input Clock Transition Time

DS90UB925Q

30143347

FIGURE 4. Serializer CML Output Load and Transition Time

30143361

FIGURE 5. Serializer Setup and Hold Times

30143349

FIGURE 6. Serializer Lock Time

30143348

FIGURE 7. Serializer CML Output Jitter

DS90UB925Q

30143336

FIGURE 8. Serial Control Bus Timing Diagram

DS90UB925Q

Functional Description

The DS90UB925Q serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to 2.975 Gbps line rate.

The serial stream contains an embedded clock, video control signals and DC-balanced video data and audio data which enhance

signal quality to support AC coupling. The serializer is intended for use with the DS90UB926Q deserializer, but is also backward

compatible with DS90UR906Q or DS90UR908Q FPD-Link II deserializer.

The DS90UB925Q serializer and DS90UB926Q deserializer incorporate an I2C compatible interface. The I2C compatible interface

allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirec-

tional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel (serializer to deseri-

alizer) as well as lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides

a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration

with other I2C compatible masters at either side of the serial link.

There are two operating modes available on DS90UB925Q, display mode and camera mode. In display mode, I2C transactions

originate from the host controller attached to the serializer and target either the deserializer or an I2C slave attached to the dese-

rializer. Transactions are detected by the I2C slave in the serializer and forwarded to the I2C master in the deserializer. Similarly,

in camera mode, I2C transactions originate from a controller attached to the deserializer and target either the serializer or an I2C

slave attached to the serializer. Transactions are detected by the I2C slave in the deserializer and forwarded to the I2C master in

the serializer.

HIGH SPEED FORWARD CHANNEL DATA TRANSFER

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync

signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 9 illustrates the serial stream per PCLK cycle. This

data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.

30143337

FIGURE 9. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps

minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.

LOW SPEED BACK CHANNEL DATA TRANSFER

The Low-Speed Backward Channel (LS_BC) of the DS90UB925Q provides bidirectional communication between the display and

host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control

data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock

information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back

channel contains the I2C, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

BACKWARD COMPATIBLE MODE

The DS90UB925Q is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II deserializers at 5-65 MHz of

PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at the line rate of 140 Mbps to 1.82 Gbps. The

backward configuration mode can be set via MODE_SEL pin (Table 1) or the configuration register (Table 6).

COMMON MODE FILTER PIN (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional

common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability.

A 0.1 μF capacitor must be connected to this pin to Ground.

DS90UB925Q

VIDEO CONTROL SIGNAL FILTER

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:

•

Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the

transition pulse must be 3 PCLK or longer.

Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no

restriction on minimum transition pulse.

VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual

display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See

Figure 10.

30143302

FIGURE 10. Video Control Signal Filter Waveform

EMI REDUCTION FEATURES

Input SSC Tolerance (SSCT)

The DS90UB925Q serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up to +/-2.5% amplitude

deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.

LVCMOS V_DDIOOPTION

1.8V or 3.3V Inputs and Outputs are powered from a separate V_DDIOsupply to offer compatibility with external system interface

signals. Note: When configuring theV_DDIOpower supplies, all the single-ended data and control input pins for device need to scale

together with the same operating V_DDIOlevels.

POWER DOWN (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through

the V_DDIO, where V_DDIO= 3.0V to 3.6V or V_DD33. To save power disable the link when the display is not needed (PDB = LOW).

When the pin is driven by the host, make sure to release it after V_DD33and V_DDIOhave reached final levels; no external components

are required. In the case of driven by the V_DDIO= 3.0V to 3.6V or V_DD33directly, a 10 kohm resistor to the V_DDIO= 3.0V to 3.6V or

V_DD33, and a >10uF capacitor to the ground are required (See Figure 21 Typical Connection Diagram).

REMOTE AUTO POWER DOWN MODE

The Serializer features a remote auto power down mode. During the power down mode of the pairing deserializer, the Serializer

enters the remote auto power down mode. In this mode, the power dissipation of the Serializer is reduced significantly. When the

Deserializer is powered up, the Serializer enters the normal power on mode automatically. This feature is enabled through the

INPUT PCLK LOSS DETECT

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A clock loss condition is

detected when PCLK drops below approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming

PCLK. Note – when PCLK is lost, the Serial Control Bus Registers values are still RETAINED.

DS90UB925Q

SERIAL LINK FAULT DETECT

The serial link fault detection is able to detect any of following seven (7) conditions

1) cable open

2) “+” to “-“ short

3) “+” short to GND

4) “-“ short to GND

5) “+” short to battery

6) “-“ short to battery

7) Cable is linked correctly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C Table 6.

PIXEL CLOCK EDGE SELECT (RFB)

The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines the edge that the

data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB is LOW (‘0’), data is latched on the

Falling edge of the PCLK.

LOW FREQUENCY OPTIMIZATION (LFMODE)

The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 1). It controls the operating frequency of the serializer. If

LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is between

5 MHz and <15 MHz. Please note when the device LFMODE is changed, a PDB reset is required.

INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)

1. On DS90UB925, set register 0xC6[5] = 1 and 0xC6[0] = 1

2. DS90UB926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device.

3. DS90UB925Q serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.

4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .

5. A read to ISR will clear the interrupt at the DS90UB925, releasing INTB.

6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the

interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UB926Q.

The system is now ready to return to step (1) at next falling edge of INTB_IN.

CONFIGURATION SELECT (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and

a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (V_R4) and V_DD33to select

one of the other 10 possible selected modes. See Figure 11 and Table 1.

30143341

FIGURE 11. MODE_SEL Connection Diagram

DS90UB925Q

TABLE 1. Configuration Select (MODE_SEL)

Ideal Ratio

V_R4/V_DD33

Ideal V_R4

(V)

Suggested

Resistor R3

kΩ (1% tol)

Suggested

Resistor R4

kΩ (1% tol)

LFMODE

Repeater

Backward I2S Channel

Compatible

(18–bit

Mode)

Open

294

280

240

226

196

169

137

124

90.9

40.2 or Any

40.2

49.9

76.8

102

0.121

0.152

0.242

0.311

0.402

0.492

0.583

0.629

0.727

0.399

0.502

0.799

1.026

1.327

1.624

1.924

2.076

2.399

130

165

191

210

243

LFMODE: L = 15 – 85 MHz (Default); H = 5 – <15 MHz

Repeater: L = Repeater Off (Default); H = Repeater On

Backward Compatible: L = Backward Compatible Off (Default); H = Backward Compatible On to 906/908 (15 - 65MHz)

I2S Channel B: L = I2S Channel B Off, Normal 24-bit RGB Mode (Default); H = I2S Channel B On, 18-bit RGB Mode with I2S_DB

Enabled.

GPIO[3:0] and GPO_REG[8:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB925Q can be used as the general purpose IOs GPIO

[3:0] in either forward channel (Inputs) or back channel (Outputs) application.

GPIO[3:0] Enable Sequence

See Table 2 for the GPIO enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q only. DS90UB926Q is

automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q, then write 0x05 to address 0x1F on

DS90UB926Q.

TABLE 2. GPIO Enable Sequencing Table

Description

Device

Forward Channel

0x12 = 0x04

Back Channel

0x12 = 0x04

Enable 18-bit

mode

DS90UB925Q

DS90UB926Q

DS90UB925Q

DS90UB926Q

DS90UB925Q

DS90UB926Q

DS90UB925Q

DS90UB926Q

DS90UB925Q

DS90UB926Q

Auto Load from DS90UB925Q

0x0F = 0x03

Auto Load from DS90UB925Q

0x0F = 0x05

GPIO3

GPIO2

GPIO1

GPIO0

0x1F = 0x05

0x1F = 0x03

0x0E = 0x30

0x0E = 0x50

0x1E = 0x50

0x1E = 0x30

0x0E = 0x03

0x0E = 0x05

0x1E = 0x05

0x0E = 0x05

0x0D = 0x93

0x0D = 0x95

0x1D = 0x95

0x1D = 0x93

GPO_REG[8:4] Enable Sequence

GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 3 for the GPO_REG

enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit on DS90UB925Q only. DS90UB926Q is automatically

configured as in the 18-bit mode.

Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UB925Q.

DS90UB925Q

TABLE 3. GPO_REG Enable Sequencing Table

Description

Device

Local Access

0x12 = 0x04

0x11 = 0x90

0x11 = 0x10

0x11 = 0x09

0x11 = 0x01

0x10 = 0x90

0x10 = 0x10

0x10 = 0x09

0x10 = 0x01

0x0F = 0x90

0x0F = 0x10

Local Output

Enable 18-bit mode

GPO_REG8

DS90UB925Q

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

GPO_REG7

GPO_REG6

GPO_REG5

GPO_REG4

DS90UB925Q

I2S TRANSMITTING

In normal 24-bit RGB operation mode, the DS90UB925Q supports 3 bits of I2S. They are I2S_CLK, I2S_WC and I2S_DA. The

optionally packetized audio information can be transmitted during the video blanking (data island transport) or during active video

(forward channel frame transport).

Secondary I2S Channel

In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in addition to the 3–

bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and I2S_WC at the input to the serializer.

This operation mode is enabled through either the MODE_SEL pin (Table 1) or through the register bit 0x12[0] (Table 6).

Table 4 below covers the range of I2S sample rates.

TABLE 4. Audio Interface Frequencies

Sample Rate (kHz)

I2S Data Word Size (bits)

I2S CLK (MHz)

1.024

44.1

1.411

1.536

3.072

192

6.144

1.536

44.1

2.117

2.304

4.608

192

9.216

2.048

44.1

2.822

3.072

6.144

192

12.288

DS90UB925Q

REPEATER APPLICATION

The DS90UB925Q and DS90UB926Q can be configured to extend data transmission over multiple links to multiple display devices.

Setting the devices into repeater mode provides a mechanism for transmitting to all receivers in the system.

Repeater Configuration

In the repeater application, in this document, the DS90UB925Q is referred to as the Transmitter or transmit port (TX), and the

DS90UB926Q is referred to as the Receiver (RX). Figure 12 shows the maximum configuration supported for Repeater imple-

mentations using the DS90UB925Q (TX) and DS90UB926Q (RX). Two levels of Repeaters are supported with a maximum of three

Transmitters per Receiver.

30143310

FIGURE 12. Maximum Repeater Application

In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C communications

upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases)

to downstream devices in the case of duplicate addresses.

At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel RGB video data,

HS/VS/DE control signals and, optionally, packetized audio data (transported during video blanking intervals). Alternatively, the

I2S audio interface may be used to transport digital audio data between receiver and transmitters in place of packetized audio. All

audio and video data is transmitted at the output of the Receiver and is received by the Transmitter.

Figure 13 provides more detailed block diagram of a 1:2 repeater configuration.

DS90UB925Q

30143332

FIGURE 13. 1:2 Repeater Configuration

Repeater Connections

The Repeater requires the following connections between the Receiver and each Transmitter Figure 14.

1) Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).

2) I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33with 4.7 kΩ resistors.

3) Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.

4) IDx pin – Each Transmitter and Receiver must have an unique I2C address.

5) MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.

6) Interrupt pin – Connect DS90UB926Q INTB_IN pin to DS90UB925Q INTB pin. The signal must be pulled up to V_DDIO

30143342

FIGURE 14. Repeater Connection Diagram

DS90UB925Q

BUILT IN SELF TEST (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the low- speed back

channel. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics.

Note: BIST is not available in backwards compatible mode.

BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or configuration register(Table

6) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33 MHz internal Oscillator

clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or 25MHz) through

the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator

clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel.

The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors.

The PASS output pin toggles to flag any payloads that are received with 1 to 35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test

or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were

detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also

contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in

the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.

Sample BIST Sequence

See Figure 15 for the BIST mode flow diagram.

Step 1:For the DS90UB925Q and DS90UB926Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of DS90UB926Q

FPD-Link III deserializer. The desired clock source is selected through BISTC pin.

Step 2:The DS90UB925Q serializer is woken up through the back channel if it is not already on. The all zero pattern on the data

pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer

acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1

to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be

monitored and counted to determine the payload error rate.

Step 3:To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test

result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected,

the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The

BIST duration is user controlled by the duration of the BISTEN signal.

Step 4:The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 16 shows the waveform diagram of a

typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to

generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly

extending the cable length, faulting the interconnect, reducing signal condition enhancements ( Rx Equalization).

30143343

FIGURE 15. BIST Mode Flow Diagram

DS90UB925Q

Forward Channel and Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal

all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on

locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and

dynamically indicates the status on PASS pin. The deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link

detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer

enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC

errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until cleared or enters

BIST mode again.

30143364

FIGURE 16. BIST Waveforms

Internal Pattern Generation

The DS90UB925Q serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated

panel through the FPD-Link III output stream. The test patterns are simple and repetitive and allow for a quick visual verification of

panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no parallel input is

applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed infor-

mation, refer to Application Note AN-2198.

DS90UB925Q

Serial Control Bus

The DS90UB925Q is configured by the use of a serial control bus that is I2C protocol compatible. Multiple serializer devices may

share the serial control bus since 16 device addresses are supported. Device address is set via R₁and R₂values on IDx pin. See

Figure 17 below.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output. The SDA is

the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to V_DD33. For most appli-

cations a 4.7 k pull-up resistor to V_DD33may be used. The resistor value may be adjusted for capacitive loading and data rate

requirements. The signals are either pulled High, or driven Low.

30143301

FIGURE 17. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a pull-down resistor

of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33to select one of the other 16 possible

addresses. See Table 6.

TABLE 5. Serial Control Bus Addresses for IDx

Suggested

Resistor R2 kΩ

(1% tol)

40.2 or Any

40.2

Ideal Ratio

V_R2/ V_DD33

Ideal V_R2

(V)

Address 8'b

Appended

Resistor R1 kΩ

(1% tol)

Open

294

Address 7'b

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x18

0x1A

0x1C

0x1E

0x20

0x22

0x24

0x26

0x28

0x2A

0x2C

0x2E

0x30

0x32

0x34

0x36

0.121

0.152

0.182

0.212

0.242

0.273

0.310

0.356

0.402

0.447

0.492

0.538

0.583

0.629

0.727

0.399

0.502

0.601

0.700

0.799

0.901

1.023

1.175

1.327

1.475

1.624

1.775

1.924

2.076

2.399

280

49.9

270

60.4

267

71.5

240

76.8

243

90.9

226

102

210

115

196

130

182

147

169

165

154

180

137

191

124

210

90.9

243

DS90UB925Q

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions

Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 18.

30143351

FIGURE 18. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the

slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges

(ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs)

the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing

data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every

data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs

after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition

or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 19 and a

WRITE is shown in Figure 20.

If the Serial Bus is not required, the three pins may be left open (NC).

30143338

FIGURE 19. Serial Control Bus — READ

30143339

FIGURE 20. Serial Control Bus — WRITE

DS90UB925Q

TABLE 6. Serial Control Bus Registers

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

0x00 I2C Device ID

7:1

Device ID 7–bit address of Serializer

ID Setting I2C ID Setting

1: Register I2C Device ID (Overrides IDx pin)

0: Device ID is from IDx pin

Remote Auto Power Down

0x01 Reset

0x00

Remote

Auto Power 1: Power down when no Bidirectional Control

Down

Channel link is detected

0: Do not power down when no Bidirectional Control

Channel link is detected

6:2

Reserved

Digital

RESET1

Reset the entire digital block including registers

This bit is self-clearing.

1: Reset

0: Normal operation

Digital

RESET0

Reset the entire digital block except registers

This bit is self-clearing

1: Reset

0: Normal operation

0x03 Configuration

0xD2

Back

channel

CRC

Back Channel Check Enable

1: Enable

0: Disable

Checker

Enable

Reserved

I2C

Automatically Acknowledge I2C Remote Write

Remote

When enabled, I2C writes to the Deserializer (or any

Write Auto remote I2C Slave, if I2C PASS ALL is enabled) are

Acknowled immediately acknowledged without waiting for the

Deserializer to acknowledge the write. This allows

higher throughput on the I2C bus

1: Enable

0: Disable

Filter

Enable

HS, VS, DE two clock filter When enabled, pulses

less than two full PCLK cycles on the DE, HS, and

VS inputs will be rejected

1: Filtering enable

0: Filtering disable

I2C Pass- I2C Pass-Through Mode

through

1: Pass-Through Enabled

0: Pass-Through Disabled

Reserved

PCLK Auto Switch over to internal OSC in the absence of PCLK

1: Enable auto-switch

0: Disable auto-switch

TRFB

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the Rising

Clock Edge.

0: Parallel Interface Data is strobed on the Falling

Clock Edge.

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

0x04 Configuration

0x80

Failsafe

State

Input Failsafe State

1: Failsafe to Low

0: Failsafe to High

Reserved

CRC Error Clear back channel CRC Error Counters

Reset

This bit is NOT self-clearing

1: Clear Counters

0: Normal Operation

Reserved

BKWD

Override

Backward Compatible mode set by MODE_SEL pin

or register

1: BC to DS90UR906Q or DS90UR908Q mode is

set by register bit

0: BC to DS90UR906Q or DS90UR908Q mode is

set by MODE_SEL pin. .

BKWD

Backward compatibility mode, device to pair with

DS90UR906Q or DS90UR908Q

1: Compatible with DS90UR906Q or DS90UR908Q

0: Normal device

LFMODE

Override

Frequency mode set by MODE_SEL pin or register

1: Frequency mode is set by register bit

0: Frequency mode is set by MODE_SEL Pin

LFMODE

Frequency mode select

1:Low frequency mode (5MHz - <15 MHz)

0: High frequency mode (15MHz - 85MHz)

0x05 I2C Control

7:5

4:3

0x00

Reserved

SDA

SDA output delay

Output

Delay

Configures output delay on the SDA output. Setting

this value will increase output delay in units of 40ns.

Nominal output delay values for SCL to SDA are

00: 240ns

01: 280ns

10: 320ns

11: 360ns

Local Write Disable remote writes to local registers

Disable

Setting the bit to a 1 prevents remote writes to local

device registers from across the control channel. It

prevents writes to the Serializer registers from an

I2C master attached to the Deserializer.

Setting this bit does not affect remote access to I2C

slaves at the Serializer

I2C Bus

Timer

Speedup

Speed up I2C bus watchdog timer

1: Watchdog timer expires after ~50 ms.

0: Watchdog Timer expires after ~1 s

I2C Bus

timer

Disable

Disable I2C bus watchdog timer

When the I2C watchdog timer may be used to detect

when the I2C bus is free or hung up following an

invalid termination of a transaction.

If SDA is high and no signalling occurs for ~1 s, the

I2C bus assumes to be free. If SDA is low and no

signaling occurs, the device attempts to clear the

bus by driving 9 clocks on SCL

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

DES 7-bit Deserializer Device ID

(dec) (hex) Name

Type

(hex)

0x06 DES ID

7:1

0x00

Device ID Configures the I2C Slave ID of the remote

Deserializer. A value of 0 in this field disables I2C

access to the remote Deserializer. This field is

automatically configured by the Bidirectional

Control Channel once RX Lock has been detected.

Software may overwrite this value, but should also

assert the FREEZE DEVICE ID bit to prevent

overwriting by the Bidirectional Control Channel.

Device ID Freeze Deserializer Device ID

Frozen

Prevents autoloading of the Deserializer Device ID

by the Bidirectional Control Channel. The ID will be

frozen at the value written.

0x07 Slave ID

7:1

0x00

Slave

7-bit Remote Slave Device ID

Device ID Configures the physical I2C address of the remote

I2C Slave device attached to the remote

Deserializer. If an I2C transaction is addressed to

the Slave Device Alias ID, the transaction will be

remapped to this address before passing the

transaction across the Bidirectional Control

Channel to the Deserializer

Reserved

0x08 Slave Alias

7:1

0x00

Slave

7-bit Remote Slave Device Alias ID

Device

Alias ID

Assigns an Alias ID to an I2C Slave device attached

to the remote Deserializer. The transaction will be

remapped to the address specified in the Slave ID

the remote I2C Slave.

Reserved

0x0A CRC Errors

0x0B

7:0

0x00

CRC Error Number of back channel CRC errors – 8 least

LSB significant bits

CRC Error Number of back channel CRC errors – 8 most

7:0

MSB

significant bits

0x0C General Status 7:4

Reserved

BIST CRC Back channel CRC error during BIST

Error

communication with Deserializer.

The bit is cleared upon loss of link, restart of BIST,

or assertion of CRC ERROR RESET in register

0x04.

PCLK

Detect

PCLK Status

1: Valid PCLK detected

0: Valid PCLK not detected

DES Error Back channel CRC error during communication with

Deserializer.

The bit is cleared upon loss of link or assertion of

CRC ERROR RESET in register 0x04.

LINK

LINK Status

Detect

1: Cable link detected

0: Cable link not detected (Fault Condition)

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

0x0D Revision ID

7:4

0xA0

Rev-ID

Revision ID: 1010

and GPIO0

Production Device

Configuration

GPIO0

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is

Output, and remote GPIO control is disabled.

GPIO0

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO0

Direction

Local GPIO Direction

1: Input

0: Output

GPIO0

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

0x0E GPIO2 and

GPIO1

0x00

GPIO2

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is

Output, and remote GPIO control is disabled.

Configurations

GPIO2

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO2

Direction

Local GPIO Direction

1: Input

0: Output

GPIO2

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

GPIO1

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is

Output, and remote GPIO control is disabled.

GPIO1

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO1

Direction

Local GPIO Direction

1: Input

0: Output

GPIO1

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

DS90UB925Q

ADD

(dec) (hex) Name

15 0x0F GPO_REG4

ADD Register

Bit(s)

Function Description

Type

(hex)

0x00

GPO_REG Local GPO_REG4 output value

and GPIO3

Configurations

4 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

(The local GPO direction is Output, and remote

GPO control is disabled)

6:5

Reserved

GPO_REG GPO_REG4 function enable

4 Enable

1: Enable GPO operation

0: Enable normal operation

GPIO3

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the GPIO

function is enabled, the local GPIO direction is

Output, and remote GPIO control is disabled.

GPIO3

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

GPIO3

Direction

Local GPIO Direction

1: Input

0: Output

GPIO3

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

0x10 GPO_REG6

and

0x00

GPO_REG Local GPO_REG6 output value

6 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

(The local GPO direction is Output, and remote

GPO control is disabled)

GPO_REG5

Configurations

6:5

Reserved

GPO_REG GPO_REG6 function enable

6 Enable

1: Enable GPO operation

0: Enable normal operation

GPO_REG Local GPO_REG5 output value

5 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.

2:1

Reserved

GPO_REG GPO_REG5 function enable

5 Enable

1: Enable GPO operation

0: Enable normal operation

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

0x11 GPO_REG8

0x00

GPO_REG Local GPO_REG8 output value

and

GPO_REG7

Configurations

8 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

(The local GPO direction is Output, and remote

GPO control is disabled)

6:5

Reserved

GPO_REG GPO_REG8 function enable

8 Enable

1: Enable GPO operation

0: Enable normal operation

GPO_REG Local GPO_REG7 output value

7 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.

2:1

Reserved

GPO_REG GPO_REG7 function enable

7 Enable

1: Enable GPO operation

0: Enable normal operation

0x12 Data Path

Control

0x00

Reserved

Pass RGB Setting this bit causes RGB data to be sent

independent of DE.

It allows operation in systems which may not use DE

to frame video data or send other data when DE is

de-asserted.

1: Pass RGB independent of DE

0: Normal operation

(DE gates RGB data transmission - RGB data is

transmitted only when DE is active)

DE Polarity The bit indicates the polarity of the DE (Data Enable)

signal.

1: DE is inverted (active low, idle high)

0: DE is positive (active high, idle low)

I2S

Repeater

Regen

I2S Repeater Regeneration

1: Repeater regenerate I2S from I2S pins

0: Repeater pass through I2S from video pins

I2S

I2S Channel B Enable

Channel B 1: Set I2S Channel B Enable from reg_12[0]

Enable

0: Set I2S Channel B Enable from MODE_SEL pin

Override

18-bit

Video

Select

18–bit video select

1: Select 18-bit video mode

0: Select 24-bit video mode

I2S

I2S Transport Mode Slect

Transport 1: Enable I2S Data Forward Channel Frame

Select

I2S

Transport

0: Enable I2S Data Island Transport

I2S Channel B Enable

Channel B 1: Enable I2S Channel B on B1 input

Enable

0: I2S Channel B disabled

DS90UB925Q

ADD

(dec) (hex) Name

19 0x13 Mode Status

ADD Register

Bit(s)

Function Description

Type

(hex)

7:5

0x10

Reserved

MODE_SE MODE_SEL Status

1: MODE_SEL decode circuit is completed

0: MODE_SEL decode circuit is not completed

Low Frequency Mode Status

Low

Frequency 1: Low frequency (5 - <15 MHz)

Mode

0: Normal frequency (15 - 85 MHz)

Repeater

Mode

Repeater Mode Status

1: Repeater mode ON

0: Repeater Mode OFF

Backward Backward Compatible Mode Status

Compatible 1: Backward compatible ON

Mode

I2S

0: Backward compatible OFF

I2S Channel B Mode Status

Channel B 1: I2S Channel B on, 18-bit RGB mode with I2S_DB

Mode

enabled

0: I2S Channel B off; normal 24-bit RGB mode

0x14 Oscillator

Clock Source

7:3

2:1

0x00

Reserved

OSC Clock OSC Clock Source

and BIST

Status

Source

(When LFMODE = 1, Oscillator = 12.5MHz ONLY)

00: External Pixel Clock

01: 33 MHz Oscillator

10: Reserved

11: 25 MHz Oscillator

BIST

Enable

Status

BIST status

1: Enabled

0: Disabled

0x16 BCC

7:1

0xFE

Timer

Value

The watchdog timer allows termination of a control

channel transaction if it fails to complete within a

programmed amount of time.

Watchdog

Control

This field sets the Bidirectional Control Channel

Watchdog Timeout value in units of 2 ms.

This field should not be set to 0

Timer

Control

Disable Bidirectional Control Channel Watchdog

Timer

1: Disables BCC Watchdog Timer operation

0: Enables BCC Watchdog Timer operation

0x17 I2C Control

0x5E

I2C Pass

All

I2C Control

1: Enable Forward Control Channel pass-through of

all I2C accesses to I2C Slave IDs that do not match

the Serializer I2C Slave ID.

0: Enable Forward Control Channel pass-through

only of I2C accesses to I2C Slave IDs matching

either the remote Deserializer Slave ID or the

remote Slave ID.

Reserved

5:4

SDA Hold Internal SDA Hold Time

Time

Configures the amount of internal hold time

provided for the SDA input relative to the SCL input.

Units are 40 ns

3:0

I2C Filter

Depth

Configures the maximum width of glitch pulses on

the SCL and SDA inputs that will be rejected. Units

are 5 ns

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

0x18 SCL High Time 7:0

0xA1

SCL HIGH I2C Master SCL High Time

Time

This field configures the high pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. Units are 40 ns for the nominal oscillator

clock frequency. The default value is set to provide

a minimum 5us SCL high time with the internal

oscillator clock running at 32.5MHz rather than the

nominal 25MHz.

0x19 SCL Low Time 7:0

0xA5

SCL LOW I2C SCL Low Time

Time This field configures the low pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. This value is also used as the SDA setup

time by the I2C Slave for providing data prior to

releasing SCL during accesses over the

Bidirectional Control Channel. Units are 40 ns for

the nominal oscillator clock frequency. The default

value is set to provide a minimum 5us SCL low time

with the internal oscillator clock running at 32.5MHz

rather than the nominal 25MHz.

0x1B BIST BC Error

7:0

0x00

BIST Back BIST Mode Back Channel CRC Error Counter

Channel This error counter is active only in the BIST mode.

CRC Error It clears itself at the start of the BIST run.

Counter

DS90UB925Q

ADD

(dec) (hex) Name

100 0x64 Pattern

Generator

Control

ADD Register

Bit(s)

Function Description

Type

(hex)

7:4

0x10

Pattern

Fixed Pattern Select

Generator This field selects the pattern to output when in Fixed

Select

Pattern Mode. Scaled patterns are evenly

distributed across the horizontal or vertical active

regions. This field is ignored when Auto-Scrolling

Mode is enabled. The following table shows the

color selections in non-inverted followed by inverted

color mode

0000: Reserved

0001: White/Black

0010: Black/White

0011: Red/Cyan

0100: Green/Magenta

0101: Blue/Yellow

0110: Horizontally Scaled Black to White/White to

Black

0111: Horizontally Scaled Black to Red/Cyan to

White

1000: Horizontally Scaled Black to Green/Magenta

to White

1001: Horizontally Scaled Black to Blue/Yellow to

White

1010: Vertically Scaled Black to White/White to

Black

1011: Vertically Scaled Black to Red/Cyan to White

1100: Vertically Scaled Black to Green/Magenta to

White

1101: Vertically Scaled Black to Blue/Yellow to

White

1110: Custom color (or its inversion) configured in

PGRS, PGGS, PGBS registers

1111: Reserved

3:1

Reserved

Pattern

Pattern Generator Enable

Generator 1: Enable Pattern Generator

Enable 0: Disable Pattern Generator

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

101

0x65 Pattern

Generator

Configuration

7:5

0x00

Reserved

Pattern

18-bit Mode Select

Generator 1: Enable 18-bit color pattern generation. Scaled

18 Bits

patterns will have 64 levels of brightness and the R,

G, and B outputs use the six most significant color

bits.

0: Enable 24-bit pattern generation. Scaled patterns

use 256 levels of brightness.

Pattern

Select External Clock Source

Generator 1: Selects the external pixel clock when using

External

Clock

internal timing.

0: Selects the internal divided clock when using

internal timing

This bit has no effect in external timing mode

(PATGEN_TSEL = 0).

Pattern

Timing Select Control

Generator 1: The Pattern Generator creates its own video

Timing

Select

timing as configured in the Pattern Generator Total

Frame Size, Active Frame Size. Horizontal Sync

Width, Vertical Sync Width, Horizontal Back Porch,

Vertical Back Porch, and Sync Configuration

registers.

0: the Pattern Generator uses external video timing

from the pixel clock, Data Enable, Horizontal Sync,

and Vertical Sync signals.

Pattern

Enable Inverted Color Patterns

Generator 1: Invert the color output.

Color Invert 0: Do not invert the color output.

Pattern

Auto-Scroll Enable:

Generator 1: The Pattern Generator will automatically move to

Auto-Scroll the next enabled pattern after the number of frames

Enable

specified in the Pattern Generator Frame Time

(PGFT) register.

0: The Pattern Generator retains the current pattern.

102

103

198

0x66 Pattern

7:0

0x00

Indirect

Address

This 8-bit field sets the indirect address for accesses

to indirectly-mapped registers. It should be written

prior to reading or writing the Pattern Generator

Indirect Data register.

Generator

Indirect

Address

See AN-2198

0x67 Pattern

Indirect

Data

When writing to indirect registers, this register

contains the data to be written. When reading from

indirect registers, this register contains the read

back value.

Generator

Indirect Data

See AN-2198

0xC6 ICR

7:6

Reserved

IS_RX_INT Interrupt on Receiver interrupt

Enables interrupt on indication from the Receiver.

Allows propagation of interrupts from downstream

devices

4:1

Reserved

INT Enable Global Interrupt Enable

Enables interrupt on the interrupt signal to the

controller.

DS90UB925Q

ADD

ADD Register

Bit(s)

Function Description

(dec) (hex) Name

Type

(hex)

199

0xC7 ISR

7:6

Reserved

IS RX INT Interrupt on Receiver interrupt

Receiver has indicated an interrupt request from

down-stream device

Reserved

4:1

INT

Global Interrupt

Set if any enabled interrupt is indicated

First byte ID code, ‘_’

240

241

242

243

244

245

0xF0 TX ID

0xF1

7:0

0x5F

0x55

0x48

0x39

0x32

0x35

ID0

ID1

ID2

ID3

ID4

ID5

Second byte of ID code, ‘U’

Third byte of ID code. Value will be ‘B’

Forth byte of ID code: ‘9’

0xF2

0xF3

0xF4

Fifth byte of ID code: “2”

0xF5

Sixth byte of ID code: “5”

DS90UB925Q

Applications Information

DISPLAY APPLICATION

The DS90UB925Q, in conjunction with the DS90UB926Q, is intended for interface between a host (graphics processor) and a

Display. It supports a 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive a three 8-bit RGB

stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio stream with an

audio sampling rate up to 192 kHz.

TYPICAL APPLICATION CONNECTION

Figure 21 shows a typical application of the DS90UB925Q serializer for an 85 MHz 24-bit Color Display Application. The CML

outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines. The serializer has an internal termination.

Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2) additional 1μF

capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2) VDDs (V_DD33and V_DDIO) for effective

noise suppression. The interface to the graphics source is with 3.3V LVCMOS levels, thus the V_DDIOpin is connected to the 3.3 V

rail. A RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.

30143344

FIGURE 21. Typical Connection Diagram

DS90UB925Q

POWER UP REQUIREMENTS AND PDB PIN

The VDDs (V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is

needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to

V_DDIO= 3.0V to 3.6V or V_DD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.

All inputs must not be driven until V_DD33and V_DDIOhas reached its steady state value.

PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power feed to the device.

Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup,

feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power /

ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which

has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical.

External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors

should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate

the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to

100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the

power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power

or ground pins to an external bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body size reduces the

parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors,

usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance

between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power

and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise

effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables

typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be

used to provide clean power to sensitive circuits such as PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML lines to prevent coupling

from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms are typically recommended for CML

interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the

receivers. The tightly coupled lines will also radiate less.

Information on the LLP style package is provided in TI Application Note: AN-1187.

CML INTERCONNECT GUIDELINES

See AN-1108 and AN-905 for full details.

•

Use 100Ω coupled differential pairs

Use the S/2S/3S rule in spacings

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500 Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web

site at: www.ti.com/lvds

DS90UB925Q

Revision

•

March 30, 2012

Web release

—

•

July 19, 2012

Converted to hybrid TI format

—

Corrected typo in “Pin Descriptions” SCL from pin 6 to pin 8

Corrected typo in “Pin Descriptions” SDA from pin 7 to pin 9

Corrected typo in “TABLE 1. Configuration Select (MODE_SEL)“ #6 ”I2S Channel B (18–bit Mode)“ from L to H

Corrected typo in TABLE 5. Serial Control Bus Addresses for IDx #11 Ideal V_R2(V) from 2.475 to 1.475

Added “Note: BIST is not available in backwards compatible mode.”

Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33

DS90UB925Q

Physical Dimensions inches (millimeters) unless otherwise noted

48–pin LLP Package (7.0 mm X 7.0 mm X 0.8 mm, 0.5 mm pitch)

NS Package Number SQA48A

Notes

Incorporated

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DS90UB925Q 相关器件

型号	制造商	描述	价格	文档
DS90UB925Q-Q1	TI	具有双向控制通道的 5 - 85MHz 24 位彩色 FPD-Link III 串行器	获取价格
DS90UB925QSQ	TI	5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel	获取价格
DS90UB925QSQ/NOPB	TI	具有双向控制通道的 5 - 85MHz 24 位彩色 FPD-Link III 串行器 \| RHS \| 48 \| -40 to 105	获取价格
DS90UB925QSQE	TI	5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel	获取价格
DS90UB925QSQE/NOPB	TI	具有双向控制通道的 5 - 85MHz 24 位彩色 FPD-Link III 串行器 \| RHS \| 48 \| -40 to 105	获取价格
DS90UB925QSQX	TI	5 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel	获取价格
DS90UB925QSQX/NOPB	TI	具有双向控制通道的 5 - 85MHz 24 位彩色 FPD-Link III 串行器 \| RHS \| 48 \| -40 to 105	获取价格
DS90UB926Q	TI	5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel	获取价格
DS90UB926Q-Q1	TI	具有双向控制通道的 5-85MHz 24 位彩色 FPD-Link III 解串器	获取价格
DS90UB926QSQ	TI	5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel	获取价格