DS90UR908QSQE/NOPB [TI]
5 - 65MHz 24 位色彩 FPD-Link II 至 FPD 链接转换器 | RHS | 48 | -40 to 105;
| 型号： | DS90UR908QSQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5 - 65MHz 24 位色彩 FPD-Link II 至 FPD 链接转换器 | RHS | 48 | -40 to 105 驱动 光电二极管 接口集成电路 驱动器 转换器 |
| 文件： | 总35页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
DS90UR908Q 5 - 65MHz 24 位彩色平面显示器-链路 (FPD-Link) II 至
FPD-Link 转换器
查询样品: DS90UR908Q-Q1
1
特性
说明
2
•
支持 5 – 65MHz（140Mbps 至 1.82Gbps 串行链
路）
DS90UR908Q 将 FPD-Link II 转换为 FPD-Link。 它
将一个单对线 (FPD-Link II) 上具有嵌入时钟的高速串
行化接口转换为 4 个低压差分信令 (LVDS) 数据/控制
数据流和 1 个 LVDS 时钟对 (FPD-Link)。 这个串行总
线方案消除了时钟和数据间的偏差问题，从而大大简化
了系统设计，减少了控制器引脚数量，并且减少了互连
线尺寸、重量和成本，并从总体上简化了印刷电路板
(PCB) 布局布线。 此外，内部 DC 均衡编码被用来支
持 AC 耦合互连。
•
5 通道（4 个数据 + 1 个时钟）FPD-Link 驱动器输
入
•
•
•
长度达 10 米的 AC 耦合生成树协议 (STP) 互连
集成型输入端接
全速 (@ Speed) 链路内置自检 (BIST) 模式和报告
引脚
•
•
•
•
•
•
•
•
•
•
•
•
可选 I2C 兼容串行控制总线
RGB888 + VS，HS，DE 支持
DS90UR908Q 转换器恢复数据 (RGB) 和控制信号并
从一个串行数据流 (FPD-Link II) 中提取时钟。 它能够
锁定进入数据流，而无需使用一个协商序列或特别的
SYNC（同步）模式，也不需要一个基准时钟。 提供
了一个链路状态 (LOCK) 输出信号。
断电模式大大减少了功率耗散
快速随机数据锁定；无需基准时钟
可调输入接收器均衡
LOCK（锁定）（实时链路状态）报告引脚
低电磁干扰 (EMI) FPD-Link 输出
针对低 EMI 的展频时钟生成 (SSCG) 选项
1.8V 或 3.3V 兼容 LVCMOS I/O 接口
汽车应用级产品：符合 AEC-Q100 2 级要求
>8kV 人体模型 (HBM) 和静电放电 (ESD) 耐受
向后兼容模式以实现与之前生产的器件的共同运行
串行输入数据流的可调输入均衡为线缆的传输介质损耗
提供补偿，并减少了介质引起的确定性抖动。 低压差
分信令的使用、输出电压电平选择特性和额外的输出展
频生成大大减少了 EMI。
由于连接至显示屏物理接口的接线更少，使用 LVDS
技术的 FPD-Link 输入非常适合于高速、低功率和低
EMI 数据传输。
应用范围
•
•
汽车导航显示屏
汽车娱乐系统显示屏
DS90UR908Q 采用 48 引脚超薄四方扁平无引线封装
(WQFN) 封装，并可在 -40˚C 至 +105˚C 的汽车 AEC-
Q100 2 级额定温度范围内运行。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
English Data Sheet: SNLS317
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
Applications Diagram
FPD-Link
FPD-Link II
FPD-Link
VDDIO
VDDIO
(1.8V or 3.3V)
(1.8V or 3.3V)
1.8V
1.8V 3.3V
RxIN3+/-
RxIN2+/-
TxOUT3+/-
TxOUT2+/-
High-Speed Serial Link
1 Pair/AC Coupled
DOUT+
DOUT-
RIN+
RIN-
HOST
Graphics
Processor
RGB Display
QVGA to XGA
24-bit Color Depth
RxIN1+/-
RxIN0+/-
TxOUT1+/-
TxOUT0+/-
100 ohm STP Cable
RxCLKIN+/-
TxCLKOUT+/-
DS90UR907Q
Converter
DS90UR908Q
Converter
CMF
LOCK
PASS
SSC[2:0]
PDB
BISTEN
VODSEL
De-Emph
LFMODE
CONFIG[1:0]
MAPSEL
MAPSEL
CONFIG[1:0]
PDB
BISTEN
SCL
SDA
ID[x]
SCL
SDA
ID[x]
OEN
OSSEL
VODSEL
Optional
Optional
Pin Diagram
RES
TxOUT0-
TxOUT0+
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
VDDA
GND
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
GND
RIN+
RIN-
DS90UR908Q
TOP VIEW
CMF
VDDA
GND
DAP = GND
GND
VDDSC
VDDSC
GND
VDDTX
2
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
Pin Name
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
PIN DESCRIPTIONS(1)
Description
Pin #
I/O, Type
FPD-Link II Input Interface
RIN+
RIN-
CMF
40
41
42
I, LVDS
I, LVDS
I, Analog
True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[3:0]+
15,19, 21,
23
O, LVDS
O, LVDS
True LVDS Data Output
TxOUT[3:0]-
16,20, 22,
24
Inverting LVDS Data Output
TxCLKOUT+
TxCLKOUT-
17
18
O, LVDS
O, LVDS
True LVDS Clock Output
Inverting LVDS Clock Output
LVCMOS Outputs
LOCK 27
O, LVMOS
LOCK Status Output
LOCK = 1, PLL is locked, output states determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN, Table 3
May be used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB
1
I, LVCMOS
Power Down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the outputs are TRI-STATE. Control registers are
RESET.
VODSEL
33
I, LVCMOS
FPD-Link Output Voltage Select, Table 4
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
OEN
30
35
36
I, LVCMOS
w/ pull-down
Output Enable Input, Table 3
OSS_SEL
LFMODE
I, LVCMOS
w/ pull-down
Output Sleep State Select Input, Table 3
I, LVCMOS
Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz)
MAPSEL
34
I, LVCMOS
FPD-Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on TxOUT3+/-, Figure 16
MAPSEL = 0, LSB on TxOUT3+/-, Figure 15
CONFIG[1:0]
11,10
I, LVCMOS
Operating Modes — Pin or Register Control
w/ pull-down Determine the device operating mode and interfacing device, Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241 or DS99R421
CONFIG[1:0] = 11: Interfacing to DS90C241
SSC[2:0]
RES
7, 3, 2
37
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select, See Table 5 and Table 6
I, LVCMOS
Reserved
w/ pull-down Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon power-
up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
28 [PASS]
STRAP
I, LVCMOS
EQ Gain Control of FPD-Link II Input
EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
(1) 1 = High, 0 = Low
Copyright © 2009–2013, Texas Instruments Incorporated
3
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
PIN DESCRIPTIONS(1) (continued)
Pin Name
Pin #
I/O, Type
Description
Optional BIST Mode
BISTEN
PASS
29
28
I, LVCMOS
BIST Enable Input – Optional
w/ pull-down BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
O, LVCMOS PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
SDA
ID[x]
5
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain
I, Analog
SDA requires an external pull-up resistor to VDDIO.
12
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail, Table 7
Power and Ground
VDDL
VDDA
VDDP
VDDSC
VDDTX
VDDIO
6, 31
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
38, 43
8
Analog Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
46, 47
13
SSC Generator Power, 1.8 V ±5%
FPD-Link Power, 3.3 V ±10%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
Ground
25
GND
9, 14, 26,
32, 39, 44,
45, 48
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
Block Diagram
DS90UR908Q œ CONVERTER
SSC[2:0]
OEN
VODSEL
SSCG
CMF
TxOUT[3]
TxOUT[2]
RIN+
RIN-
TxOUT[1]
TxOUT[0]
TxCLKOUT
EQ
Error
Detector
PASS
PDB
SCL
SCA
LOCK
Timing and
Control
ID[x]
PLL
BISTEN
OSS_SEL
LFMODE
Figure 1. FPD-Link II to FPD-Link Convertor
4
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDTX (3.3V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
−0.3V to +2.5V
−0.3V to +4.0V
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDDTX + 0.3V)
+150°C
Receiver Input Voltage
LVDS Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
48L WQFN Package
Maximum Power Dissipation Capacity at 25°C
Derate about 25°C
1/ θJA°C/W
27.7 °C/W
3.0 °C/W
θJA
θJC
ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pFs
Air Discharge (RIN+, RIN−
)
≥±15 kV
≥±8 kV
Contact Discharge (RIN+, RIN−
)
ESD Rating (ISO10605), RD = 330Ω, CS = 150/330pF
ESD Rating (ISO10605), RD = 2kΩ, CS = 150/330pF
Air Discharge (RIN+, RIN−
)
≥±15 kV
≥±8 kV
Contact Discharge (RIN+, RIN−
)
ESD Rating (HBM)
≥±8 kV
ESD Rating (HBM)
≥±8 kV
ESD Rating (CDM)
≥±1.25 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) For soldering specifications see product folder at www.ti.com and SNOA549
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
1.71
1.71
3.0
Nom
1.8
Max
1.89
1.89
3.6
Units
V
Supply Voltage (VDDn
LVCMOS Supply Voltage (VDDIO) OR
LVCMOS Supply Voltage (VDDIO
)
1.8
V
)
3.3
V
Operating Free Air Temperature (TA)
TxCLKOUT Frequency
Supply Noise(1)
−40
5
+25
+105
65
°C
MHz
mVP-P
100
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
Copyright © 2009–2013, Texas Instruments Incorporated
5
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
DC Electrical Characteristics(1)(2)(3)(4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link LVDS Output
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
VODSEL = H
VODSEL = L
VODSEL = H
100
200
250
450
500
900
4
400
600
mV
mV
|VOD
|
Differential Output Voltage
mVp-p
mVp-p
mV
Differential Output Voltage
A-B
VODp-p
ΔVOD
VOS
RL = 100Ω
Figure 8
TxCLKOUT+,
TxCLKOUT-,
TxOUT[3:0]+,
TxOUT[3:0]-
Output Voltage Unbalance
Offset Voltage
50
1.0
-10
1.2
1.2
1
1.5
V
V
ΔVOS
Offset Voltage Unbalance
Output Short Circuit Current
50
mV
IOS
Vout = GND
OEN = GND,
Vout =VDDTX, or GND
-5
mA
IOZ
Output TRI-STATE® Current
+10
µA
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
PDB,
VODSEL,
OEN,
2.2
VDDIO
0.8
V
V
GND
OSS_SEL,
MAPSEL,
LFMODE,
SSC[2:0],
BISTEN
IIN
Input Current
VIN = 0V or VDDIO
-15
±1
+15
μA
VDDIO
0.25
-
VOH
High Level Output Voltage
IOH = −2 mA
VDDIO
V
VOL
IOS
Low Level Output Voltage
Output Short Circuit Current
IOL = +2 mA
VOUT = 0V
GND
-45
0.2
V
LOCK, PASS
mA
PDB = 0V, OSS_SEL = 0V, VOUT = 0V
or VDDIO
IOZ
TRI-STATE® Output Current
-10
+10
µA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
PDB,
VODSEL,
OEN,
OSS_SEL,
MAPSEL,
LFMODE,
SSC[2:0],
BISTEN
0.7*
VDDIO
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VDDIO
V
V
0.3*
VDDIO
GND
IIN
Input Current
VIN = 0V or VDDIO
-10
±1
+10
μA
VDDIO
- 0.2
VOH
High Level Output Voltage
IOH = −2 mA
VDDIO
V
VOL
IOS
IOZ
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE® Output Current
IOL = +2 mA
GND
0.2
V
LOCK, PASS
VOUT = 0V
-13
mA
µA
VOUT = 0V or VDDIO
-15
+15
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(3) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
(4) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
6
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
DC Electrical Characteristics(1)(2)(3)(4) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II LVDS RECEIVER DC SPECIFICATIONS
Differential Input Threshold
High Voltage
VTH
+50
mV
mV
VCM = +1.2V (Internal VBIAS
)
Differential Input Threshold Low
Voltage
VTL
-50
80
RIN+, RIN-
Common Mode Voltage,
Internal VBIAS
VCM
RT
1.2
V
Input Termination
100
120
95
Ω
SUPPLY CURRENT
All VDD(1.8)
pins
IDD1
VDDn= 1.89V
85
mA
Checker Board Pattern,
VODSEL = H
SSC{2:0] = 000
Figure 2
Supply Current
(includes load current)
65 MHz Clock
IDDTX1
IDDIO1
VDDTX = 3.6V VDDTX
40
0.3
0.8
50
0.8
1.5
mA
mA
mA
VDDIO=1.89V
VDDIO
VDDIO = 3.6V
All VDD(1.8)
pins
IDD2
VDDn= 1.89V
95
mA
Checker Board Pattern,
VODSEL = H
SSC[2:0] = 111
Figure 2
Supply Current
(includes load current)
65 MHz Clock
IDDTX2
VDDTX = 3.6V VDDTX
40
0.3
0.8
mA
mA
mA
VDDIO=1.89V
VDDIO
IDDIO2
VDDIO = 3.6V
All VDD(1.8)
pins
IDDZ
VDD= 1.89V
0.15
2.00
mA
PDB = 0V, All other
LVCMOS Inputs = 0V
IDDTXZ
VDDTX = 3.6V VDDTX
0.01
0.01
0.01
0.10
0.08
0.08
mA
mA
mA
Supply Current Power Down
VDDIO=1.89V
VDDIO
IDDIOZ
VDDIO = 3.6V
Copyright © 2009–2013, Texas Instruments Incorporated
7
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II
SSC[2:0] = 000
5 MHz
5 MHz
65 MHz
65 MHz
7
14
6
ms
ms
ms
ms
SSC[2:0] = 111
SSC[2:0] = 000
SSC[2:0] = 111
tDDLT
Lock Time, Figure 7(1)
8
Input Jitter Frequency <
2 MHz
>0.9
UI
UI
EQ = Off
tIJIT
Input Jitter Tolerance, Figure 10 SSC[2:0] = 000
Input Jitter Frequency >
6 MHz
TxCLKOUT± = 65 MHz
> 0.5
FPD-Link Output
tTLHT
tTHLT
tDCCJ
Low to High Transition Time
0.3
0.3
900
75
0.6
0.6
ns
ns
ps
ps
TxCLKOUT±,
TxOUT[3:0]±
RL = 100Ω
High to Low Transition Time
5 MHz
2100
125
Cycle-to-Cycle Output
Jitter(2)(3)(4)
TxCLKOUT±
65 MHz
tTTP1
tTTP0
tTPP6
tTTP5
tTTP4
tTTP3
tTTP2
ΔtTTP
Transmitter Pulse Position for
bit 1
1
2
3
4
5
6
7
UI
UI
UI
UI
UI
UI
UI
Transmitter Pulse Position for
bit 0
Transmitter Pulse Position for
bit 6
Transmitter Pulse Position for
bit 5
5 - 65 MHz, Figure 9
TxOUT[3:0]±
Transmitter Pulse Position for
bit 4
Transmitter Pulse Position for
bit 3
Transmitter Pulse Position for
bit 2
Offset Transmitter Pulse
Position (bit 6— bit 0)
65 MHz, Figure 9
SeeFigure 4
< +0.1
10*T
7
UI
T
tDD
Delay-Latency
tTPDD
Power Down Delay, active to
OFF
65 MHz, Figure 5
65 MHz, Figure 6
12
55
ns
ns
tTXZR
Enable Delay, OFF to active
40
LVCMOS Outputs
tCLH Low to High Transition Time
tCHL
5
5
15
15
ns
ns
ns
ns
CL = 8 pF, Figure 3
LOCK, PASS
PASS
High to Low Transition Time
5 MHz
570
50
580
65
BIST PASS Valid Time,
BISTEN = 1, Figure 11
tPASS
65 MHz
SSCG Mode
fDEV
Spread Spectrum
Clocking Deviation
Frequency
TxCLKOUT = 5 to 65
MHz,
SSC[2:0] = ON
See(4)
See(4)
±0.5
8
±2
%
fMOD
Spread Spectrum
Clocking Modulation
Frequency
TxCLKOUT = 5 to 65
MHz,
SSC[2:0] = ON
100
kHz
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(3) Specification is ensured by characterization and is not tested in production.
(4) Specification is ensured by design and is not tested in production.
8
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Recommended Timing for the Serial Control Bus
Over 3.3V operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
0
Typ
Max
100
400
Units
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
kHz
0
tLOW
SCL Low Period
SCL High Period
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
us
us
us
us
us
tHIGH
Standard Mode
Fast Mode
tHD;STA Hold time for a start or a
repeated start condition,
Figure 12
Standard Mode
Fast Mode
0.6
4.7
0.6
us
us
us
tSU:STA Set Up time for a start or a
repeated start condition,
Figure 12
Standard Mode
Fast Mode
tHD;DAT Data Hold Time, Figure 12
Standard Mode
Fast Mode
0
3.45
0.9
us
us
ns
ns
us
us
us
us
ns
ns
ns
ns
0
tSU;DAT Data Set Up Time, Figure 12
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
tSU;STO Set Up Time for STOP
Condition, Figure 12
Standard Mode
Fast Mode
tBUF
Bus Free Time Between STOP Standard Mode
and START, Figure 12
Fast Mode
tr
SCL & SDA Rise Time,
Figure 12
Standard Mode
Fast Mode
1000
300
300
300
tf
SCL & SDA Fall Time,
Figure 12
Standard Mode
Fast mode
DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
0.7*
VDDIO
Input High Level
SDA and SCL
SDA and SCL
VDDIO
V
VIL
0.3*
VDDIO
Input Low Level Voltage
Input Hysteresis
GND
V
VHY
VOL
Iin
>50
mV
V
SDA, IOL = 0.5mA
0
0.36
+10
SDA or SCL, Vin = VDDIO or GND
-10
µA
ns
ns
ns
ns
ns
pF
tR
SDA RiseTime – READ
SDA Fall Time – READ
800
50
SDA, RPU = X, Cb ≤ 400pF, Figure 12
tF
tSU;DAT Set Up Time — READ
tHD;DAT Hold Up Time — READ
540
600
50
See Figure 12
SDA or SCL
tSP
Cin
Input Filter
Input Capacitance
<5
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AC Timing Diagrams and Test Circuits
+V
OD
TxCLKOUT
-V
OD
+V
OD
TxOUT[odd]
-V
OD
+V
OD
TxOUT[even]
-V
OD
Cycle N
Cycle N+1
Figure 2. Checkerboard Data Pattern
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 3. LVCMOS Transition Times
START
BIT
STOP START
BIT BIT
STOP START
BIT BIT
STOP START STOP
BIT BIT BIT
SYMBOLN+3
SYMBOLN
SYMBOLN+1
SYMBOLN+2
R
0-23
IN
2
3
2
3
2
3
2
3
0
1
2
0
1
2
0
1
2
0
1
2
DCA, DCB
t
DD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Delay – Latency
PDB
VILmax
RIN
X
t
TPDD
LOCK
PASS
Z
Z
TxCLKOUT
TxOUT[3:0]
Z
Z
Figure 5. FPD-Link & LVCMOS Powerdown Delay
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PDB
LOCK
t
TXZR
OEN
VIHmin
Z
Z
TxCLKOUT
TxOUT[3:0]
Figure 6. FPD-Link Outputs Enable Delay
PDB
VIH(min)
R ±
IN
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 7. PLL Lock Times
|VOD|
VOS
GND
+VOD
0V
VODp-p
-VOD
t
t
THLT
TLHT
Figure 8. FPD-Link (LVDS) Single-ended and Differential Waveforms
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Cycle N
TxCLKOUT±
TxOUT[3:0]±
bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
t
t
t
TTP1
TTP2
TTP3
1UI
2UI
Dt
3UI
4UI
TTP
t
t
TTP4
TTP5
5UI
6UI
7UI
t
t
TTP6
TTP7
Figure 9. FPD-Link Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
tIJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t
IJIT
Figure 10. Receiver Input Jitter Tolerance
BISTEN
VIL
MAX
t
PASS
PASS
(w/ errors)
VOL
MAX
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 11. BIST PASS Waveform
12
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tr
tf
tBUF
SDA
tSU;DAT
tHD;STA
tSU;STO
tLOW
tSP
tf
tSU;STA
tHD;DAT
SCL
tr
tHIGH
tHD;STA
S
Sr
P
S
Figure 12. Serial Control Bus Timing Diagram
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Functional Description
The DS90UR908Q receives 27-bits of data (24-high speed bits and 3 low speed bits) over a single serial FPD-
Link II pair operating at 140Mbps to 1.82Gbps. The serial stream contains an embedded clock, video control
signals and the DC-balance information which enhances signal quality and supports AC coupling. The receiver
converts the serial stream into a 5-channel (4 data and 1 clock) FPD-Link LVDS Interface. The device is intended
to be used with the DS90UR907Q or the DS90UR905Q FPD-Link II serializers, but is backward compatible with
previous generation of FPD-Link II as well.
The device converts a single input serial data stream to a FPD-Link output bus, and also provides a signal check
for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the
optional serial control bus. It features enhance signal quality on the link by supporting the FPD-Link II data
coding that provides randomization, scrambling, and DC balancing of the data. It also includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data, FPD-Link LVDS Output interface, and also the output spread spectrum clock generation (SSCG) support.
The power saving features include a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
The DS90UR908Q can lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. It also synchronizes to the serializer regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The DS90UR908Q recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream.
The DS90UR907Q / DS90UR908Q chipset supports 24-bit color depth, HS, VS and DE video control signals and
up to three over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS90UR908Q will receive a pixel of data in the following format: C1 and C0 represent the embedded clock
in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled data. DCB is the
DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit
determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically.
Figure 13 illustrates the serial stream per PCLK cycle.
Note: The figure only illustrates the bits but does not actually represent the bit location as the bits are scrambled
and balanced continuously.
b
1
0
b
1
1
D
C
A
b
0
b
1
b
2
b
3
b
5
b
9
C
1
b
4
b
6
b
7
b
8
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 13. FPD-Link II Serial Stream
The device supports clocks in the range of 5 MHz to 65 MHz. With every clock cycle 24 bits of payload are
received along with the four overhead bits. Thus, the line rate is 1.82 Gbps maximum (140 Mbps minimum) with
an effective data rate of 1.56 Gbps maximum. The link is extremely efficient at 86% (24/28).
OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR908Q is backward compatible with previous generations of FPD-Link II serializers. Configuration
modes are provided for backwards compatibility with the DS90C241 FPD-Link II Generation 1, and also the
DS90UR241 or DS99R421 FPD-Link II Generation 2 serializer by setting the respective mode with the
CONFIG[1:0] pins as shown in Table 1. The selection also determine whether the Video Control Signal filter
feature is enabled or disabled in Normal mode. This feature may be controlled by pin or by Register.
14
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Table 1. DS90UR908Q Configuration Modes
CONFIG1
CONFIG0
Mode
Des Device
L
L
L
H
L
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
Backwards Compatible GEN1
DS90UR907Q, DS90UR905Q
DS90UR907Q, DS90UR905Q
DS90UR241, DS99R421
DS90C241
H
H
H
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
Normal Mode with Control Signal Filter Disabled:
–
DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 14.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
HS/VS/DE
OUT
Figure 14. Video Control Signal Filter Wavefrom
COLOR BIT MAPPING SELECT
The DS90UR908Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs
on TxOUT[3] shown in Figure 15 or MSBs on TxOUT[3] shown in Figure 16. The user selects which mapping
scheme is controlled by MAPSEL pin or by Register.
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TxCLKOUT +/-
Previous cycle
Current cycle
R[1]
(bit 22)
R[0]
(bit 21)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
TxOUT3 +/-
DE
VS
HS
B[7]
B[6]
B[5]
B[4]
(bit 20)
(bit 19)
(bit 18)
(bit 17)
(bit 16)
(bit 15)
(bit 14)
TxOUT2 +/-
TxOUT1 +/-
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
TxOUT0 +/-
Figure 15. 8–bit FPD-LInk Mapping: LSB's on TxOUT3
TxCLKOUT +/-
Previous cycle
Current cycle
B[7]
(bit 26)
R[7]
(bit 22)
R[6]
(bit 21)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
TxOUT3 +/-
TxOUT2 +/-
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
TxOUT1 +/-
TxOUT0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 16. 8–bit FPD-LInk Mapping: MSB's on TxOUT3
FPD-LINK II INPUT
Common Mode Filter Pin (CMF) — Optional
The DS90UR908Q provides access to the center tap of the internal termination. A capacitor may be placed on
this pin for additional common-mode filtering of the differential pair. This can be useful in high noise
environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Input Equalizer Gain (EQ)
The DS90UR908Q can enable receiver input equalization of the serial stream to compensate the cable loss and
increase the eye opening to the input. The equalization feature may be controlled by the EQ pin (strap option)
Table 4 or by register Table 8.
16
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Table 2. EQ Pin Configuration Table
EQ (Strap Option)
Effect
EQ = Off
~12 dB
L
H
POWER SAVING FEATURES
PowerDown Feature (PDB)
The DS90UR908Q has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the Des when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream
stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and
output valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Stop Stream SLEEP Feature
The DS90UR908Q will enter a low power SLEEP state when the input serial stream is stopped. A STOP
condition is detected when the embedded clock bits are not present. When the serial stream starts again, the
Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional
Serial Bus Control Registers values are RETAINED.
OUTPUT INTERFACES (LVCMOS & FPD-LINK)
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is Low and the FPD-Link
interface state is determined by the state of the OSS_SEL pin.
After the DS90UR908Q completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the FPD-Link outputs. The TxCLK
output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered
clock (or vice versa). Note that the FPD-Link outputs may be held in an inactive state (TRI-STATE) through the
use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
Table 3. Output State Table
INPUTS
OEN
OUTPUTS
OTHER OUTPUTS
PDB
OSS_SEL
LOCK
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
L
X
X
L
X
X
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
L
H
H
H
L
H
H
X
L
L
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE or OSC Output through Register bit
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
H
L
L
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
H
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
H
H
X
H
(Normal operating mode)
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LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS outputs can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility. The 1.8 V
levels will offer a system power savings. This applies to the following pins: PASS and LOCK.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is controlled by the VODSEL input.
Table 4. VODSEL Configuration Table
VODSEL
Result
L
VOD is 250mV TYP (500mVp-p)
VOD is 400mV TYP (800mVp-p)
H
SSCG GENERATION — OPTIONAL
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 5 and Table 6. This feature may be controlled by pins
or by register. The LFMODE should be set appropriately if the SSCG is being used. Set LFMODE High if the
clock frequency is between 5 MHz and 20 MHz, set LFMODE Low if the clock frequency is between 20 MHz and
65 MHz.
Table 5. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
Result
LFMODE = L (20 - 65 MHz)
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.9
fmod (kHz)
L
L
L
L
L
H
L
OFF
L
H
H
L
±1.2
CLK/2168
CLK/1300
L
H
L
±1.9
H
H
H
H
±2.3
L
H
L
±0.7
H
H
±1.3
H
±1.7
Table 6. SSCG Configuration (LFMODE = H) — Des Output
SSC[2:0] Inputs
Result
LFMODE = H (5 - 20 MHz)
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.7
fmod (kHz)
L
L
L
L
L
H
L
OFF
L
H
H
L
±1.3
CLK/625
CLK/385
L
H
L
±1.8
H
H
H
H
±2.2
L
H
L
±0.7
H
H
±1.2
H
±1.7
18
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Frequency
fdev(max)
F
F
PCLK+
F
PCLK
fdev(min)
Time
PCLK-
1/fmod
Figure 17. SSCG Waveform
OSCILLATOR OUTPUT — OPTIONAL
The DS90UR908Q provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin and the register. See Table 3, Table 8, and Figure 18.
PDB
RIN
active serial stream
X
(Diff.)
H
H
LOCK
TxOUT[3:0]
TxCLKOUT
L
L
L
Z
Z
Z
Z
Z
Z
f
f
Z
Z
PASS
OFF
Active
OSC Output
Active
OFF
OSC Output
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Figure 18. TxCLKOUT Output Oscillator Option Enabled
Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only an input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
The PASS output pin toggles to flag any payloads that are received with 1 to 24 bit errors. The BISTM pin
selects the operational mode of the PASS pin. If BISTM = L, the PASS pins reports the final result only. If BISTM
= H, the PASS pins counts payload errors and also results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the Des BISTEN pin.
Sample BIST Sequence
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See Figure 19 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q or DS90UR905Q in BIST Mode by setting BISTEN = H. The BIST Mode is
enabled via the BISTEN pin. An RxCLKIN or PCLK is required for all the Ser options. When the DS90UR908Q
detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut
off.
Step 2: Place the DS90UR908Q in BIST mode by setting the BISTEN = H. The Device is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the DS90UR908Q BISTEN pin is set Low. It stops checking the data and the
final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one
or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 20 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 19. BIST Mode Flow Diagram
20
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BISTEN
(Serializer)
BISTEN
(DS90UR908Q)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
X
X
PASS
X = bit error(s)
DATA
(internal)
X
PASS
FAIL
Prior Result
BIST
Result
Normal
PRBS
Normal
BIST Test
BIST Duration
Held
Figure 20. BIST Waveforms
Serial Bus Control — Optional
The DS90UR908Q may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 21.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
V
10k
DDIO
ID[X]
4.7k
4.7k
R
ID
HOST
DS90UR908Q
SCL
SDA
SCL
SDA
To other
Devices
Figure 21. Serial Control Bus Connection
Copyright © 2009–2013, Texas Instruments Incorporated
21
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 22. START and STOP Conditions
The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 7 for the Des. Do not tie ID[x] directly to ground.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 22.
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 7. ID[x] Resistor Value
Resistor
RID kΩ
(5%tol)
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
k
Figure 23. Serial Control Bus — READ
Register Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
Figure 24. Serial Control Bus — WRITE
22
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
Table 8. Serial Bus Control Registers
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
0
0
Des Config 1
7
6
R/W
R/W
0
LFMODE
MAPSEL
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
0
FPD-Link Map Select
0: LSB on TxOUT3+/-
1: MSB on TxOUT3+/-
5
4
R/W
R/W
R/W
0
0
Reserved
Reserved
CONFIG
Reserved
Reserved
3:2
00
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards Compatible (DS90UR241)
11: Backwards Compatible (DS90C241)
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG Control
0: Configurations set from control pins / STRAP pin
1: Configurations set from registers (except I2C_ID)
1
2
1
2
Slave ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 11100 ID[X]
00
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71); 8b ' 1110 0010 (h'E2)
7b '1110 010 (h'72); 8b ' 1110 0100 (h'E4)
7b '1110 011 (h'73); 8b ' 1110 0110 (h'E6)
7b '1110 110 (h'76); 8b ' 1110 1100 (h'EC)
All other addresses are Reserved.
Des Features 1
7
6
R/W
R/W
R/W
R/W
0
0
OEN
Output Enable Input, Table 3
Output Sleep State Select, Table 3
Reserved
OSS_SEL
Reserved
VODSEL
5:4
3
00
0
Differential Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
2:0
R/W
00
OSC_SEL
000: OFF
001: Reserved
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
Copyright © 2009–2013, Texas Instruments Incorporated
23
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
Table 8. Serial Bus Control Registers (continued)
ADD ADD Register Name
(dec) (hex)
Bit(s)
R/W Defau Function
Description
lt
(bin)
3
3
Des Features 2
7:5
R/W
000 EQ Gain
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
4
R/W
0
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
3
R/W
R/W
Reserved
Reserved
2:0
000 SSC
IF LFMODE = 0, then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/1300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
000: SSCG OFF
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
24
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS90UR908Q, in conjunction with the DS90UR907Q or DS90UR905Q, is intended for interfacing between a
host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768
display formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three
control bits (VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 65 MHz. The device
may also be used in 18-bit color applications. In this application three to six general purpose signals may also be
send from host to display.
TYPICAL APPLICATION CONNECTION
Figure 25 shows a typical application of the DS90UR908Q for a 65 MHz XGA Display. The LVDS inputs utilize
100 nF coupling capacitors to the line and the Receiver provides internal termination. Bypass capacitors are
placed near the power supply pins. Ferrite beads are placed on the power lines for effective noise suppression.
DS90UR908Q
3.3V
1.8V
FB4
FB1
VDDL
VDDTX
C6
C7
C11
C3
C4
C8
C12
C9
VDDL
FB2
VDDIO
FB5
VDDA
VDDA
VDDIO
C13
C10
FB3
VDDP
C5
VDDSC
VDDSC
TxCLKOUT+
TxCLKOUT-
C1
C2
TxOUT3+
TxOUT3-
TxOUT2+
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
RIN+
FPD-Link
Interface
Serial
FPD-Link II
Interface
LVDS
100 Ohm
Termination
RIN-
CMF
C14
BISTEN
PDB
Host
Control
LOCK
PASS
R
C15
1.8V
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
10k
RID
ID[X]
SCL
SDA
C1 - C2 = 0.1 mF (50 WV)
C3 œ C10 = 0.1 mF
C11 - C14 = 4.7 mF
C15 = >10 mF
CONFIG1
CONFIG0
RES
GND
8
SSC[2]
SSC[1]
SSC[0]
DAP (GND)
R = 10 kW
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 kW
Low DC resistance ( <1W)
Figure 25. DS90UR908Q Typical Connection Diagram
Copyright © 2009–2013, Texas Instruments Incorporated
25
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn), VDDTX and VDDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies
may power up in any order, however device operation should be initiated only after all supplies are in their valid
operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this
optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done
by simply holding the PDB pin at a Low, or with an external RC delay based off the VDDIO rail which would then
need to lag the others in time. If the PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a
10 uF cap to GND to delay the PDB input signal.
TRANSMISSION MEDIA
The FPD-Link II chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The serializer and deserializer provide internal terminations providing a clean signaling
environment. The interconnect for LVDS should present a differential impedance of 100 Ω. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-
shielded cables may be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR908Q to attain lock to the active data stream
during a live insertion event.
ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit and 18-bit
Applications. When connecting to earlier generations of FPD-Link II serializer devices, a color mapping review is
recommended to ensure the correct connectivity is obtained. Table 9 provides examples for interfacing between
DS90UR908Q and different deserializers.
Table 9. Alternate Color / Data Mapping
FPD-Link
Bit Number
RGB (LSB
Example)
DS90UR905Q
DS90UR241
DS99R421
DS90C241
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
TxOUT3
N/A
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
TxOUT2
RxIN2
TxOUT1
RxIN1
Bit 8
DIN8
DIN8
Bit 7
DIN7
DIN7
26
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
FPD-Link
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
Table 9. Alternate Color / Data Mapping (continued)
Bit Number
RGB (LSB
Example)
DS90UR905Q
DS90UR241
DS99R421
DS90C241
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
G2
R7
R6
R5
R4
R3
R2
G2
R7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN23
DIN22
DIN21
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN23
DIN22
DIN21
R6
TxOUT0
R5
RxIN0
R4
R3
R2
N/ADIN12
OS2
OS1
OS0
DS90UR908Q
Settings
MAPSEL = 0
CONFIG [1:0] =
00
CONFIG [1:0] = 10
CONFIG [1:0] =
11
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50µF to 100µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
Copyright © 2009–2013, Texas Instruments Incorporated
27
DS90UR908Q-Q1
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com.cn
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
28
Copyright © 2009–2013, Texas Instruments Incorporated
DS90UR908Q-Q1
www.ti.com.cn
ZHCSB30H –SEPTEMBER 2009–REVISED APRIL 2013
Revision History
•
•
•
•
03/30/2010 — Initial Release
07/26/2010 — Update all final AC and DC parameter limits
08/09/2010 — Update Pin Description of VODSEL
04/16/2013 — Changed layout of National Data Sheet to TI format
Copyright © 2009–2013, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UR908QSQ/NOPB
DS90UR908QSQE/NOPB
DS90UR908QSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
90UR908Q
SN
SN
90UR908Q
90UR908Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UR908QSQ/NOPB WQFN
DS90UR908QSQE/NOPB WQFN
DS90UR908QSQX/NOPB WQFN
RHS
RHS
RHS
48
48
48
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
1.3
1.3
1.3
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UR908QSQ/NOPB
DS90UR908QSQE/NOPB
DS90UR908QSQX/NOPB
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000
250
356.0
208.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
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