DS91D176TMAX [TI]
DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers; DS91D176 / DS91C176 100MHz的单通道M- LVDS收发器
| 型号： | DS91D176TMAX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers |
| 文件： | 总19页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS91C176, DS91D176
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SNLS146L –MARCH 2006–REVISED APRIL 2013
DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers
Check for Samples: DS91C176, DS91D176
1
FEATURES
DESCRIPTION
The DS91C176 and DS91D176 are 100 MHz single
2
•
•
•
•
DC to 100+ MHz / 200+ Mbps Low Power, Low
EMI Operation
channel M-LVDS (Multipoint Low Voltage Differential
Signaling) transceivers designed for applications that
utilize multipoint networks (e.g. clock distribution in
ATCA and uTCA based systems). M-LVDS is a new
bus interface standard (TIA/EIA-899) optimized for
multidrop networks. Controlled edge rates, tight input
receiver thresholds and increased drive strength are
sone of the key enhancements that make M-LVDS
devices an ideal choice for distributing signals via
multipoint networks.
Optimal for ATCA, uTCA Clock Distribution
Networks
Meets or Exceeds TIA/EIA-899 M-LVDS
Standard
Wide Input Common Mode Voltage for
Increased Noise Immunity
•
•
•
•
DS91D176 has Type 1 Receiver Input
DS91C176 has Type 2 Receiver with Fail-safe
Industrial Temperature Range
The
DS91C176/DS91D176
are
half-duplex
transceivers that accept LVTTL/LVCMOS signals at
the driver inputs and convert them to differential M-
LVDS signals. The receiver inputs accept low voltage
differential signals (LVDS, B-LVDS, M-LVDS, LV-
PECL and CML) and convert them to 3V LVCMOS
signals. The DS91D176 has a M-LVDS type 1
receiver input with no offset. The DS91C176 has an
Space Saving SOIC-8 Package
M-LVDS type
functionality.
2 receiver which enable failsafe
Typical Application in an ATCA Clock Distribution Network
Slot Card N
Slot Card N+1
MLVDS Transceivers
MLVDS Transceivers
80W RT
80W RT
CLK1A (8 KHz)
CLK1B (8 KHz)
80W RT
80W RT
80W RT
80W RT
CLK2A (19.44 MHz)
CLK2B (19.44 MHz)
80W RT
80W RT
80W RT
80W RT
CLK3A (User Defined up to 100 MHz)
CLK3B (User Defined up to 100 MHz)
80W RT
80W RT
ATCA Backplane
Figure 1. System Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS91C176, DS91D176
SNLS146L –MARCH 2006–REVISED APRIL 2013
www.ti.com
Connection and Logic Diagram
Top View
Figure 2. SOIC Package
See Package Number D0008A
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
High
High
150 mV
50 mV
V
ID
0 V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 3. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNLS146L –MARCH 2006–REVISED APRIL 2013
(1)(2)
Absolute Maximum Ratings
Supply Voltage, VCC
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
−1.8V to +4.1V
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
833 mW
Derate SOIC Package
6.67 mW/°C above +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
150°C/W
63°C/W
θJC
Maximum Junction Temperature
Storage Temperature Range
150°C
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
260°C
ESD Ratings:
(HBM 1.5kΩ, 100pF)
≥ 8 kV
≥ 250 V
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
≥ 1000 V
(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
3.0
Typ
Max
3.6
Units
V
Supply Voltage, VCC
3.3
Voltage at Any Bus Terminal (Separate or Common-Mode)
Differential Input Voltage VID
−1.4
+3.8
2.4
V
V
LVTTL Input Voltage High VIH
2.0
0
VCC
0.8
V
LVTTL Input Voltage Low VIL
V
Operating Free Air Temperature TA
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2) (3) (4)
Parameter
Test Conditions
Min
Typ
Max
Units
M-LVDS Driver
|VAB
|
Differential output voltage magnitude
RL = 50Ω, CL = 5pF
See Figure 4 and Figure 6
480
−50
0.3
0
650
+50
2.1
mV
mV
V
ΔVAB
Change in differential output voltage magnitude
between logic states
0
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5pF
See Figure 4 and Figure 5
(VOS(PP) @ 500KHz clock)
1.8
|ΔVOS(SS)
|
Change in steady-state common-mode output
voltage between logic states
+50
mV
VOS(PP)
VA(OC)
VB(OC)
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
135
mV
V
See Figure 7
0
0
2.4
2.4
V
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2) All typicals are given for VCC = 3.3V and TA = 25°C.
(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4) CL includes fixture capacitance and CD includes probe capacitance.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)
Parameter
Test Conditions
Min
Typ
Max
Units
VP(H)
VP(L)
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
RL = 50Ω, CL = 5pF,CD = 0.5pF
See Figure 9 and Figure 10
1.2VSS
V
(5)
−0.2V
SS
V
IIH
High-level input current (LVTTL inputs)
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
Differential short-circuit output current
VIH = 2.0V
VIL = 0.8V
-15
15
15
μA
μA
V
IIL
-15
-1.5
-43
VIKL
IOS
IIN = -18mA
See Figure 8
43
mA
M-LVDS Receiver
VIT+ Positive-going differential input voltage threshold
See FUNCTION TABLES Type 1
20
94
50
mV
mV
mV
mV
V
Type 2
See FUNCTION TABLES Type 1
Type 2
150
VIT−
Negative-going differential input voltage threshold
−50
50
20
94
VOH
VOL
IOZ
High-level output voltage (LVTTL output)
Low-level output voltage (LVTTL output)
TRI-STATE output current
IOH = −8mA
2.4
2.7
0.28
IOL = 8mA
0.4
10
V
VO = 0V or 3.6V
−10
μA
mA
IOSR
Short-circuit receiver output current (LVTTL output) VO = 0V
-48
-90
M-LVDS Bus (Input and Output) Pins
IA
Transceiver input/output current
VA = 3.8V, VB = 1.2V
32
µA
µA
µA
µA
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V
VA = −1.4V, VB = 1.2V
VB = 3.8V, VA = 1.2V
−20
−32
+20
IB
Transceiver input/output current
32
VB = 0V or 2.4V, VA = 1.2V
VB = −1.4V, VA = 1.2V
−20
−32
−4
+20
IAB
Transceiver input/output differential current (IA − IB) VA = VB, −1.4V ≤ V ≤ 3.8V
+4
32
IA(OFF)
Transceiver input/output power-off current
Transceiver input/output power-off current
Transceiver input/output power-off differential
VA = 3.8V, VB = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
µA
µA
µA
µA
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
−20
−32
+20
VA = −1.4V, VB = 1.2V,
DE =VCC
0V ≤ VCC ≤ 1.5V
IB(OFF)
VB = 3.8V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
32
VB = 0V or 2.4V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
−20
−32
−4
+20
VB = −1.4V, VA = 1.2V,
DE = VCC
0V ≤ VCC ≤ 1.5V
IAB(OFF)
VA = VB, −1.4V ≤ V ≤ 3.8V,
DE = VCC
current (IA(OFF) − IB(OFF)
)
+4
0V ≤ VCC ≤ 1.5V
CA
Transceiver input/output capacitance
Transceiver input/output capacitance
Transceiver input/output differential capacitance
VCC = OPEN
9
9
pF
pF
pF
CB
CAB
CA/B
5.7
Transceiver input/output capacitance balance
(CA/CB)
1.0
(5) Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.
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SNLS146L –MARCH 2006–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)
Parameter
Test Conditions
Min
Typ
Max
Units
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
DE = GND, RE = VCC
20
6
29.5
9.0
mA
mA
mA
TRI-STATE Supply Current
Receiver Supply Current
DE = GND, RE = GND
14
18.5
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2)
Parameter
DRIVER AC SPECIFICATION
Test Conditions
Min
Typ
Max
Units
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
Figure 9 and Figure 10
1.3
1.3
3.4
3.1
300
5.0
5.0
420
1.3
3.0
3.0
8
ns
ns
tPHL
Differential Propagation Delay High to Low
(3) (4)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
Pulse Skew |tPLHD − tPHLD
|
ps
(5) (5)
Part-to-Part Skew
ns
(4)
Rise Time
1.0
1.0
1.8
1.8
ns
(4)
Fall Time
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
See Figure 11 and Figure 12
ns
tPZL
8
ns
tPLZ
8
ns
tPHZ
8
ns
(4)
(6)
tJIT
Random Jitter, RJ
100 MHz Clock Pattern
2.5
5.5
psrms
Mbps
fMAX
Maximum Data Rate
200
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
See Figure 13, Figure 14 and Figure 15
2.0
2.0
4.7
5.3
0.6
7.5
7.5
1.7
1.3
2.5
2.5
10
ns
ns
tPHL
Propagation Delay High to Low
(3) (4)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
Pulse Skew |tPLHD − tPHLD
|
ns
(5) (4)
Part-to-Part Skew
ns
(4)
Rise Time
0.5
0.5
1.2
1.2
ns
(4)
Fall Time
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
RL = 500Ω, CL = 15 pF
See Figure 16 and Figure 17
ns
tPZL
10
ns
tPLZ
10
ns
tPHZ
10
ns
fMAX
200
Mbps
(1) All typicals are given for VCC = 3.3V and TA = 25°C.
(2) CL includes fixture capacitance and CD includes probe capacitance.
(3) tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.
(5) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) Stimulus and fixture Jitter has been subtracted.
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Test Circuits and Waveforms
Figure 4. Differential Driver Test Circuit
A
~ 2.1V
B
~ 1.5V
DV
OS(SS)
V
OS
V
OS(PP)
Figure 5. Differential Driver Waveforms
Figure 6. Differential Driver Full Load Test Circuit
Figure 7. Differential Driver DC Open Test Circuit
6
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Figure 8. Differential Driver Short-Circuit Test Circuit
Figure 9. Driver Propagation Delay and Transition Time Test Circuit
Figure 10. Driver Propagation Delays and Transition Time Waveforms
Figure 11. Driver TRI-STATE Delay Test Circuit
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Figure 12. Driver TRI-STATE Delay Waveforms
Figure 13. Receiver Propagation Delay and Transition Time Test Circuit
Figure 14. Type 1 Receiver Propagation Delay and Transition Time Waveforms
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Figure 15. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 16. Receiver TRI-STATE Delay Test Circuit
Figure 17. Receiver TRI-STATE Delay Waveforms
FUNCTION TABLES
Table 1. DS91D176/DS91C176 Transmitting(1)
Inputs
Outputs
RE
X
DE
D
B
L
A
H
L
2.0V
2.0V
0.8V
2.0V
0.8V
X
X
H
Z
X
Z
(1) X — Don't care condition
Z — High impedance state
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Table 2. DS91D176 Receiving(1)
Inputs
Output
RE
DE
A − B
≥ +0.05V
≤ −0.05V
0V
R
H
L
0.8V
0.8V
0.8V
2.0V
0.8V
0.8V
0.8V
0.8V
X
Z
X
(1) X — Don't care condition
Z — High impedance state
Table 3. DS91C176 Receiving(1)
Inputs
Output
RE
DE
A − B
≥ +0.15V
≤ +0.05V
0V
R
H
L
0.8V
0.8V
0.8V
2.0V
0.8V
0.8V
0.8V
0.8V
L
X
Z
(1) X — Don't care condition
Z — High impedance state
Table 4. DS91D176 Receiver Input Threshold Test Voltages(1)
Resulting Differential
Input Voltage
Resulting Common-Mode
Input Voltage
Applied Voltages
Receiver Output
VIA
VIB
VID
VIC
R
H
L
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
2.400V
−2.400V
0.050V
−0.050V
−0.050V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Table 5. DS91C176 Receiver Input Threshold Test Voltages(1)
Resulting Differential
Input Voltage
Resulting Common-Mode
Input Voltage
Applied Voltages
Receiver Output
VIA
VIB
VID
VIC
R
H
L
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
10
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SNLS146L –MARCH 2006–REVISED APRIL 2013
PIN DESCRIPTONS
Pin No.
Name
R
Description
1
2
Receiver output pin
RE
Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the
receiver is enabled.
3
4
5
6
7
8
DE
D
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.
Driver input pin
GND
A
Ground pin
Non-inverting driver output pin/Non-inverting receiver input pin
Inverting driver output pin/Inverting receiver input pin
Power supply pin, +3.3V ± 0.3V
B
VCC
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Typical Performance Characteristics – DS91D176/DS91C176
Supply Current
vs.
Frequency
Output VOD
vs.
Load Resistance
Supply Current measured using a clock pattern with driver terminated VCC = 3.3V, TA = +25°C
to 50ohms . VCC = 3.3V, TA = +25°C.
Figure 18.
Figure 19.
12
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REVISION HISTORY
Changes from Revision K (April 2013) to Revision L
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
DS91C176TMA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
8
8
8
95
TBD
Call TI
CU SN
Call TI
CU SN
CU SN
Call TI
CU SN
Call TI
DS91C
176MA
DS91C176TMA/NOPB
DS91C176TMAX
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
D
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
DS91C
176MA
2500
2500
95
TBD
DS91C
176MA
DS91C176TMAX/NOPB
DS91D176TMA/NOPB
DS91D176TMAX
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
DS91C
176MA
Green (RoHS
& no Sb/Br)
DS91D
176MA
2500
2500
TBD
DS91D
176MA
DS91D176TMAX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
DS91D
176MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS91C176TMAX
DS91C176TMAX/NOPB
DS91D176TMAX
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.5
6.5
6.5
6.5
5.4
5.4
5.4
5.4
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
DS91D176TMAX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS91C176TMAX
DS91C176TMAX/NOPB
DS91D176TMAX
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
349.0
349.0
349.0
349.0
337.0
337.0
337.0
337.0
45.0
45.0
45.0
45.0
DS91D176TMAX/NOPB
Pack Materials-Page 2
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