DS91D180TMAX/NOPB [TI]
100MHz M-LVDS 线路驱动器/接收器组合 | D | 14 | -40 to 85;
| 型号： | DS91D180TMAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100MHz M-LVDS 线路驱动器/接收器组合 | D | 14 | -40 to 85 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：1115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair
Check for Samples: DS91C180, DS91D180
1
FEATURES
DESCRIPTION
The DS91D180 and DS91C180 are 100 MHz M-
2
•
•
•
•
DC to 100+ MHz / 200+ Mbps Low Power, Low
EMI Operation
LVDS (Multipoint Low Voltage Differential Signaling)
line driver/receiver pairs designed for applications
that utilize multipoint networks (e.g. clock distribution
in ATCA and uTCA based systems). M-LVDS is a
bus interface standard (TIA/EIA-899) optimized for
multidrop networks. Controlled edge rates, tight input
receiver thresholds and increased drive strength are
sone of the key enhancments that make M-LVDS
devices an ideal choice for distributing signals via
multipoint networks.
Optimal for ATCA, uTCA Clock Distribution
Networks
Meets or Exceeds TIA/EIA-899 M-LVDS
Standard
Wide Input Common Mode Voltage for
Increased Noise Immunity
•
•
DS91D180 has Type 1 Receiver Input
DS91C180 has Type 2 Receiver Input for Fail-
Safe Functionality
The DS91D180/DS91C180 driver input accepts
LVTTL/LVCMOS signals and converts them to
differential
M-LVDS
signal
levels.
The
•
•
Industrial Temperature Range
DS91D180/DS91C180 receiver accepts low voltage
differential signals (LVDS, B-LVDS, M-LVDS, LV-
PECL and CML) and converts them to 3V LVCMOS
signals. The DS91D180 device has a M-LVDS type 1
receiver input with no offset.The DS91C180 device
has a type 2 receiver input which enable failsafe
functionality.
Space Saving SOIC-14 Package (JEDEC MS-
012)
Typical Application in an ATCA Clock Distribution Network
Slot Card N
Slot Card N+1
MLVDS Drivers/Receivers
MLVDS Drivers/Receivers
CLK1A (8 KHz)
CLK1B (8 KHz)
80W RT
80W RT
80W RT
80W RT
CLK2A (19.44 MHz)
CLK2B (19.44 MHz)
80W RT
80W RT
80W RT
80W RT
CLK3A (User Defined up to 100 MHz)
CLK3B (User Defined up to 100 MHz)
80W RT
80W RT
80W RT
80W RT
ATCA Backplane
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Figure 1. Connection Diagram
Top View
See Package Number D0014A
Logic Diagram
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
High
High
150 mV
50 mV
V
ID
0 V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 2. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
(1)(2)
Absolute Maximum Ratings
Supply Voltage, VCC
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
−1.8V to +4.1V
−0.3V to (VCC + 0.3V)
1.1 W
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
Maximum Package Power Dissipation at +25°C
SOIC Package
Derate SOIC Package
8.8 mW/°C above +25°C
113.7 °C/W
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA
θJC
36.9 °C/W
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
ESD Ratings:
150°C
−65°C to +150°C
260°C
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
≥ 5 kV
≥ 250 V
≥ 1000 V
(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
3.0
Typ
Max
3.6
Units
V
Supply Voltage, VCC
3.3
Voltage at Any Bus Terminal (Separate or Common-Mode)
Differential Input Voltage VID
−1.4
+3.8
2.4
V
V
High Level Input Voltage VIH
2.0
0
VCC
0.8
V
Low Level Input Voltage VIL
V
Operating Free Air Temperature TA
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
M-LVDS Driver
|VYZ
|
Differential output voltage magnitude
RL = 50Ω, CL = 5pF
Figure 3 and Figure 5
480
−50
0.3
0
650
+50
2.1
mV
mV
V
ΔVYZ
Change in differential output voltage magnitude
between logic states
0
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5pF
Figure 3 and Figure 4
1.8
|ΔVOS(SS)
|
Change in steady-state common-mode output voltage
between logic states
+50
mV
VOS(PP)
VY(OC)
VZ(OC)
VP(H)
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
(VOS(pp) @ 500KHz clock)
Figure 6
143
mV
V
0
0
2.4
2.4
V
RL = 50Ω, CL = 5pF,
CD = 0.5pF
1.2VSS
V
VP(L)
Figure 8 and Figure 9(5)
−0.2VSS
V
IIH
High-level input current (LVTTL inputs)
VIH = 2.0V
-15
15
μA
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2) All typicals are given for VCC = 3.3V and TA = 25°C.
(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4) CL includes fixture capacitance and CD includes probe capacitance.
(5) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol
IIL
Parameter
Conditions
Min
-15
-1.5
-43
Typ
Max
Units
μA
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
Differential short-circuit output current
VIL = 0.8V
IIN = -18 mA
Figure 7
15
VIKL
IOS
V
43
mA
M-LVDS Receiver
VIT+ Positive-going differential input voltage threshold
See Function Tables
See Function Tables
Type 1
Type 2
Type 1
Type 2
20
94
50
mV
mV
mV
mV
V
150
VIT−
Negative-going differential input voltage threshold
−50
50
20
94
VOH
VOL
IOZ
High-level output voltage
IOH = −8mA
IOL = 8mA
2.4
2.7
0.28
Low-level output voltage
0.4
10
V
TRI-STATE output current
VO = 0V or 3.6V
VO = 0V
−10
μA
mA
IOSR
Short circuit Rrceiver output current (LVTTL Output)
-90
-48
M-LVDS Bus (Input and Output) Pins
IA, IY
Receiver input or driver high-impedance output
current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = GND
32
µA
µA
µA
µA
µA
µA
µA
VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE
= GND
−20
−32
+20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = GND
IB, IZ
Receiver input or driver high-impedance output
current
VB,Z = 3.8V, VA,Y = 1.2V,
DE = GND
32
VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE
= GND
−20
−32
−4
+20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = GND
IAB, IYZ
Receiver input or driver high-impedance output
differential current (IA − IB or IY − IZ)
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, DE
= GND
+4
32
IA(OFF)
IY(OFF)
,
Receiver input or driver high-impedance output
power-off current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = 0V
µA
µA
µA
µA
µA
µA
µA
0V ≤ VCC ≤ 1.5V
VA,Y = 0V or 2.4V, VB,Z = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
−20
−32
+20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
IB(OFF)
IZ(OFF)
,
Receiver input or driver high-impedance output
power-off current
VB,Z = 3.8V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
32
VB,Z = 0V or 2.4V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
−20
−32
−4
+20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = 0V
0V ≤ VCC ≤ 1.5V
IAB(OFF)
IYZ(OFF)
,
Receiver input or driver high-impedance output
power-off differential current
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V,
DE = 0V
+4
(IA(OFF) − IB(OFF) or IY(OFF) − IZ(OFF)
Receiver input capacitance
Driver output capacitance
)
0V ≤ VCC ≤ 1.5V
CA, CB
CY, CZ
CAB
VCC = OPEN
5.1
8.5
2.5
5.5
pF
pF
pF
pF
Receiver input differential capacitance
Driver output differential capacitance
CYZ
4
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol
CA/B
CY/Z
Parameter
Conditions
Min
Typ
Max
Units
,
Receiver input or driver output capacitance balance
(CA/CB or CY/CZ)
1.0
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
ICCB
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
DE = GND, RE = VCC
17
7
29.5
9.0
mA
mA
mA
mA
TRI-STATE Supply Current
Receiver Supply Current
DE = GND, RE = GND
DE = VCC, RE = GND
14
20
18.5
29.5
Supply Current, Driver and Receiver Enabled
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
1.0
1.0
3.4
3.1
300
5.5
5.5
420
1.9
3.0
3.0
8
ns
ns
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
(3) (4)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
Pulse Skew |tPLHD − tPHLD
|
Figure 8 and Figure 9
ps
(5) (4)
Part-to-Part Skew
ns
(4)
Rise Time
1.0
1.0
1.8
1.8
ns
(4)
Fall Time
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
ns
tPZL
8
ns
tPLZ
Figure 10 and Figure 11
8
ns
tPHZ
8
ns
(4)
tJIT
Random Jitter, RJ
100MHz clock pattern(6)
2.5
5.5
psrms
Mbps
fMAX
Maximum Data Rate
200
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
2.0
4.7
5.3
0.6
7.5
7.5
1.9
1.5
3.0
3.0
10
ns
ns
tPHL
Propagation Delay High to Low
Figure 12 Figure 13 and Figure 14
(3)(4)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
Pulse Skew |tPLHD − tPHLD
|
ns
(5)(4)
Part-to-Part Skew
ns
Rise Time(4)
Fall Time(4)
0.5
0.5
1.2
1.2
ns
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
RL = 500Ω, CL = 15 pF
ns
tPZL
Figure 15 and Figure 16
10
ns
tPLZ
10
ns
tPHZ
10
ns
fMAX
200
Mbps
(1) All typicals are given for V = 3.3V and TA = 25°C.
(2) CL includes fixture capacitance and CD includes probe capacitance.
(3) tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) Stimulus and fixture jitter has been subtracted.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Test Circuits and Waveforms
Figure 3. Differential Driver Test Circuit
A
~ 2.1V
B
~ 1.5V
DV
OS(SS)
V
OS
V
OS(PP)
Figure 4. Differential Driver Waveforms
Figure 5. Differential Driver Full Load Test Circuit
Figure 6. Differential Driver DC Open Test Circuit
6
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
Figure 7. Differential Driver Short-Circuit Test Circuit
Figure 8. Driver Propagation Delay and Transition Time Test Circuit
Figure 9. Driver Propagation Delays and Transition Time Waveforms
Figure 10. Driver TRI-STATE Delay Test Circuit
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Figure 11. Driver TRI-STATE Delay Waveforms
Figure 12. Receiver Propagation Delay and Transition Time Test Circuit
Figure 13. Type 1 Receiver Propagation Delay and Transition Time Waveforms
8
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
Figure 14. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 15. Receiver TRI-STATE Delay Test Circuit
Figure 16. Receiver TRI-STATE Delay Waveforms
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
FUNCTION TABLES
Table 1. DS91D180/DS91C180 Transmitting(1)
Inputs
Outputs
DE
D
Z
L
Y
H
L
2.0V
2.0V
0.8V
2.0V
0.8V
X
H
Z
Z
(1) X — Don't care condition
Z — High impedance state
Table 2. DS91D180 Receiving(1)
Inputs
Output
RE
A − B
≥ +0.05V
≤ −0.05V
0V
R
H
L
0.8V
0.8V
0.8V
2.0V
X
Z
X
(1) X — Don't care condition
Z — High impedance state
Table 3. DS91C180 Receiving(1)
Inputs
Output
RE
A − B
R
H
L
0.8V
0.8V
0.8V
2.0V
≥ +0.15V
≤ +0.05V
0V
L
X
Z
(1) X — Don't care condition
Z — High impedance state
Table 4. DS91D180 Receiver Input Threshold Test Voltages(1)
Applied Voltages
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VIC
R
H
L
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
2.400V
−2.400V
0.050V
−0.050V
−0.050V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
10
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
Table 5. DS91C180 Receiver Input Threshold Test Voltages(1)
Applied Voltages
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VIC
R
H
L
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
PIN DESCRIPTIONS
Pin No.
Name
NC
R
Description
1, 8
2
No connect.
Receiver output pin
3
RE
Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the
receiver is enabled.
4
5
DE
D
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.
Driver input pin
6, 7
9
GND
Y
Ground pin
Non-inverting driver output pin
Inverting driver output pin
Inverting receiver input pin
Non-inverting receiver input pin
Power supply pin, +3.3V ± 0.3V
10
Z
11
B
12
A
13, 14
VCC
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS91C180 DS91D180
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision L (April 2013) to Revision M
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS91C180 DS91D180
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS91C180TMA/NOPB
DS91C180TMAX/NOPB
DS91D180TMA/NOPB
DS91D180TMAX/NOPB
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
14
14
14
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
DS91C180
TMA
ACTIVE
ACTIVE
ACTIVE
2500 RoHS & Green
55 RoHS & Green
2500 RoHS & Green
SN
SN
SN
DS91C180
TMA
DS91D180
TMA
DS91D180
TMA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS91C180TMAX/NOPB
DS91D180TMAX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
9.35
9.35
2.3
2.3
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS91C180TMAX/NOPB
DS91D180TMAX/NOPB
SOIC
SOIC
D
D
14
14
2500
2500
367.0
356.0
367.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS91C180TMA/NOPB
DS91D180TMA/NOPB
D
D
SOIC
SOIC
14
14
55
55
495
495
8
8
4064
4064
3.05
3.05
Pack Materials-Page 3
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
DS91M047TMA/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, ROHS COMPLIANT, SOIC-16, Line Driver or Receiver
NSC
©2020 ICPDF网 联系我们和版权申明