DS91D180TMA [NSC]
100 MHz M-LVDS Line Driver/Receiver Pair; 100MHz的M- LVDS线路驱动器/接收器对
| 型号： | DS91D180TMA |
| 厂家： | 
National Semiconductor |
| 描述： | 100 MHz M-LVDS Line Driver/Receiver Pair |
| 文件： | 总14页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 20, 2007
DS91D180/DS91C180
100 MHz M-LVDS Line Driver/Receiver Pair
no offset.The DS91C180 device has a type 2 receiver input
which enable failsafe functionality.
General Description
The DS91D180 and DS91C180 are 100 MHz M-LVDS (Mul-
tipoint Low Voltage Differential Signaling) line driver/receiver
pairs designed for applications that utilize multipoint networks
(e.g. clock distribution in ATCA and uTCA based systems).
M-LVDS is a new bus interface standard (TIA/EIA-899) opti-
mized for multidrop networks. Controlled edge rates, tight
input receiver tresholds and increased drive strength are one
of the key enhencments that make M-LVDS devices an ideal
choice for distributing signals via multipoint networks.
Features
DC to 100+ MHz / 200+ Mbps low power, low EMI
operation
■
Optimal for ATCA, uTCA clock distribution networks
■
■
■
Meets or exceeds TIA/EIA-899 M-LVDS Standard
Wide Input Common Mode Voltage for Increased Noise
Immunity
The DS91D180/DS91C180 driver input accepts LVTTL/LVC-
MOS signals and converts them to differential M-LVDS signal
levels. The DS91D180/DS91C180 receiver accepts low volt-
age differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL
and CML) and converts them to 3V LVCMOS signals. The
DS91D180 device has a M-LVDS type 1 receiver input with
DS91D180 has type 1 receiver input
■
■
DS91C180 has type 2 receiver input for fail-safe
functionality
Industrial temperature range
■
■
Space saving SOIC-14 package (JEDEC MS-012)
Typical Application in an ATCA Clock Distribution Network
20041930
© 2007 National Semiconductor Corporation
200419
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Connection Diagram
Logic Diagram
20041926
Top View
20041925
Order Number DS91D180TMA, DS91C180TMA
See NS Package Number M14A
Ordering Information
Order Number
DS91D180TMA
DS91C180TMA
Receiver Input
type 1
Function
Package Type
SOIC/M14A
SOIC/M14A
Data (0V threshold receiver)
Control (offset fail-safe receiver)
type 2
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a con-
ventional threshold that is centered at the midpoint of the input
amplitude, VID/2. A type 2 receiver has a built in offset that is
100mV greater then VID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.
20041940
FIGURE 1. M-LVDS Receiver Input Thresholds
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2
ESD Ratings:
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
≥ 5 kV
≥ 250 V
≥ 1000 V
Supply Voltage, VCC
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
−1.8V to +4.1V
−0.3V to (VCC + 0.3V)
Recommended Operating
Conditions
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
Min Typ Max Units
Supply Voltage, VCC
3.0 3.3 3.6
V
V
Voltage at Any Bus Terminal
ꢀ(Separate or Common-Mode)
Differential Input Voltage VID
High Level Input Voltage VIH
Low Level Input Voltage VIL
Operating Free Air
−1.4
+3.8
Maximum Package Power Dissipation at +25°C
SOIC Package
Derate SOIC Package
Thermal Resistance
ꢀθJA
1.1 W
2.4
VCC
0.8
V
V
V
8.8 mW/°C above +25°C
2.0
0
113.7 °C/W
ꢀθJC
36.9 °C/W
150°C
−65°C to +150°C
Temperature TA
−40 +25 +85
°C
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 seconds)
260°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8)
Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Driver
|VYZ
|
Differential output voltage magnitude
480
650
mV
RL = 50Ω, CL = 5pF
Figure 2 and Figure 4
Change in differential output voltage magnitude
between logic states
ΔVYZ
−50
0.3
0
+50
2.1
mV
V
VOS(SS)
Steady-state common-mode output voltage
1.8
RL = 50Ω, CL = 5pF
Figure 2 and Figure 3
Change in steady-state common-mode output
voltage between logic states
|ΔVOS(SS)
|
0
+50
mV
VOS(PP)
VY(OC)
VZ(OC)
VP(H)
Peak-to-peak common-mode output voltage
(VOS(pp) @ 500KHz clock)
143
mV
V
Maximum steady-state open-circuit output voltage Figure 5
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
0
0
2.4
2.4
V
1.2VSS
V
RL = 50Ω, CL = 5pF,
CD = 0.5pF
VP(L)
Voltage overshoot, high-to-low level output
−0.2VS
V
Figure 7 and Figure 8 (Note 9)
S
IIH
High-level input current (LVTTL inputs)
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
Differential short-circuit output current
VIH = 2.0V
VIL = 0.8V
IIN = -18 mA
Figure 6
-15
15
15
μA
μA
V
IIL
-15
-1.5
-43
VIKL
IOS
43
mA
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Function Tables
Type 1
Type 2
Type 1 −50
20
94
50
mV
mV
mV
mV
V
150
VIT−
Negative-going differential input voltage threshold See Function Tables
20
Type 2
50
94
VOH
VOL
IOZ
High-level output voltage
Low-level output voltage
TRI-STATE output current
IOH = −8mA
IOL = 8mA
2.4
2.7
0.28
0.4
10
V
VO = 0V or 3.6V
−10
-90
μA
mA
IOSR
Short circuit Rrceiver output current (LVTTL Output) VO = 0V
-48
3
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Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Bus (Input and Output) Pins
IA, IY
Receiver input or driver high-impedance output
current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = GND
32
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE
= GND
−20
−32
+20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = GND
IB, IZ
Receiver input or driver high-impedance output
current
VB,Z = 3.8V, VA,Y = 1.2V,
DE = GND
32
VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE
= GND
−20
−32
−4
+20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = GND
IAB, IYZ
Receiver input or driver high-impedance output
differential current (IA − IB or IY − IZ)
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, DE
= GND
+4
32
IA(OFF)
,
Receiver input or driver high-impedance output
power-off current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = VCC = 1.5V
IY(OFF)
VA,Y = 0V or 2.4V, VB,Z = 1.2V,
DE = VCC = 1.5V
−20
−32
+20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = VCC = 1.5V
IB(OFF)
IZ(OFF)
,
Receiver input or driver high-impedance output
power-off current
VB,Z = 3.8V, VA,Y = 1.2V,
DE = VCC = 1.5V
32
VB,Z = 0V or 2.4V, VA,Y = 1.2V,
DE = VCC = 1.5V
−20
−32
+20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = VCC = 1.5V
IAB(OFF)
,
Receiver input or driver high-impedance output
power-off differential current
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V,
−4
+4
µA
IYZ(OFF)
VCC = 1.5V, DE = 1.5V
(IA(OFF) − IB(OFF) or IY(OFF) − IZ(OFF)
Receiver input capacitance
Driver output capacitance
)
CA, CB
CY, CZ
CAB
VCC = OPEN
5.1
8.5
2.5
5.5
pF
pF
pF
pF
Receiver input differential capacitance
Driver output differential capacitance
CYZ
CA/B
,
Receiver input or driver output capacitance balance
(CA/CB or CY/CZ)
1.0
CY/Z
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
ICCB
Driver Supply Current
17
7
29.5
9.0
mA
mA
mA
mA
RL = 50Ω, DE = VCC, RE = VCC
DE = GND, RE = VCC
TRI-STATE Supply Current
Receiver Supply Current
DE = GND, RE = GND
DE = VCC, RE = GND
14
20
18.5
29.5
Supply Current, Driver and Receiver Enabled
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4
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8)
Symbol
Parameter
Conditions
Min
Typ
Max Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
Differential Propagation Delay High to Low
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Part-to-Part Skew (Notes 6, 9)
Rise Time (Note 9)
1.0
1.0
3.4
3.1
5.5
5.5
420
1.9
3.0
3.0
8
ns
ns
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
tPHL
Figure 7 and Figure 8
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
300
ps
ns
1.0
1.0
1.8
1.8
ns
Fall Time (Note 9)
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Random Jitter, RJ (Note 9)
ns
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
tPZL
8
ns
Figure 9 and Figure 10
tPLZ
8
ns
tPHZ
8
ns
tJIT
100MHz clock pattern (Note 7)
2.5
5.5
psrms
Mbps
fMAX
Maximum Data Rate
200
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
2.0
4.7
5.3
0.6
7.5
7.5
1.9
1.5
3.0
3.0
10
ns
ns
Figures 11, 12 and Figure 13
tPHL
Propagation Delay High to Low
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Part-to-Part Skew (Notes 6, 9)
Rise Time (Note 9)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
ns
ns
0.5
0.5
1.2
1.2
ns
Fall Time (Note 9)
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
ns
RL = 500Ω, CL = 15 pF
Figure 14 and Figure 15
tPZL
10
ns
tPLZ
10
ns
tPHZ
10
ns
fMAX
200
Mbps
Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for VCC = 3.3V and TA = 25°C.
Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
Note 5: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 7: Stimulus and fixture jitter has been subtracted.
Note 8: CL includes fixture capacitance and CD includes probe capacitance.
Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
5
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Test Circuits and Waveforms
20041914
FIGURE 2. Differential Driver Test Circuit
20041924
FIGURE 3. Differential Driver Waveforms
20041922
FIGURE 4. Differential Driver Full Load Test Circuit
20041912
FIGURE 5. Differential Driver DC Open Test Circuit
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6
20041927
FIGURE 6. Differential Driver Short-Circuit Test Circuit
20041916
FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit
20041918
FIGURE 8. Driver Propagation Delays and Transition Time Waveforms
7
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20041919
FIGURE 9. Driver TRI-STATE Delay Test Circuit
20041921
FIGURE 10. Driver TRI-STATE Delay Waveforms
20041915
FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit
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8
20041917
FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
20041923
FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
20041913
FIGURE 14. Receiver TRI-STATE Delay Test Circuit
9
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20041920
FIGURE 15. Receiver TRI-STATE Delay Waveforms
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10
Function Tables
DS91D180/DS91C180 Transmitting
Inputs Outputs
DE
D
Z
Y
H
L
2.0V
2.0V
0.8V
2.0V
0.8V
X
L
H
Z
Z
X — Don't care condition
Z — High impedance state
DS91D180 Receiving
DS91C180 Receiving
Inputs Output
A − B
Inputs
A − B
Output
RE
R
H
L
RE
R
H
L
0.8V
0.8V
0.8V
0.8V
≥ +0.05V
≥ +0.15V
≤ −0.05V
≤ +0.05V
0.8V
2.0V
0V
X
Z
0.8V
2.0V
0V
L
Z
X
X
X — Don't care condition
Z — High impedance state
X — Don't care condition
Z — High impedance state
DS91D180 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Input Voltage
Receiver
Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
2.400V
−2.400V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
−0.050V
−0.050V
0.050V
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91C180 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Resulting Common-Mode
Input Voltage
Receiver
Output
Voltage
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
11
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Pin Descriptions
Pin No.
Name
NC
R
Description
1, 8
2
No connect.
Receiver output pin
3
RE
Receiver enable pin: When RE is high, the receiver is disabled. When
RE is low or open, the receiver is enabled.
4
DE
Driver enable pin: When DE is low, the driver is disabled. When DE
is high, the driver is enabled.
5
6, 7
9
D
GND
Y
Driver input pin
Ground pin
Non-inverting driver output pin
Inverting driver output pin
Inverting receiver input pin
Non-inverting receiver input pin
Power supply pin, +3.3V ± 0.3V
10
Z
11
B
12
A
13, 14
VCC
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS91D180TMA, DS91C180TMA
See NS package Number M14A
13
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