DS91M040TSQ/NOPB [TI]
125MHz 四路 M-LVDS 收发器 | RTV | 32 | -40 to 85;
| 型号： | DS91M040TSQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 125MHz 四路 M-LVDS 收发器 | RTV | 32 | -40 to 85 驱动 接口集成电路 电视 驱动器 |
| 文件： | 总23页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS91M040
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SNLS283M –FEBRUARY 2008–REVISED APRIL 2013
DS91M040 125 MHz Quad M-LVDS Transceiver
Check for Samples: DS91M040
1
FEATURES
DESCRIPTION
The DS91M040 is a quad M-LVDS transceiver
designed for driving / receiving clock or data signals
to / from up to four multipoint networks.
2
•
DC - 125 MHz / 250 Mbps Low Jitter, Low
Skew, Low Power Operation
•
Wide Input Common Mode Voltage Range
Allows up to ±1V of GND Noise
M-LVDS (Multipoint LVDS) is a new family of bus
interface devices based on LVDS technology
specifically designed for multipoint and multidrop
cable and backplane applications. It differs from
standard LVDS in providing increased drive current to
handle double terminations that are required in multi-
point applications. Controlled transition times
minimize reflections that are common in multipoint
configurations due to unterminated stubs. M-LVDS
devices also have a very large input common mode
voltage range for additional noise margin in heavily
loaded and noisy backplane environments.
•
•
•
Conforms to TIA/EIA-899 M-LVDS Standard
Pin Selectable M-LVDS Receiver Type (1 or 2)
Controlled Transition Times (2.0 ns typ)
Minimize Reflections
•
8 kV ESD on M-LVDS I/O pins protects
adjoining components
•
•
Flow-Through Pinout Simplifies PCB Layout
Small 5 mm x 5 mm WQFN-32 Space Saving
Package
A
single DS91M040 channel is
a half-duplex
APPLICATIONS
transceiver that accepts LVTTL/LVCMOS signals at
the driver inputs and converts them to differential M-
LVDS signal levels. The receiver inputs accept low
voltage differential signals (LVDS, BLVDS, M-LVDS,
LVPECL and CML) and convert them to 3V LVCMOS
signals. The DS91M040 supports both M-LVDS type
1 and type 2 receiver inputs.
•
•
•
Multidrop / Multipoint Clock and Data
Distribution
High-Speed, Low Power, Short-Reach
Alternative to TIA/EIA-485/422
Clock Distribution in AdvancedTCA (ATCA)
and MicroTCA (μTCA, uTCA) Backplanes
System Diagram
Line Card in SLOT 1
DS91M040
Line Card in SLOT N-1
Line Card in SLOT N
M-LVDS Receivers
M-LVDS Receivers
R
Z
Z
Z
Z
R
T
R
T
R
T
R
T
T
T
T
T
0
0
0
0
R
R
R
R
T
= Z
LOADED
BACKPLANE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS91M040
SNLS283M –FEBRUARY 2008–REVISED APRIL 2013
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Connection Diagram
RO0
DI0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
B0
A0
B1
A1
B2
A2
B3
A3
RO1
DI1
DAP
RO2
DI2
(GND)
RO3
DI3
Logic Diagram
FSEN1
DE0
DI0
B0
A0
RE0
RO0
DE1
DI1
B1
A1
RE1
RO1
MDE
DE2
DI2
B2
A2
RE2
RO2
DE3
DI3
B3
A3
RE3
RO3
FSEN2
2
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PIN DESCRIPTIONS
Number
Name
RO
I/O, Type
O, LVCMOS
I, LVCMOS
Description
1, 3, 5, 7
Receiver output pin.
26, 28, 13, 15
RE
Receiver enable pin: When RE is high, the receiver is disabled. When RE is
low, the receiver is enabled. There is a 300 kΩ pullup resistor on this pin.
25, 27, 14, 16
DE
I, LVCMOS
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the
driver is enabled. There is a 300 kΩ pulldown resistor on this pin.
2, 4, 6, 8
31, DAP
DI
GND
A
I, LVCMOS
Power
Driver input pin.
Ground pin and pad.
17, 19, 21, 23
18, 20, 22, 24
11, 12, 29, 30
32
I/O, M-LVDS
I/O, M-LVDS
Power
Non-inverting driver output pin/Non-inverting receiver input pin
Inverting driver output pin/Inverting receiver input pin
Power supply pin, +3.3V ± 0.3V
B
VDD
FSEN1
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs
9
FSEN2
MDE
I, LVCMOS
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs
10
Master enable pin. When MDE is H, the device is powered up. When MDE is L,
the device overrides all other control and powers down.
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
High
High
150 mV
50 mV
V
ID
0 V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 1. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Power Supply Voltage
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
−1.9V to +5.5V
Continuous
LVCMOS Input Voltage
LVCMOS Output Voltage
M-LVDS I/O Voltage
M-LVDS Output Short Circuit Current Duration
Junction Temperature
+140°C
Storage Temperature Range
−65°C to +150°C
+260°C
Lead Temperature Range Soldering (4 sec.)
Maximum Package Power Dissipation @ +25°C
RTV Package
3.91W
Derate RTV Package
34 mW/°C above +25°C
+29.4°C/W
Package Thermal Resistance (4-Layer, 2 oz. Cu,
JEDEC)
θJA
θJC
+2.8°C/W
ESD Susceptibility
HBM(3)
MM(4)
CDM(5)
≥8 kV
≥250V
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
Typ
Max
3.6
Units
V
Supply Voltage, VDD
3.3
Voltage at Any Bus Terminal (Separate or Common-Mode)
Differential Input Voltage VID
−1.4
+3.8
2.4
V
V
LVTTL Input Voltage High VIH
2.0
0
VDD
0.8
V
LVTTL Input Voltage Low VIL
V
Operating Free Air Temperature TA
−40
+25
+85
°C
4
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DC Electrical Characteristics(1)(2)(3)(4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
M-LVDS Driver
|VAB
|
Differential output voltage magnitude
RL = 50Ω, CL = 5 pF
480
−50
0.3
0
650
+50
2.1
mV
mV
V
ΔVAB
Change in differential output voltage magnitude
between logic states
Figure 2
Figure 4
0
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5 pF
1.6
|ΔVOS(SS)
|
Change in steady-state common-mode output voltage Figure 2
between logic states
+50
mV
Figure 3
VA(OC)
VB(OC)
VP(H)
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output(5)
Voltage overshoot, high-to-low level output(5)
Figure 5
0
0
2.4
2.4
V
V
V
RL = 50Ω, CL = 5pF,CD = 0.5 pF
Figure 7
Figure 8
1.2VSS
VP(L)
−0.2V
SS
V
IIH
High-level input current (LVTTL inputs)
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
Differential short-circuit output current(6)
VIH = 3.6V
VIL = 0.0V
IIN = -18 mA
Figure 6
-15
15
15
μA
μA
V
IIL
-15
-1.5
-43
VCL
IOS
43
mA
M-LVDS Receiver
VIT+ Positive-going differential input voltage threshold
See Truth Tables
See Truth Tables
Type 1
16
100
20
50
mV
mV
mV
mV
V
Type 2
Type 1
Type 2
150
VIT−
Negative-going differential input voltage threshold
−50
50
94
VOH
VOL
IOZ
High-level output voltage (LVTTL output)
Low-level output voltage (LVTTL output)
TRI-STATE output current
IOH = −8mA
IOL = 8mA
2.4
2.7
0.28
0.4
10
V
VO = 0V or 3.6V
VO = 0V
−10
μA
mA
IOSR
Short-circuit receiver output current (LVTTL output)
-50
-90
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
(4) CL includes fixture capacitance and CD includes probe capacitance.
(5) Specification is ensured by characterization and is not tested in production.
(6) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DC Electrical Characteristics(1)(2)(3)(4) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
M-LVDS Bus (Input and Output) Pins
IA
Transceiver input/output current
Transceiver input/output current
VA = 3.8V, VB = 1.2V
32
µA
µA
µA
µA
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V
VA = −1.4V, VB = 1.2V
VB = 3.8V, VA = 1.2V
−20
−32
+20
IB
32
VB = 0V or 2.4V, VA = 1.2V
VB = −1.4V, VA = 1.2V
VA = VB, −1.4V ≤ V ≤ 3.8V
−20
−32
−4
+20
IAB
Transceiver input/output differential current (IA − IB)
+4
32
IA(OFF)
Transceiver input/output power-off current
VA = 3.8V, VB = 1.2V,
DE = 0V
µA
µA
µA
µA
µA
µA
µA
0V ≤ VDD ≤ 1.5V
VA = 0V or 2.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−20
−32
+20
VA = −1.4V, VB = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IB(OFF)
Transceiver input/output power-off current
VB = 3.8V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
32
VB = 0V or 2.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
−20
−32
−4
+20
VB = −1.4V, VA = 1.2V,
DE = 0V
0V ≤ VDD ≤ 1.5V
IAB(OFF)
Transceiver input/output power-off differential current VA = VB, −1.4V ≤ V ≤ 3.8V,
(IA(OFF) − IB(OFF)
)
DE = 0V
+4
0V ≤ VDD ≤ 1.5V
CA
Transceiver input/output capacitance
VDD = OPEN
7.8
7.8
3
pF
pF
pF
CB
Transceiver input/output capacitance
CAB
CA/B
Transceiver input/output differential capacitance
Transceiver input/output capacitance balance (CA/CB)
1
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
ICCPD
Driver Supply Current
RL = 50Ω, DE = H, RE = H
DE = L, RE = H
DE = L, RE = L
MDE = L
67
22
32
3
75
26
38
5
mA
mA
mA
mA
TRI-STATE Supply Current
Receiver Supply Current
Power Down Supply Current
6
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Switching Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATIONS
tPLH
tPHL
tSKD1
Differential Propagation Delay Low to High
Differential Propagation Delay High to Low
Pulse Skew(4)(5)
RL = 50Ω, CL = 5 pF,
1.5
1.5
3.3
3.3
30
5.5
5.5
125
ns
ns
ps
CD = 0.5 pF
Figure 7
Figure 8
tSKD2
tSKD3
tSKD4
tTLH
Channel-to-Channel Skew(4)(6)
Part-to-Part Skew(4)(7)
Part-to-Part Skew(4)(8)
Rise Time(4)
100
0.8
200
1.6
ps
ns
ns
ns
ns
ns
ns
ns
4
1.2
1.2
2.0
2.0
7.5
8.0
7.0
3.0
tTHL
Fall Time(4)
3.0
tPZH
tPZL
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
RL = 50Ω, CL = 5 pF,
11.5
11.5
11.5
CD = 0.5 pF
tPLZ
Figure 9
Figure 10
tPHZ
Disable Time (Active High to Z)
7.0
11.5
ns
RECEIVER AC SPECIFICATIONS
tPLH Propagation Delay Low to High
tPHL
CL = 15 pF
1.5
1.5
3.0
3.1
4.5
4.5
ns
ns
Propagation Delay High to Low
Figure 11
Figure 12
Figure 13
tSKD1A
tSKD1B
tSKD2
tSKD3
tSKD4
tTLH
Pulse Skew (Receiver Type 1)(4)(5)
Pulse Skew (Receiver Type 2)(4)(5)
Channel-to-Channel Skew(4)(6)
Part-to-Part Skew(4)(7)
Part-to-Part Skew(8)
Rise Time(4)
55
475
60
325
800
300
1.2
3
ps
ps
ps
ns
ns
ns
ns
ns
ns
0.6
0.3
0.3
1.1
0.65
3
1.6
1.6
5.5
5.5
tTHL
Fall Time(4)
tPZH
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
RL = 500Ω, CL = 15 pF
tPZL
Figure 14
Figure 15
3
tPLZ
tPHZ
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
3.5
3.5
5.5
5.5
ns
ns
GENERIC AC SPECIFICATIONS
tWKUP
Wake Up Time(4)
500
ms
(Master Device Enable (MDE) time)
fMAX
Maximum Operating Frequency(4)
125
MHz
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
(3) CL includes fixture capacitance and CD includes probe capacitance.
(4) Specification is ensured by characterization and is not tested in production.
(5) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(6) tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.
(7) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(8) tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
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Test Circuits and Waveforms
Figure 2. Differential Driver Test Circuit
A
~ 1.9V
B
~ 1.3V
DV
OS(SS)
V
OS
V
OS(PP)
Figure 3. Differential Driver Waveforms
Figure 4. Differential Driver Full Load Test Circuit
Figure 5. Differential Driver DC Open Test Circuit
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Figure 6. Differential Driver Short-Circuit Test Circuit
Figure 7. Driver Propagation Delay and Transition Time Test Circuit
Figure 8. Driver Propagation Delays and Transition Time Waveforms
Figure 9. Driver TRI-STATE Delay Test Circuit
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Figure 10. Driver TRI-STATE Delay Waveforms
Figure 11. Receiver Propagation Delay and Transition Time Test Circuit
Figure 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
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Figure 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 14. Receiver TRI-STATE Delay Test Circuit
Figure 15. Receiver TRI-STATE Delay Waveforms
TRUTH TABLES
DS91M040 Transmitting(1)
Inputs
Outputs
RE
X
DE
H
DI
H
L
B
L
A
H
L
X
H
H
Z
X
L
X
Z
(1) X — Don't care condition
Z — High impedance state
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DS91M040 as Type 1 Receiving(1)
Inputs
Output
FSEN
RE
L
DE
X
A − B
RO
L
L
L
≥ +0.05V
≤ −0.05V
H
L
L
X
L
X
−0.05V
Undefined
≤ A-B ≤ +0.05V
L
H
X
X
Z
(1) X — Don't care condition
Z — High impedance state
DS91M040 as Type 2 Receiving(1)
Inputs
Output
FSEN
RE
DE
X
A − B
RO
H
H
H
L
L
L
≥ +0.15V
≤ +0.05V
H
L
X
X
+0.05V
Undefined
≤ A-B ≤ +0.15V
H
H
X
X
Z
(1) X — Don't care condition
Z — High impedance state
DS91M040 Type 1 Receiver Input Threshold Test Voltages(1)
Applied Voltages
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VICM
R
H
L
2.400V
0.000V
3.800V
3.750V
−1.350V
−1.400V
0.000V
2.400V
3.750V
3.800V
−1.400V
−1.350V
2.400V
−2.400V
0.050V
−0.050V
0.050V
−0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91M040 Type 2 Receiver Input Threshold Test Voltages(1)
Applied Voltages
Resulting Differential Input Voltage
Resulting Common-Mode Input
Voltage
Receiver Output
VIA
VIB
VID
VIC
R
H
L
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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Typical Performance Characteristics
2.8
2.8
f = 125 MHz
f = 125 MHz
V
= 3.0 V
CC
V
CC
= 3.0 V
2.5
2.2
2.5
2.2
1.9
1.9
V
CC
= 3.6 V
V
= 3.6 V
CC
1.6
1.3
1.6
1.3
V
= 3.3 V
CC
V
= 3.3 V
CC
1.0
-50
1.0
-50
-10
30
70
110
150
-10
30
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Driver Rise Time as a Function of Temperature
Figure 17. Driver Fall Time as a Function of Temperature
900
4.5
V
= 3.0 V
CC
f = 125 MHz
750
600
4.0
3.5
450
3.0
V
CC
= 3.6 V
300
150
2.5
2.0
f = 1 MHz
= 3.3V
V
= 3.3 V
CC
V
CC
= 25°C
T
A
0
1.5
-50
0
25
50
75
100
125
-10
30
70
110
150
TEMPERATURE (°C)
RESISTIVE LOAD (W)
Figure 18. Driver Output Signal Amplitude as a Function of
Resistive Load
Figure 19. Driver Propagation Delay (tPLHD) as a Function
of Temperature
4.5
180
V
= 3.0 V
CC
f = 125 MHz
4.0
3.5
150
120
3.0
90
f = 125 MHz
V
CC
= 3.6 V
V
CC
= 3.3V
2.5
2.0
60
30
T
= 25°C
A
V
= 3.3 V
CC
R
L
= 50W (On all CH)
DE
= H
= H
0,1,2,3
RE*
0,1,2,3
1.5
-50
0
-10
30
70
110
150
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 20. Driver Propagation Delay (tPHLD) as a Function
of Temperature
Figure 21. Driver Power Supply Current as a Function of
Frequency
Copyright © 2008–2013, Texas Instruments Incorporated
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DS91M040
SNLS283M –FEBRUARY 2008–REVISED APRIL 2013
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Typical Performance Characteristics (continued)
90
3.8
f = 125 MHz
= 3.3V
V
CC
= 25°C
75
60
3.5
3.2
TYPE 2
T
A
V
ID
= 200 mV
45
2.9
f = 125 MHz
= 3.3V
30
15
2.6
2.3
TYPE 1
V
CC
T
A
= 25°C
DE
= L
0,1,2,3
RE*
= L
0,1,2,3
100
0
2.0
-4.0
0
25
50
75
125
-2.4
-0.8
0.8
2.4
4.0
FREQUENCY (MHz)
INPUT COMMON MODE VOLTAGE (V)
Figure 22. Receiver Power Supply Current as a Function of
Frequency
Figure 23. Receiver Propagation Delay (tPLHD) as a
Function of Input Common Mode Voltage
3.8
f = 125 MHz
V
= 3.3V
CC
3.5
3.2
T
= 25°C
A
V
ID
= 200 mV
TYPE 2
2.9
2.6
2.3
TYPE 1
2.0
-4.0
-2.4
-0.8
0.8
2.4
4.0
INPUT COMMON MODE VOLTAGE (V)
Figure 24. Receiver Propagation Delay (tPHLD) as a Function of Input Common Mode Voltage
14
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS91M040
DS91M040
www.ti.com
SNLS283M –FEBRUARY 2008–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision L (April 2013) to Revision M
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
Copyright © 2008–2013, Texas Instruments Incorporated
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15
Product Folder Links: DS91M040
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS91M040TSQ/NOPB
DS91M040TSQE/NOPB
DS91M040TSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
M040TS
SN
SN
M040TS
M040TS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS91M040TSQ/NOPB
WQFN
RTV
RTV
RTV
32
32
32
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
DS91M040TSQE/NOPB WQFN
DS91M040TSQX/NOPB WQFN
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS91M040TSQ/NOPB
DS91M040TSQE/NOPB
DS91M040TSQX/NOPB
WQFN
WQFN
WQFN
RTV
RTV
RTV
32
32
32
1000
250
208.0
208.0
356.0
191.0
191.0
356.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022, Texas Instruments Incorporated
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