DS92LV090ATVEHX/NOPB [TI]
9 通道总线 LVDS 收发器 | PM | 64 | -40 to 85;
| 型号： | DS92LV090ATVEHX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9 通道总线 LVDS 收发器 | PM | 64 | -40 to 85 驱动 接口集成电路 驱动器 |
| 文件： | 总19页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92LV090A
www.ti.com
SNLS025D –APRIL 2000–REVISED APRIL 2013
DS92LV090A 9 Channel Bus LVDS Transceiver
Check for Samples: DS92LV090A
1
FEATURES
DESCRIPTION
The DS92LV090A is one in a series of Bus LVDS
transceivers designed specifically for the high speed,
low power proprietary backplane or cable interfaces.
The device operates from a single 3.3V power supply
and includes nine differential line drivers and nine
receivers. To minimize bus loading, the driver outputs
and receiver inputs are internally connected. The
separate I/O of the logic side allows for loop back
support. The device also features a flow through pin
out which allows easy PCB routing for short stubs
between its pins and the connector.
2
•
•
•
•
•
Bus LVDS Signaling
3.2 Nanosecond Propagation Delay Max
Chip to Chip Skew ±800ps
Low Power CMOS Design
High Signaling Rate Capability (Above 100
Mbps)
•
0.1V to 2.3V Common Mode Range for VID
200mV
=
•
•
±100 mV Receiver Sensitivity
The driver translates 3V TTL levels (single-ended) to
differential Bus LVDS (BLVDS) output levels. This
allows for high speed operation, while consuming
minimal power with reduced EMI. In addition, the
differential signaling provides common mode noise
rejection of ±1V.
Supports Open and Terminated Failsafe on
Port Pins
•
•
3.3V Operation
Glitch Free Power Up/Down (Driver & Receiver
Disabled)
•
Light Bus Loading (5 pF Typical) per Bus
LVDS Load
The receiver threshold is less than ±100 mV over a
±1V common mode range and translates the
differential Bus LVDS to standard (TTL/CMOS)
levels. (See Applications Information Section for more
details.)
•
•
•
•
Designed for Double Termination Applications
Balanced Output Impedance
Product Offered in 64 Pin LQFP Package
High Impedance Bus Pins on Power off (VCC
0V)
=
•
•
Driver Channel to Channel Skew (Same
Device) 230ps Typical
Receiver Channel to Channel Skew (Same
Device) 370ps Typical
Simplified Functional Diagram
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
DS92LV090A
SNLS025D –APRIL 2000–REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 2. Top View
Package Number PM0064
PIN DESCRIPTIONS
Pin Name
Pin #
Input/Output
Descriptions
DO+/RI+
27, 31, 35, 37, 41, 45,
47, 51, 55
I/O
I/O
I
True Bus LVDS Driver Outputs and Receiver Inputs.
Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
TTL Driver Input.
DO−/RI−
DIN
26, 30, 34, 36, 40, 44,
46, 50, 54
2, 6, 12, 18, 20, 22, 58,
60, 62
RO
3, 7, 13, 19, 21, 23, 59,
61, 63
O
TTL Receiver Output.
RE
DE
17
16
I
Receiver Enable TTL Input (Active Low).
Driver Enable TTL Input (Active High).
I
GND
4, 5, 9, 14, 25, 56
Power
Ground for digital circuitry (must connect to GND on PC board). These pins
connected internally.
VCC
AGND
AVCC
NC
10, 15, 24, 57, 64
28, 33, 43, 49, 53
29, 32, 42, 48, 52
1, 8, 11, 38, 39
Power
Power
Power
N/A
VCC for digital circuitry (must connect to VCC on PC board). These pins
connected internally.
Ground for analog circuitry (must connect to GND on PC board). These pins
connected internally.
Analog VCC (must connect to VCC on PC board). These pins connected
internally.
Leave open circuit, do not connect.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNLS025D –APRIL 2000–REVISED APRIL 2013
(1)(2)(3)
Absolute Maximum Ratings
Supply Voltage (VCC
Enable Input Voltage (DE, RE)
Driver Input Voltage (DIN
)
4.0V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
>4.5 kV
)
Receiver Output Voltage (ROUT
Bus Pin Voltage (DO/RI±)
)
ESD (HBM 1.5 kΩ, 100 pF)
Driver Short Circuit Duration
Receiver Short Circuit Duration
momentary
momentary
Maximum Package Power Dissipation at 25°C
LQFP
1.74 W
Derate LQFP Package
13.9 mW/°C
71.7°C/W
θja
θjc
10.9°C/W
Junction Temperature
+150°C
Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)
−65°C to +150°C
260°C
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD, ΔVOD and VID
.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device
operation.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.0
Max
3.6
Units
V
Supply Voltage (VCC
)
Receiver Input Voltage
Operating Free Air Temperature
Maximum Input Edge Rate (20% to 80%)
Data
0.0
2.4
V
−40
+85
°C
(1)
Δt/ΔV
ns/V
ns/V
1.0
3.0
Control
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
Copyright © 2000–2013, Texas Instruments Incorporated
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SNLS025D –APRIL 2000–REVISED APRIL 2013
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DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified
(1)(2)
Symbol
Parameter
Conditions
Pin
Unit
Min
Typ
Max
s
mV
mV
V
VOD
ΔVOD
VOS
Output Differential Voltage
VOD Magnitude Change
Offset Voltage
RL = 27Ω, Figure 3
DO+/RI+,
DO−/RI−
240
300
460
27
1.1
1.3
5
1.5
10
ΔVOS
VOH
VOL
Offset Magnitude Change
Driver Output High Voltage(3)
Driver Output Low Voltage(3)
mV
V
RL = 27Ω
RL = 27Ω
1.4
1.1
1.65
0.95
V
(4)
IOSD
Output Short Circuit Current
VOD = 0V, DE = VCC, Driver outputs
shorted together
|36|
|65|
mA
(5)
VOH
Voltage Output High
VID = +300 mV
Inputs Open
IOH = −400 µA
ROUT
V
CC−0.2
CC−0.2
V
V
V
Inputs Terminated,
RL = 27Ω
VCC−0.2
V
VOL
IOD
Voltage Output Low
IOL = 2.0 mA, VID = −300 mV
VID = 300mV, VOUT = VCC−1.0V
VID = −300mV, VOUT = 1.0V
DE = 0V, VCM = 1.5V
0.05
|75|
|75|
0.075
V
Receiver Output Dynamic
−110
mA
mA
mV
mV
(4)
Current
110
VTH
Input Threshold High
DO+/RI+,
DO−/RI−
+100
VTL
Input Threshold Low
−100
VCMR
Receiver Common Mode Range
|VID|/2
2.4 −
|VID|/2
V
IIN
Input Current
DE = 0V, RE = 2.4V,
VIN = +2.4V or 0V
−20
±1
±1
+20
µA
VCC = 0V, VIN = +2.4V or 0V
−20
2.0
+20
VCC
0.8
µA
V
VIH
VIL
IIH
Minimum Input High Voltage
Maximum Input Low Voltage
Input High Current
DIN, DE, RE
GND
−20
−20
−1.5
V
VIN = VCC or 2.4V
VIN = GND or 0.4V
ICLAMP = −18 mA
±10
±10
−0.8
+20
+20
µA
µA
V
IIL
Input Low Current
VCL
ICCD
Input Diode Clamp Voltage
Power Supply Current Drivers
Enabled, Receivers Disabled
No Load, DE = RE = VCC
DIN = VCC or GND
,
VCC
55
73
35
80
80
80
mA
mA
mA
ICCR
ICCZ
ICC
Power Supply Current Drivers
Disabled, Receivers Enabled
DE = RE = 0V, VID = ±300mV
Power Supply Current, Drivers
and Receivers TRI-STATE
DE = 0V; RE = VCC
,
DIN = VCC or GND
Power Supply Current, Drivers
and Receivers Enabled
DE = VCC; RE = 0V,
DIN = VCC or GND,
RL = 27Ω
170
210
+20
mA
µA
IOFF
Power Off Leakage Current
VCC = 0V or OPEN,
DIN, DE, RE = 0V or OPEN,
VAPPLIED = 3.6V (Port Pins)
DO+/RI+,
DO−/RI−
−20
COUTPUT Capacitance @ Bus Pins
cOUTPUT Capacitance @ ROUT
DO+/RI+,
DO−/RI−
5
7
pF
pF
ROUT
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified except VOD, ΔVOD and VID
.
(2) All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
(3) The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.
(4) Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
(5) VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
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SNLS025D –APRIL 2000–REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
(2)
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tTLH
Differential Prop. Delay High to Low
RL = 27Ω,
Figure 4, Figure 5,
CL = 10 pF
0.6
0.6
1.4
1.4
80
2.2
2.2
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
(2)
Differential Prop. Delay Low to High
(3)
Differential Skew |tPHLD–tPLHD
|
(4)
Chip to Chip Skew
1.6
0.45
1.2
1.2
8
(5)
Channel to Channel Skew
0.25
0.6
0.5
3
Transition Time Low to High
Transition Time High to Low
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
tTHL
tPHZ
RL = 27Ω,
Figure 6, Figure 7,
CL = 10 pF
tPLZ
3
8
tPZH
3
8
tPZL
3
8
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
(2)
tPHLD
tPLHD
tSDK1
tSDK2
tSDK3
tTLH
Differential Prop. Delay High to Low
Figure 8, Figure 9,
CL = 35 pF
1.6
1.6
2.4
2.4
80
3.2
3.2
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
(2)
Differential Prop Delay Low to High
(3)
Differential Skew |tPHLD–tPLHD
|
(4)
Chip to Chip Skew
1.6
0.60
2.5
2.5
10
8
(5)
Channel to Channel Skew
0.35
1.5
1.5
4.5
3.5
3.5
3.5
Transition Time Low to High
Transition Time High to Low
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
tTHL
tPHZ
RL = 500Ω,
Figure 10, Figure 11,
CL = 35 pF
tPLZ
tPZH
8
tPZL
8
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) Propagation delays are specified by design and characterization.
(3) tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.
(4) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
(5) Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device,
either edge.
Copyright © 2000–2013, Texas Instruments Incorporated
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SNLS025D –APRIL 2000–REVISED APRIL 2013
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APPLICATIONS INFORMATION
General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028),
AN-903 (SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008).
There are a few common practices which should be implied when designing PCB for Bus LVDS signaling.
Recommended practices are:
•
•
•
Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface
mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer
ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and
ground. The capacitors should be as close as possible to the VCC pin.
–
–
Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors should be used.
•
•
•
Use the termination resistor which best matches the differential impedance of your transmission line.
Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
•
Use controlled impedance media. The backplane and connectors should have a matched differential
impedance.
Table 1. Functional Table
MODE SELECTED
DRIVER MODE
DE
H
L
RE
H
L
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
L
H
L
H
Table 2. Transmitter Mode
INPUTS
OUTPUTS
DE
H
DIN
L
DO+
L
DO−
H
H
H
H
L
H
0.8V< DIN <2.0V
X
X
X
L
Z
Z
Table 3. Receiver Mode(1)
INPUTS
OUTPUT
RE
(RI+) – (RI−)
L (< −100 mV)
H (> +100 mV)
−100 mV < VID < +100 mV
X
L
L
L
H
X
Z
L
H
(1) X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
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SNLS025D –APRIL 2000–REVISED APRIL 2013
Test Circuits and Timing Waveforms
Figure 3. Differential Driver DC Test Circuit
Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms
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SNLS025D –APRIL 2000–REVISED APRIL 2013
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Figure 6. Driver TRI-STATE Delay Test Circuit
Figure 7. Driver TRI-STATE Delay Waveforms
Figure 8. Receiver Propagation Delay and Transition Time Test Circuit
Figure 9. Receiver Propagation Delay and Transition Time Waveforms
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SNLS025D –APRIL 2000–REVISED APRIL 2013
Figure 10. Receiver TRI-STATE Delay Test Circuit
Figure 11. Receiver TRI-STATE Delay Waveforms
Typical Bus Application Configurations
Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications
Figure 13. Multi-Point Bus Applications
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SNLS025D –APRIL 2000–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92LV090ATVEH/NOPB
DS92LV090ATVEHX/NOPB
ACTIVE
LQFP
LQFP
PM
64
64
160
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DS92LV090A
TVEH
ACTIVE
PM
1000 RoHS & Green
SN
DS92LV090A
TVEH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV090ATVEHX/
NOPB
LQFP
PM
64
1000
330.0
24.4
12.35 12.35
2.2
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
LQFP PM 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS92LV090ATVEHX/
NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS92LV090ATVEH/
NOPB
PM
LQFP
64
160
8 X 20
150
322.6 135.9 7620 15.2
13.1
13
Pack Materials-Page 3
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
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EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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