HD3SS212_V01 [TI]
HD3SS212 5.4Gbps DisplayPort 1.2 2-to-1 Differential Switch;
| 型号： | HD3SS212_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HD3SS212 5.4Gbps DisplayPort 1.2 2-to-1 Differential Switch |
| 文件： | 总26页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD3SS212
SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
HD3SS212 5.4Gbps DisplayPort 1.2 2-to-1 Differential Switch
1 Features
3 Description
•
•
•
•
•
Compatible with DisplayPort 1.2 electrical standard
2:1 switching supporting data rates up to 5.4Gbps
Supports HPD switching
Wide -3dB differential BW of over 5.4 GHz
Excellent dynamic characteristics (at 2.7GHz)
– Crosstalk = –50dB
The HD3SS212 is a high-speed passive switch
capable of switching two full DisplayPort 4 lane ports
from one of two sources to one target location in an
application. For DisplayPort applications that
HD3SS212 also supports switching of the Auxiliary
(AUX) and Hot Plug Detect (HPD) signals. HPD path
is a buffer which requires a 125kΩ pull-down resistor
on the HPDC line.
– Isolation = –22dB
– Insertion loss = –1.4dB
A typical application would be a mother board that
includes two GPUs that need to drive one DisplayPort
sink. The GPU is selected by the Dx_SEL pin. The
HD3SS212 is offered in a 48-ball bfBGA package and
specified to operate from a single supply voltage of
3.3V over full industrial temperature range of –40°C to
105°C.
– Return loss = –11 dB
– Max bit-bit skew = 4 ps
•
•
VDD operating range 3.3 V ±10%
Small 5 mm x 5 mm x 1 mm, 48-ball nFBGA
package
Output enable (oe) pin disables switch to save
power
•
•
Device Information (1)
Power consumption
PART NUMBER
PACKAGE
BODY SIZE (NOM)
– HD3SS212 <10mW (standby <30µW when OE
= L)
HD3SS212
nFBGA (48)
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
PC & notebooks
Tablets
Connected peripherals & printers
VDD
4
DAz (p)
SEL = 0
4
DAz (n)
4
(p)
(n)
DCz
DCz
(z= 0,1,2or3)
4
4
4
DBz(p)
DBz(n)
SEL = 1
SEL
Dx_SEL
SEL
HPDA
HPDB
SEL = 0
HPDC
125kW
SEL = 1
SEL
AUXA(p)
AUXA(n)
SEL = 0
(p)
AUXC
AUXC
(n)
AUXB(p)
AUXB(n)
SEL = 1
OE
HD3SS212
GND
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS212
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Function.....................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
7.1 Test Timing Diagrams................................................. 8
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 13
10 Layout...........................................................................16
10.1 Layout Guidelines................................................... 16
10.2 Layout Example...................................................... 16
11 Device and Documentation Support..........................17
11.1 Receiving Notification of Documentation Updates..17
11.2 Community Resource..............................................17
11.3 Trademarks............................................................. 17
12 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2016) to Revision D (December 2020)
Page
•
NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
Changed u*jr BGA to nFBGA............................................................................................................................. 1
Changed u*jr ZQE to nFBGA ZXH. Updated thermal information......................................................................5
Corrected typo from HD3SS3412 to HD3SS212..............................................................................................16
•
•
•
Changes from Revision B (January 2014) to Revision C (October 2016)
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .......... 1
Deleted Ordering Information table. See POA at the end of the datasheet. ......................................................1
•
Changes from Revision A (March 2012) to Revision B (January 2014)
Page
•
Changed OE to OE throughout document..........................................................................................................1
Changes from Revision * (December 2011) to Revision A (March 2012)
Page
•
Changed Description From: full industrial temperature range of –40°C to 85°C To: full industrial temperature
range of –40°C to 105°C.....................................................................................................................................1
Added Operating Temperature to the Abs Max Table.........................................................................................5
Changed the Operating free-air temperature From MAX = 85°C To: 105°C...................................................... 5
Changed the values of ψJT and ψJB in the Thermal Information table................................................................5
Changed the MAX value of Leakage current (Dx_SEL), VDD = 0 V From: 8µA To: 10µA.................................6
•
•
•
•
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
5 Pin Configuration and Function
1
2
3
4
5
6
7
8
9
Dx_SEL
VDD
DA0(n)
DA1(n)
DA2(n)
DA3(p)
DA3(n)
A
B
C
D
E
F
OE
DC0(n)
DC0(p)
NC
GND
DA0(p)
DA1(p)
DA2(p)
DB0(p)
GND
DB0(n)
DC1(n)
DC2(n)
DC3(n)
DC1(p)
DC2(p)
DC3(p)
GND
DB1(p)
DB2(p)
DB3(p)
GND
DB1(n)
DB2(n)
DB3(n)
G
AUXC(n)
HPDC
AUXC(p)
HPDA
HPDB
GND
VDD
NC
NC
AUXB(p)
AUXB(n)
GND
NC
AUXA(p)
AUXA(n)
H
J
NC
Table 5-1. Pin Functions
PIN
PIN NAME
I/O
DESCRIPTION
A1
Dx_SEL
Control I
High Speed Port Selection Control Pins
B4
A4
DA0(p)
DA0(n)
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B5
A5
DA1(p)
DA1(n)
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
B6
A6
DA2(p)
DA2(n)
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
A8
A9
DA3(p)
DA3(n)
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
B8
B9
DB0(p)
DB0(n)
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
D8
D9
DB1(p)
DB1(n)
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
E8
E9
DB2(p)
DB2(n)
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
F8
F9
DB3(p)
DB3(n)
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
B2
B1
DC0(p)
DC0(n)
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
D2
D1
DC1(p)
DC1(n)
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
E2
E1
DC2(p)
DC2(n)
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
F2
F1
DC3(p)
DC3(n)
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
H9
J9
AUXA(p)
AUXA(n)
Port A AUX Positive Signal
Port A AUX Negative Signal
H6
J6
AUXB(p)
AUXB(n)
Port B AUX Positive Signal
Port B AUX Negative Signal
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Table 5-1. Pin Functions (continued)
PIN
PIN NAME
I/O
DESCRIPTION
H2
H1
AUXC(p)
AUXC(n)
Port C AUX Positive Signal
Port C AUX Negative Signal
I/O
J2, H3, J1
B7
HPDA/B/C
OE
I/O
I
Port A/B/C Hot Plug Detect
Output Enable
A2, J4
VDD
Supply
3.3V Positive power supply voltage
B3, C8, G2,
G8, H4, H7
GND
NC
Supply
Negative power supply voltage
Electrically not connected
C2, H5, H8,
J5, J8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.5
–0.5
–0.5
–40
MAX
UNIT
V
Supply voltage range(3)
Voltage range
VDD
4
4
Differential I/O
Control pin
V
VCC +0.5
105
V
Operating free-air temperature
Continuous power dissipation
Storage temperature
°C
See Section 6.4
–55
125
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM) (1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM) (2)
(1) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(2) Tested in accordance with JEDEC Standard 22, Test Method A115-A
6.3 Recommended Operating Conditions
Nominal values for all parameters are at VCC = 3.3V and TA = 25°C, all temperature limits are specified by design
PARAMETER
Supply voltage
Input high voltage
Input low voltage
CONDITIONS
MIN
NOM
MAX
UNIT
VDD
VIH
VIL
3.0
3.3
3.6
V
V
V
Control Pins, Signal Pins (Dx_SEL, OE) (HPDC, 5V Tolerant)
Control Pins, Signal Pins (Dx_SEL, OE, HPDC)
2.0
VDD
0.8
–0.1
Differential voltage (Dx,
AUXx)
VI/O_Diff
VI/O_CM
Switch I/O diff voltage
0
0
1.8
2.0
Vpp
V
Common voltage (Dx,
AUXx)
Switch I/O common mode voltage
Operating free-air
temperature
–40
105
°C
6.4 Thermal Information
HD3SS212
nFBGA (ZXH)
48-Ball
64.9
THERMAL METRIC(1)
UNIT
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
28.7
Junction-to-board thermal resistance
36.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.0
ψJB
36.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
under recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DEVICE PARAMETERS
IIH
IIL
Input high current (Dx_SEL)
Input low current (Dx_SEL)
VDD = 3.6 V, VIN = VDD
3
0.01
2
10 µA
VDD = 3.6 V, VIN = GND
1
5
µA
VDD = 3.3 V, Vi = 2V, OE = 3.3V
VDD = 0 V, Vi = 2 V, OE = 3.3 V
Leakage current (Dx_SEL)
6
10
2
ILK
µA
Leakage current (HPDA)
Leakage current (HPDB)
Device shut down current
VDD = 3.3 V, Vi = 2 V, OE = 3.3 V; Dx_SEL=3.3 V
VDD = 3.3 V, Vi = 2 V, OE = 3.3 V; Dx_SEL=GND
VDD = 3.6 V, OE = GND
0.01
0.01
2
Ioff
5
µA
VDD = 3.6 V, Dx_SELx = VCC/GND; Outputs
floating
IDD
Supply current
2.5
5
mA
DA, DB, DC HIGH SPEED SIGNAL PATH
CON
COFF
RON
Outputs ON capacitance
Outputs OFF capacitance
Output ON resistance
Vi = 0 V, Outputs open, Switch ON
1.5
1
pF
pF
Ω
Vi = 0 V, Outputs open, Switch OFF
VDD = 3.3 V, VCM = 0.5V - 1.5 V, IO = –40 mA
6.5
10
On resistance match between pairs of the
same channel
ΔRON
VDD = 3.3 V; -0.35V ≤ VI ≤ 1.2 V; IO = –40 mA
VDD = 3.3 V; -0.35 V ≤ VI ≤ 1.2 V
1.5
Ω
Ω
On resistance flatness (RON (MAX) – RON
RFLAT_ON
1.3
)
(MAIN)
AUXx SIGNAL PATH
CON
COFF
RON
Outputs ON capacitance
Vi = 0 V, Outputs open, Switch ON
9
3
7
pF
pF
Ω
Outputs OFF capacitance
Output ON resistance
Vi = 0 V, Outputs open, Switch OFF
VDD = 3.3 V, VCM = 0.5 V - 1.5 V, IO = -40 mA
12
DEVICE PARAMETERS (under recommended operating conditions; RL, Rsc = 50 Ω unless otherwise noted
tPD
Switch propagation delay
Rsc and RL = 50 Ω, See Figure 7-2
200 ps
Ton
Dx_SEL -to-Switch Ton (Data and AUX)
Dx_SEL -to-Switch Toff (Data and AUX)
Dx_SEL -to-Switch Ton (HPD)
Dx_SEL -to-Switch Toff (HPD)
Inter-pair output skew (CH-CH)
Intra-pair output skew (bit-bit)
175
175
275
275
250
ns
Rsc and RL = 50 Ω, See Figure 7-1
Toff
250
Ton
350
ns
350
RL = 50 Ω, See Figure 7-1
Toff
TSK(O)
TSK(b-b)
50
ps
4
Rsc and RL = 1 kΩ, See Figure 7-2
1
–17
–11
–50
–22
–0.7
–1.4
–1.7
–1
1.35 GHz, See Section 6.6
2.7 GHz, See Section 6.6
2.7 GHz
RL
Dx Differential return loss(1)
dB
XTALK
OIRR
Dx Differential crosstalk(1)
Dx Differential off-isolation(1)
2.7 GHz, See Section 6.6
f = 1.35 GHz, See Section 6.6
f = 2.7 GHz, See Section 6.6
f = 5.4 GHz, See Section 6.6
f = 360 MHz
Dx Differential insertion loss(1)
AUX Differential insertion loss(1)
dB
dB
IL
(1) For Return Loss, Crosstalk, Off-Isolation, and Insertion Loss values the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
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6.6 Typical Characteristics
0
-5
0
-5
-10
-10
-15
-20
-25
-30
-15
-20
-25
-30
1E10 2E10
1E8
1E9
1E8
1E9
1E10 2E8
Frequency - Hz
Frequency - Hz
Figure 6-2. Return Loss
Figure 6-1. Insertion Loss and -3dB Bandwidth
0
-20
-40
-60
-80
-100
1E8
1E9
1E10 2E10
Frequency - Hz
Figure 6-3. OF Isolation
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7 Parameter Measurement Information
7.1 Test Timing Diagrams
50%
Dx_SEL
90%
VOUT
10%
Ton
Toff
Figure 7-1. Select to Switch Ton and Toff
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Vcc
50 Ω
DAx/DBx(p)
DAx/DBx(n)
DCx(p)
50 Ω
50 Ω
DCx(n)
50 Ω
SEL
DAx/DBx(p)
50%
50%
DAx/DBx(n)
DCx(p)
50%
50%
DCx(n)
DCx(p)
tP1
t2
tP2
t4
t1
t3
50%
DCx(n)
DCy(p)
tSK(O)
DCy(n)
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any
two pairs of outputs
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
Figure 7-2. Propagation Delay and Skew
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8 Detailed Description
8.1 Overview
The HD3SS212 is a high-speed passive switch offered in an industry standard 48-pin u*BGA package available
in a common footprint shared by several other vendors. The device is specified to operate from a single supply
voltage of 3.3 V over the industrial temperature range of -40°C to 105°C.
The HD3SS212 is a generic 4-CH high-speed mux/demux type of switch that can be used for routing high-speed
signals between two different locations on a circuit board. The HD3SS212 will also support several other high-
speed data protocols with a differential amplitude of < 1800 mVpp and a common-mode voltage of < 2.0 V, as
with USB 3.0 and DisplayPort 1.2. For Display Port Applications the HD3SS212 also supports switching of both
the Auxiliary and Hot Plug Detect signals.
The device’s High Speed Port Selection Control input (Dx_SEL) pin can easily be controlled by an available
GPIO pin within a system.
8.2 Functional Block Diagram
VDD
4
DAz (p)
SEL = 0
4
DAz (n)
4
(p)
(n)
DCz
DCz
(z= 0,1,2or3)
4
4
4
DBz(p)
DBz(n)
SEL = 1
SEL
Dx_SEL
SEL
HPDA
HPDB
SEL = 0
HPDC
SEL = 1
125kW
SEL
AUXA(p)
AUXA(n)
SEL = 0
(p)
AUXC
AUXC
(n)
AUXB(p)
AUXB(n)
SEL = 1
OE
HD3SS212
GND
8.3 Feature Description
Refer to Section 8.2.
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The HD3SS212 behaves as a two to one using high bandwidth pass gates. The input port is selected using the
Dx_SEL pin according to Table 8-1.
Table 8-1. Switch Control Logic
CONTROL LINES
Dx_SEL
SWITCHED I/O PINS(1) (2)
DCz(p) PIN
z = 0, 1, 2 or 3
DCz(n) PIN
z = 0, 1, 2 or 3
HPDC PIN
AUXC(p) PIN
AUXC(n) PIN
L
DAz(p)
DBz(p)
DAz(n)
DBz(n)
HPDA
HPDB
AUXA(p)
AUXA(n)
H
AUXVB(p)
AUXVB(n)
(1) OE pin - For nomal operation, drive OE high. Driving the OE pin low will disable the switch to enable power savings.
(2) The ports which are not selected by the Control Lines will be in High Impedance State.
8.4 Device Functional Modes
The HD3SS212 can be operated in normal operation mode or in shut down mode. In normal operation, the input
ports of the HD3SS212 are routed to the output ports according to Table 8-1. In shut down mode the HD3SS212
is disabled to enable power savings with a typical current consumption of 5 µA. The functional mode is selected
through the OE input pin with High for normal operation and LOW for shut down.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 AC Coupling Caps
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the
preferred option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and
C-packs should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor
value of 0.1 µF is best and the value should be match for the ± signal pair. The placement should be along the
TX pairs on the system board, which are usually routed on the top layer of the board. There are several
placement options for the AC coupling capacitors. Because the switch requires a bias voltage, the capacitors
must only be placed on one side of the switch. If they are placed on both sides of the switch, a biasing voltage
should be provided. A few placement options are shown below. In Figure 9-1, the coupling capacitors are placed
between the switch and endpoint. In this situation, the switch is biased by the system/host controller.
Port A
RX
Device/
Endpoint
Port B
TX
TX
System/Host
Controller
Port A
Port B
RX
RX
Device/
Endpoint
TX
Figure 9-1. AC Coupling Capacitors Between Switch TX and Endpoint TX
In Figure 9-2, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Port A
RX
Device/
Endpoint
Port B
TX
TX
System/Host
Controller
Port A
Port B
RX
RX
Device/
Endpoint
TX
Figure 9-2. AC Coupling Capacitors on Host TX and Endpoint TX
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If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides
of the switch (shown in Figure 9-3). A biasing voltage of less than 2 V is required in this case.
VBIAS
Port A
RX
Device/
Endpoint
Port B
TX
VBIAS
System/Host
Controller
TX
RX
Port A
Port B
RX
Device/
Endpoint
TX
Figure 9-3. AC Coupling Capacitors on Both Sides of Switch
9.2 Typical Application
DAx (p)
DAx (n)
4
4
DCx(p)
DCx(n)
4
4
GPU/
Source A
AUXAx
HPDA
2
Sink/
Connector
AUXCx
HPDC
2
HPDB
AUXBx
2
GPU/
Source B
Dx_SEL
Control
AUX _SEL
DBx (p)
DBx (n)
4
4
HD3SS212
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Figure 9-4. Dual Source Connection Block Diagram
9.2.1 Design Requirements
Table 9-1 lists the design parameters.
Table 9-1. Design Parameters
DESIGN PARAMETERS
Input voltage range
Decoupling capacitors
AC capacitors
EXAMPLE VALUE
3.3 V
0.1 µF
75 nF – 200 nF (100 nF shown) USBAA TX p and
AC capacitors n lines require AC capacitors.
Alternate mode signals may or may not require AC
capacitors
9.2.2 Detailed Design Procedure
•
Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-µF bypass
capacitor
•
Use +3.3-V TTL/CMOS logic level at SEL
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HD3SS212
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
•
•
Use controlled-impedance transmission media for all the differential signals
Ensure the received complimentary signals are with a differential amplitude of < 1800 mVpp and a common-
mode voltage of < 2V.
9.2.3 Application Curves
0
-5
0
-5
-10
-15
-20
-25
-10
-15
-20
-25
-30
-30
1E8
1E10 2E10
1E8
1E9
1E9
Frequency - Hz
1E10 2E8
Frequency - Hz
Figure 9-6. Return Loss
Figure 9-5. Insertion Loss and -3dB Bandwidth
0
-20
-40
-60
-80
-100
1E8
1E9
1E10 2E10
Frequency - Hz
Figure 9-7. OF Isolation
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HD3SS212
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
Power Supply Recommendations
The HD3SS212 requires +3.3-V digital power sources. VDD 3.3 supply must have 0.1-µF bypass capacitors to
VSS (ground) in order for proper operation. The recommendation is one capacitor for each power terminal. Place
the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller
value capacitors like 0.01-µF are also recommended on the digital supply terminals.
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HD3SS212
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
10 Layout
10.1 Layout Guidelines
•
Decoupling caps should be placed next to each power terminal on the HD3SS212. Take care to minimize the
stub length of the race connecting the capacitor to the power pin.
•
•
•
•
Avoid sharing vias between multiple decoupling caps
Place vias as close as possible to the decoupling cop solder pad
Widen VDD/GND planes to reduce effect if static and dynamic IR drop
The VBUS traces/planes must be wide enough to carry maximum of 2-A current
10.2 Layout Example
Use controlled-impedance
Transmission media for all
Differential signals
VDD3P3
VDD3P3
AX+
AX-
BX+
BX-
CX+
CX-
VSS
SEL
VBUS
GND
3.3V Logic level
VBUS traces wide
enough to carry 2A
current
Figure 10-1. Layout Example
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HD3SS212
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SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resource
11.3 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
PACKAGING INFORMATION
Orderable Device
HD3SS212ZQER
HD3SS212ZQET
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LIFEBUY
BGA
MICROSTAR
JUNIOR
ZQE
48
48
2500 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
HD3SS212
LIFEBUY
BGA
ZQE
250
RoHS & Green
SNAGCU
-40 to 85
HD3SS212
MICROSTAR
JUNIOR
HD3SS212ZXHR
HD3SS212ZXHT
ACTIVE
ACTIVE
NFBGA
ZXH
ZXH
48
48
2500 RoHS & Green
250 RoHS & Green
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
HD3SS212
HD3SS212
NFBGA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS212ZXHR
HD3SS212ZXHT
NFBGA
NFBGA
ZXH
ZXH
48
48
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS212ZXHR
HD3SS212ZXHT
NFBGA
NFBGA
ZXH
ZXH
48
48
2500
250
336.6
336.6
336.6
336.6
31.8
31.8
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0048A
A
5.1
4.9
B
BALL A1 CORNER
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
(0.5) TYP
4 TYP
J
(0.5) TYP
H
G
F
SYMM
4
TYP
E
D
C
0.35
48X Ø
0.25
B
A
0.15
0.05
C A B
C
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
SYMM
4225133 /A 08/2019
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0048A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
SYMM
48X (Ø0.25)
G
H
J
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225133 /A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZXH0048A
(0.5) TYP
3
1
2
4
5
6
7
8
9
A
B
(0.5) TYP
C
D
E
F
METAL
TYP
SYMM
(R0.05) TYP
G
H
J
48X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 20X
4225133 /A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2021, Texas Instruments Incorporated
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