HD3SS3202 [TI]
2 通道 10Gbps 2:1/1:2 USB 3.1 差分多路复用器/多路信号分离器;
| 型号： | HD3SS3202 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2 通道 10Gbps 2:1/1:2 USB 3.1 差分多路复用器/多路信号分离器 复用器 |
| 文件： | 总27页 (文件大小：1452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
HD3SS3202 双通道差动 2:1/1:2 USB 3.1 多路复用器/多路信号分离器
1 特性
3 说明
1
•
提供面向支持 USB 3.1 第 1 代和第 2 代数据传输
速率的 USB Type-C™ 生态系统的解决方案
HD3SS3202 是多路复用器或多路信号分离器配置中的
高速双向无源开关， 适用于 支持 USB 3.1 第 1 代和
第 2 代数据传输速率的 USB Type-C™ 应用。该器件
可通过控制引脚 SEL 在两个差动通道（端口 B 到端口
A，或者端口 C 到端口 A）间切换。
•
兼容 MIPI DSI/CSI-2 DPHY、LVDS、第 III 代
PCIE、SATA Express、SATA
•
•
•
运行速率高达 10Gbps
-3dB 差动带宽宽达 8GHz 以上
出色动态特性（5GHz 时）
HD3SS3202 是一款通用的模拟差动无源开关。该器件
适用于任何要求共模电压范围为 0 至 2V 和要求差动信
号的最大差动幅度为 1800mVpp 的应用。该器件具有
自适应跟踪功能，可确保通道在完全共模电压范围内保
持不变。
–
–
–
–
串扰 = -41dB
断开隔离 = –20dB
插入损耗 = –2.4dB
回波损耗 = –8dB
该器件可在确保信号眼图最低衰减程度的条件下实现高
速开关，且不会明显增加抖动。它的运行功率低于
1.65mW（典型值）。它具有可供 OEn 引脚使用的关
断模式，可实现低于 0.02µW（典型值）的功率。
•
•
•
•
•
双向“多路复用器/多路信号分离器”差动开关
支持 0 到 2V 共模电压
单电源电压 VCC：3.3V±10%
0°C 至 70°C 的商用温度范围 (HD3SS3202)
-40°C 至 85°C 的工业温度范围 (HD3SS3202I)
器件信息(1)
器件型号
封装
封装尺寸（标称值）
2 应用
HD3SS3202
HD3SS3202I
UQFN (16)
2.60mm x 1.80mm
•
•
•
•
•
•
•
USB Type-C™ 生态系统
台式机和笔记本电脑
共享 I/O 端口
扩展坞
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
显示器、电视
机顶盒
网络监控摄像头
简化原理图
B0+
B0œ
A0+
A0œ
C0+
C0œ
SEL
B1+
B1œ
A1+
A1œ
C1+
C1œ
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEO1
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 14
9.3 Systems Examples.................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 High-Speed Performance Parameters...................... 5
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 接收文档更新通知 ................................................. 19
12.2 社区资源................................................................ 19
12.3 商标....................................................................... 19
12.4 静电放电警告......................................................... 19
12.5 术语表 ................................................................... 19
13 机械、封装和可订购信息....................................... 19
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (May 2018) to Revision A
Page
•
Changed ICC max from 0.6mA to 0.8mA................................................................................................................................. 5
2
Copyright © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
RSV Package
16-Pin UQFN
Top View
A0n
GND
VCC
A1p
1
12
11
10
9
B1p
B1n
C0p
C0n
2
3
4
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0n
NO.
1
I/O
G
Port A, channel 0, high-speed negative signal
Ground
GND
VCC
2
3
P
3.3-V power
A1p
4
I/O
I/O
Port A, channel 1, high-speed positive signal
Port A, channel 1, high-speed negative signal
A1n
5
Port select pin. To help with noise immunity, a 0.01 µF capacitor to GND on this pin is
suggested.
L: Port A to Port B
H: Port A to Port C
SEL
6
I
C1n
C1p
C0n
C0p
B1n
B1p
B0n
B0p
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port C, channel 1, high-speed negative signal (connector side)
Port C, channel 1, high-speed positive signal (connector side)
Port C, channel 0, high-speed negative signal (connector side)
Port C, channel 0, high-speed positive signal (connector side)
Port B, channel 1, high-speed negative signal (connector side)
Port B, channel 1, high-speed positive signal (connector side)
Port B, channel 0, high-speed negative signal (connector side)
Port B, channel 0, high-speed positive signal (connector side)
8
9
10
11
12
13
14
Active-low chip enable. To help with noise immunity, a 0.01 µF capacitor to GND on this pin
is suggested.
L: Normal operation
H: Shutdown
OEn
A0p
15
16
I
I/O
Port A, channel 0, high-speed positive signal
Copyright © 2018, Texas Instruments Incorporated
3
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–65
MAX
UNIT
VCC
Supply voltage
Voltage
4
2.5
V
Differential I/O
Control pins
V
VCC+ 0.5
150
Tstg
Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
VCC
0.8
1.8
2
UNIT
V
VCC
Vih
Supply voltage
3.3
Input high voltage (SEL, OEn pins)
Input low voltage (SEL, OEn pins)
High-speed signal pins differential voltage
High speed signal pins common mode voltage
2
V
Vil
–0.1
0
V
Vdiff
Vcm
Vpp
V
0
HD3SS3202RSV
HD3SS3202IRSV
0
70
TA
Operating free-air/ambient temperature
°C
–40
85
6.4 Thermal Information
HD3SS3202
RSV (VQFN)
16 PINS
117.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52.1
52.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ψJB
51.1
RθJC(bot)
n/a
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
MAX
0.8
1
UNIT
mA
µA
ICC
Device active current
VCC = 3.3 V, OEn = 0
ISTDN
CON
COFF
Device shutdown current
Output ON capacitance to GND
Output OFF capacitance to GND
VCC = 3.3 V, OEn = VCC
0.005
0.6
pF
0.8
pF
VCC = 3.3 V; VCM = 0 to 2 V;
IO = –8 mA
RON
Output ON resistance
5
8
0.7
1
Ω
Ω
Ω
On-resistance match between pairs of the
same channel
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
ΔRON
On-resistance flatness RON(MAX) –
RON(MIN)
RFLAT_ON
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
IIH,CTRL
IIL,CTRL
Input high current, control pins (SEL, OEn)
Input low current, control pins (SEL, OEn)
1
1
µA
µA
VIN = 2 V for selected port, A and B
with SEL = 0, and A and C with
SEL = VCC
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
IIH,HS
1
µA
VIN = 2 V for non-selected port, C
with SEL = 0, and B with
SEL = VCC
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
IIH,HS
100
140
1
µA
µA
(1)
Input low current, high-speed pins
[Ax/Bx/Cx][p/n]
IIL,HS
(1) There is a 20-kΩ pull-down in non-selected port.
6.6 High-Speed Performance Parameters
PARAMETER
TEST CONDITION
MIN
TYP
-0.4
-0.4
-1.3
-2.0
-2.4
8
MAX
UNIT
ƒ = 0.3 MHz
ƒ = 0.625 MHz
IL
Differential insertion loss
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
dB
BW
RL
–3-dB bandwidth
GHz
dB
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
-27
-11
-9
Differential return loss
-8
-77
-23
-21
-20
-82
-44
-41
-41
OIRR
Differential OFF isolation
Differential crosstalk
dB
dB
XTALK
Copyright © 2018, Texas Instruments Incorporated
5
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ps
tPD
Switch propagation delay (see 图 4)
80
0.5
0.5
6
tSW_ON
tSW_OFF
tSK_INTRA
tSK_INTER
Switching time SEL-to-Switch ON (see 图 3)
Switching time SEL-to-Switch OFF (see 图 3)
Intra-pair output skew (see 图 4)
µs
µs
ps
Inter-pair output skew (see 图 4)
20
54
63
59
57
56
53
50
50
50
50
50
ps
ƒ = 100 MHz
ƒ = 200 MHz
ƒ = 300 MHz
ƒ = 400 MHz
ƒ = 500 MHz
ƒ = 600 MHz
ƒ = 700 MHz
ƒ = 750 MHz
ƒ = 800 MHz
ƒ = 900 MHz
ƒ = 1000 MHz
16
33
33
33
33
33
33
33
33
31
30
tPD
Average propagation delay, see 图 1
ps
6.8 Typical Characteristics
70
60
50
40
30
20
10
0
Average Prop Delay
0
5E+8
1E+9
1.5E+9
Frequency (Hz)
D001
图 1. Average Propagation Delay vs Frequency
6
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
7 Parameter Measurement Information
VCC
RSC = 50 Ω
Axp
Bxp/Cxp
RL = 50 Ω
RSC = 50 Ω
Axn
Bxn/Cxn
RL = 50 Ω
图 2. Test Setup
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
图 3. Switch On and Off Timing Diagram
版权 © 2018, Texas Instruments Incorporated
7
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Parameter Measurement Information (接下页)
2.6-V Max
50%
50%
VIN
0 V
2.6-V Max
50%
50%
VOUT
0 V
tPD
VOUTp
VOUTn
50%
TSK_INTRA
B0/C0
VOUT
50%
50%
50%
50%
B1/C1
VOUT
tSK_INTER
图 4. Timing Diagrams and Test Setup
8
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
8 Detailed Description
8.1 Overview
The HD3SS3202 is a generic analog differential passive switch that can works for any high-speed interface
applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It uses adaptive tracking to ensures the channel remain unchanged for the entire
common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with little added jitter. It consumes < 1.65 mW (typ) of power when operational and has a
shutdown mode exercisable by OEn pin resulting < .02 µW (typical).
8.2 Functional Block Diagram
B0+
B0œ
A0+
A0œ
C0+
C0œ
SEL
B1+
B1œ
A1+
A1œ
C1+
C1œ
8.3 Feature Description
8.3.1 Output Enable and Power Savings
The HD3SS3202 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes little current to save the maximum power. To enter standby mode, the OEn
control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control
pin should be pulled low to GND.
HD3SS3202 consumes < 1.65 mW (typ) of power when operational and has a shutdown mode exercisable by
the OEn pin resulting < .02 µW (typ).
版权 © 2018, Texas Instruments Incorporated
9
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
8.4 Device Functional Modes
表 1. Port Select Control Logic(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
SEL = L
B0p
SEL = H
C0p
A0p
A0n
A1p
A1n
B0n
C0n
B1p
C1p
B1n
C1n
(1) The HD3SS3202 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
10
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The HD3SS3202 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing high-
speed signals between two different locations on a circuit board. The HD3SS3202 supports several high-speed
data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of < 2 V, as with USB
3.1 and DisplayPort 1.2. The device has one select input (SEL) pin that can be controlled by an available GPIO
pin within a system or from a microcontroller.
The HD3SS3202 with its adaptive common mode tracking technology can support applications where the
common mode is different between the RX and TX pair. The two USB3.1 Type C connector applications show
both a host and device side. The cable between the two connectors swivels the pairs to properly route the
signals to the correct pin. The other applications are more generic because different connectors can be used.
Many interfaces require AC coupling between the transmitter and receiver. The 0201 capacitors are the preferred
option to provide AC coupling; 0402 size capacitors also work. Avoid the capacitors greater than 0402 and C-
packs. When placing AC coupling capacitors, symmetric placement is best. The designer should place them
along the TX pairs on the system board, which are usually routed on the top layer of the board.
The AC coupling capacitors have several placement options. Because the HD3SS3202 requires a bias voltage,
the designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. 图 5 shows a few placement options. The coupling capacitors are placed
between the HD3SS3202 and endpoint. In this situation, the HD3SS3202 is biased by the system/host controller.
RX
Port B
Device/
TX
Endpoint
Port C
System/Host
TX
controller
Port B
RX
RX
Device/
Port C
Endpoint
TX
图 5. AC Coupling Capacitors between HD3SS3202 TX and Endpoint TX
版权 © 2018, Texas Instruments Incorporated
11
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Application Information (接下页)
In 图 6, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation,
the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
RX
Port B
Device/
TX
Endpoint
Port C
System/Host
TX
controller
Port B
RX
RX
Device/
Port C
Endpoint
TX
图 6. AC Coupling Capacitors on Host TX and Endpoint TX
If the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of
the switch (shown in 图 7). A biasing voltage of < 2 V is required in this case.
VBIAS
RX
Port B
Device/
TX
Endpoint
VBIAS
Port C
System/Host
TX
controller
Port B
RX
RX
Device/
Endpoint
Port C
TX
VBIAS can be GND
Capacitor and resistor values depend upon application.
图 7. AC Coupling Capacitors on Both Sides of Switch
12
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
Application Information (接下页)
The HD3SS3202 can be used with the USB Type C connector to support the connector’s flip ability. 图 8
provides the generic location for the AC coupling capacitors for this application.
Down Facing Port
Up Facing Port
TX1+
RX1+
TX1œ
RX1œ
RX+
TX+
TX
RX
RX1+
TX1+
RXœ
TXœ
RX1œ
TX1œ
System/Host
Controller
Hub
TX2+
TX2œ
RX2+
RX2œ
RX2+
RX2œ
TX2+
TX2œ
TX+
RX+
TX
TXœ
RX
RXœ
图 8. AC Coupling Capacitors for USB Type C
版权 © 2018, Texas Instruments Incorporated
13
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
9.2 Typical Applications
9.2.1 Down Facing Port for USB3.1 Type C
HD3SS3202
B0+
A2
A3
SSTXp1
SSTXn1
A1
GND
GND
GND
GND
B0t
C0+
C0t
B12
A0+
SSTXp
B2
SSTXp2
SSTXn2
SSRXp1
SSRXn1
SSRXp2
SSRXn2
A12
B1
A0t
SSTXn
SSRXp
B3
A1+
B11
B10
A11
A10
A5
B1+
A1t
OEn
SEL
SSRXn
USB Host
B1t
C1+
C1t
Optional
Controller
10 lQ
3.3V
CC1
CC2
B5
GND
USB-C
0.1 µF
3.3V
CC
Controller
图 9. Down Facing Port for USB3.1 Type C Connector
9.2.1.1 Design Requirements
The HD3SS3202 can be designed into many different applications. All the applications have certain requirements
for the system to work properly. The HD3SS3202 requires 3.3-V ±10% VCC rail. The OEn pin must be low for
device to work; otherwise, it disables the outputs. This pin can be driven by a processor. The expectation is that
one side of the device has AC coupling capacitors. 表 2 provides information on expected values to perform
properly.
表 2. Design Parameters
DESIGN PARAMETER
VALUE
3.3 V
VCC
AXp/n, BXp/n, CXp/n CM input voltage
Control/OEn pin max voltage for low
Control/OEn pin min voltage for high
AC coupling capacitor
0 to 2 V
0.8 V
2.0 V
75 nF to 265 nF.
100 kΩ
RBIAS (图 9) when needed
9.2.1.2 Detailed Design Procedure
The HD3SS3202 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 1 to 2 inches of board trace and a connector on either end.
To design in the HD3SS3202, the designer needs to understand the following.
•
•
•
•
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
Provide a control signal for the SEL and OEn pins. It may be necessary to include a 0.01µF to GND on each
of these pins to help with noise immunity.
•
See the application schematics on recommended decouple capacitors from VCC pins to ground
14
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
9.2.1.3 Application Curves
图 10 shows the eye at the input of the HD3SS3202 and 图 11 at the output of the HD3SS3202.
图 10. Source 10 Gbps Eye Diagram
图 11. HD3SS3202 10 Gbps Output Eye Diagram
9.3 Systems Examples
9.3.1 Up Facing Port for USB3.1 Type C
HD3SS3202
A2
B0+
SSTXp1
A1
GND
A3
SSTXn1
B0-
B12
A0+
A0-
GND
B2
SSTXp
SSTXn
SSTXp2
C0+
C0-
A12
GND
GND
B3
SSTXn2
SSRXP1
SSRXn1
SSRXp2
SSRXn2
B1
SSRXp
SRTXn
A1+
A1-
B11
B10
B1+
B1-
USB Device
OEn
SEL
A11
A10
C1+
C1-
Optional
Controller
10 kW
3.3V
A5
B5
CC1
CC2
GND
USB-C
0.1 µF
3.3V
CC
Controller
图 12. Up Facing Port for USB3.1 USB Type-C Connector
版权 © 2018, Texas Instruments Incorporated
15
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Systems Examples (接下页)
9.3.2 PCIE/USB
HD3SS3202
TXp1
TXn1
RXp1
RXn1
B0+
B0t
B1+
B1t
TXp
A0+
TXn
RXp
A0t
PCIe Connector
A1+
C0+
TXp2
TXn2
RXp2
RXn2
RXn
A1t
OEn
SEL
C0t
C1+
C1t
PCIE/USB
Optional
Controller
USB Connector
10 lQ
3.3V
GND
3.3V
0.1 µF
图 13. PCIE Motherboard
9.3.3 PCIE/eSATA
HD3SS3202
B0+
PCIE Controller
RXp1
B0t
RXn1
TXp1
TXn1
A0+
B1+
A0t
B1t
A1+
TXp
TXn
RXp
C0+
RXp2
RXn2
TXp2
TXn2
RXn
MINI CARD
mSATA Connector
A1t
C0t
OEn
C1+
SEL
Optional
Controller
C1t
eSATA Controller
10 lQ
3.3V
GND
3.3V
0.1 µF
图 14. PCIE and eSATA Combo
16
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
Systems Examples (接下页)
9.3.4 USB/eSATA
HD3SS3202
USB Controller
RXp1
B0+
B0t
B1+
B1t
RXn1
TXp1
TXn1
TXp
A0+
TXn
RXp
A0t
A1+
C0+
RXp2
RXn2
TXp2
RXn
A1t
OEn
SEL
C0t
C1+
C1t
USB/eSATA Connector
Optional
TXn2
Controller
eSATA Controller
10 lQ
3.3V
GND
0.1 µF
3.3V
图 15. eSATA and USB 3.1 Combo Connector
9.3.5 MIPI Camera Serial Interface
HD3SS3202
CSI-2 Camera
B0+
D0p
D0n
B0t
B1+
B1t
D0p
A0+
CLKp
CLKn
D0n
A0t
CLKp
A1+
C0+
D0p
CLKn
A1t
OEn
SEL
C0t
C1+
C1t
D0n
CSI-2 RX Chipset
CLKp
CLKn
Optional
Controller
10 lQ
CSI-2 Camera
GND
3.3V
0.1 µF
图 16. CSI Camera Array
版权 © 2018, Texas Instruments Incorporated
17
HD3SS3202
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
10 Power Supply Recommendations
The HD3SS3202 does not require a power supply sequence. TI recommends placing a 100nF de-coupling
capacitor at the device VCC near the pin.
11 Layout
11.1 Layout Guidelines
11.2 Layout Example
Example 4 layer PCB Stackup
Top Layer 1 (Signal)
Inner Layer 2 (GND)
Inner Layer 3 (VCC)
Bottom Layer 4 (Signal)
Via to layer 2 (GND)
Via to layer 3 (VCC)
9
12
13
8
SEL
OEn
5
16
4
1
GND
VCC
Place closed to
HD3SS3202
Copyright © 2018, Texas Instruments Incorporated
图 17. HD3SS3202 Basic Layout Example
18
版权 © 2018, Texas Instruments Incorporated
HD3SS3202
www.ti.com.cn
ZHCSIB1A –MAY 2018–REVISED SEPTEMBER 2018
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3202IRSVR
HD3SS3202IRSVT
HD3SS3202RSVR
HD3SS3202RSVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
3202
3202
3202
3202
NIPDAUAG
NIPDAUAG
NIPDAUAG
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS3202IRSVR
HD3SS3202IRSVT
HD3SS3202RSVR
HD3SS3202RSVT
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
16
16
16
16
3000
250
178.0
178.0
178.0
178.0
13.5
13.5
13.5
13.5
2.1
2.1
2.1
2.1
2.9
2.9
2.9
2.9
0.75
0.75
0.75
0.75
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS3202IRSVR
HD3SS3202IRSVT
HD3SS3202RSVR
HD3SS3202RSVT
UQFN
UQFN
UQFN
UQFN
RSV
RSV
RSV
RSV
16
16
16
16
3000
250
189.0
189.0
189.0
189.0
185.0
185.0
185.0
185.0
36.0
36.0
36.0
36.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明