HD3SS3212-Q1 [TI]
汽车类双通道差动 2:1 和 1:2 USB3.2 多路复用器和多路信号分离器;
| 型号： | HD3SS3212-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双通道差动 2:1 和 1:2 USB3.2 多路复用器和多路信号分离器 复用器 |
| 文件： | 总29页 (文件大小：2021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
HD3SS3212-Q1 双通道差分 2:1/1:2 USB3.2 多路复用器/多路信号分离器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100 标准
温度等级 2：–40°C 至 +105°C，TA
HD3SS3212-Q1 是一款采用多路复用器或多路信号分
离器配置的高速双向无源开关。它适用于支持 USB
3.2 第 1 代和第 2 代数据速率的 USB Type-C™ 应
用。SEL 控制引脚可在两个差动通道（端口 B 到端口
A 或端口 C 到端口 A）之间切换。
–
•
提供面向支持第 1 代和第 2 代 USB 3.2 数据速率
的 USB Type-C™ 生态系统的多路复用器/多路信
号分离器解决方案
•
与 MIPI DSI/CSI、FPD-Link III、LVDS 以及 PCIe
第 II 代、第 III 代兼容
HD3SS3212-Q1 是一款通用的模拟差动无源开关。该
器件适用于任何要求 0V 至 2V 共模电压范围和差动振
幅高达 1800mVpp 的差动信号的高速接口应用。自适
应跟踪功能可确保通道在整个共模电压范围内保持不
变。
•
•
•
运行速率高达 10Gbps
-3dB 差动带宽宽达 8GHz 以上
出色的动态特性（5GHz 时）
–
–
–
–
串扰 = –28dB
关断隔离 = –19dB
插入损耗 = –2dB
回损 = –8dB
该器件的出色动态特性允许进行高速开关，使信号眼图
具有最小的衰减，并且不会明显增加抖动。它在运行时
消耗的功率低于 1.65mW。OEn 引脚具有关断模式，
从而可实现低于 0.02µW 的功耗。
•
•
•
•
双向“多路复用器/多路信号分离器”差分开关
支持 0V 至 2V 的共模电压
器件信息(1)
3.3V 的单电源电压 VCC
器件型号
封装
封装尺寸（标称值）
采用汽车友好型 QFN 封装
（2.5mm x 4.5mm，间距为 0.5mm）
2.50mm × 4.50mm ×
0.5mm 间距
HD3SS3212-Q1
VQFN (20)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
•
•
USB Type-C™ 生态系统
汽车媒体接口
音响主机
后座娱乐系统
FPD-Link II 和 FPD-Link III 开关
MIPI DSI/CSI-2 开关
空格
简化原理图
HD3SS3212-Q1
USB3.1 Host
SSTXp
B0p
TXp1
TXn1
B0n
A0p
A0n
SSTXn
C0p
C0n
TXp2
TXn2
RXp1
RXn1
RXp2
RXn2
SEL
B1p
SSRXp
SSRXn
A1p
A1n
B1n
C1p
C1n
OEn
CC1
CC2
TP
GND
3.3V
CC
Controller
Copyright © 2018, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEQ6
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 14
9.3 Systems Examples.................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 High-Speed Performance Parameters...................... 5
6.7 Switching Characteristics.......................................... 6
Parameter Measurement Information .................. 6
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 接收文档更新通知 ................................................. 19
12.2 社区资源................................................................ 19
12.3 商标....................................................................... 19
12.4 静电放电警告......................................................... 19
12.5 术语表 ................................................................... 19
13 机械、封装和可订购信息....................................... 20
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2018) to Revision A
Page
•
将文档从预告信息 更改为生产 数据........................................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
5 Pin Configuration and Functions
RKS Package
20-Pin VQFN
Top View
OEn
A0p
A0n
GND
VCC
A1p
A1n
SEL
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
B0p
B0n
B1p
B1n
C0p
C0n
C1p
C1n
Thermal
Pad
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
VCC
6
P
I
3.3-V power
Active-low chip enable
L: Normal operation
H: Shutdown
OEn
2
A0p
A0n
3
I/O
I/O
G
Port A, channel 0, high-speed positive signal
Port A, channel 0, high-speed negative signal
Ground
4
GND
A1p
A1n
5, 11, 20
7
8
I/O
I/O
Port A, channel 1, high-speed positive signal
Port A, channel 1, high-speed negative signal
Port select pin.
SEL
9
I
L: Port A to Port B
H: Port A to Port C
C1n
C1p
C0n
C0p
B1n
B1p
B0n
B0p
NC1
NC2
12
13
14
15
16
17
18
19
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NA
NA
Port C, channel 1, high-speed negative signal (connector side)
Port C, channel 1, high-speed positive signal (connector side)
Port C, channel 0, high-speed negative signal (connector side)
Port C, channel 0, high-speed positive signal (connector side)
Port B, channel 1, high-speed negative signal (connector side)
Port B, channel 1, high-speed positive signal (connector side)
Port B, channel 0, high-speed negative signal (connector side)
Port B, channel 0, high-speed positive signal (connector side)
Can be left not connected or can be fed to VCC or tied to GND.
10
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when
the port is selected.
Copyright © 2018–2019, Texas Instruments Incorporated
3
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–65
MAX
UNIT
VCC
Supply voltage
Voltage
4
2.5
V
Differential I/O
Control pins
V
VCC+ 0.5
150
Tstg
Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100- 011
CDM ESD Classification Level C6
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
1.7
–0.1
0
MAX
UNIT
V
VCC
Vih
Supply voltage
3.6
VCC
0.8
1.8
2
Input high voltage (SEL, OEn pins)
Input low voltage (SEL, OEn pins)
High-speed signal pins differential voltage
High speed signal pins common mode voltage
Operating free-air/ambient temperature
V
Vil
V
Vdiff
Vcm
TA
Vpp
V
0
HD3SS3212-Q1
-40
105
°C
6.4 Thermal Information
HD3SS3212-Q1
THERMAL METRIC(1)
RKS (VQFN)
20 PINS
58.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
59.9
Junction-to-board thermal resistance
32.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.9
ψJB
32
RθJC(bot)
16.7
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
4
Copyright © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
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ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
MAX
0.8
1
UNIT
mA
µA
ICC
Device active current
VCC = 3.3 V, OEn = 0
ISTDN
CON
COFF
Device shutdown current
VCC = 3.3 V, OEn = VCC
0.005
0.6
Output ON capacitance to GND
Output OFF capacitance to GND
pF
0.8
pF
VCC = 3.3 V; VCM = 0 to 2 V;
IO = –8 mA
RON
Output ON resistance
5
8
Ω
Ω
On-resistance match between pairs of the same
channel
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V; IO =
–8 mA
ΔRON
0.7
RFLAT_ON
IIH,CTRL
IIL,CTRL
On-resistance flatness RON(MAX) – RON(MIN)
Input high current, control pins (SEL, OEn)
Input low current, control pins (SEL, OEn)
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
1
1
1
Ω
µA
µA
VIN = 2 V for selected port, A and B with
SEL = 0, and A and C with
IIH,HS
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
1
µA
SEL = VCC
VIN = 2 V for non-selected port, C with
SEL = 0, and B with
SEL = VCC
IIH,HS
IIL,HS
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
Input low current, high-speed pins [Ax/Bx/Cx][p/n]
100
140
1
µA
µA
(1)
(1) There is a 20-kΩ pull-down in non-selected port.
6.6 High-Speed Performance Parameters
PARAMETER
TEST CONDITION
MIN
TYP
-0.4
-0.4
-1
MAX
UNIT
ƒ = 0.3 MHz
ƒ = 0.625 MHz
IL
Differential insertion loss
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
dB
-1.8
-2.0
9
BW
RL
–3-dB bandwidth
GHz
dB
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 0.3 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
-25
-11
-9
Differential return loss
-8
-75
-23
-21
-19
-70
-35
-30
-28
OIRR
Differential OFF isolation
Differential crosstalk
dB
dB
XTALK
Copyright © 2018–2019, Texas Instruments Incorporated
5
HD3SS3212-Q1
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6.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ps
tPD
Switch propagation delay (see 图 3)
Switching time SEL-to-Switch ON (see 图 2)
Switching time SEL-to-Switch OFF (see 图 2)
Switching time OEn-to-Switch ON
ƒ > 1 GHz
80
0.5
0.5
2
tSW_ON
µs
tSW_OFF
tSW_OEn_ON
tSW_OEn_OFF
µs
µs
Switching time OEn-to-Switch OFF
0.1
µs
Intra-pair Skew = P -
N
tSK_INTRA_A0B0
tSK_INTRA_A0C0
tSK_INTRA_A1B1
Intra-pair output skew for path A0 to B0. (see 图 3)
Intra-pair output skew for path A0 to C0. (see 图 3)
Intra-pair output skew for path A1 to B1. (see 图 3)
4.5
1.25
-0.75
-4
ps
ps
ps
Intra-pair Skew = P -
N
Intra-pair Skew = P -
N
Intra-pair Skew = P -
N
tSK_INTRA_A1C1
tSK_INTER
Intra-pair output skew for path A1 to C1. (see 图 3)
Inter-pair output skew (see 图 3)
ps
ps
20
7 Parameter Measurement Information
VCC
RSC = 50 Ω
Bxp/Cxp
Bxn/Cxn
Axp
RL = 50 Ω
RSC = 50 Ω
Axn
RL = 50 Ω
图 1. Test Setup
6
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
Parameter Measurement Information (接下页)
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
图 2. Switch On and Off Timing Diagram
版权 © 2018–2019, Texas Instruments Incorporated
7
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
Parameter Measurement Information (接下页)
2.6-V Max
50%
50%
VIN
0 V
2.6-V Max
50%
50%
VOUT
0 V
tPD
VOUTp
50%
TSK_INTRA
VOUTn
B0/C0
VOUT
50%
50%
50%
50%
B1/C1
VOUT
tSK_INTER
图 3. Timing Diagrams and Test Setup
8
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
8 Detailed Description
8.1 Overview
The HD3SS3212-Q1 is a generic analog differential passive switch that can work for any high-speed interface
applications requiring a common mode voltage range of 0 V to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It consumes less than 1.65 mW of power when operational and
has a shutdown mode exercisable by OEn pin resulting less than 0.02 µW.
8.2 Functional Block Diagram
B0+
B0œ
A0+
A0œ
C0+
C0œ
SEL
B1+
B1œ
A1+
A1œ
C1+
C1œ
8.3 Feature Description
8.3.1 Output Enable and Power Savings
The HD3SS3212-Q1 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the
OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn
control pin should be pulled low to GND or dynamically controlled to switch between H or L.
HD3SS3212-Q1 consumes < 1.65 mW of power when operational and has a shutdown mode exercisable by the
EN pin resulting < 0.02 µW.
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HD3SS3212-Q1
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www.ti.com.cn
8.4 Device Functional Modes
表 1. Port Select Control Logic(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
SEL = L
B0p
SEL = H
C0p
A0p
A0n
A1p
A1n
B0n
C0n
B1p
C1p
B1n
C1n
(1) The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
10
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HD3SS3212-Q1
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ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The HD3SS3212-Q1 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing
high-speed signals between two different locations on a circuit board. The HD3SS3212-Q1 supports several
high-speed data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V,
as with USB 3.2 and DisplayPort 1.4. The device’s one select input (SEL) pin can easily be controlled by an
available GPIO pin within a system or from a microcontroller.
The HD3SS3212-Q1 with its adaptive common mode tracking technology can support applications where the
common mode is different between the RX and TX pair. The two USB 3.2 Type C connector applications show
both a host and device side. The cable between the two connectors swivels the pairs to properly route the
signals to the correct pin. The other applications are more generic because different connectors can be used.
Many interfaces require AC coupling between the transmitter and receiver. The 0201 capacitors are the preferred
option to provide AC coupling; 0402 size capacitors also work. Avoid the 0603 or larger size capacitors and C-
packs. When placing AC coupling capacitors, symmetric placement is best. The designer should place them
along the TX pairs on the system board, which are usually routed on the top layer of the board.
The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the
designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. 图 4 shows a few placement options. The coupling capacitors are placed
between the switch and endpoint. In this situation, the switch is biased by the system/host controller.
0.1 µF
RX
Port B
Device/
Endpoint
TX
Port C
System/Host
controller
TX
0.1 µF
Port B
RX
RX
Device/
Endpoint
0.1 µF
Port C
TX
0.1 µF
图 4. AC Coupling Capacitors between Switch TX and Endpoint TX
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Application Information (接下页)
In 图 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation,
the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
RX
0.1 µF
Port B
Device/
Endpoint
TX
Port C
System/Host
controller
TX
0.1 µF
Port B
RX
RX
Device/
Port C
Endpoint
TX
0.1 µF
图 5. AC Coupling Capacitors on Host TX and Endpoint TX
If the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of
the switch (shown in 图 6). A biasing voltage of <2 V is required.
VBIAS
RX
Port B
Device/
Endpoint
TX
VBIAS
Port C
System/Host
controller
TX
Port B
RX
RX
Device/
Endpoint
Port C
TX
VBIAS can be GND
Capacitor and resistor values depend upon application
图 6. AC Coupling Capacitors on Both Sides of Switch
12
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ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
Application Information (接下页)
The HD3SS3212-Q1 can be used with the USB Type C connector to support the connector’s flip ability. 图 7
provides the generic location for the AC coupling capacitors for this application.
Down Facing Port
Up Facing Port
TX1+
RX1+
TX1œ
RX1œ
RX+
TX+
RX1+ 0.1 µF
TX1+
RXœ
TX
RX
TXœ
RX1œ
TX1œ
System/Host
Controller
Hub
0.1 µF
TX2+
RX2+
TX+
RX+
TX2œ
RX2œ
TX
TXœ
RX
RXœ
0.1 µF
RX2+
TX2+
RX2œ
TX2œ
0.1 µF
图 7. AC Coupling Capacitors for USB Type C
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9.2 Typical Applications
9.2.1 Down Facing Port for USB3.1 Type C
HD3SS3212-Q1
B0+
A2
A3
SSTXp1
SSTXn1
A1
GND
GND
GND
GND
B0t
B12
A0+
C0+
A0t
C0t
A1+
SSTXp
B2
SSTXp2
SSTXn2
SSRXp1
SSRXn1
SSRXp2
SSRXn2
A12
B1
SSTXn
SSRXp
B3
B11
B10
A11
A10
A5
B1+
A1t
SSRXn
USB Host
B1t
OEn
C1+
SEL
Optional
Controller
10 lQ
C1t
3.3V
CC1
CC2
B5
GND
USB-C
0.1 µF
3.3V
CC
Controller
Copyright © 2018, Texas Instruments Incorporated
图 8. Down Facing Port for USB3.1 Type C Connector
9.2.1.1 Design Requirements
The HD3SS3212-Q1 can be designed into many different applications. All the applications have certain
requirements for the system to work properly. The HD3SS3212-Q1 requires 3.3-V ±10% VCC rail. The OEn pin
must be low for device to work otherwise it disables the outputs. This pin can be driven by a processor. The
expectation is that one side of the device has AC coupling capacitors. 表 2 provides information on expected
values to perform properly.
表 2. Design Parameters
DESIGN PARAMETER
VALUE
3.3 V
VCC
AXp/n, BXp/n, CXp/n CM input voltage
Control/OEn pin max voltage for low
Control/OEn pin min voltage for high
AC coupling capacitor
0 V to 2 V
0.8 V
2.0 V
75 to 265 nF
100 kΩ
RBIAS (图 8) when needed
9.2.1.2 Detailed Design Procedure
The HD3SS3212-Q1 is a high-speed passive switch device that can behave as a mux or demux. Because this is
a passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 2 to 3 inches of board trace and a connector on either end.
To design in the HD3SS3212-Q1, the designer needs to understand the following.
•
•
•
•
•
•
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Depending upon the application, determine the best place to put the AC coupling capacitor.
Provide a control signal for the SEL and OEn pins.
The thermal pad must be connected to ground.
See the application schematics on recommended decouple capacitors from VCC pins to ground
14
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
9.2.1.3 Application Curves
图 9 and 图 11 shows the eye at the input of the HD3SS3212-Q1. 图 10 and 图 12 shows the eye at the output of
the HD3SS3212-Q1.
图 9. 5 Gbps Source Eye Diagram
图 10. 5 Gbps Output Eye Diagram
图 12. 10 Gbps Output Eye Diagram
图 11. 10 Gbps Source Eye Diagram
版权 © 2018–2019, Texas Instruments Incorporated
15
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
9.3 Systems Examples
9.3.1 Up Facing Port for USB 3.2 Type C
HD3SS3212-Q1
A2
B0+
SSTXp1
A1
GND
A3
SSTXn1
B0-
B12
A0+
A0-
GND
B2
SSTXp2
SSTXp
SSTXn
C0+
C0-
A12
GND
GND
B3
SSTXn2
SSRXP1
SSRXn1
SSRXp2
SSRXn2
B1
SSRXp
SRTXn
A1+
A1-
B11
B10
B1+
B1-
USB Device
OEn
SEL
A11
A10
C1+
C1-
Optional
Controller
10 kW
3.3V
A5
B5
CC1
CC2
GND
USB-C
0.1 µF
3.3V
CC
Controller
Copyright © 2018, Texas Instruments Incorporated
图 13. Up Facing Port for USB 3.2 USB Type-C Connector
9.3.2 PCIe/SATA/USB
HD3SS3212-Q1
TXp1
TXn1
RXp1
RXn1
B0+
B0t
B1+
B1t
TXp
A0+
TXn
RXp
A0t
PCIe Connector
A1+
C0+
TXp2
TXn2
RXp2
RXn2
RXn
A1t
OEn
SEL
C0t
C1+
C1t
PCIE/USB
Optional
Controller
USB Connector
10 lQ
3.3V
GND
3.3V
0.1 µF
Copyright © 2018, Texas Instruments Incorporated
图 14. PCIE Motherboard
16
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
Systems Examples (接下页)
9.3.3 PCIE/eSATA
HD3SS3212-Q1
B0+
PCIE Controller
RXp1
B0t
RXn1
TXp1
TXn1
A0+
B1+
A0t
B1t
A1+
TXp
TXn
RXp
C0+
RXp2
RXn2
TXp2
RXn
MINI CARD
mSATA Connector
A1t
C0t
OEn
C1+
SEL
Optional
C1t
TXn2
Controller
eSATA Controller
10 lQ
3.3V
GND
3.3V
0.1 µF
Copyright © 2018, Texas Instruments Incorporated
图 15. PCIe and eSATA Combo
9.3.4 USB/eSATA
HD3SS3212-Q1
B0+
USB Controller
RXp1
B0t
RXn1
TXp1
TXn1
TXp
A0+
B1+
A0t
B1t
A1+
TXn
RXp
C0+
RXp2
RXn2
TXp2
RXn
A1t
C0t
OEn
USB/eSATA Connector
Optional
C1+
SEL
C1t
TXn2
Controller
eSATA Controller
10 lQ
3.3V
GND
0.1 µF
3.3V
Copyright © 2018, Texas Instruments Incorporated
图 16. eSATA and USB 3.2 Combo Connector
版权 © 2018–2019, Texas Instruments Incorporated
17
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
10 Power Supply Recommendations
The HD3SS3212-Q1 does not require a power supply sequence. TI also recommends to place ample decoupling
capacitors at the device VCC near the pin.
11 Layout
11.1 Layout Guidelines
On a high-K board, TI always recommends to solder the PowerPAD™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the HD3SS3212-Q1
can operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board, for the device to operate across the temperature range, the designer must use a 1-oz Cu
trace connecting the GND pins to the thermal land. A general PCB design guide for PowerPAD packages is
provided in PowerPAD Thermally-Enhanced Package, SLMA002.
11.2 Layout Example
图 17. HD3SS3212-Q1 Basic Layout Example for Application Shown
in Down Facing Port for USB3.1 Type C
18
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请转至 TI.com.cn 上您的器件的产品文件夹。请在右上角单击通知我 按钮进行注册，即可收
到产品信息更改每周摘要（如有）。有关更改的详细信息，请查看任意已修订文档的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2018–2019, Texas Instruments Incorporated
19
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
PACKAGE OUTLINE
RKS0020A
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1 0.1
2X 0.5
(0.2) TYP
11
10
14X 0.5
EXPOSED
THERMAL PAD
9
12
2X
3.5
3 0.1
2
19
0.3
20X
1
20
0.2
0.1
0.05
PIN 1 ID
(OPTIONAL)
C A
B
0.5
0.3
20X
4222490/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
版权 © 2018–2019, Texas Instruments Incorporated
21
HD3SS3212-Q1
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
1
20
20X (0.6)
2
19
20X (0.25)
(1.25)
SYMM
(3)
(4.3)
16X (0.5)
(R0.05) TYP
12
9
(
0.2) VIA
TYP
10
11
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222490/A 10/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
22
版权 © 2018–2019, Texas Instruments Incorporated
HD3SS3212-Q1
www.ti.com.cn
ZHCSIR3A –SEPTMEBER 2018–REVISED JUNE 2019
EXAMPLE STENCIL DESIGN
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
20
1
20X (0.6)
2
19
20X (0.25)
2X (1.31)
16X (0.5)
SYMM
(4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
11
10
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222490/A 10/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
版权 © 2018–2019, Texas Instruments Incorporated
23
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3212RKSRQ1
HD3SS3212RKSTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RKS
RKS
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
HD3212Q
HD3212Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS3212RKSRQ1
HD3SS3212RKSTQ1
VQFN
VQFN
RKS
RKS
20
20
3000
250
180.0
180.0
12.4
12.4
2.8
2.8
4.8
4.8
1.2
1.2
4.0
4.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS3212RKSRQ1
HD3SS3212RKSTQ1
VQFN
VQFN
RKS
RKS
20
20
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
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