HD3SS3411IRWAR [TI]
3.3V PCI Express 3.0 单通道模拟差动开关 | RWA | 14 | -40 to 105;
| 型号： | HD3SS3411IRWAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V PCI Express 3.0 单通道模拟差动开关 | RWA | 14 | -40 to 105 开关 PC 输出元件 |
| 文件： | 总22页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
HD3SS3411 单通道差分 2:1 复用器/解复用器
1 特性
3 说明
1
•
兼容多种接口标准，包括 FPD-Link、LVDS、PCIE
第 II 代和第 III 代、XAUI 以及 USB3.1
HD3SS3411 是一款高速双向无源开关，可采用复用器
或解复用器两种配置。该器件可通过控制引脚 SEL 在
两条差分通道（端口 B 至端口 A 或端口 C 至端口 A）
之间进行切换。
•
•
•
运行速率高达 10Gbps
-3dB 差分带宽宽达 7.5GHz 左右
出色动态特性（4GHz 时）
HD3SS3411 是一款通用模拟差分无源开关，适用于所
有高速接口应用，前提条件是该应用在 0V 至 2V 共模
电压范围内发生偏置并且具有幅值高达 1800 mVpp 的
差分信令。该器件采用自适应跟踪，可确保信道在整个
共模电压范围内保持不变。
–
–
–
插入损耗 = -1.1dB
回波损耗 = -11.3dB
断开隔离 = –19dB
•
•
•
•
双向“复用/解复用”差分开关
支持 0V 到 2V 共模电压
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。该器件在工
作模式下的功耗 < 2mW；在关断模式下的功耗
< 2µW（可通过 OEn 引脚切换模式）。
单电源电压 VCC：3.3V±10%
-40°C 至 105°C 的工业温度范围
2 应用
•
•
•
•
•
工业数据交换
器件信息(1)
台式机和笔记本个人电脑 (PC)
服务器/储存区网络
PCI EXPress 背板
共享 I/O 端口
器件型号
HD3SS3411
HD3SS3411I
封装
封装尺寸（标称值）
WQFN (14)
3.50mm x 3.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
VCC
Bp
Bn
Ap
An
Cp
Cn
SEL
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASEB6
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application Information and Implementation ..... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................... 9
8.3 Design Requirements.............................................. 10
8.4 Detailed Design Procedure ..................................... 10
8.5 Application Curves .................................................. 12
Power Supply Recommendations...................... 12
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 14
11 器件和文档支持 ..................................................... 15
11.1 文档支持 ............................................................... 15
11.2 社区资源................................................................ 15
11.3 商标....................................................................... 15
11.4 静电放电警告......................................................... 15
11.5 Glossary................................................................ 15
12 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
日期
修订版本
注释
2015 年 11 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
5 Pin Configuration and Functions
RWA Package
14 Pin (WQFN)
Top View
OEn
GND
14
1
2
3
4
5
6
Ap
An
13 Bp
12 Bn
11 GND
VCC
GND
RSVD
10 Cp
Cn
9
7
8
SEL
GND
Pin Functions
NAME
Ap
NO
2
TYPE
I/O
DESCRIPTION
Port A, High Speed Positive Signal
Port A, High Speed Negative Signal
Port B, High Speed Positive Signal
Port B, High Speed Negative Signal
Port C, High Speed Positive Signal
Port C, High Speed Negative Signal
An
3
I/O
Bp
13
12
10
9
I/O
Bn
I/O
Cp
I/O
Cn
I/O
5,8,11,14,
Pad
GND
G
Ground
Active Low Chip Enable
L: Normal operation
H: Shutdown
OEn
RSVD
SEL
1
6
7
4
I
I/O
I
Reserved Pin – connect or pull-down to GND
Port select pin
L: Port A to Port B
H: Port A to Port C
VCC
P
3.3 V power
Copyright © 2015, Texas Instruments Incorporated
3
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
Supply voltage range (VCC
)
Absolute minimum/maximum supply voltage range
4
V
Differential I/O
Control pin
2.5
Voltage range
V
VDD + 0.5
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
VCC
0.8
1.8
2
UNIT
V
VCC
VIH
VIL
Supply voltage
Input high voltage (SEL, OEn Pin)
Input low voltage (SEL OEn Pin)
High speed signal pins differential voltage
Common mode voltage (differential pins)
Operating free-air temperature
2
V
–0.1
0
V
VDiff
VCM
TA
VPP
V
0
–40
105
°C
6.4 Thermal Information
HD3SS3411
RWA (WQFN)
14 PINS
50.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
63.1
26.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
ψJB
26.5
RθJC(bot)
7.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.6
0.3
0.6
MAX
0.8
UNITS
mA
ICC
Device active Current
Device shutdown Current
Outputs ON Capacitance
VCC = 3.3 V, OEn = 0
VCC = 3.3 V, OEn = 0
ISTDN
CON
0.6
µA
pF
VCC = 3.3 V; VCM = 0 V to 2 V ;
IO = –8 mA
RON
Output ON resistance
5
8
0.5
1
Ω
Ω
On resistance match between pairs of
the same channel
VCC = 3.3 V ; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
ΔRON
On resistance flatness
(RON(MAX) – RON(MAIN)
R(FLAT_ON)
IIH(CTRL)
IIL(CTRL)
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
Ω
Input high current, control pins
(SEL, OEn)
1
µA
µA
Input low current, control pins
(SEL, OEn)
1
[A/B/C][p/n] VIN = 2 V for selected port,
A and B with SEL= 0, and A and C with
SEL = VCC
1
µA
[A/B/C][p/n] VIN = 2 V for non-selected
port, C with SEL= 0, and B with
SEL = VCC
(Note there is a 20 KΩ pull-down in non-
selected port)
IIH(HS)
Input high current, high speed pins
Input low current, high speed pins
100
140
1
µA
µA
IIL(HS)
[A/B/C][p/n]
High Speed Performance
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
–0.5
–0.7
–1.1
7.5
IL
Differential Insertion Loss
dB
GHz
dB
BW
RL
-3 dB Bandwidth
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
–26.4
–16.6
–11.3
–75
Differential return loss
f = 0.3 MHz
f = 2.5 GHz
f = 4 GHz
OI
Differential OFF isolation
Differential Crosstalk
–22
dB
dB
–19
Xtalk
f = 4 GHz
–35
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ps
tPD
Switch propagation delay
Switching time
80
0.5
5
tSW
ns
tSK_INTRA
Intra-pair output skew
ps
Copyright © 2015, Texas Instruments Incorporated
5
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
6.7 Typical Characteristics
0
-5
2
0
-2
-10
-15
-20
-25
-30
-4
-6
-8
-10
-12
0
2
4
6
8
10
0
2
4
6
8
10
Frequency (GHz)
Frequency (GHz)
D001
D002
Figure 1. Return Loss vs Frequency
Figure 2. Insertion Loss vs Frequency
6
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
7 Detailed Description
7.1 Overview
The HD3SS3411 is a high-speed bi-directional passive switch in mux or demux configurations. Based on control
pin SEL, the device switches one differential channels between Port B or Port C to Port A.
The HD3SS3411 is a generic analog differential passive switch that can work for any high speed interface
applications as long as it is biased at a common mode voltage range of 0 V to 2 V and has differential signaling
with differential amplitude up to 1800 mVpp. The device employs an adaptive tracking that ensures the channel
remains unchanged for entire common mode voltage range.
Table 1. MUX Pin Connections(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A
CHANNEL
PORT A CHANNEL
SEL = L
Bp
SEL = H
Cp
Ap
An
Bn
Cn
(1) The HD3SS3411 can tolerate polarity inversions for all differential signals on Ports A, B and C. Care
should be taken to ensure the same polarity is maintained on Port A vs. Port B/C.
7.2 Functional Block Diagram
VCC
Bp
Bn
Ap
An
Cp
Cn
SEL
GND
7.3 Feature Description
7.3.1 Output Enable and Power Savings
The HD3SS3411 has two power modes, normal operating mode and shutdown mode. During shutdown mode,
the device consumes very-little current to save the maximum power. The OEn control pin is used to toggle
between the two modes.
HD3SS3411 consumes < 2 mW of power when operational and has a shutdown mode exercisable by the OEn
pin resulting < 20 µW.
Copyright © 2015, Texas Instruments Incorporated
7
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
7.4 Device Functional Modes
The OEn control pin selects the functional mode of HD3SS3411. To enter standby/shutdown mode, the OEn
control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control
pin should be pulled low to GND or dynamically controlled to switch between H or L.
Table 2. Device Power Modes
OEn
L
Device State
Normal
Signal Pins
Normal
H
Shutdown
Tri-stated
8
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
8 Application Information and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
HD3SS3411 mux channels have independent adaptive common mode tracking allowing RX and TX paths to
have different common mode voltage simplifying system implementation and avoiding inter-operational issues.
HD3SS3411 mux does not provide common mode biasing for the channel. Therefore, it is required that the
device is biased from either side for all active channels.
The HD3SS3411 supports several high-speed data protocols with a differential amplitude of < 1800 mVpp and a
common mode voltage of < 2 V, as with USB 3.1 and DisplayPort 1.3. The one select input (SEL) pin can be
controlled by an available GPIO pin within a system or from a microcontroller.
8.2 Typical Application
{erializer !
/amera !
ë5533
(3ꢄ3ë) (1ꢄ8ë or 3ꢄ3ë)
ë55Lꢃ
5!Ç!
t/[Y
Lmage
{ensor
w(7;0)
D(7;0)
.(7;0)
I{
ë{
59
wD. 5isplay
720p
24-biꢁ color
depꢁh
C{òꢂ/
wLꢂ+
wLꢂ-
L2/
100 ohm {Çt /able
t/[Y
t5.
ꢃ{{_{9[
ꢃ9ꢂ
[ꢃ/Y
t!{{
L2{ !Ü5Lꢃ
({Ç9w9ꢃ)
ꢀ/[Y
5eserializer
5!Ç!
t/[Y
ꢀꢃ59_{9[
LꢂÇ._Lꢂ
ëideo
{ource
{/[
{5!
L5ó
5!t
L2/
{erializer .
Figure 3. FPD Link III Application
Copyright © 2015, Texas Instruments Incorporated
9
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
8.3 Design Requirements
For this design example, use the values shown in Table 3.
Table 3. Design Paramerters
PARAMETER
VALUE
3.3 V
VCC voltage
Ap/n, Bp/n, Cp/n CM input voltage
SEL/OEn pin max voltage for low
SEL/OEn pin min voltage for high
0 V to 2 V
0 V
3.3 V
8.4 Detailed Design Procedure
8.4.1 AC Coupling Capacitors
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling, and the 0603 size capacitors will also work. The 0805 size capacitors and C-
packs should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value
of 0.1 µF is best and the value should be match for the ± signal pair. The placement should be along the TX
pairs on the system board, which are usually routed on the top layer of the board.
There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage,
the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. A few placement options are shown below. In Figure 4, the coupling
capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host
controller.
Figure 4. AC Coupling Capacitors Between Switch TX and Endpoint TX
10
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
Detailed Design Procedure (continued)
In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX
If the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of
the switch (shown in Figure 6). A biasing voltage of less than 2 V is required in this case.
Figure 6. AC Coupling Capacitors on Both Sides of Switch
Copyright © 2015, Texas Instruments Incorporated
11
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
8.5 Application Curves
Figure 7. 6 Gbps Source Eye Diagram
Figure 8. 6 Gbps Output Eye Diagram
9 Power Supply Recommendations
There is no power supply sequence required for HD3SS3411. However, it is recommended that OEn is asserted
low after device supply VCC is stable and in specifications. It is also recommended that ample decoupling
capacitors are placed at the device VCC near the pin.
12
Copyright © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
10 Layout
10.1 Layout Guidelines
10.1.1 Critical Routes
•
The high speed differential signals must be routed with great care to minimize signal quality degradation
between the connector and the source or sink of the high speed signals by following the guidelines provided
in this document. Depending on the configuration schemes, the speed of each differential pair can reach a
maximum speed of 10 Gbps. These signals are to be routed first before other signals with highest priority.
•
Each differential pair should be routed together with controlled differential impedance of 85-Ω to 90-Ω and 50-
Ω common mode impedance. Keep away from other high speed signals. The number of vias should be kept
to minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width.
Route all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer.
No 90 degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the
angle of the bend should be greater than 135 degrees.
•
Length matching:
–
Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
The inter-pair matching of the differential pairs is not as critical as intra-pair matching.
•
•
•
Keep high speed differential pair traces adjacent to ground plane.
Do not route differential pairs over any plane split.
ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path.
•
For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS3411 pins can be
swapped.
10.1.2 General Routing/Placement Rules
•
Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the
plane.
•
•
Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines.
All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
•
•
All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high
frequency return current path.
•
•
Route differential traces over a continuous plane with no interruptions.
Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
•
•
Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep
out distance where possible.
Decoupling caps should be placed next to each power terminal on the HD3SS3411. Care should be taken to
minimize the stub length of the trace connecting the capacitor to the power pin.
•
•
•
Avoid sharing vias between multiple decoupling caps.
Place vias as close as possible to the decoupling cap solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
Copyright © 2015, Texas Instruments Incorporated
13
HD3SS3411
ZHCSEC8 –NOVEMBER 2015
www.ti.com.cn
10.2 Layout Example
ꢂ9n and {9[ can be conꢀrolled
by µ/. ꢂ9n can also be ꢀied
ꢀo ëcc wiꢀh resisꢀor
ꢁaꢀch Iigh {peed ꢀraces
lengꢀh as close as possible ꢀo
minimize {kew
ꢁaꢀch Iigh {peed ꢀraces
lengꢀh as close as possible ꢀo
minimize {kew
OEn
100nF
100nF
Ap
An
Bp
Bn
VCC
GND
tlace ë// decoupling caps as
close ꢀo ë// pins as possible
Cp
Cn
GND
RSVD
GND
Figure 9. Layout
14
版权 © 2015, Texas Instruments Incorporated
HD3SS3411
www.ti.com.cn
ZHCSEC8 –NOVEMBER 2015
11 器件和文档支持
11.1 文档支持
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
15
重要声明
德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的 JESD48 提
供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。
TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其
他条款可能适用于其他类型 TI 产品及服务的使用或销售。
复制 TI 数据表上 TI 信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。TI 对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去
相关 TI 产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。
买方和在系统中整合 TI 产品的其他开发人员（总称“设计人员”）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且
应全权 负责并确保 应用的安全性， 及设计人员的 应用 （包括应用中使用的所有 TI 产品）应符合所有适用的法律法规及其他相关要求。设计
人员就自己设计的 应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够 (1) 预见故障的危险后果，(2) 监视故障及其后
果，以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含 TI 产品的任何 应用前， 将彻底测试该等 应用
和 该等应用中所用 TI 产品的 功能。
TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称“TI 资
源”），旨在帮助设计人员开发整合了 TI 产品的 应用， 如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、
访问或使用任何特定的 TI 资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定 TI 资源。
TI 所提供的 TI 资源，并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明；也未导致 TI 承担任何额外的义务或责任。
TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外，TI 未进行任何其他测试。
设计人员只有在开发包含该等 TI 资源所列 TI 产品的 应用时， 才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或
其他法理授予您任何TI知识产权的任何其他明示或默示的许可，也未授予您 TI 或第三方的任何技术或知识产权的许可，该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡
发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索，包括但不限于因组合产品所致或
与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管 TI 是否获悉可能会产生上述损害赔
偿，TI 概不负责。
除 TI 已明确指出特定产品已达到特定行业标准（例如 ISO/TS 16949 和 ISO 26262）的要求外，TI 不对未达到任何该等行业标准要求而承担
任何责任。
如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何 TI 产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备）。此类设备包括但不限于，美国食品药品监督管理局认定为 III 类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI 可能明确指定某些产品具备某些特定资格（例如 Q100、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的
应用选择适合的 产品， 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2017 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS3411IRWAR
HD3SS3411IRWAT
ACTIVE
ACTIVE
WQFN
WQFN
RWA
RWA
14
14
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
3411I
3411I
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
RWA0014A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
B
A
PIN 1 INDEX AREA
3.65
3.35
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2.05 0.1
2X 1.5
(0.2) TYP
7
8
6
9
2X
2
8X 0.5
2
13
0.30
0.18
14X
1
14
0.1
C A
B
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
14X
4221612/B 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWA0014A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.05)
2X (1.5)
SYMM
1
14
14X (0.6)
2
13
14X (0.24)
SYMM
(3.3)
(0.775)
8X (0.5)
9
6
(
0.2) VIA
TYP
7
8
(0.775)
(R0.05) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221612/B 02/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWA0014A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
4X ( 0.92)
1
14
14X (0.6)
2
13
14X (0.24)
(3.3)
SYMM
(0.56)
8X (0.5)
9
6
METAL
TYP
7
SYMM
(3.3)
8
(R0.05) TYP
(0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4221612/B 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明