HPA01054DAPR [TI]
24-Channel, 12-Bit PWM LED Driver with Internal Oscillator; 24通道,12位PWM LED驱动器,内部振荡器型号: | HPA01054DAPR |
厂家: | TEXAS INSTRUMENTS |
描述: | 24-Channel, 12-Bit PWM LED Driver with Internal Oscillator |
文件: | 总29页 (文件大小:1308K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC5947
www.ti.com ................................................................................................................................................. SBVS114A–JULY 2008–REVISED SEPTEMBER 2008
24-Channel, 12-Bit PWM LED Driver with
Internal Oscillator
1
FEATURES
•
Noise Reduction:
23
•
24 Channels, Constant Current Sink Output
30-mA Capability (Constant Current Sink)
12-Bit (4096 Steps) PWM Grayscale Control
LED Power-Supply Voltage up to 30 V
VCC = 3.0 V to 5.5 V
–
4-channel grouped delay to prevent inrush
current
•
•
•
•
•
•
Operating Temperature: –40°C to +85°C
APPLICATIONS
•
•
•
•
Static LED Displays
Message Boards
Amusement Illumination
TV Backlighting
Constant Current Accuracy:
–
–
Channel-to-Channel = ±2% (typ)
Device-to-Device = ±2% (typ)
•
•
•
CMOS Logic Level I/O
DESCRIPTION
30-MHz Data Transfer Rate (Standalone)
15-MHz Data Transfer Rate (Cascaded Devices,
SCLK Duty = 50%)
The TLC5947 is a 24-channel, constant current sink
LED driver. Each channel is individually adjustable
with 4096 pulse-width modulated (PWM) steps. PWM
control is repeated automatically with the
programmed grayscale (GS) data. GS data are
written via a serial interface port. The current value of
all 24 channels is set by a single external resistor.
•
Shift Out Data Changes With Falling Edge to
Avoid Data Shift Errors
•
•
•
Auto Display Repeat
4-MHz Internal Oscillator
Thermal Shutdown (TSD):
The TLC5947 has a thermal shutdown (TSD) function
that turns off all output drivers during an
over-temperature condition. All of the output drivers
automatically restart when the temperature returns to
normal conditions.
–
Automatic shutdown at over temperature
conditions
–
Restart under normal temperature
VLED
VLED
VLED
VLED
¼
¼
¼
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
OUT23
SOUT
OUT0
SIN
OUT23
SOUT
DATA
SIN
SCLK
SCLK
SCLK
XLAT
BLANK
VCC
VCC
Controller
XLAT
TLC5947
TLC5947
ICn
XLAT
BLANK
IC1
VCC
GND
VCC
GND
BLANK
IREF
IREF
RIREF
RIREF
3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLC5947
SBVS114A–JULY 2008–REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC5947DAPR
TLC5947DAP
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 2000
Tube, 46
TLC5947
HTSSOP-32 PowerPAD™
TLC5947RHBR
TLC5947RHB
Tape and Reel, 3000
Tape and Reel, 250
TLC5947
5-mm × 5-mm QFN-32
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC5947
–0.3 to +6.0
38
UNIT
V
VCC
IO
Supply voltage: VCC
Output current (dc)
Input voltage range
OUT0 to OUT23
mA
V
VI
SIN, SCLK, XLAT, BLANK
SOUT
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to +33
+150
V
VO
Output voltage range
OUT0 to OUT23
V
TJ(MAX)
TSTG
Operating junction temperature
Storage temperature range
°C
°C
kV
V
–55 to +150
2
Human body model (HBM)
ESD rating
Charged device model (CDM)
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
PACKAGE
HTSSOP-32 with
42.54 mW/°C
5318 mW
3403 mW
2765 mW
PowerPAD soldered(1)
HTSSOP-32 with
22.56 mW/°C
27.86 mW/°C
2820 mW
3482 mW
1805 mW
2228 mW
1466 mW
1811 mW
PowerPAD not soldered(2)
QFN-32(3)
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) With PowerPAD not soldered onto copper area on PCB.
(3) The package thermal impedance is calculated in accordance with JESD51-5.
2
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TLC5947
www.ti.com ................................................................................................................................................. SBVS114A–JULY 2008–REVISED SEPTEMBER 2008
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5947
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3.0
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Constant output sink current
OUT0 to OUT23
30
VIH
VIL
0.7 × VCC
GND
VCC
V
0.3 × VCC
V
IOH
IOL
SOUT
SOUT
–3
3
mA
mA
mA
IOLC
OUT0 to OUT23
2
–40
–40
30
Operating free-air temperature
range
TA
TJ
+85
°C
°C
Operating junction temperature
+125
AC Characteristics: VCC = 3 V to 5.5 V
SCLK, Standalone operation
SCLK, Duty 50%, cascade operation
SCLK = High-level pulse width
SCLK = Low-level pulse width
XLAT, BLANK High-level pulse width
SIN–SCLK↑
30
15
MHz
MHz
ns
fSCLK
Data shift clock frequency
Pulse duration
TWH0
TWL0
TWH1
TSU0
TSU1
TSU2
TH0
12
10
30
5
ns
ns
ns
Setup time
Hold time
XLAT↑–SCLK↑
100
30
3
ns
XLAT↑–BLANK↓
ns
SIN–SCLK↑
ns
TH1
XLAT↑–SCLK↑
10
ns
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ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5947
PARAMETER
TEST CONDITIONS
IOH = –3 mA at SOUT
MIN
TYP
MAX
VCC
0.4
1
UNIT
V
VOH
VOL
IIN
High-level output voltage
Low-level output voltage
Input current
VCC – 0.4
IOL = 3 mA at SOUT
V
VIN = VCC or GND at SIN, XLAT, and BLANK
–1
µA
SIN/SCLK/XLAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 24 kΩ
ICC1
0.5
1
3
6
mA
mA
mA
mA
mA
µA
SIN/SCLK/XLAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 3.3 kΩ
ICC2
Supply current (VCC
)
SIN/SCLK/XLAT = low, BLANK = low, VOUTn = 1 V,
RIREF = 3.3 kΩ, GSn = FFFh
ICC3
15
45
SIN/SCLK/XLAT = low, BLANK = low, VOUTn = 1 V,
RIREF = 1.6 kΩ, GSn = FFFh
ICC4
30
90
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.6 kΩ
IOLC
Constant output current
Output leakage current
27.7
30.75
33.8
0.1
±4
BLANK = high, VOUTn = 30 V, RIREF = 1.6 kΩ,
At OUT0 to OUT23
IOLK
Constant current error
(channel-to-channel)(1)
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.6 kΩ, At OUT0 to OUT23
ΔIOLC
ΔIOLC1
ΔIOLC2
ΔIOLC3
±2
±2
±1
±2
%
Constant current error
(device-to-device)(2)
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.6 kΩ
±7
%
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.6 kΩ, At OUT0 to OUT23
Line regulation(3)
Load regulation(4)
±3
%/V
%/V
All OUTn = ON, VOUTn = 1 V to 3 V, VOUTfix = 1 V,
RIREF = 1.6 kΩ, At OUT0 to OUT23
±6
TDOWN
THYS
Thermal shutdown threshold
Thermal error hysteresis
Reference voltage output
Junction temperature(5)
Junction temperature(5)
RIREF = 1.6 kΩ
+150
+5
+162
+10
+175
+20
°C
°C
V
VIREF
1.16
1.20
1.24
(1) The deviation of each output from the average of OUT0–OUT23 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT22 + IOUT23
)
24
.
(2) The deviation of the OUT0–OUT23 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT22 + IOUT23
)
- (Ideal Output Current)
24
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOUT(IDEAL) = 41 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
D (%/V) =
100
´
(IOUTn at VCC = 3.0 V)
5.5 V - 3 V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
3 V - 1 V
D (%/V) =
´
(IOUTn at VOUTn = 1 V)
(5) Not tested. Specified by design.
4
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SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 150 Ω, RIREF = 1.6 kΩ, and VLED = 5.5 V. Typical values at
VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5947
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
15
UNIT
ns
tR0
tR1
tF0
tF1
SOUT
OUTn
SOUT
OUTn
Rise time
15
40
ns
10
15
ns
Fall time
100
300
ns
Internal oscillator
frequency
fOSC
2.4
4
5.6
MHz
tD0
tD1
tD2
tD3
tD4
SCLK↓ to SOUT
15
20
24
48
72
25
40
33
66
99
ns
ns
ns
ns
ns
BLANK↑ to OUT0 sink current off
Propagation delay time
OUT0 current on to OUT1/5/9/13/17/21 current on
OUT0 current on to OUT2/6/10/14/18/22 current on
OUT0 current on to OUT3/7/11/15/19/23 current on
15
30
45
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
LSB
MSB
D
Q
SOUT
Grayscale (12 Bits ´ 24 Channels) Data
Shift Register
CK
SCLK
0
287
288
LSB
MSB
Grayscale (12 Bits ´ 24 Channels) Data
XLAT
Data Latch
0
287
288
12 Bits PWM Timing Control
24
4 MHz
Internal
Oscillator
Thermal
Detection
BLANK
24-Channel, Constant Current Driver
IREF
GND
¼
OUT0
OUT1
OUT22 OUT23
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DEVICE INFORMATION
5-mm × 5-mm QFN-32(1)
HTSSOP-32
DAP PACKAGE
RHB PACKAGE
(TOP VIEW)
(TOP VIEW)
GND
BLANK
SCLK
SIN
1
2
3
4
5
6
7
8
9
32 VCC
31 IREF
30 XLAT
OUT15
15 OUT14
OUT13
14
SOUT
XLAT
25
26
16
29 SOUT
28 OUT23
27 OUT22
26 OUT21
25 OUT20
24 OUT19
23 OUT18
22 OUT17
21 OUT16
20 OUT15
19 OUT14
18 OUT13
17 OUT12
OUT0
OUT1
OUT2
OUT3
OUT4
IREF 27
28
29
30
13 OUT12
12 OUT11
11 OUT10
VCC
GND
Thermal Pad
(Bottom Side)
Thermal Pad
(Bottom Side)
BLANK
OUT9
10
SCLK 31
32
OUT5 10
OUT6 11
OUT7 12
OUT8
SIN
9
OUT8
OUT9
13
14
15
16
OUT10
OUT11
(1) This device is product preview.
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB
pattern.
6
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TERMINAL FUNCTIONS
TERMINAL
NAME
SIN
DAP
RHB
I/O
DESCRIPTION
4
32
I
Serial input for grayscale data
Serial data shift clock. Schmitt buffer input. Data present on the SIN pin are shifted into the shift
register with the rising edge of the SCLK pin. Data are shifted to the MSB side by 1-bit
synchronizing of the rising edge of SCLK. The MSB data appears on SOUT at the falling edge of
SCLK. A rising edge on the SCLK input is allowed 100 ns after an XLAT rising edge.
SCLK
XLAT
3
31
26
I
I
The data in the grayscale shift register are moved to the grayscale data latch with a low-to-high
transition on this pin. When the XLAT rising edge is input, all constant current outputs are forced
off until the next grayscale display period. The grayscale counter is not reset to zero with a rising
edge of XLAT.
30
Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0
through OUT23) are forced off, the grayscale PWM timing controller initializes, and the grayscale
counter resets to '0'. When BLANK is low, all constant current outputs are controlled by the
grayscale PWM timing controller.
BLANK
IREF
2
31
29
5
30
27
25
1
I
This pin sets the constant current value. OUT0 through OUT23 constant sink current is set to the
desired value by connecting an external resistor between IREF and GND.
I/O
O
Serial data output. This output is connected to the shift register placed after the MSB of the
grayscale shift register. Therefore, the MSB data of the grayscale shift register appears at the
falling edge of SCLK. This function reduces the data shifting errors caused by small timing
margins between SIN and SCLK.
SOUT
OUT0
Constant current output. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
O
OUT1
6
2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Power-supply voltage
Power ground
OUT2
7
3
OUT3
8
4
OUT4
9
5
OUT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
1
6
OUT6
7
OUT7
8
OUT8
9
OUT9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
29
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
VCC
GND
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
GND
SOUT
GND
Figure 1. SIN, SCLK, XLAT, BLANK
Figure 2. SOUT
OUTn
GND
Figure 3. OUT0 Through OUT23
TEST CIRCUITS
RL
CL
VCC
GND
VCC
VCC
IREF
OUTn
SOUT
VLED
VCC
RIREF
CL
GND
Figure 4. Rise Time and Fall Time Test Circuit for OUTn
Figure 5. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
OUTn
VCC
IREF
RIREF
GND OUT23
VOUTn
VOUTFIX
Figure 6. Constant Current Test Circuit for OUTn
8
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TIMING DIAGRAMS
TWH0, TWL0, TWH1
:
VCC
INPUT(1) 50%
GND
TWH
TWL
TSU0, TSU1, TSU2, TH0, TH1
:
VCC
CLOCK
INPUT(1)
50%
GND
VCC
TSU
TH
DATA/CONTROL
INPUT(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4
:
VCC
INPUT(1)
50%
GND
tD
VOH or VOUTn
90%
50%
10%
OUTPUT
VOL or VOUTn
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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GS0
0A
GS23 GS23 GS23 GS23 GS23
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS23 GS23 GS23 GS23 GS23 GS23 GS23
11C 10C 9C 8C 7C 6C 5C
SIN
11B
10B
9B
8B
7B
TSU0
fSCLK
TH1
TWH0
TH0
TSU1
SCLK
XLAT
1
2
3
4
5
285 286 287 288
1
2
3
4
5
6
7
TWH1
TWL0
TSU2
TWH1
BLANK
tD1
Grayscale
Latch Data
(Internal)
Previous Grayscale Data
Latest Grayscale Data
Counter
Value
4094 4096
4093 4095
fOSC
¼
0 0 0 0 1 2 3 4 5 0 0 0 0 0 1 2
¼
¼
¼
1
2
3
4
Oscillator
Clock
(Internal)
tD0
GS23 GS23 GS23 GS23 GS23
11A 8A 7A
10A 9A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS23
11B
GS23 GS23 GS23 GS23 GS23 GS23
SOUT
10B
9B
8B
7B
6B
5B
tR0/tF0
OFF
ON
OUT0/4/8/
12/16/20(1)
tR1
tF1
OFF
ON
OUT1/5/9/
13/17/21(1)
tD2
OFF
ON
OUT2/6/10/
14/18/22(1)
tD3
OFF
ON
OUT3/7/11/
15/19/23(1)
tD4
(1) GS data = FFFh.
Figure 9. Grayscale Data Write and OUTn Operation Timing
10
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
100000
10000
1000
6000
5000
4000
3000
2000
1000
0
TLC5947DAP
PowerPAD Soldered
24600
TLC5947RHB
9840
TLC5947DAP
PowerPAD Not Soldered
4920
3280
2460
1968
1640
30
0
5
10
15
20
25
-40
0
20
60
80
100
-20
40
Output Current (mA)
Free-Air Temperature (°C)
Figure 10.
Figure 11.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
35
30
25
20
15
10
5
35
34
33
32
31
30
29
28
27
26
25
TA = +25°C
IO = 30 mA
IO = 30 mA
IO = 25 mA
IO = 20 mA
IO = 15 mA
IO = 10 mA
IO = 5 mA
TA = -40°C
IO = 2 mA
TA = +25°C
TA = +85°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 12.
Figure 13.
ΔIOLC vs AMBIENT TEMPERATURE
ΔIOLC vs OUTPUT CURRENT
4
3
4
3
IO = 30 mA
TA = +25°C
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
-40
-20
0
20
40
60
80
100
0
5
10
15
20
25
30
Ambient Temperature (°C)
Output Current (mA)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
INTERNAL OSCILLATOR FREQUENCY
vs AMBIENT TEMPERATURE
CONSTANT CURRENT OUTPUT
VOLTAGE WAVEFORM
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CH1-OUT0
(GSData = 001h)
CH1 (2 V/div)
CH2 (2 V/div)
VCC = +3.3 V
VCC = +5 V
IOLCMax = 30 mA
TA = +25°C
CH2-OUT0
(GSData = 002h)
RL = 150 W
CL = 15 pF
VLED = 5.5 V
CH3 (2 V/div)
CH3-OUT23
(GSData = 003h)
Time (100 ns/div)
-40
-20
0
20
35
55
70
85
Ambient Temperature (°C)
Figure 16.
Figure 17.
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DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant current value for all channels is set by an external resistor (RIREF) placed between IREF and GND.
The resistor (RIREF) value is calculated by Equation 1.
VIREF (V)
RIREF (W) = 41 ´
IOLC (mA)
(1)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V).
IOLC must be set in the range of 2 mA to 30 mA. The constant sink current characteristic for the external resistor
value is shown in Figure 10. Table 1 describes the constant current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLC (mA, Typical)
RIREF (Ω)
1640
30
25
20
15
10
5
1968
2460
3280
4920
9840
2
24600
GRAYSCALE (GS) CONTROL FUNCTION
Each constant current sink output OUT0–OUT23 (OUTn) turns on (starts to sink constant current) at the fifth
rising edge of the grayscale internal oscillator clock after the BLANK signal transitions from high to low if the
grayscale data latched into the grayscale data latch are not zero. After turn-on, the number of rising edges of the
internal oscillator is counted by the 12-bit grayscale counter. Each OUTn output is turned off once its
corresponding grayscale data values equal the grayscale counter or the counter reaches 4096d (FFFh). The
PWM control operation is repeated as long as BLANK is low. OUTn is not turned on when BLANK is high. The
timing is shown in Figure 18. All outputs are turned off at the XLAT rising edge. After that, each output is
controlled again from the first clock of the internal oscillator for the next display period, based on the latest
grayscale data.
When the IC is powered on, the data in the grayscale data shift register and latch are not set to default values.
Therefore, grayscale data must be written to the GS latch before turning on the constant current output. BLANK
should be at a high level when powered on to keep the outputs off until valid grayscale data are written to the
latch. This avoids the LED being randomly illuminated immediately after power-up. If having the outputs turn on
at power-up is not a problem for the application, then BLANK does not need to be held high. The grayscale
functions can be controlled directly by grayscale data writing, even though BLANK is connected to GND.
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BLANK
1027
1026
1025
1030
1029
1028
2049
2048
1031 2047
2052
2051
2050
3073
3072
3071
3076
3075
3074
4096
4095
4094 1 2
Counter Value
64
66
0
0
0
0
1
2
3
63
65
3077
Internal
Oscillator
Clock
Grayscale counter starts to count from 5th clock of the internal oscillator clock after BLANK goes low.
Drivers do not turn on when grayscale data are ‘0’.
OFF
ON
OUTn
(GS Data = 000h)
Dotted line indicates BLANK is high.
T = Internal CLK ´ 1
T = Internal CLK ´ 2
T = Internal CLK ´ 3
OFF
ON
OUTn
(GS Data = 001h)
OFF
ON
OUTn
(GS Data = 002h)
OFF
ON
OUTn
(GS Data = 003h)
T = Internal
CLK ´ 63
OFF
ON
OUTn
(GS Data = 03Fh)
T = Internal CLK ´ 64
T = Internal CLK ´ 65
OFF
ON
OUTn
(GS Data = 040h)
OFF
ON
OUTn
(GS Data = 041h)
T = Internal CLK ´ 1024
T = Internal CLK ´ 1025
OFF
ON
OUTn
(GS Data = 400h)
OFF
ON
OUTn
(GS Data = 401h)
T = Internal CLK ´ 2048
OFF
ON
OUTn
(GS Data = 800h)
T = Internal CLK ´ 3072
OFF
ON
OUTn
(GS Data = C00h)
T = Internal CLK ´ 4094
OFF
ON
OUTn
(GS Data = FFEh)
T = Internal CLK ´ 4095
OFF
ON
OUTn
(GS Data = FFFh)
Figure 18. PWM Operation
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REGISTER CONFIGURATION
The TLC5947 has a grayscale (GS) data shift register and data latch. Both the GS data shift register and latch
are 288 bits long and are used to set the PWM timing for the constant current driver. Table 2 shows the on duty
cycle for each GS data. Figure 19 shows the shift register and data latch configuration. The data at the SIN pin
are shifted to the LSB of the shift register at the rising edge of the SCLK pin; SOUT data are shifted out on the
falling edge of SCLK. The timing diagram for data writing is shown in Figure 20. The driver on duty is controlled
by the data in the GS data latch.
Grayscale Data Shift Register (12 Bits ´ 24 Channels)
GS Data for OUT23
MSB
287
GS Data for OUT22
¼
¼
GS Data for OUT1
GS Data for OUT0
LSB
0
276
275
12
11
SIN
GS Data for
Bit 11 of
OUT23
GS Data for GS Data for
Bit 11 of
OUT22
GS Data for
Bit 11 of
OUT0
GS Data for
Bit 0 of OUT1
GS Data for
Bit 0 of OUT0
¼
¼
¼
¼
Bit 0 of
OUT23
SOUT
SCLK
¼
¼
GS Data for OUT23
MSB
287
GS Data for OUT22
GS Data for OUT1
GS Data for OUT0
LSB
0
276
275
12
11
GS Data for
Bit 11 of
OUT23
GS Data for GS Data for
Bit 11 of
OUT22
GS Data for
Bit 11 of
OUT0
GS Data for
Bit 0 of OUT1
GS Data for
Bit 0 of OUT0
¼
¼
¼
Bit 0 of
OUT23
XLAT
Grayscale Data Latch (12 Bits ´ 24 Channels)
288 Bits
To PWM Timing Control Block
Figure 19. Grayscale Data Shift Register and Latch Configuration
Table 2. GS Data versus On Duty
GS DATA
(Binary)
GS DATA
(Decimal)
GS DATA
(Hex)
DUTY OF DRIVER TURN-ON
TIME (%)
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
—
0
000
001
002
003
—
0.00
0.02
0.05
0.07
—
1
2
3
—
0111 1111 1111
1000 0000 0000
1000 0000 0001
—
2047
2048
2049
—
7FF
800
801
—
49.98
50.00
50.02
—
1111 1111 1101
1111 1111 1110
1111 1111 1111
4093
4094
4095
FFD
FFE
FFF
99.93
99.95
99.98
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GS data are transferred from the shift register to the latch by the rising edge of XLAT. When powered up, the
data in the grayscale shift register and data latch are not set to default values. Therefore, grayscale data must be
written to the GS latch before turning on the constant current output. BLANK should be at a high level when
powered on to avoid falsely turning on the constant current outputs due to random values in the latch at
power-up. All of the constant current outputs are forced off when BLANK is high. However, if the random values
turning on at power-up is not a concern in the application, BLANK can be at any level. GS can be controlled
correctly with the grayscale data writing functions, even if BLANK is connected to GND. Equation 2 determines
each output on duty.
GSn
On Duty (%) =
´ 100
4096
(2)
where:
GSn = the programmed grayscale value for OUTn (GSn = 0 to 4095)
GS0 GS23 GS23 GS23 GS23 GS23
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS23 GS23 GS23 GS23 GS23 GS23
11C 10C 9C 8C 7C 6C
SIN
0A
11B
10B
9B
8B
7B
SCLK
XLAT
1
2
3
4
5
285 286 287 288
1
2
3
4
5
6
7
Shift Register
Bit 0 Data (Internal)
GS0 GS23 GS23 GS23 GS23
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS23 GS23 GS23 GS23 GS23 GS23
11C 10C 9C 8C 7C 6C
0A
11B
10B
9B
8B
Shift Register
Bit 1 Data (Internal)
GS0
1A
GS0 GS23 GS23 GS23
0A 11B 10B 9B
GS0
4B
GS0
3B
GS0
2B
GS0
1B
GS0 GS23 GS23 GS23 GS23 GS23
0B 11C 10C 9C 8C 7C
Shift Register
Bit 286 Data (Internal)
GS23 GS23 GS23 GS23 GS23
10A 9A 8A 7A 6A
GS0
1A
GS0 GS23 GS23
0A 11B 10B
GS23 GS23 GS23 GS23 GS23 GS23
9B 8B 7B 6B 5B 4B
Shift Register
Bit 287 Data (Internal)
GS23 GS23 GS23 GS23 GS23
11A 10A 9A 8A 7A
GS0
2A
GS0 GS23 GS23
1A 0A 11B
GS23 GS23 GS23 GS23 GS23 GS23
10B 9B 8B 7B 6B 5B
Grayscale Latch Data
(Internal)
Previous Grayscale Latch Data
Latest Grayscale Latch Data
GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS23
11B
GS23 GS23 GS23 GS23 GS23 GS23
GS23 GS23 GS23 GS23 GS23
11A 10A 9A 8A 7A
SOUT
10B
9B
8B
7B
6B
5B
4094 4096
4093 4095
4094 4096
4093 4095
¼
¼
¼
¼
1
2
3
4
1
2
3
4
5
6
7 8
Oscillator Clock
(Internal)
OFF
OFF
OUT0/4/8/12/16/20(1)
OUT1/5/9/13/17/21(1)
OUT2/6/10/14/18/22(1)
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OUT3/7/11/15/19/23(1)
ON
ON
ON
(1) GS data = FFFh.
Figure 20. Grayscale Data Write Operation
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AUTO DISPLAY REPEAT FUNCTION
This function can repeat the total display period without any timing control signal, as shown in Figure 21.
BLANK
GS Counter Value
2048
2047 2049 4094
4095
2048
2047 2049 4094
4095
4095
4094 40961
¼
¼
¼
¼
¼
0
0
0
0
1
2
3
0
1
2
3
0
1
2
3
0
0
0
0
0
0
1
2
2
Internal Oscillator Clock
Grayscale counter starts to count from the fifth clock
of the internal oscillator clock after BLANK goes low.
Display period is turned on again by
the auto display repeat function.
OFF
OUTn
(GS Data = 001h)
ON
OFF
OUTn
(GS Data = 800h)
ON
OFF
OUTn
(GS Data = FFFh)
ON
First
Display Period
Second
Display Period
First Display Period
(4096 Internal Clock)
Second Display Period
(4096 Internal Clock)
Four Internal Clock Intervals After BLANK Goes Low
Nth Display Period
Four Internal Clock Intervals After BLANK Goes Low
Figure 21. Auto Display Repeat Operation
THERMAL SHUTDOWN (TSD)
The thermal shutdown (TSD) function turns off all constant current outputs immediately when the IC junction
temperature exceeds the high temperature threshold (T(TEF) = +162° C, typ). The outputs will remain disabled as
long as the over-temperature condition exists. The outputs are turned on again at the first clock after the IC
junction temperature falls below the temperature of T(TEF) – T(HYS). Figure 22 shows the TSD operation.
TJ < T(TEF) - T(HYS)
TJ < T(TEF) - T(HYS)
TJ ³ T(TEF)
TJ ³ T(TEF)
IC Junction Temperature (TJ)
High
Low
BLANK
4096
4095
4096
4096
4095
4096
4095
4096
4095
4096
1
2
3
1
2
4095
1
2
1
2
1
2
1
2
4095
1 2
Internal Oscillator Clock
OFF
OFF
OFF
OUTn
(GS Data = FFFh)
ON
ON
Figure 22. TSD Operation
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NOISE REDUCTION
Large surge currents may flow through the IC and the board on which the device is mounted if all 24 LED
channels turn on simultaneously at the start of each grayscale cycle. These large current surges could introduce
detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5947 turns on the LED
channels in a series delay, to provide a current soft-start feature. The output current sinks are grouped into four
groups of six channels each. The first group is OUT0, 4, 8, 12, 16, 20; the second group is OUT1, 5, 9, 13, 17,
21; the third group is OUT2, 6, 10, 14, 18, 22; and the fourth group is OUT3, 7, 11, 15, 19, 23. Each group turns
on sequentially with a small delay between groups; see Figure 9. Both turn-on and turn-off are delayed.
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package (illustrated in
Figure 11) to ensure correct operation. Equation 3 calculates the power dissipation of the device:
PD = (VCC ´ ICC) + (VOUT ´ IOLC ´ N ´ dPWM
)
(3)
Where:
•
•
•
•
•
•
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IOLC = LED current adjusted by RIREF resistor
N = number of OUTn driving LED at the same time
dPWM = duty ratio defined by GS value
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
TLC5947DAP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
VQFN
DAP
32
32
32
32
32
32
32
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TLC5947
TLC5947DAPG4
TLC5947DAPR
TLC5947DAPRG4
TLC5947RHBR
TLC5947RHBRG4
TLC5947RHBT
TLC5947RHBTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DAP
DAP
DAP
RHB
RHB
RHB
RHB
46
Green (RoHS
& no Sb/Br)
TLC5947
TLC5947
TLC5947
2000
2000
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC
5947
VQFN
Green (RoHS
& no Sb/Br)
TLC
5947
VQFN
Green (RoHS
& no Sb/Br)
TLC
5947
VQFN
250
Green (RoHS
& no Sb/Br)
TLC
5947
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC5947DAPR
TLC5947RHBR
TLC5947RHBT
HTSSOP
VQFN
DAP
RHB
RHB
32
32
32
2000
3000
250
330.0
330.0
180.0
24.4
12.4
12.4
8.6
5.3
5.3
11.5
5.3
1.6
1.5
1.5
12.0
8.0
24.0
12.0
12.0
Q1
Q2
Q2
VQFN
5.3
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC5947DAPR
TLC5947RHBR
TLC5947RHBT
HTSSOP
VQFN
DAP
RHB
RHB
32
32
32
2000
3000
250
367.0
367.0
210.0
367.0
367.0
185.0
45.0
35.0
35.0
VQFN
Pack Materials-Page 2
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