INA597_V02 [TI]
INA597 High-Precision, Wide-Bandwidth e-trim⢠Difference Amplifier;
| 型号： | INA597_V02 |
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TEXAS INSTRUMENTS |
| 描述： | INA597 High-Precision, Wide-Bandwidth e-trim⢠Difference Amplifier |
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INA597
SBOS385B – AUGUST 2019 – REVISED APRIL 2021
INA597 High-Precision, Wide-Bandwidth e-trim™ Difference Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
Low offset voltage: 200 μV (maximum)
Low offset voltage drift: ±5 μV/°C (maximum)
Low noise: 18 nV/√Hz at 1 kHz
Low gain error: ±0.03% (maximum)
High common-mode rejection: 88 dB (minimum)
Wide bandwidth: 2-MHz GBW
Low quiescent current: 1.1 mA per amplifier
High slew rate: 18 V/μs
High capacitive load drive capability: 500 pF
Wide supply range:
– Single-supply: 4.5 V to 36 V
– Dual-supply: ±2.25 V to ±18 V
Specified temperature range:
–40°C to +125°C
Packages: 8-pin SOIC and VSSOP, 10-pin VSON
The INA597 is
a
low-power, wide-bandwidth,
difference amplifier for cost-sensitive applications.
The INA597 consists of a precision operational
amplifier (op amp) and a precision resistor network.
Excellent tracking of resistors maintains gain accuracy
and common-mode rejection over temperature.
Unique features such as low offset (200 μV,
maximum), low offset drift (5 μV/°C maximum) high
slew rate (18 V/μs), and high capacitive load drive
of up to 500 pF make the INA597 a robust,
high-performance difference amplifier for high-voltage
industrial applications.
•
•
The common-mode range of the internal op amp
extends to the negative supply, and enables the
device to operate in single-supply applications. The
device operates on single (4.5 V to 36 V) or dual
supplies (±2.25 V to ±18 V).
2 Applications
•
•
•
•
•
•
•
•
Data acquisition (DAQ)
Sensor modules and tags for asset tracking
Flow transmitter
Optical module
Power supply module
AC drive position feedback
Servo drive position feedback
Voltage conditioning module
The difference amplifier is the foundation of many
commonly used circuits. The INA597 provides this
circuit function without using an expensive precision
resistor network.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
3.00 mm × 3.00 mm
SOIC (8)
INA597
VSON (10)
VSSOP (8)
(1) For all available packages, see the package option
addendum at the end of the data sheet.
VCC
20
15
10
5
V+
INA597
SENSE
œIN
6 kꢀ
6 kꢀ
12 kꢀ
12 kꢀ
œ
ADC
16 Bits Out
AIN
OUT
REF
+
+IN
Vœ
1
2
V
=
∂ V+IN - VœIN
(
)
OUT
0
-80
-60
-40
-20
0
20
40
60
80
Differential Input Data Acquisition
D004
Offset Voltage (mV)
Typical Distribution of Offset Voltage (RTO)
G = 1/2, VS = ±18 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA597
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................4
7.5 Electrical Characteristics: G = 1/2 ..............................5
7.6 Electrical Characteristics: G = 2 .................................6
7.7 Typical Characteristics................................................7
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................30
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................33
12.1 Documentation Support.......................................... 33
12.2 Receiving Notification of Documentation Updates..33
12.3 Support Resources................................................. 33
12.4 Trademarks.............................................................33
12.5 Electrostatic Discharge Caution..............................33
12.6 Glossary..................................................................33
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2021) to Revision B (April 2021)
Page
•
Added DRC package and associated content....................................................................................................1
Changes from Revision * (August 2019) to Revision A (February 2021)
Page
•
•
•
•
•
•
Added D package and associated content......................................................................................................... 1
Added input current (max) to Absolute Maximum Ratings ................................................................................ 4
Deleted input voltage (max) from Absolute Maximum Ratings ..........................................................................4
Changed common-mode voltage (min and max) in Electrical Characteristics .................................................. 4
Added input impedance specifications to Electrical Characteristics ..................................................................4
Changed Fig. 6-39, Positive Output Voltage vs Output Current (sourcing) G = ½, Y-axis unit from µV to V......7
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5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
G = 0.5 V/V or 2 V/V
G = 0.5 V/V or 2 V/V
G = 0.2 V/V
INA597 Cost-effective, wide-bandwidth e-trim™ difference amplifier
INA592 High-precision, wide-bandwidth e-trim™ difference amplifier
INA159 High-speed, precision, gain of 0.2 level translation difference amplifier
INA137 Audio differential line receiver ±6 dB (G = 1/2 or 2)
G = 0.5 V/V or 2 V/V
G = 1 V/V
INA132 Low-power, single-supply difference amplifier
INA819 35-µV offset, 0.4 µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision instrumentation amplifier
INA821 35-µV offset, 0.4 µV/°C VOS drift, 7-nV/√Hz noise, high-bandwidth, precision instrumentation amplifier
INA333 25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA
G = 1 + 50 kΩ / RG
G = 1 + 49.4 kΩ / RG
G = 1 + 100 kΩ / RG
PGA280 20-mV to ±10-V Programmable Gain IA With 3-V or 5-V Differential Output; Analog Supply up to ±18 V Digital programmable
PGA112 Precision Programmable Gain Op Amp With SPI
Digital programmable
6 Pin Configuration and Functions
REF
1
–INOP
REF
–IN
1
2
3
4
5
10
9
+INOP
NC
8
7
6
NC
V+
œ
œIN
2
Thermal
Pad
+
8
V+
+IN
3
4
OUT
+IN
7
OUT
SENSE
Vœ
5
SENSE
V–
6
NC = No Connection
Not to scale
Figure 6-1. D (8-Pin SOIC) and DGK (8-Pin VSSOP)
Packages, Top View
Figure 6-2. DRC (10-Pin VSON With Thermal Pad)
Package, Top View
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
NAME
DRC (VSON)
12-kΩ resistor to noninverting terminal of op amp.
+IN
3
2
4
I
I
Used as positive input in G = ½ configuration.
Used as reference pin in G = 2 configuration.
12-kΩ resistor to inverting terminal of op amp.
Used as negative input in G = ½ configuration.
Connect to output in G = 2 configuration.
–IN
3
+INOP
–INOP
NC
—
—
8
10
1
I
I
Direct connection to noninverting terminal of op amp
Direct connection to inverting terminal of op amp
No internal connection (can be left floating)
Output
9
—
O
OUT
6
7
6-kΩ resistor to noninverting terminal of op amp.
Used as reference pin in G = ½ configuration.
Used as positive input in G = 2 configuration.
REF
1
5
2
6
I
I
6-kΩ resistor to inverting terminal of op amp.
Connect to output in G = ½ configuration.
Used as negative input in G = 2 configuration.
SENSE
V+
V–
7
4
8
5
—
—
Positive (highest) power supply
Negative (lowest) power supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
Single supply, (V+) to (V–)
V±
Dual supply, (V+) – (V–)
±18
10
V
IIN
IS
Input current
mA
Output short circuit (to ground)
Operating temperature
Junction temperature
Storage temperature
Continuous
–55
TA
TJ
125
125
150
°C
°C
°C
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Section 7.3.
Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
7.2 ESD Ratings
VALUE
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply, VS = (V+) to (V–)
Dual supply, VS = (V+) – (V–)
V±
TA
Supply voltage
±2.25
–40
±18
125
V
Specified temperature
°C
7.4 Thermal Information
INA597
THERMAL METRIC(1)
D
DGK
8 PINS
115
DRC
UNIT
8 PINS
158
10 PINS
47.4
49.6
21.0
0.8
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.6
78.7
3.9
52.4
59.2
9.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
77.3
N/A
58.3
N/A
20.9
5.3
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: G = 1/2
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE (RTO)
G = 1/2, RTO, TA = 25°C, VS = ±2.25 V to ±3
±14
±14
±200
±200
±5.0
±5
µV
µV
V,
VCM = –3V
VOS
Input offset voltage
G = 1/2, RTO, TA = 25°C, VS = ±3 V to ±18
V, VCM = VS / 2
Input offset voltage
drift
dVOS/dT
PSRR
±0.7
±0.5
µV/°C
µV/V
Power-supply
rejection ratio
VS = ±3 V to ±18 V
INPUT VOLTAGE
Common-mode
voltage
3[(V–)–0.1]
–2VREF
VCM
VOUT = 0 V
3(V+)–2VREF
V
TA = 25°C
88
82
88
72
100
90
dB
dB
dB
dB
RTO, 3 [(V−) – 0.1 V)] ≤
VCM ≤ 3 [(V+) – 3 V]
TA = –40°C to +125°C
TA = 25°C
Common-mode
rejection ratio
CMRR
100
90
RTO, 3 [(V+) - 1.5 V)] ≤
VCM ≤ 3 [(V+))]
TA = –40°C to +125°C
INPUT IMPEDANCE
zid
Differential
VO = 0 V
24
9
kΩ
kΩ
zic
Common-mode
GAIN
G
Initial
1/2
±0.01
±0.2
1
V/V
%
GE
Gain error
VOUT = –10 V to +10 V, VS = ±15 V
VOUT = –10 V to +10 V, VS = ±15 V
±0.03
Gain error drift(1)
±0.5 ppm/°C
ppm
Gain nonlinearity
OUTPUT
Positive rail
Negative rail
170
190
220
220
mV
mV
Output voltage
swing
VO
Short-circuit
current
ISC
±65
mA
NOISE
Output voltage
noise
f = 0.1 Hz to 10 Hz, RTO
f = 1 kHz, RTO
3
μVpp
Vn
Output voltage
noise density
18
nV/√Hz
FREQUENCY RESPONSE
Small signal
GBW
Amplitude = –3 dB
2.0
MHz
bandwidth
SR
tS
Slew rate
18
1
V/µs
µs
To 0.1%
VOUT = 10-V step
VOUT = 10-V step
Settling time
To 0.01%
1.3
µs
Total harmonic
distortion + noise
f = 1 kHz, VOUT = 2.8 VRMS
0.00038
–116
%
dB
ns
THD+N
tDR
Noise floor, RTO
80-kHz bandwidth, VOUT = 3.5 VRMS
Overload recovery
time
200
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7.5 Electrical Characteristics: G = 1/2 (continued)
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
TA = 25°C
1.1
1.2
1.5
mA
mA
IQ
Quiescent current IOUT = 0 mA
TA = –40°C to +125°C
(1) Specified by wafer test to 95% confidence level.
7.6 Electrical Characteristics: G = 2
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE (RTO)
G = 2, RTO, TA = 25°C, VS = ±2.25 V to ±3
V , VCM = –1.5V
±28
±400
µV
VOS
Input offset voltage
G = 2, RTO, TA = 25°C, VS = ±3 V to ±18
±28
±1.4
±1
±400
±10
±5
µV
V,
VCM = VS / 2
dVOS/dT Input offset voltage drift
µV/°C
µV/V
Power-supply rejection
PSRR
ratio
VS = ±2.25 V to ±18 V
INPUT VOLTAGE
3/2[(V–)–
0.1]–0.5VREF
3/2(V+)–
0.5VREF
VCM
Common-mode voltage
VOUT = 0 V
V
TA = 25°C
82
80
82
65
94
84
94
84
dB
dB
dB
dB
RTO, 1.5 [(V−) – 0.1 V)]
≤ VCM ≤ 1.5 [(V+) – 3 V)]
TA = –40°C to +125°C
TA = 25°C
Common-mode rejection
ratio
CMRR
RTO, 1.5 [(V+) - 1.5 V)]
≤ VCM ≤ 1.5 [(V+))]
TA = –40°C to +125°C
INPUT IMPEDANCE
zid
Differential
VO = 0 V
12
9
kΩ
kΩ
zic
Common-mode
GAIN
G
Initial
2
±0.01
±0.25
1
V/V
%
GE
Gain error
VOUT = –10 V to +10 V, VS = ±15 V
VOUT = –10 V to +10 V, VS = ±15 V
±0.03
Gain error drift (1)
±0.5 ppm/°C
ppm
Gain nonlinearity
OUTPUT
Positive rai
130
140
±65
180
180
mV
mV
mA
VO
Output voltage swing
Short-circuit current
Negative rail
ISC
NOISE
Output voltage noise
f = 0.1 Hz to 10 Hz, RTO
f = 1 kHz, RTO
6
μVpp
Vn
Output voltage noise
density
36
nV/√Hz
FREQUENCY RESPONSE
GBW
SR
Small signal bandwidth
Slew rate
Amplitude = –3 dB
0.8
18
MHz
V/µs
µs
To 0.1%
VOUT = 10-V step
1.0
1.7
tS
Settling time
To 0.01%
VOUT = 10-V step
µs
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7.6 Electrical Characteristics: G = 2 (continued)
at VS = ±2.25 V to ±18 V, TA = 25°C, VCM = VOUT = VS / 2, RL = 10 kΩ connected to ground, and REF pin connected to
ground (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Total harmonic distortion +
noise
f = 1 kHz, VOUT = 2.8 VRMS
0.00066
%
THD+N
tDR
Noise floor, RTO
80-kHz bandwidth, VOUT = 3.5 VRMS
–110
200
dB
ns
Overload recovery time
POWER SUPPLY
TA = 25°C
1.1
1.2
1.5
mA
mA
IQ Quiescent current
IOUT = 0 mA
TA = –40°C to +125°C
(1) Specified by wafer test to 95% confidence level.
7.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Table 7-1. Table of Graphs
DESCRIPTION
Typical Distribution of Offset Voltage (RTO) G= 1/2, VS = ±2.25 V
Typical Distribution of Offset Voltage (RTO) G= 2, , VS = ±2.25 V
Typical Distribution of Offset Voltage (RTO) G= 1/2, , VS = ±18 V
Typical Distribution of Offset Voltage (RTO) G= 2, VS = ±18 V
Typical Distribution of Offset Voltage Drift (RTO) G = 1/2
Typical Distribution of Offset Voltage Drift (RTO) G = 2
Output Offset Voltage vs Temperature G = 1/2
Output Offset Voltage vs Temperature G = 2
Offset Voltage vs Common-Mode Voltage G = 1/2
Offset Voltage vs Common-Mode Voltage G = 2
Input Bias Current vs Temperature G = 1/2 and G = 2
Input Offset Current vs Temperature
FIGURE
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
Figure 7-23
Figure 7-24
Figure 7-25
Figure 7-26
Figure 7-27
Figure 7-28
Figure 7-29
Figure 7-30
Figure 7-31
Figure 7-32
Figure 7-33
Input Bias Current vs Common Mode Voltage G = 1/2
Input Bias Current vs Common Mode Voltage G = 2
Typical CMRR Distribution G= 1/2, Vs = ±2.25 V
Typical CMRR Distribution G = 2, Vs = ±2.25 V
Typical CMRR Distribution G= 1/2, Vs = ±18 V
Typical CMRR Distribution G = 2, Vs = ±18 V
CMRR vs Temperature G= 1/2
CMRR vs Temperature G= 2
Common-Mode Rejection Ratio vs Frequency (RTI) G = 1/2 and 2
Maximum Output Voltage vs Frequency
PSRR vs Temperature G = 1/2
PSRR vs Temperature G = 2
PSRR vs Frequency (RTI) G = 1/2
PSRR vs Frequency (RTI) G = 2
Typical Distribution of Gain Error G = 1/2, VS = ±2.25 V
Typical Distribution of Gain Error G = 2, VS = ±2.25 V
Gain Error vs Temperature G = 1 /2
Gain Error vs Temperature G = 2
Closed-Loop Gain vs Frequency G = 1/2
Closed-Loop Gain vs Frequency G = 2
Voltage Noise Spectral Density vs Frequency (RTI) G = 1/2
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7.7 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Table 7-1. Table of Graphs (continued)
DESCRIPTION
Voltage Noise Spectral Density vs Frequency (RTI) G = 2
0.1-Hz to 10-Hz RTI Voltage Noise G = 1/2
FIGURE
Figure 7-34
Figure 7-35
Figure 7-36
Figure 7-37
Figure 7-38
Figure 7-39
Figure 7-40
Figure 7-41
Figure 7-42
Figure 7-43
Figure 7-44
Figure 7-45
Figure 7-46
Figure 7-47
Figure 7-48
Figure 7-49
Figure 7-50
Figure 7-51
Figure 7-52
Figure 7-53
Figure 7-54
Figure 7-55
Figure 7-56
Figure 7-57
Figure 7-58
Figure 7-59
Figure 7-60
Figure 7-61
Figure 7-62
Figure 7-63
Figure 7-64
Figure 7-65
Figure 7-66
Figure 7-67
Figure 7-68
Figure 7-69
Figure 7-70
Figure 7-71
Figure 7-72
Figure 7-73
0.1-Hz to 10-Hz RTI Voltage Noise G = 2
Integrated Output Voltage Noise vs Noise Bandwidth G = 1/2
Integrated Output Voltage Noise vs Noise Bandwidth G = 2
Positive Output Voltage vs Output Current (sourcing) G = 1/2
Positive Output Voltage vs Output Current (sourcing) G = 2
Negative Output Voltage vs Output Current (sinking) G = 1/2
Negative Output Voltage vs Output Current (sinking) G = 2
Settling Time G = 1/2
Settling Time G = 2
Large Signal Step Response G = 1/2
Large Signal Step Response G =2
Slew Rate over Temperature
Overload Recovery (Normalized to 0V)
Small-Signal Overshoot vs Capacitive Load G = 1/2
Small-Signal Overshoot vs Capacitive Load G = 2
Small-Signal Step Response G = 1/2
Small-Signal Step Response G = 2
THD+N vs Frequency G = 1/2
THD+N vs Frequency G = 2
THD+N Ratio vs Output Amplitude G = 1/2
THD+N Ratio vs Output Amplitude G = 2
Supply Current vs Temperature G = 1/2
Supply Current vs Temperature G = 2
Supply Current vs Supply Voltage G = 1/2
Supply Current vs Supply Voltage G = 2
Short Circuit Current vs Temperature G = 1/2
Short Circuit Current vs Temperature G = 2
Differential-Mode EMI Rejection Ratio G = 1/2
Differential-Mode EMI Rejection Ratio G = 2
Common-Mode EMI Rejection Ratio G = 1/2
Common-Mode EMI Rejection Ratio G = 2
Input Common-Mode Voltage vs Output Voltage G = 1/2, Bipolar Supply
Input Common-Mode Voltage vs Output Voltage G= 2, Bipolar Supply
Input Common-Mode Voltage vs Output Voltage G = 1/2, 5-V Supply
Input Common-Mode Voltage vs Output Voltage G = 2, 5-V Supply
Input Common-Mode Voltage vs Output Voltage G = 1/2, 36-V Supply
Input Common-Mode Voltage vs Output Voltage G = 2, 36-V Supply
Closed-Loop Output Impedance vs Frequency
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
50
40
30
20
10
0
50
40
30
20
10
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
D001
D002
Offset Voltage (mV)
Offset Voltage (mV)
N = 470
G = 1/2
Mean = 0.82 μV
VS = ±2.25 V
Std. Dev. = 2.91 μV
VCM = –3 V
N = 470
G = 2
Mean = 1.64 μV
VS = ±2.25 V
Std. Dev. = 5.82 μV
VCM = –3 V
Figure 7-1. Typical Distribution of Offset Voltage (RTO)
Figure 7-2. Typical Distribution of Offset Voltage (RTO)
20
20
15
10
5
15
10
5
0
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
D003
D004
Offset Voltage (mV)
Offset Voltage (mV)
N = 470
G = 1/2
Mean = –5.22 μV Std. Dev. = 8.38 μV
N = 470
G = 2
Mean = –10.43 μV Std. Dev. = 16.77 μV
Figure 7-3. Typical Distribution of Offset Voltage (RTO)
Figure 7-4. Typical Distribution of Offset Voltage (RTO)
30
35
30
25
20
15
10
5
25
20
15
10
5
0
0
-2 -1.6 -1.2 -0.8 -0.4
0
0.4 0.8 1.2 1.6
2
-4 -3.2 -2.4 -1.6 -0.8
0
0.8 1.6 2.4 3.2
4
D005
D006
Offset Voltage Drift (mV/èC)
Offset Voltage Drift (mV/èC)
N = 30
Mean = –0.075 μV/°C Std. Dev. = 0.502 μV/°C
N = 30
G = 2
Mean = –0.325 μV/°C Std. Dev. = 0.887 μV/°C
G = 1/2
Figure 7-5. Typical Distribution of Offset Voltage Drift (RTO)
Figure 7-6. Typical Distribution of Offset Voltage Drift (RTO)
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
100
50
150
100
50
0
0
-50
-100
-150
-200
-250
-300
-50
-100
-150
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D007
D05018
G = 1/2
30 units
G = 2
30 units
Figure 7-7. Output Offset Voltage vs Temperature
Figure 7-8. Output Offset Voltage vs Temperature
1500
1000
750
500
1000
500
250
0
0
-250
-500
-750
-1000
-500
-1000
-1500
-60
-40
-20
Common-Mode Voltage (V)
0
20
40
60
-30 -25 -20 -15 -10 -5
0
Common-Mode Voltage (V)
5
10 15 20 25 30
D009
D010
G = 1/2
12 units
G = 2
12 units
Figure 7-9. Offset Voltage vs Common-Mode Voltage
Figure 7-10. Offset Voltage vs Common-Mode Voltage
1200
100
1000
800
600
400
200
0
0
-100
-200
-300
-400
-500
-600
-200
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D011
D012
Figure 7-11. Input Bias Current vs Temperature
Figure 7-12. Input Offset Current vs Temperature
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
3500
3000
2500
2000
1500
1000
500
3500
3000
2500
2000
1500
1000
500
0
0
-500
-1000
-1500
-500
-1000
-1500
-40èC
25èC
125 èC
-40èC
25èC
125èC
-60
-40
-20
Common-Mode Voltage (V)
0
20
40
60
-30 -25 -20 -15 -10 -5
0
Common-Mode Voltage (V)
5
10 15 20 25 30
D013
D014
G = 1/2
G = 2
Figure 7-13. Input Bias Current vs Common-Mode Voltage
Figure 7-14. Input Bias Current vs Common-Mode Voltage
30
30
25
20
15
10
5
25
20
15
10
5
0
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
D015
D016
Common-Mode Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
N = 470
G = 1/2
Mean = 6.01 μV/V
VS = ±2.25 V
Std. Dev. = 4.85 μV/V
N = 470
G= 2
Mean = –6.22 μV/V
VS = ±2.25 V
Std. Dev. = 10.74 μV/V
Figure 7-15. Typical CMRR Distribution
Figure 7-16. Typical CMRR Distribution
40
30
25
20
15
10
5
30
20
10
0
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
-80
-60
-40
-20
0
20
40
60
80
D017
D018
Common-Mode Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
N = 470
G = 1/2
Mean = 4.86 μV/V
Std. Dev. = 4.75 μV/V
N = 470
Mean = –8.64 μV/V
Std. Dev. = 9.70 μV/V
G = 2
Figure 7-17. Typical CMRR Distribution
Figure 7-18. Typical CMRR Distribution
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
-5
-10
-15
-20
-25
-30
35
30
25
20
15
10
5
0
-5
-10
-15
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D019
D020
G = 1/2
24 units
Figure 7-19. CMRR vs Temperature
G = 2
24 units
Figure 7-20. CMRR vs Temperature
40
35
30
25
20
15
10
5
120
100
80
VS
VS
=
=
1ꢀ V
4 V
G = 1/2
G = 2
60
40
20
100m
0
1
1
10
100
1k
10k 100k
1M
10M
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
Frequency (Hz)
D056
G = 1/2 and G = 2
Figure 7-22. Maximum Output Voltage vs Frequency
Figure 7-21. Common-Mode Rejection Ratio vs Frequency,
Referred-to-Input
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D023
D024
G = 1/2
24 units
Figure 7-23. PSRR vs Temperature
G = 2
24 units
Figure 7-24. PSRR vs Temperature
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
140
120
100
80
140
120
100
80
PSRR+
PSRR+
̶
̶
PSRR
PSRR
60
60
40
40
20
20
0
0
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
G = 1/2
G = 2
Figure 7-25. PSRR vs Frequency (RTI)
Figure 7-26. PSRR vs Frequency (RTI)
50
40
30
20
10
50
40
30
20
10
0
0
0
-0.03
0.005
0.01
0.015
0.02
0.025
0.03
-0.025
-0.02
-0.015
-0.01
-0.005
0
D027
D028
Gain Error (%)
Gain Error (%)
N = 470
G = 1/2
Mean = 0.0085%
Std. Dev. = 0.0014%
N = 470
G = 2
Mean = –0.0076%
Std. Dev. = 0.0015%
Figure 7-27. Typical Distribution of Gain Error
Figure 7-28. Typical Distribution of Gain Error
0.01
-0.002
-0.0025
-0.003
-0.0035
-0.004
-0.0045
-0.005
-0.0055
-0.006
-0.0065
-0.007
-0.0075
-0.008
-0.0085
-0.009
-0.0095
-0.01
0.00.8
0.00.6
0.00.4
0.00.2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D029
D030
G = 1 /2
30 units
G = 2
30 units
Figure 7-30. Gain Error vs Temperature
Figure 7-29. Gain Error vs Temperature
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
10
20
10
0
0
-10
-20
-30
-10
CLOAD = 20 pF
CLOAD = 100 pF
CLOAD = 20 pF
CLOAD = 100 pF
-20
100
1k
10k 100k
Frequency (Hz)
1M
10M
100
1k
10k 100k
Frequency (Hz)
1M
10M
D032
D031
G = 2
Figure 7-32. Closed-Loop Gain vs Frequency
G = 1/2
Figure 7-31. Closed-Loop Gain vs Frequency
1000
100
10
1000
100
10
1
100m
1
100m
1
10
100
Frequency (Hz)
1k
10k
100k
1
10
100
Frequency (Hz)
1k
10k
100k
D033
D034
G = 1/2
G = 2
Figure 7-33. Voltage Noise Spectral Density vs Frequency (RTI) Figure 7-34. Voltage Noise Spectral Density vs Frequency (RTI)
Time (1 s/div)
Time (1 s/div)
G = 2
Figure 7-36. 0.1-Hz to 10-Hz RTI Voltage Noise
G = 1/2
Figure 7-35. 0.1-Hz to 10-Hz RTI Voltage Noise
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
100
10
1
100
10
1
0.1
0.1
1
10
100 1k
Frequency (Hz)
10k
100k
1
10
100 1k
Frequency (Hz)
10k
100k
D037
D038
G = 1/2
G = 2
Figure 7-37. Integrated Output Voltage Noise vs Noise
Bandwidth
Figure 7-38. Integrated Output Voltage Noise vs Noise
Bandwidth
18
18
-40èC
-40èC
25èC
85èC
125èC
17.5
17.5
17
25èC
17
85èC
125èC
16.5
16.5
16
16
15.5
15
15.5
15
14.5
14
14.5
14
13.5
13
13.5
13
12.5
12
12.5
12
11.5
11.5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad (mA)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
G = 1/2
G = 2
Figure 7-39. Positive Output Voltage vs Output Current
(Sourcing)
Figure 7-40. Positive Output Voltage vs Output Current
(Sourcing)
-14
-14
-14.25
-14.5
-14.75
-15
-40èC
25èC
85èC
125èC
-14.25
-14.5
-14.75
-15
-40èC
25èC
85èC
125èC
-15.25
-15.5
-15.75
-16
-15.25
-15.5
-15.75
-16
-16.25
-16.5
-16.75
-17
-16.25
-16.5
-16.75
-17
-17.25
-17.5
-17.75
-18
-17.25
-17.5
-17.75
-18
-5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
ILoad ( mA )
G = 1/2
G = 2
Figure 7-41. Negative Output Voltage vs Output Current
(Sinking)
Figure 7-42. Negative Output Voltage vs Output Current
(Sinking)
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
Falling
Rising
Falling
Rising
Time (1 ms/div)
Time (1 ms/div)
D043
D044
G = 1/2
G = 2
Figure 7-43. Settling Time
Figure 7-44. Settling Time
VIN–
VIN+
VOUT
VIN-
VIN +
VOUT
Time (1 μs/div)
Time (1 ms/div)
D046
G = 2
Figure 7-46. Large-Signal Step Response
G = 1/2
Figure 7-45. Large-Signal Step Response
30
24
18
12
Negative
Positive
Rising
Falling
-60
-35
-10
15
40
65
90
115
140
Time (200 μs/div)
Temperature (èC)
D047
Figure 7-47. Slew Rate Over Temperature
Figure 7-48. Overload Recovery (Normalized to 0 V)
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
10
100
Capacitance (pF)
1000
10
100
Capacitance (pF)
1000
G = 1/2
G = 2
Figure 7-49. Small-Signal Overshoot vs Capacitive Load
Figure 7-50. Small-Signal Overshoot vs Capacitive Load
VIN-
VIN +
VOUT
VIN–
VIN+
VOUT
Time (1 ms/div)
Time (1 μs/div)
D051
G = 2
G = 1/2
Figure 7-51. Small-Signal Step Response
Figure 7-52. Small-Signal Step Response
1
-40
1
0.1
-40
RL = 10 kW
RL = 2 kW
RL = 600 W
RL = 10 kW
RL = 2 kW
RL = 600 W
0.1
-60
-60
0.01
-80
0.01
-80
0.001
0.0001
-100
-120
0.001
0.0001
-100
-120
100
1k
Frequency (Hz)
10k
100
1k
Frequency (Hz)
10k
D053
D054
G = 1/2
VOUT = 3.5 VRMS
G = 2
VOUT = 3.5 VRMS
Figure 7-53. THD+N vs Frequency
Figure 7-54. THD+N vs Frequency
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
1
-40
1
-40
RL = 10 kW
RL = 2 kW
RL = 600 W
RL = 10 kW
RL = 2 kW
RL = 600 W
0.1
-60
0.1
-60
0.01
-80
0.01
-80
0.001
-100
-120
0.001
-100
-120
0.0001
0.0001
10m
100m
Output Amplitude (VRMS
1
10
10m
100m
Output Amplitude (VRMS
1
10
)
)
D055
D056
G = 1/2
G = 2
Figure 7-55. THD+N Ratio vs Output Amplitude
Figure 7-56. THD+N Ratio vs Output Amplitude
1.1
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
1.08
1.06
1.04
1.02
1
0.99
0.98
0.97
0.96
0.98
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D057
D058
G = 1/2
30 units
G = 2
30 units
Figure 7-57. Supply Current vs Temperature
Figure 7-58. Supply Current vs Temperature
5
4.5
4
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
0
5
10
15
20
Total Supply (V)
25
30
35
40
0
5
10
15
20
Total Supply (V)
25
30
35
40
D060
D059
G = 2
30 units
G = 1/2
30 units
Figure 7-60. Supply Current vs Supply Voltage
Figure 7-59. Supply Current vs Supply Voltage
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
90
60
30
0
90
60
30
0
-30
-60
-90
-30
-60
-90
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D062
D061
G = 2
30 units
G = 1/2
30 units
Figure 7-62. Short Circuit Current vs Temperature
Figure 7-61. Short Circuit Current vs Temperature
160
150
140
130
120
110
100
90
140
120
100
80
60
10M
100M
Frequency (Hz)
1G
10G
10M
100M
1G
10G
Frequency (Hz)
G = 1/2
G = 2
Figure 7-64. Differential-Mode EMI Rejection Ratio
Figure 7-63. Differential-Mode EMI Rejection Ratio
180
140
130
120
110
100
90
160
140
120
100
80
80
60
10M
70
10M
100M
Frequency (Hz)
1G
10G
100M
1G
10G
Frequency (Hz)
D065
G = 1/2
G = 2
Figure 7-66. Common-Mode EMI Rejection Ratio
Figure 7-65. Common-Mode EMI Rejection Ratio
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SBOS385B – AUGUST 2019 – REVISED APRIL 2021
7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
80
60
40
30
VS = ê2.25 V
VS = ê18 V
VS = ê2.25 V
VS = ê18 V
40
20
20
10
0
0
-20
-40
-60
-80
-10
-20
-30
-40
-20 -16 -12
-8
-4
Output Voltage (V)
0
4
8
12
16
20
-20
-15
-10
-5
Output Voltage (V)
0
5
10
15
20
D067
D068
G = 1/2
Bipolar supply
VREF = 0 V
G = 2
Bipolar supply
VREF = 0 V
Figure 7-67. Input Common-Mode Voltage vs Output Voltage
Figure 7-68. Input Common-Mode Voltage vs Output Voltage
20
10
15
10
5
7.5
5
2.5
0
0
-5
-2.5
-5
-10
-1.25
0
1.25
2.5
Output Voltage (V)
3.75
5
6.25
-1.25
0
1.25
2.5
Output Voltage (V)
3.75
5
6.25
D069
D070
G = 1/2
5-V supply
VREF = 0 V
G = 2
5-V supply
VREF = 0 V
Figure 7-69. Input Common-Mode Voltage vs Output Voltage
Figure 7-70. Input Common-Mode Voltage vs Output Voltage
120
100
80
60
50
40
30
20
10
0
60
40
20
0
-20
-40
-60
-10
-20
0
4
8
12
16
Output Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Output Voltage (V)
20
24
28
32
36
40
D071
D072
G = 1/2
36-V supply
VREF = 0 V
G = 2
36-V supply
VREF = 0 V
Figure 7-71. Input Common-Mode Voltage vs Output Voltage
Figure 7-72. Input Common-Mode Voltage vs Output Voltage
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VOUT = VS / 2, RL = 10 kΩ, REF pin connected to ground, G = 1/2 (unless otherwise noted)
1000
100
10
1
0.1
0.01
0.001
0.0001
G = 2
G = 0.5
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D073
Figure 7-73. Closed-Loop Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The INA597 consists of a high-precision, e-trim™ operational amplifier and four trimmed resistors. These
resistors can be connected to make a wide variety of amplifier configurations, including difference, noninverting,
and inverting configurations. Using the on-chip resistors of the INA597 provides the designer with several
advantages over a discrete design. The INA597 also includes internal compensation capacitors, as shown in
Section 8.2.
8.2 Functional Block Diagram
V+
INA597
12 kꢀ
6 kꢀ
œIN
SENSE
16 pF
œ
OUT
+
16 pF
Vœ
12 kꢀ
6 kꢀ
+IN
REF
Vœ
8.3 Feature Description
Much of the dc performance of op-amp circuits depends on the accuracy of the surrounding resistors. The
resistors on the INA597 are laid out to be tightly matched. The resistors of each part are matched on-chip and
tested for their matching accuracy. As a result of this trimming and testing, the INA597 provides high accuracy
for specifications such as gain drift, common-mode rejection, and gain error.
8.4 Device Functional Modes
The INA597 measures voltages beyond the rails. For the G = ½ and G = 2 difference amplifier configurations,
see the input voltage range in Section 7 for details. The INA597 can be configured in several ways; see
Figure 9-5 to Figure 9-9. These configurations rely on the internal, matched resistors; therefore, all of these
configurations have excellent gain accuracy and gain drift.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Figure 9-1 shows the basic connections required for operation of the INA597. Connect power supply bypass
capacitors close to the device pins.
The differential input signal is connected to pins 2 and 3, as shown. The source impedances connected to the
inputs must be nearly equal to provide good common-mode rejection. An 8-Ω mismatch in source impedance
degrades the common-mode rejection of a typical device to approximately 80 dB. Gain accuracy is also slightly
affected. If the source has a known impedance mismatch, use an additional resistor in series with one input to
preserve good common-mode rejection.
9.2 Typical Applications
9.2.1 Basic Power-Supply and Signal Connections
V–
V+
1 µF
1 µF
4
7
INA597
R1
R2
2
3
5
6
V2
12 kW
6 kW
R3
V3
RL
12 kW
R4
6 kW
VOUT = V3 – V2
1
REF
Figure 9-1. Basic Power-Supply and Signal Connections
9.2.1.1 Design Requirements
For the application shown in Figure 9-1, the design requirements are:
•
•
Gain of G = ½
VREF = 0 V
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Operating Voltage
The INA597 operates from single (4.5 V to 36 V) or dual (±2.25 V to ±18 V) supplies with excellent
performance. Specifications are production tested with +5-V and ±15-V supplies. Most behavior remains
unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage
are shown in Section 7.7. The internal op amp in the INA597 is a single-supply design. This design allows linear
operation with the op amp common-mode voltage equal to, or slightly less than V– (or single-supply ground).
Although input voltages on pins 2 and 3 that are less than the negative supply voltage do not damage the
device, operation in this region is not recommended. Transient conditions at the inverting input terminal less than
the negative supply can cause a positive feedback condition that could lock the device output to the negative rail.
The INA597 accurately measures differential signals that are greater than the positive power supply. For
example with G = ½, the linear common-mode range extends to nearly three times the positive power supply
voltage; see Section 7.7, as well as Section 9.2.1.2.3.
9.2.1.2.2 Offset Voltage Trim
The INA597 is production trimmed for low offset voltage and drift. Most applications require no external offset
adjustment. Figure 9-2 shows an optional circuit for trimming the output offset voltage. The output is referred to
the output reference terminal (pin 1), which is normally grounded. A voltage applied to the REF pin is summed
with the output signal. This configuration can be used to null offset voltage. To maintain good common-mode
rejection, make sure the source impedance of a signal applied to the REF pin is less than 8 Ω. For low
impedance at the REF pin, the trim voltage can be buffered with an op amp, such as the OPA177.
INA597
R1
R2
2
5
6
V2
VO
8 W
R3
3
V3
R
4
+15 V
1
REF
R = 237 kW
VO = V3 –V2
Offset Adjustment
Range = 5ꢀꢀ ꢁV
1ꢀꢀ kW
8 W
–15 V
NOTE: For 75ꢀ0ꢁV rangeꢂ R = 158 kW.
Figure 9-2. Offset Adjustment
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9.2.1.2.3 Input Voltage Range
The INA597 measures input voltages beyond the supply rails. The internal resistors divide down the voltage
before the voltage reaches the internal op amp and provide protection to the op amp inputs. Figure 9-3 shows
an example of how the voltage division works in a difference-amplifier configuration. For the INA597 to measure
correctly, the input voltages at the input nodes of the internal op amp must stay less than 0.1 V of the positive
supply rail, and can exceed the negative supply rail by 0.1 V. See Section 10 for more details.
R4
-INOP =
∂ V-IN
R3 + R4
R3
R4
VœIN
œIN
SENSE
œ
OUT
+
R1
R2
V+IN
+IN
REF
R2
+INOP =
∂ V+IN
R1+ R2
Figure 9-3. Voltage Division in the Difference Amplifier Configuration
The INA597 has integrated ESD diodes at the inputs that provide overvoltage protection. This feature simplifies
system design by eliminating the need for additional external protection circuitry, and enables a more robust
system. The voltages at any of the inputs of the parts in G = ½ configuration with ±18 V supplies can safely
range from +VS − 54 V up to −VS + 54 V. For example, on ±10-V supplies, the input voltages can go as high as
±30 V.
9.2.1.2.4 Capacitive Load Drive Capability
The INA597 can drive large capacitive loads, even at low supplies. The device is stable with a 500-pF load; see
Section 7.7.
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9.2.1.3 Application Curve
The interaction between the output stage of an operational amplifier (op amp) and capacitive loads can impact
the stability of the circuit. Throughout the industry, op-amp output-stage requirements have changed greatly
since their original creation. Classic output stages with the class-AB common-emitter bipolar junction transistor
(BJT) have now been replaced with common-collector BJT and common-drain complementary metal-oxide
semiconductor (CMOS) devices. Both of these technologies enable rail-to-rail output voltages for single-supply
and battery-powered applications. A result of changing these output-stage structures is that the op-amp
open-loop output impedance (Zo) changed from the largely resistive behavior of early BJT op amps to a
frequency-dependent ZO that features capacitive, resistive, and inductive portions. Proper understanding of
ZO over frequency—and also the resulting closed-loop output impedance over frequency—is crucial for the
understanding of loop gain, bandwidth, and stability analysis. Figure 9-4 shows how the INA597 closed-loop
output impedance varies over frequency.
1000
100
10
1
0.1
0.01
0.001
0.0001
G = 2
G = 0.5
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D073
VS = ±18 V
Figure 9-4. Closed-Loop Output Impedance vs Frequency
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9.2.2 Precision Instrumentation Amplifier
The INA597 can be combined with op amps to form a complete instrumentation amplifier (IA) with specialized
performance characteristics, as shown in Figure 9-5.
V1
INA597
–IN
A1
2
5
R2
6
R1
VO
R2
1
3
A2
V2
+IN
VO = (1 + 2R2 / R1) (V2 – V1)
Figure 9-5. Precision Instrumentation Amplifier
9.2.3 Low Power, High-Output Current, Precision, Difference Amplifier
BUF634 inside feedback
loop contributes no error.
INA597
2
5
6
1
–IN
V
BUF634
O
R
L
3
(Low IQ mode)
+IN
Figure 9-6. Low Power, High-Output Current, Precision, Difference Amplifier
9.2.4 Pseudoground Generator
V+
V+
3
INA597
2
5
7
6
(V+) / 2
1
4
Ground
Ground
Figure 9-7. Pseudoground Generator
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9.2.5 Differential Input Data Acquisition
5 V
7
INA597
2
5
6
1
–IN
12 Bits
Out
ADS7806
0-V to 4-V
Input
3
+IN
4
VCM = 0 V to 8 V
tS = 45 µs (4-V Step to 0.01%)
Figure 9-8. Differential Input Data Acquisition
9.2.6 Precision Voltage-to-Current Conversion
V+
12.5 kꢀ
50 kꢀ
1 kꢀ
0-V to 10-V in
7
œ
Set R1 = R2
6 kꢀ
12 kꢀ
5
2
15 V
2
+
R1
R2
VœIN
œ
OPA192
6
R1
INA597
2N3904
+
50.1 ꢀ
VOUT
6
REF10
R3
R4
1
3
10 V
R2
V+IN
VREF
50.1 ꢀ
6 kꢀ
12 kꢀ
4
4
For 4-mA to 20-mA applications,
the REF10 sets the 4-mA,
low-scale output for the 0-V input.
RL
IOUT = 4 mA to 20 mA
≈
∆
«
’
1
1
IOUT = 2∂ V+IN - V-IN
+
(
)
÷
40 kW R2 ◊
Figure 9-9. Precision Voltage-to-Current Conversion
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9.2.7 Additional Applications
Texas Instruments offers many complete high-performance instrumentation amplifiers. See Table 9-1 for some of
the products with related performance.
Table 9-1. Recommended Op Amp Products to Use With the INA597
A1, A2
FEATURE
SIMILAR TI IA
OPA27
Low noise
INA103
OPA129
OPA177
OPA2130
OPA2234
OPA2237
Ultra-low bias current (fA)
Low offset drift, low noise
Low power, FET-input (pA)
Single supply, precision, low power
SIngle supply, low power, 8-pin MSOP
INA116
INA114, INA128
INA111
INA122. INA118
INA122, INA126
The difference amplifier is a highly versatile building block that is useful in a wide variety of applications. See the
INA105 data sheet for additional applications ideas, including:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current receiver with compliance to rails
Precision unity-gain inverting amplifier
±10-V precision voltage reference
±5-V precision voltage reference
Precision unity-gain buffer
Precision average value amplifier
Precision G = 2 amplifier
Precision summing amplifier
Precision G = 1/2 amplifier
Precision bipolar offsetting
Precision summing amplifier with gain
Instrumentation amplifier guard drive generator
Precision summing instrumentation amplifier
Precision absolute value buffer
Precision voltage-to-current converter with differential inputs
Differential input voltage-to-current converter for low IOUT
Isolating current source
Differential output difference amplifier
Isolating current source with buffering amplifier for greater accuracy
Window comparator with window span and window center inputs
Precision voltage-controlled current source with buffered differential inputs and gain
Digitally controlled gain of ±1 amplifier
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10 Power Supply Recommendations
The nominal performance of the INA597 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in Section 7.7.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
•
•
Take care to make sure that both input paths are well-matched for source impedance and capacitance to
avoid converting common-mode signals into differential signals.
Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
•
•
Place the external components as close to the device as possible.
Keep the traces as short as possible.
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11.2 Layout Example
Vœ
V+
1 ꢁF
1 ꢁF
C1
C2
4
7
12 kꢀ
6 kꢀ
2
5
VœIN
SENSE
œIN
R1
R2
œ
6
VOUT
+
OUT
RL
R3
R4
3
1
V+IN
VREF = GND
REF
+IN
12 kꢀ
6 kꢀ
1
=
VOUT
∂ V+IN - V-IN
(
)
2
+V
Low-impedance
connection for reference
terminal
GND
C2
Use ground pours for
shielding the input signal
pairs
INA597
1
8
7
6
NC
REF
œ
2
V+
œIN
œIN
+
3
+IN
OUT
+IN
VOUT
4
Vœ
5
SENSE
C1
GND
RL
Place bypass capacitors
as close to IC as
possible
GND
œV
Figure 11-1. Example Schematic and Associated PCB Layout for SOIC and VSSOP Packages
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Vœ
V+
1 ꢁF
1 ꢁF
C1
C2
5
8
12 kꢀ
6 kꢀ
3
6
VœIN
SENSE
œIN
R1
R2
œ
1
-INOP
7
VOUT
+
10
OUT
+INOP
RL
R3
R4
4
2
V+IN
VREF = GND
REF
+IN
12 kꢀ
6 kꢀ
1
=
VOUT
∂ V+IN - V-IN
(
)
2
Low-impedance
connection for
reference terminal
INA597
1
2
GND
Þ INOP
+INOP
10
REF
NC
V+
9
8
œ
œIN
œIN
3
4
5
+
C2
+IN
+IN
OUT
7
6
+INOP
Vœ
SENSE
GND
NC= No Connection
RL
C1
Use ground pours
for shielding
the input
Place bypass capacitors
as close to IC as
possible
signal pairs
œV
Figure 11-2. Example Schematic and Associated PCB Layout with VSON Package
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Universal Difference Amplifier Evaluation Module user's guide
Texas Instruments, Precision Signal-Conditioning Solutions for Motor-Control Position Feedback technical
brief
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA597IDGKR
INA597IDGKT
INA597IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1WT6
1WT6
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
NIPDAU
8
3000 RoHS & Green
3000 RoHS & Green
INA597
IN597
INA597IDRCR
INA597IDRCT
INA597IDT
VSON
VSON
SOIC
DRC
DRC
D
10
10
8
-40 to 125
-40 to 125
250
250
RoHS & Green
RoHS & Green
IN597
INA597
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA597IDGKR
INA597IDGKT
INA597IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
330.0
330.0
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
6.4
3.3
3.3
6.4
3.4
3.4
5.2
3.3
3.3
5.2
1.4
1.4
2.1
1.1
1.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q2
Q2
Q1
8
3000
3000
250
INA597IDRCR
INA597IDRCT
INA597IDT
VSON
VSON
SOIC
DRC
DRC
D
10
10
8
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA597IDGKR
INA597IDGKT
INA597IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
366.0
366.0
853.0
367.0
210.0
210.0
364.0
364.0
449.0
367.0
185.0
185.0
50.0
50.0
35.0
35.0
35.0
35.0
8
3000
3000
250
INA597IDRCR
INA597IDRCT
INA597IDT
VSON
VSON
SOIC
DRC
DRC
D
10
10
8
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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